WEBVTT

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Hey everybody!

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Welcome to Japan! Welcome to Sagami Bay.

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we're here not far from Enoshima Island

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I wanted to talk about Tomachie

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and step you through some of the basics

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unfortunately

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there will be a few slides to look at first

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just to get the new folks oriented

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to what Tomachie's all about

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let's take a look Tomachie is a printed circuit board

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design quality platform

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it's designed to perform a schematic review

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before the layout occurs and why does it exist

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well for a couple of reasons

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we had started because Intellitech customers

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couldn't get the test points in the design

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it was really happening too late

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the circuit board would even be completely laid out

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or fabricated by the time

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the designers were talking to the test departments

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about what they needed for test

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so we wanted to get started a little bit earlier

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and the way to get the test points inserted

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was to offer something for the design engineers

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which was

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checking the design

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and what we found is that the printed circuit board risk

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it's cheapest to fix during the schematic phase

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than it is during the layout phase right

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or during purchasing

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or after the printed circuit boards are actually made

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there's a shift left here to save on cost

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to catch these problems very early on

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we want the issues to surface

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such as the not recommended for new designs

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not having enough test points

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or not having the test points in the right places

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we want to check borderline non-functional

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or even designs that won't pass the compliance test

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and so we want to know that ahead of time

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before we get into spending time during layout

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and the first step that we do

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is to make sure that the design can be checked with AI

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so we're doing two checks

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one's the quality gate

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where we're looking at the connectivity

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then we're looking at the BOM component data

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or looking to see that the values

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the capacitance and voltage and tolerance and footprint

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are all correct and match the part number

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for instance

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making sure that the properties are

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behind those schematic symbols

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that you see

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that the properties for the design are present

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before we go off and use AI

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because AI needs to have all the data correct

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if you don't give it the correct data

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then it's not going to give you the correct answer

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so there's a lot of individual attributes,

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the quality of the schematic symbol,

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how the pins are characterized,

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part numbers and so forth.

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All of that has to be correct.

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We give you a report that you can run

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and you get that information

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at the schematic capture time

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we're also going to insert test points as well

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during that process so

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these deterministic checks

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reduce the risk during BOM purchase

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because we're validating

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that the part number that's being used

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matches all the properties

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that are present or should be present in the design

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and then once that we know that it is good

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you get a score and if your score is high enough

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It has to be a 75 or 80

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out of 100. When your score is high enough

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then we'll run the AI

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checks with the data sheets as well.

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This prevents people from spending money on a run

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that is not going to work well,

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because there's a lot of information missing

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from the schematic: the capacitors don't have values

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or the resistors don't have values

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so we're catching all that up front

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then we're going to go off and check the datasheets

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we're going to check all the different components

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that are present, and check the limits

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against the voltage rails that are there,

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make sure that all the ecosystem parts

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that a regulator or some other IC needs;

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all those ecosystem parts

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are actually present in the schematic

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and designed correctly. As I said,

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the design-for-test is part of that review,

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We're looking at AXI inspection,

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AOI (automated optical inspection),

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flying probe or ICT (in-circut test),

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depending if you're building a BON (bed-of-nails fixture),

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and then boundary scan too.

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We're pulling in all the software

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from the Intellitech Group for boundary scan,

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and then analyzing the schematic

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to understand the location of,

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the nets that are not covered for test well,

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and where, if we insert additional test points,

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could we get higher fault coverage.

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Then, we insert test points into the native eCAD

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Altium, OrCAD, KiCad

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EasyEDA, those are all supported.

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We write out the eCAD data

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after inserting the test points.

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When we find errors and issues,

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these findings become part of a managed workflow,

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so it's not just a check but also we give you a status,

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and then enable you to share with your stakeholders

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that status.

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When you resolve findings that are problematic

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that are in the report, you can select from a menu

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the disposition of that particular finding.

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So it's a design quality platform.

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It's not just a checker for design mistakes,

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It's something that every team member can work with

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and has a little something for every team member,

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design, purchasing,

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manufacturing test and embedded software;

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management of the schematic quality

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that's there.

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Let's take a look at how you upload your design,

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and some of the characteristics of the Tomachie platform,

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and what it can do 

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for your company.

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Let's look at the website and upload our first design.

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There is a language picker for picking languages,

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17 different languages,

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If your stakeholders require a language

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other than English, it's supported.

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It gives you the flow of what we're doing,

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which is parsing the schematics,

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analyzing, inserting test points,

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then giving you a preliminary report and an email link,

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then an opportunity to do AI enrichment,

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and then you get a link for that report as well.

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I've entered in my email address

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and I've selected the Cricket-Node design

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which is a design created by Eli Hughes

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a very good designer. He's with the WaveNumber LLC.

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He has a GitHub location with some of his tools,

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and Cricket-Node is one of the designs

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that he shared on GitHub.

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You don't need to enter the top level information,

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or the variant, the tools will take the last variant

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that you worked with,

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or you can specify the variant if you need to.

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In this case, there's no other variants

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Its a single design, a single sheet,

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that's done, I believe,

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in Altium.  You have Design-for-Test,

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it's going to take too much time to go through all of this,

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but you can take a look and share this with your

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test engineers.

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You can select

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where you want to have test points inserted,

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the default is to not insert test points

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on all the nets.

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There's choices for whether you're going to do manual

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or optical inspection.

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These will be determined most likely by your EMS,

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whomever's building the PCBs for you.

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We default to flying probe,

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but in-circuit test, and all-in-one

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testers like Intellitech's are

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are also choices that you can use.

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You can dial in your fault coverage, but....

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I'm not going to get into the details of that quite yet.

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We'll do that in a separate video.

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Kelvin test-points and different types of boundary-scan test,

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but, you cant take the defaults.

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That's probably a good starting point,

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I will make a second video

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to describe how to optimize the test point insertion

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and do that in conjunction with various test methods.

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There's also PCOLA/SOQ scoring and you can adjust that

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but that's another separate video, also.

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How to deal with PCOLA/SOQ?

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You can leave the defaults

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unless you know,

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or your test engineers know how to set differently

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in order to perform the right kind of fault coverage

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for your environment.  After you review it,

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you can click and say "I've reviewed",

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reviewed the design

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for test options available for the PCB.

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Then you click this,

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to say that you agree to the CDA.

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We also accept company CDAs,

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There's a separate page for that,

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where you can have us sign off on one of your

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your own confidentiality agreements.

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We have a basic one on the website

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that explains how

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we're not sharing your designs with any third parties,

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It goes through the steps of the confidentiality protection.

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Next step, you tell it you want to analyze the schematic,

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and it will upload the design.

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You should get a submitted successfully

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so you know that all your schematic sheets were found

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and there weren't any issues with the design pages,

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then you'll get it submitted successfully.

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Then you look at your

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your email link to start processing.

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You'll get an email,

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and then you click the button to say "start processing".

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what this does

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is, just validate that the address that you submitted

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is a valid email address.  It starts the process

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after you submit the design

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and when it's done processing

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you'll get another email

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that tells you that the report is ready.

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There's three items that are displayed

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on the preliminary run, the report,

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a modified design which has test points in it,

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and a Tomachie-generated BOM.

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You can compare that BOM

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with the one from the ECAD tool

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that you're using.  You get a quick summary of

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what's there so this scores very well,

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86 out of 100.

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This just tells you some stats, like there are

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14 ICs and one sheet with all of that in there,

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and then it brings you into the AI portion.

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Before you go on to the AI portion,

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it's probably best to take a look at the report.

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so let's do that, so here's the report.

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and as I said it's Eli Hughes' design.

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it's very very good design

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He's a very good designer.

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and that 86/100 has been reduced.

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it will tell you what it took points off for

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and mostly it'on fault coverage

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This design has a good number of test points in it

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and Tomachie is just looking for a few more test points.

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The score can be improved drastically

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by putting in addditional test points.

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Also some power rails are found

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which don't have voltage on them.

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The +VIN is the input voltage

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and when we run the AI, it will ask us

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what's the specification for this particular voltage.

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It becomes a little more clear

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the AI needs to know all the external

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voltage rails. It can calculate

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the ones that are not external,

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such as VBATT for instance,

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or +VIN those aren't understood by AI

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as to what voltage range is allowed there.

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We will enter that in in the next phase,

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I'll show you how to do that.

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It looks like there might be some part numbers

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that didn't match their values.

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This preliminary run is checking that the part number,

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matches the component.

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There's an issue here:

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where the part number decode,

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it's a 6.8 uH

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inductor plus or minus 30%.

270
00:11:23.300 --> 00:11:25.333
But, on the schematic it says it's a

271
00:11:25.800 --> 00:11:28.800
plus or minus 20%.  It's very close,

272
00:11:28.833 --> 00:11:31.466
just there's a discrepancy there on

273
00:11:31.466 --> 00:11:34.066
on what the tolerance is. But, all the other

274
00:11:34.066 --> 00:11:36.266
parts are correct. This analysis is a very good check

275
00:11:36.266 --> 00:11:38.666
just to make sure that BOM represents

276
00:11:38.666 --> 00:11:40.100
what the schematic is showing

277
00:11:40.100 --> 00:11:41.900
for values that are present.

278
00:11:42.400 --> 00:11:44.766
Another key section is the power overview.

279
00:11:45.100 --> 00:11:46.500
It just give you some basics,

280
00:11:46.500 --> 00:11:48.800
that the tools are able to determine

281
00:11:48.800 --> 00:11:51.366
the power rails that are present

282
00:11:51.466 --> 00:11:53.100
It states what the source is,

283
00:11:53.100 --> 00:11:55.166
and then what the consumers are.

284
00:11:55.233 --> 00:11:57.833
As I mentioned, it annotates that.

285
00:11:57.833 --> 00:11:59.800
It found one power rail that it doesnt

286
00:11:59.800 --> 00:12:02.800
know what the voltage is.  That's solved

287
00:12:02.800 --> 00:12:04.200
by entering it in the website page.

288
00:12:04.200 --> 00:12:06.400
Tomachie generates other parts of the report,

289
00:12:06.500 --> 00:12:10.566
what your LSSI is; the chip supports SWD

290
00:12:10.566 --> 00:12:12.100
so then that's part of this section.

291
00:12:12.400 --> 00:12:14.766
You'll get insight into 

292
00:12:14.766 --> 00:12:16.900
your high speed

293
00:12:17.000 --> 00:12:20.166
HSSI and memory. 

294
00:12:20.166 --> 00:12:22.866
Here it discusses the class

295
00:12:22.866 --> 00:12:25.266
that was assigned to the differential pair

296
00:12:25.733 --> 00:12:29.666
It asks for something with a little bit more detail.

297
00:12:29.766 --> 00:12:32.600
the class assigned is just "USB".

298
00:12:33.000 --> 00:12:35.066
If you're doing your own design,

299
00:12:35.066 --> 00:12:37.366
you're doing the schematic capture and the layout,

300
00:12:37.366 --> 00:12:40.566
then "USB" might be enough to tell you what's needed

301
00:12:40.566 --> 00:12:43.866
at layout, but Tomachie is looking for 

302
00:12:43.866 --> 00:12:47.666
impedance in the class, the 90 ohms for USB 2.0

303
00:12:47.666 --> 00:12:49.400
The class name should be "90_ohms"

304
00:12:49.400 --> 00:12:51.300
which would tell the layout engineer

305
00:12:51.300 --> 00:12:55.933
the correct impedance for the traces on USB 2.0.

306
00:12:56.066 --> 00:12:57.233
The report will characterize

307
00:12:57.233 --> 00:13:00.766
the memory. The QSPI in this design doesn't

308
00:13:00.766 --> 00:13:02.466
have issues, other than test points.

309
00:13:02.466 --> 00:13:04.766
Test points would allow you to do on board programming

310
00:13:04.800 --> 00:13:06.666
direct programming of the device.

311
00:13:06.666 --> 00:13:10.633
But, you can also do in-system programming via U5

312
00:13:10.633 --> 00:13:12.033
Tomachie detects that is an option.

313
00:13:12.033 --> 00:13:15.533
It knows whether you can use the SWD port

314
00:13:15.566 --> 00:13:17.800
and be able to load programming data

315
00:13:18.000 --> 00:13:20.566
if you want to do programming indirectly.

316
00:13:20.600 --> 00:13:23.333
Functional analysis is blank,

317
00:13:23.366 --> 00:13:25.600
during the preliminary run

318
00:13:25.600 --> 00:13:26.900
because we don't have the data sheets.

319
00:13:26.900 --> 00:13:28.666
AI is going to help us with datasheets.

320
00:13:28.666 --> 00:13:30.033
The report does indicate, the basics

321
00:13:30.033 --> 00:13:31.866
of what is going to be analyzed

322
00:13:31.866 --> 00:13:34.533
and what ICs are present that need to be looked at.

323
00:13:34.600 --> 00:13:37.000
Tere's a design for test section,

324
00:13:37.000 --> 00:13:39.533
which gives you all the web-page settings,

325
00:13:39.566 --> 00:13:40.766
just for reference.

326
00:13:40.766 --> 00:13:43.833
and then it reports the PCB fault coverage.

327
00:13:43.833 --> 00:13:45.966
Check marks are given here

328
00:13:45.966 --> 00:13:48.633
for having test points appropriately

329
00:13:48.633 --> 00:13:50.166
on most of the power rails.

330
00:13:50.433 --> 00:13:53.500
The report also shows where test points are needed,

331
00:13:53.500 --> 00:13:54.866
that are not present.

332
00:13:55.000 --> 00:13:56.966
Mr. Hughes has very good ground test points.

333
00:13:57.100 --> 00:14:00.066
There's four of them.  Tomachie's default is six,

334
00:14:00.066 --> 00:14:01.766
but it's still a very good number.

335
00:14:01.766 --> 00:14:04.566
The report indicates where the inserted test points are,

336
00:14:05.000 --> 00:14:07.166
then it will calculate what the fault coverage is

337
00:14:07.166 --> 00:14:09.500
as well it gives you the coverage

338
00:14:09.500 --> 00:14:12.466
based on the type of test that's being performed

339
00:14:12.466 --> 00:14:13.966
or the optical inspection.

340
00:14:14.366 --> 00:14:17.300
Now that's a whole video in itself

341
00:14:17.300 --> 00:14:18.400
to go through all that.

342
00:14:18.400 --> 00:14:19.700
So I can't do that right now,

343
00:14:19.700 --> 00:14:22.200
We're skipping through a little bit,

344
00:14:22.200 --> 00:14:23.900
because we're just covering the basics

345
00:14:23.900 --> 00:14:26.166
of how to get your design submitted.

346
00:14:26.500 --> 00:14:30.600
That's the overview now on that page.

347
00:14:31.066 --> 00:14:33.166
Now you do have the opportunity

348
00:14:33.166 --> 00:14:36.000
to perform the AI enrichment.

349
00:14:36.000 --> 00:14:39.500
This is the +VIN; it needs to know what your

350
00:14:39.500 --> 00:14:41.300
your nominal external power is.

351
00:14:41.300 --> 00:14:44.766
I believe this is a 12 volt system

352
00:14:44.833 --> 00:14:47.733
and I think it might go down to 6V

353
00:14:48.100 --> 00:14:50.466
with excursions that go up to 18V.

354
00:14:50.633 --> 00:14:52.866
The designer knows better than I do,

355
00:14:53.233 --> 00:14:55.500
for a battery based PCB.

356
00:14:55.500 --> 00:14:58.400
6-18V might be considered a reasonable range.

357
00:14:58.566 --> 00:15:00.033
and then you have selections

358
00:15:00.033 --> 00:15:04.800
of the de-rating policy, so you select the environment

359
00:15:04.800 --> 00:15:06.500
here. We're just going to select commercial

360
00:15:06.500 --> 00:15:08.866
so it will be 25 degrees C

361
00:15:08.866 --> 00:15:12.000
but that temperature will go up to 40 degrees C

362
00:15:12.000 --> 00:15:13.166
in a commercial environment.

363
00:15:13.166 --> 00:15:15.766
AI needs to know the upper limit.

364
00:15:16.200 --> 00:15:21.266
There's individual limits for each one of these,

365
00:15:21.500 --> 00:15:24.033
that you can adjust if you don't think

366
00:15:24.033 --> 00:15:26.733
the maximum ambient temperature is going to be 40

367
00:15:27.033 --> 00:15:29.166
then you can adjust that downwards.

368
00:15:29.166 --> 00:15:34.533
Capacitor voltage is going to be derated by 20%,

369
00:15:34.566 --> 00:15:37.366
and so you'll have 80% of the specified voltage range

370
00:15:37.433 --> 00:15:40.366
Each one of these can be adjusted to winding,

371
00:15:40.366 --> 00:15:42.700
voltage, saturation current, etc.

372
00:15:42.866 --> 00:15:44.500
This is just the default de-rating

373
00:15:44.500 --> 00:15:46.566
and it's a whole video in itself,

374
00:15:46.566 --> 00:15:48.300
so I'm not going to cover it all right now,

375
00:15:48.300 --> 00:15:49.666
but just to make you familiar

376
00:15:49.666 --> 00:15:51.900
that de-ratings are available

377
00:15:51.900 --> 00:15:53.700
and you can adjust those

378
00:15:53.700 --> 00:15:55.666
if you need to meet certain standards.

379
00:15:55.666 --> 00:15:57.366
Tomachie gives you three selections,

380
00:15:57.400 --> 00:15:59.900
We're not giving you the military one at this point,

381
00:15:59.900 --> 00:16:01.766
but the automotive and industrial

382
00:16:01.766 --> 00:16:02.900
will be a little bit more restrictive,

383
00:16:02.900 --> 00:16:05.700
obviously the de-rating is going to be greater.

384
00:16:05.700 --> 00:16:07.966
Let's just select commercial for right now.

385
00:16:08.100 --> 00:16:10.800
Now, when I do the AI analysis

386
00:16:11.233 --> 00:16:13.300
if I've reviewed the modified design

387
00:16:13.300 --> 00:16:16.000
I can use that instead of the the original.

388
00:16:16.000 --> 00:16:19.600
The modified design has the test points in it.

389
00:16:19.833 --> 00:16:22.200
I'll leave that deselected for right now,

390
00:16:22.200 --> 00:16:24.366
because we didn't review the modified design.

391
00:16:24.366 --> 00:16:26.133
We'll do that in a separate video.

392
00:16:26.566 --> 00:16:27.266
and then

393
00:16:27.266 --> 00:16:30.366
we have a choice of how much detail in the analysis:

394
00:16:30.366 --> 00:16:31.266
economy, standard

395
00:16:31.266 --> 00:16:34.200
or premium.  That's also another separate video.

396
00:16:34.200 --> 00:16:36.700
We'll stick with "standard" for right now.

397
00:16:36.800 --> 00:16:39.033
It's a very good trade-off between performance,

398
00:16:39.033 --> 00:16:41.700
the capability and depth of the LLM model

399
00:16:42.166 --> 00:16:45.366
and cost.  Let's select: design-overview,

400
00:16:45.366 --> 00:16:48.500
power-overview, functional-analysis

401
00:16:48.700 --> 00:16:50.366
EMC/ESD analysis,

402
00:16:50.400 --> 00:16:52.366
HSSI and memory analysis.

403
00:16:52.366 --> 00:16:54.966
If HSSI or Memory didn't exist,

404
00:16:55.066 --> 00:16:56.766
the selection would not be present.

405
00:16:56.933 --> 00:16:59.033
With AI, and included free

406
00:16:59.033 --> 00:17:01.733
will be the "certificate of accomplishment".

407
00:17:01.833 --> 00:17:03.366
A permanent record of

408
00:17:03.366 --> 00:17:06.000
the type of design you're capable of creating,

409
00:17:06.100 --> 00:17:07.866
without showing specific secrets.

410
00:17:07.866 --> 00:17:10.466
T=Your current employer

411
00:17:10.466 --> 00:17:12.200
doesn't want you to take their schematic

412
00:17:12.200 --> 00:17:15.433
and bring it with you to the next job interview.

413
00:17:15.433 --> 00:17:16.166
What Tomachie does, is

414
00:17:16.166 --> 00:17:20.366
enable you to prove how good a designer you are,

415
00:17:20.366 --> 00:17:21.833
by using that certificate

416
00:17:21.833 --> 00:17:23.300
which is permanently available on the website.

417
00:17:23.466 --> 00:17:26.300
It characterizes the design

418
00:17:26.400 --> 00:17:29.600
without giving away intellectual property details

419
00:17:29.600 --> 00:17:30.833
of your current employer or client.

420
00:17:30.833 --> 00:17:32.600
Tomachie also generates an EDIF netlist,

421
00:17:32.600 --> 00:17:34.633
much better than your eCAD tool does.

422
00:17:34.633 --> 00:17:36.233
It has all the part properties,

423
00:17:36.233 --> 00:17:38.200
nets, pin names and pin numbersl

424
00:17:38.233 --> 00:17:40.400
a much more capable EDIF generator

425
00:17:40.400 --> 00:17:42.300
than what you'll get out of the eCAD.

426
00:17:42.700 --> 00:17:46.466
If there are Linux/Zephyr capable processors,

427
00:17:46.466 --> 00:17:50.433
then Tomachie generates a "device tree source overlay" file.

428
00:17:50.433 --> 00:17:52.500
And that's a separate video

429
00:17:52.500 --> 00:17:54.933
as well, going into those details.

430
00:17:55.033 --> 00:17:56.466
Once you've selected

431
00:17:56.466 --> 00:17:59.566
all of the areas, that you need to enrich,

432
00:17:59.566 --> 00:18:03.000
then you can purchase coins.

433
00:18:03.366 --> 00:18:06.900
One coin is about US$1, right now.

434
00:18:07.000 --> 00:18:09.133
If you have a coupon from Tomachie,

435
00:18:09.300 --> 00:18:10.966
then you can apply that coupon,

436
00:18:10.966 --> 00:18:13.500
which will reduce the number of coins that you

437
00:18:13.500 --> 00:18:14.733
you need to purchase.

438
00:18:14.966 --> 00:18:17.433
The purchases are done through Stripe,

439
00:18:17.433 --> 00:18:19.866
so none of your credit card information

440
00:18:19.866 --> 00:18:22.500
is being stored on Tomachie website.

441
00:18:22.800 --> 00:18:24.533
It's all being done through Stripe

442
00:18:24.833 --> 00:18:27.600
which is well-known around the world.

443
00:18:27.666 --> 00:18:30.700
Once you purchase, Tomachie will start the analysis.

444
00:18:31.200 --> 00:18:33.600
To save time, I've already generatd the report.

445
00:18:33.600 --> 00:18:38.066
I'm going to go bring us to the analysis page.

446
00:18:38.333 --> 00:18:42.266
Here is the Cricket Node with the AI-based analysis.

447
00:18:42.300 --> 00:18:45.533
A few points are reduced from the prior report.

448
00:18:45.800 --> 00:18:49.033
We can see the cause of those reductions.

449
00:18:49.033 --> 00:18:52.400
There's a number of medium level issues

450
00:18:52.400 --> 00:18:56.000
that need to be resolved.  It's a very good design,

451
00:18:56.200 --> 00:19:00.566
but Tomachie professional-level may be harsh

452
00:19:00.566 --> 00:19:01.400
on "project/DIY" based boards,

453
00:19:01.400 --> 00:19:04.300
that aren't really meant for a production environment.

454
00:19:04.300 --> 00:19:04.566
We can

455
00:19:04.566 --> 00:19:07.566
take a look and see what some of the issues are.

456
00:19:07.666 --> 00:19:09.366
There's a link that brings you directly there.

457
00:19:09.366 --> 00:19:12.200
The power findings link,

458
00:19:12.200 --> 00:19:14.200
will tell us what errors were found.

459
00:19:14.400 --> 00:19:16.533
Let's review the prose description,

460
00:19:16.633 --> 00:19:18.566
see what the text looks like.

461
00:19:18.833 --> 00:19:20.766
The report includes a design overview,

462
00:19:20.766 --> 00:19:22.600
and it will explain about the PCB.

463
00:19:22.600 --> 00:19:25.266
In this case it's not my board,

464
00:19:25.266 --> 00:19:27.466
so this is very useful for me,

465
00:19:27.466 --> 00:19:28.266
because I don't know it well.

466
00:19:28.266 --> 00:19:30.466
You can learn what the board does very quickly

467
00:19:30.466 --> 00:19:32.766
by reading the prose. It's very clear.

468
00:19:32.766 --> 00:19:35.100
It offers the description of the design,

469
00:19:35.100 --> 00:19:36.500
and the temperature ratings of the components.

470
00:19:36.566 --> 00:19:39.033
If we go down now to the power overview

471
00:19:39.033 --> 00:19:41.666
We'll get a more in depth analysis

472
00:19:41.666 --> 00:19:43.400
in the Power Tree overview

473
00:19:43.466 --> 00:19:45.866
which will explain about the board,

474
00:19:46.200 --> 00:19:47.900
the 12V protection that's present.

475
00:19:48.300 --> 00:19:50.233
Explains about the buck converter,

476
00:19:50.233 --> 00:19:50.600
loop

477
00:19:50.600 --> 00:19:53.600
stability that's present with the output capacitance,

478
00:19:54.366 --> 00:19:56.700
Some issues are being discussed,

479
00:19:56.700 --> 00:19:58.833
it's in the prose but it's also in the findings.

480
00:19:58.833 --> 00:20:01.400
Let's take a look at the findings

481
00:20:01.500 --> 00:20:05.166
and one of the findings is that the VDDH pin

482
00:20:05.233 --> 00:20:08.766
is on the far side of a zero-ohm linking resistor

483
00:20:08.966 --> 00:20:11.800
and these diodes D6 and D7.

484
00:20:12.033 --> 00:20:16.200
The datasheet explains that

485
00:20:16.200 --> 00:20:18.466
there should be decoupling,

486
00:20:18.466 --> 00:20:20.600
should be some capacitance there

487
00:20:20.600 --> 00:20:22.166
that's local to the chip.

488
00:20:22.166 --> 00:20:23.933
Let's take a look at the design,

489
00:20:24.000 --> 00:20:25.900
let's just see where that is.

490
00:20:25.900 --> 00:20:29.233
There's two ways of powering this board,

491
00:20:29.233 --> 00:20:30.633
one's through VBUS

492
00:20:30.633 --> 00:20:33.733
and another is through a 12 volt interface

493
00:20:34.000 --> 00:20:36.300
So he's got a diode OR here

494
00:20:36.300 --> 00:20:39.366
and then that 0 ohm that we just discussed

495
00:20:39.366 --> 00:20:40.966
and that goes into VDDH.

496
00:20:41.033 --> 00:20:43.333
You can see there's no decoupling here,

497
00:20:43.466 --> 00:20:45.333
the finding is correct

498
00:20:45.466 --> 00:20:49.233
that having the 4.7 uF capacitor local here

499
00:20:49.233 --> 00:20:53.000
at this point on Y2.  You can see even for a very,

500
00:20:53.000 --> 00:20:55.533
very competent and good designer,

501
00:20:55.833 --> 00:20:59.400
that Tomachie is going to find very subtle issues.

502
00:20:59.866 --> 00:21:02.200
Here there is bulk capacitance,

503
00:21:02.366 --> 00:21:04.200
I guess I didn't show that on the schematic

504
00:21:04.200 --> 00:21:07.533
We can look at the 5 volt rail,

505
00:21:07.666 --> 00:21:09.466
that's not exactly where I wanted to stop

506
00:21:09.466 --> 00:21:12.700
but so we can look at the 5 volt net that's here

507
00:21:12.700 --> 00:21:19.800
so the battery 12 volt comes in through Q6,

508
00:21:19.800 --> 00:21:22.700
and it's protected and goes into the regulator,

509
00:21:22.700 --> 00:21:24.400
and the output of the regulator

510
00:21:24.466 --> 00:21:27.500
does have 150 uF

511
00:21:27.800 --> 00:21:28.500
three times

512
00:21:28.500 --> 00:21:33.700
so this 5 volts is very well regulated,

513
00:21:33.700 --> 00:21:35.766
but the finding is correct

514
00:21:35.766 --> 00:21:39.433
that capacitance is on the other side of the

515
00:21:39.433 --> 00:21:42.266
impedance of the resistor and a diode.

516
00:21:42.266 --> 00:21:46.100
So we would want to put a 4.7 uF

517
00:21:46.100 --> 00:21:48.466
capacitor there to satisfy the Nordic

518
00:21:48.466 --> 00:21:49.966
datasheet. The second finding,

519
00:21:49.966 --> 00:21:51.700
I'm not gonna go through all of these,

520
00:21:51.800 --> 00:21:53.400
but just to give you an idea.

521
00:21:53.433 --> 00:21:55.500
The second one is VBUS,

522
00:21:55.700 --> 00:21:57.766
we can see if that's accurate

523
00:21:58.366 --> 00:21:59.266
as well.

524
00:21:59.266 --> 00:22:01.666
It's coming in on the USB connection,

525
00:22:01.800 --> 00:22:06.366
and there's a test point and the protection diodes

526
00:22:06.433 --> 00:22:10.033
but there's nothing present. a slight oversight

527
00:22:10.033 --> 00:22:12.800
that there's no capacitance available either

528
00:22:12.800 --> 00:22:17.033
on the VBUS line so this would be something that

529
00:22:17.033 --> 00:22:19.900
that would be straightforward to go and fix.

530
00:22:19.900 --> 00:22:21.033
Well thank you very much

531
00:22:21.033 --> 00:22:22.966
I hope you enjoyed learning

532
00:22:22.966 --> 00:22:24.600
some of the basics of Tomachie,

533
00:22:24.900 --> 00:22:27.900
and what it can do there's a lot more to discuss

534
00:22:27.900 --> 00:22:32.100
the de-ratings, output of the device tree source file,

535
00:22:32.433 --> 00:22:34.266
the insertion of the test points

536
00:22:34.566 --> 00:22:36.666
but I think this is all we can do for right now

537
00:22:36.666 --> 00:22:37.966
I appreciate your attention,

538
00:22:37.966 --> 00:22:40.266
I hope you upload your first design to Tomachie

539
00:22:40.266 --> 00:22:42.700
and thank you very much for watching!