Power Control / bias supply (EN, VCTRL) SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) F1 PTC_32V_5A_1206 DCR 14 mΩ Q7 AONR21307 Rds(on) 11 mΩ R37 10R R45 0R U19 3.1 mA +5V Fig. 3 5 V 5 V Net-(D18-A2) 5 V Net-(Q7-D) 5 V Net-(Q7-S1) Net-(U19-VIN) SOURCE J9 5 V out Figure 2 J9 +5V SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 6 loads, at least 1.52 mA 3 loads, at least 1.06 mA L1 8u2 DCR 68 mΩ R29 0R R50 0R R47 → R48 → GND 50 µA R58 → U2_175 532 µA R5 → U2_173 532 µA U3 506 µA U4 506 µA U5 506 µA U6 5 µA J2_2 leaves the board J2_4 leaves the board J6_18 leaves the board +3V3 Fig. 4 3.3 V +5V Fig. 2 5 V 5V_OTG_1 5 V 5V_OTG_2 5 V HDMI_5V 5 V 3.3 V Net-(C52-Pad1) 5 V Net-(U14-EN) U11 load switch U12 load switch U14 load switch SMPS U20 3.3 V out efficiency 89.6 % J8 5V_OTG_1: 500 mA 5V_OTG_2: 500 mA Figure 3 +5V +3V3 SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 12 loads, at least 2.05 mA R10 0R R27 0R R59 0R R6 0R R8 0R R28 → U13_4 165 µA R31 → U16_2 35.1 µA R43 → U19_7 500 µA R44 → U19_6 500 µA R4 → U2_177 16.5 µA R9 → U2_189 current unknown U16 1 µA U3 332 µA U4 332 µA U5 332 µA U6 5 µA U7 draws what it drives J2_1 leaves the board J2_17 leaves the board J5_4 leaves the board +3V3 Fig. 3 3.3 V +BATT 3.3 V 3V3_LAN1 Fig. 5 3.3 V 3.3 V Net-(C1-Pad1) 3.3 V Net-(C2-Pad1) 3.3 V Net-(C3-Pad1) 3.3 V Net-(U13-VIN) SD_PWR 3.3 V U13 load switch U8 load switch U2 Net-(C1-Pad1): 303 mA Net-(C2-Pad1): draws what it drives Net-(C3-Pad1): draws what it drives +BATT: 2.12 A Figure 4 +3V3 1 of 19 loads without a current +3V3 3V3_LAN1 SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 4 loads, 2.33 mA 4 loads, current unknown FB2 120R DCR 50 mΩ R12 → U9_12 165 µA R16 → U9_11 2 mA R18 → U9_41 165 µA R36 draws what it drives R55 draws what it drives R56 draws what it drives R57 draws what it drives U10 1 µA MAKES A SUPPLY U9 3V3_LAN1: 96 mA VDD33A_LAN1: 177 mA 3V3_LAN1 Fig. 4 3.3 V VDD18CORE_LAN1 1.8 V VDD33A_LAN1 3.3 V Figure 5 3V3_LAN1 SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 5 loads, at least 117 µA R35 → GND 117 µA J7_A4 leaves the board J7_A9 leaves the board J7_B4 leaves the board J7_B9 leaves the board USB_BOOT_VBUS 5 V SOURCE J1 5 V out Figure 6 J1 SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) C40 || R26 1n0_2kV || 1M C44 || R30 1n0_2kV || 1M C56 || R54 1n0_2kV || 1M Earth Net-(J6-CKS) Net-(J7-SHIELD) GND GND GND Figure 7 Earth, Net-(J6-CKS), Net-(J7-SHIELD) SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) TERMINAL J3 J3 external load voltage and current not stated K1 IM03GR RELAY1_COM RELAY1_NO Figure 8 J3 1 of 1 loads without a current
Figure 1: Power tree overview
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) F1 PTC_32V_5A_1206 DCR 14 mΩ Q7 AONR21307 Rds(on) 11 mΩ R37 10R R45 0R U19 3.1 mA +5V Fig. 3 5 V 5 V Net-(D18-A2) 5 V Net-(Q7-D) 5 V Net-(Q7-S1) Net-(U19-VIN) SOURCE J9 5 V out
Figure 2: power entering at J9
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 6 loads, at least 1.52 mA 3 loads, at least 1.06 mA L1 8u2 DCR 68 mΩ R29 0R R50 0R R47 → R48 → GND 50 µA R58 → U2_175 532 µA R5 → U2_173 532 µA U3 506 µA U4 506 µA U5 506 µA U6 5 µA J2_2 leaves the board J2_4 leaves the board J6_18 leaves the board +3V3 Fig. 4 3.3 V +5V Fig. 2 5 V 5V_OTG_1 5 V 5V_OTG_2 5 V HDMI_5V 5 V 3.3 V Net-(C52-Pad1) 5 V Net-(U14-EN) U11 load switch U12 load switch U14 load switch SMPS U20 3.3 V out efficiency 89.6 % J8 5V_OTG_1: 500 mA 5V_OTG_2: 500 mA
Figure 3: +5V rail
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 12 loads, at least 2.05 mA R10 0R R27 0R R59 0R R6 0R R8 0R R28 → U13_4 165 µA R31 → U16_2 35.1 µA R43 → U19_7 500 µA R44 → U19_6 500 µA R4 → U2_177 16.5 µA R9 → U2_189 current unknown U16 1 µA U3 332 µA U4 332 µA U5 332 µA U6 5 µA U7 draws what it drives J2_1 leaves the board J2_17 leaves the board J5_4 leaves the board +3V3 Fig. 3 3.3 V +BATT 3.3 V 3V3_LAN1 Fig. 5 3.3 V 3.3 V Net-(C1-Pad1) 3.3 V Net-(C2-Pad1) 3.3 V Net-(C3-Pad1) 3.3 V Net-(U13-VIN) SD_PWR 3.3 V U13 load switch U8 load switch U2 Net-(C1-Pad1): 303 mA Net-(C2-Pad1): draws what it drives Net-(C3-Pad1): draws what it drives +BATT: 2.12 A
Figure 4: +3V3 rail
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 4 loads, 2.33 mA 4 loads, current unknown FB2 120R DCR 50 mΩ R12 → U9_12 165 µA R16 → U9_11 2 mA R18 → U9_41 165 µA R36 draws what it drives R55 draws what it drives R56 draws what it drives R57 draws what it drives U10 1 µA MAKES A SUPPLY U9 3V3_LAN1: 96 mA VDD33A_LAN1: 177 mA 3V3_LAN1 Fig. 4 3.3 V VDD18CORE_LAN1 1.8 V VDD33A_LAN1 3.3 V
Figure 5: 3V3_LAN1 rail
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 5 loads, at least 117 µA R35 → GND 117 µA J7_A4 leaves the board J7_A9 leaves the board J7_B4 leaves the board J7_B9 leaves the board USB_BOOT_VBUS 5 V SOURCE J1 5 V out
Figure 6: power entering at J1
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) C40 || R26 1n0_2kV || 1M C44 || R30 1n0_2kV || 1M C56 || R54 1n0_2kV || 1M Earth Net-(J6-CKS) Net-(J7-SHIELD) GND GND GND
Figure 7: Chassis and shield connections
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) TERMINAL J3 J3 external load voltage and current not stated K1 IM03GR RELAY1_COM RELAY1_NO
Figure 8: power carried through K1
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