MB2059

1 · Executive summary

Rails with failures come first, then warnings, then by nominal voltage. Grey “no limit” and “not analysed” cells were not checked against anything, so they are not passes. Drop is measured from the setpoint and includes the return path.

Issues to resolve

• WARN
  Design · U7: appears in multiple schdocs with PDN_ROLE

  Only the first occurrence is used
• WARN
  Design · U8: appears in multiple schdocs with PDN_ROLE

  Only the first occurrence is used
• WARN
  Design · REGULATOR on U23#1: Vin=4.5468 V was inferred 1 SERIES hop(s) upstream of PDN1_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN1_GAIN explicitly
• WARN
  Design · SERIES on R89#1: auto-inferred PDN1_P_NET='EXT_EN5', PDN1_N_NET='EXT_EN1' from 2-pin connectivity
• WARN
  Design · REGULATOR on U9#5: Vin=4.5468 V was inferred 1 SERIES hop(s) upstream of PDN5_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN5_GAIN explicitly
• WARN
  Design · REGULATOR on U9#6: Vin=4.5468 V was inferred 1 SERIES hop(s) upstream of PDN6_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN6_GAIN explicitly
• WARN
  Design · REGULATOR on U9#7: Vin=4.5468 V was inferred 1 SERIES hop(s) upstream of PDN7_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN7_GAIN explicitly
• WARN
  Design · SERIES on R39#1: auto-inferred PDN1_P_NET='NetR40_2', PDN1_N_NET='3V3' from 2-pin connectivity
• WARN
  Design · SERIES on R31#1: auto-inferred PDN1_P_NET='GND', PDN1_N_NET='NetCN11_12' from 2-pin connectivity
• WARN
  Design · SERIES on R3#1: auto-inferred PDN1_P_NET='GND', PDN1_N_NET='LCD_INT' from 2-pin connectivity
• WARN
  Design · SERIES on R14#1: auto-inferred PDN1_P_NET='VDD_SDCARD', PDN1_N_NET='3V3' from 2-pin connectivity
• WARN
  Design · SERIES on R105#1: auto-inferred PDN1_P_NET='BUTTON.TAMP', PDN1_N_NET='VBAT' from 2-pin connectivity
• WARN
  Design · 0R link on R90 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging EXT_EN1 / NetR89_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R90 (Power_PMIC.SchDoc): auto-bridged EXT_EN1 ↔ NetR89_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R91 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VDDIO / NetD2_1. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R91 (Power_MPU.SchDoc): auto-bridged VDDIO ↔ NetD2_1 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R102 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VREF+ / VDDA1V8. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R102 (Power_MPU.SchDoc): auto-bridged VREF+ ↔ VDDA1V8 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R103 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VDDA1V8 / NetC130_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R103 (Power_MPU.SchDoc): auto-bridged VDDA1V8 ↔ NetC130_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R29 (MP215_11x11.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetC35_1 / OSC32_OUT. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R29 (MP215_11x11.SchDoc): auto-bridged NetC35_1 ↔ OSC32_OUT as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R18 (SDcard.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging SD.uSD_DETECT / NetCN7_10. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R18 (SDcard.SchDoc): auto-bridged SD.uSD_DETECT ↔ NetCN7_10 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R30 (MP215_11x11.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging HSE_OUT / NetC48_1. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R30 (MP215_11x11.SchDoc): auto-bridged HSE_OUT ↔ NetC48_1 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R101 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetR101_2 / NRST. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R101 (Power_PMIC.SchDoc): auto-bridged NetR101_2 ↔ NRST as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R74 (LCD_connector.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetR74_2 / LCD_BL. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R74 (LCD_connector.SchDoc): auto-bridged NetR74_2 ↔ LCD_BL as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R68 (LCD_connector.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging 5V_VIN / VL. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R68 (LCD_connector.SchDoc): auto-bridged 5V_VIN ↔ VL as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R15 (SDcard.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VDD_SDCARD / VDD_FLASH. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R15 (SDcard.SchDoc): auto-bridged VDD_SDCARD ↔ VDD_FLASH as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R71 (LCD_connector.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging LCD_BL_A / VH. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R71 (LCD_connector.SchDoc): auto-bridged LCD_BL_A ↔ VH as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R42 (Ethernet_RMII.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging ETH1.MDINT / NetR41_1. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R42 (Ethernet_RMII.SchDoc): auto-bridged ETH1.MDINT ↔ NetR41_1 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R40 (Ethernet_RMII.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging ETH1.NRST / NetR40_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R40 (Ethernet_RMII.SchDoc): auto-bridged ETH1.NRST ↔ NetR40_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R98 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetC128_2 / VDD3V3_USB. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R98 (Power_MPU.SchDoc): auto-bridged NetC128_2 ↔ VDD3V3_USB as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R26 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging PWR_ON / NetR26_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R26 (Power_PMIC.SchDoc): auto-bridged PWR_ON ↔ NetR26_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R24 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging PWR_CPU_ON / NetR24_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R24 (Power_PMIC.SchDoc): auto-bridged PWR_CPU_ON ↔ NetR24_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R22 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NRSTC1MS / NetR22_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R22 (Power_PMIC.SchDoc): auto-bridged NRSTC1MS ↔ NetR22_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · pdn.json: Rail VBUS: CN10's cable allowance 250 mOhm at the rail's 812.8 mA: the source is set 203.2 mV below its minimum
• WARN
  Design · pdn.json: Rail VBUS: worst case, source CN10 at its minimum 4.5468 V (nominal 5 V)
• WARN
  Design · pdn.json: Rail VBAT: no source traced in the schematic
• WARN
  Design · pdn.json: Rail 3V3: worst case, regulator U23 at the low end of its output band 3.153 V (set 3.3 V)
• WARN
  Design · pdn.json: U23 (3V3): regulated at its feedback point, R88_2 on 3V3
• WARN
  Design · pdn.json: Rail VDD3V3_USB: worst case, regulator U9 at the low end of its output band 3.23 V (set 3.3 V)
• WARN
  Design · pdn.json: Rail VDD1_DDR: worst case, regulator U9 at the low end of its output band 1.728 V (set 1.8 V)
• WARN
  Design · pdn.json: Rail VDDA1V8: worst case, regulator U9 at the low end of its output band 1.728 V (set 1.8 V)
• WARN
  Design · pdn.json: Rail VDDA1V8_AON: worst case, regulator U9 at the low end of its output band 1.728 V (set 1.8 V)
• WARN
  Design · pdn.json: Rail VDD2_DDR: worst case, regulator U9 at the low end of its output band 1.084 V (set 1.1 V)
• WARN
  Design · pdn.json: U9 (VDD2_DDR): regulated at its feedback point, LNK3_2 on VDD2_DDR
• WARN
  Design · pdn.json: U18 (LCD_BL_A): no stated voltage; no REGULATOR, so LCD_BL_A is not driven
• WARN
  Design · pdn.json: Rail VDDCORE: worst case, regulator U9 at the low end of its output band 0.8077 V (set 0.82 V)
• WARN
  Design · pdn.json: U9 (VDDCORE): regulated at its feedback point, LNK1_2 on VDDCORE
• WARN
  Design · pdn.json: Rail VDDCPU: worst case, regulator U9 at the low end of its output band 0.788 V (set 0.8 V)
• WARN
  Design · pdn.json: U9 (VDDCPU): regulated at its feedback point, LNK2_2 on VDDCPU
• WARN
  Design · pdn.json: Rail VDDIO: worst case, regulator U9 at the low end of its output band 3.23 V (set 3.3 V)
• WARN
  Design · pdn.json: Rail VDD_FLASH: worst case, regulator U9 at the low end of its output band 3.23 V (set 3.3 V)
• WARN
  Design · pdn.json: U14: load switch, a SERIES of 0.05 Ohm from VBUS to 5V_VIN (not a regulator)
• WARN
  Design · pdn.json: U14: load switch, a SERIES of 0.05 Ohm from VBUS to 5V_VIN (not a regulator)
• WARN
  Design · pdn.json: L6: inside U23's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: L6: DC resistance not in the file; bridged at 1 mOhm
• WARN
  Design · pdn.json: L3: inside U9's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: L2: inside U9's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: L1: inside U9's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: R46 on 5V_VIN: its current is counted in U14's figure; no SINK
• WARN
  Design · pdn.json: U15 on 3V3: 2 die supplies, none named as the current's; drawn at all its pins
• WARN
  Design · pdn.json: R47 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: R49 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: R50 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: R53 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: U7 on VDDA1V8: 6 die supplies, none named as the current's; drawn at all its pins
• WARN
  Design · pdn.json: U7 [VDDIO2] on VDDA1V8: I/O current 2.7 mA ESTIMATED, not a data-sheet figure (5 of 6 VDDIO2 bank pins connected (not connected: U7_C15): U7_A14 M2…

  pdn.json: U7 [VDDIO2] on VDDA1V8: I/O current 2.7 mA ESTIMATED, not a data-sheet figure (5 of 6 VDDIO2 bank pins connected (not connected: U7_C15): U7_A14 M2.SDMMC2_D0: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_A15 M2.SDMMC2_D3: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_B14 M2.SDMMC2_D1: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_D14 M2.SDMMC2_CK: SDMMC clock 50 MHz, 20 pF x 1.8 V x f = 1.8 mA; U7_E11 M2.SDMMC2_CMD: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U7 on VDDA1V8_AON: its current is VDDA18AON's, drawn at those pins; PDR_ON draw none stated (no SINK)
• WARN
  Design · pdn.json: U7 on VREF+: current not known; no SINK, so VREF+'s drop is a lower bound
• WARN
  Design · pdn.json: U7 [VDDQDDR] on VDD2_DDR: I/O current 58.4 mA ESTIMATED, not a data-sheet figure (32 of 52 VDDQDDR bank pins connected (not connected: U7_F18, U7_F…

  pdn.json: U7 [VDDQDDR] on VDD2_DDR: I/O current 58.4 mA ESTIMATED, not a data-sheet figure (32 of 52 VDDQDDR bank pins connected (not connected: U7_F18, U7_F21, U7_G19, U7_G21, U7_H18, U7_H20, U7_J17, U7_K18, U7_K19, U7_K20, U7_K21, U7_L17, U7_L19, U7_M19, U7_M20, U7_N19, U7_P18, U7_P19, U7_P20, U7_P21): 32 LPDDR4 LVSTL x 7.3 mA x 25 % - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U8 on VDD2_DDR: 3 die supplies, none named as the current's; drawn at all its pins
• WARN
  Design · pdn.json: Rail VBAT: nothing in the file drives it; its loads are left out: U7
• WARN
  Design · pdn.json: U7 on VDDCORE: its current is VDDCORE's, drawn at those pins; VDDCSI draw none stated (no SINK)
• WARN
  Design · pdn.json: U7: draws what it drives (figure is with all peripherals disabled; VDD/VDDIO1/VDDIO3 I/O current follows pin activity and loads); its own current 2…

  pdn.json: U7: draws what it drives (figure is with all peripherals disabled; VDD/VDDIO1/VDDIO3 I/O current follows pin activity and loads); its own current 2900 uA is used, so the rail's drop is a lower bound
• WARN
  Design · pdn.json: U7 on VDDIO: its current is VDD's, drawn at those pins
• WARN
  Design · pdn.json: U7 [VDDIO3] on VDDIO: I/O current 0.91344 mA ESTIMATED, not a data-sheet figure (11 of 12 VDDIO3 bank pins connected (not connected: U7_E15): U7_A6…

  pdn.json: U7 [VDDIO3] on VDDIO: I/O current 0.91344 mA ESTIMATED, not a data-sheet figure (11 of 12 VDDIO3 bank pins connected (not connected: U7_E15): U7_A6 SD.uSD_DETECT: static line: 0 = 0 mA; U7_B4 M2.SAI1_SCKA: SAI clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_B6 M2.SAI1_SDB: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_B7 M2.SAI1_FSA: SAI static line: 0 = 0 mA; U7_B11 BT_HOST_WAKE: static line: 0 = 0 mA; U7_C4 GPIO.SPI1_NSS: SPI static line: 0 = 0 mA; U7_C7 GPIO.SPI1_MISO: SPI input: 0 = 0 mA; U7_C9 M2.SAI1_SDA: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_C10 CAM_RESET: static line: 0 = 0 mA; U7_D4 GPIO.SPI1_SCK: SPI clock 10 MHz, 20 pF x 3.3 V x f = 0.66 mA; U7_D8 CAM_ENABLE: static line: 0 = 0 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U7 [VDD] on VDDIO: I/O current 32.5774 mA ESTIMATED, not a data-sheet figure (102 of 110 VDD bank pins connected (not connected: U7_A10, U7_AA10, U…

  pdn.json: U7 [VDD] on VDDIO: I/O current 32.5774 mA ESTIMATED, not a data-sheet figure (102 of 110 VDD bank pins connected (not connected: U7_A10, U7_AA10, U7_D6, U7_K2, U7_V6, U7_V14, U7_W12, U7_Y18): U7_A7 I2C2.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_A18 GPIO.SDMMC3_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_A19 GPIO.SDMMC3_D1: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_AA6 LED2: resistive load, on all the time (upper bound): R57 100k to GND: V/R 0.033 mA = 0.033 mA; U7_AA7 LCD_BL: resistive load, on all the time (upper bound): R75 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_AA11 ETH1.MDIO: MDIO data 2.5 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0206 mA; U7_AA14 LED3: resistive load, on all the time (upper bound): R56 100k to GND: V/R 0.033 mA = 0.033 mA; U7_AA15 UART4_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_AA18 LED1: static line: 0 = 0 mA; U7_B8 USART1_RTS: UART static line: 0 = 0 mA; U7_B10 MDF.SDI3: MDF input: 0 = 0 mA; U7_B16 GPIO.SDMMC3_D0: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_B18 GPIO.SDMMC3_CMD: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C5 BT_REG_ON: static line: 0 = 0 mA; U7_C6 USART1_CTS: UART static line: 0 = 0 mA; U7_C8 USART1_RX: UART input: 0 = 0 mA; U7_C16 GPIO.SDMMC3_CK: SDMMC clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_C17 GPIO.SDMMC3_D3: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D3 LCD_VSYNC: LTDC static line: 0 = 0 mA; U7_E3 LCD_HSYNC: LTDC static line: 0 = 0 mA; U7_E4 LCD_DE: LTDC static line: 0 = 0 mA; U7_E5 GPIO.SPI1_MOSI: SPI data 10 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.165 mA; U7_E7 I2C2.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_E9 WL_REG_ON: static line: 0 = 0 mA; U7_F1 LCD_B4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F2 LCD_B5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F3 LCD_B6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F4 LCD_B3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_G1 USART1_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_G2 LCD_B2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_G3 BUTTON.TAMP: static line: 0 = 0 mA; U7_G5 LCD_B7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H2 LCD_G6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H3 LCD_G5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H4 LCD_G4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_J3 LCD_G3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_J5 LCD_G7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_K1 GPIO.SAI2_SDB: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_K3 LCD_G2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_K4 I2C3.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_K6 LED4: resistive load, on all the time (upper bound): R55 100k to GND: V/R 0.033 mA = 0.033 mA; U7_L3 LCD_R7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_L5 I2C3.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_M2 LCD_R6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_M3 LCD_INT: LTDC input: 0 = 0 mA; U7_M4 LCD_R5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_N3 LCD_R4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_N5 LCD_R3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_P1 GPIO.USART6_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_P2 GPIO.USART6_CTS: UART static line: 0 = 0 mA; U7_P3 LCD_R2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_P4 BUTTON.USER2: static line: 0 = 0 mA; U7_P6 LCD_DISP: resistive load, on all the time (upper bound): R1 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_R5 BUTTON.USER1: static line: 0 = 0 mA; U7_T2 NRSTC1MS: static line: 0 = 0 mA; U7_T3 I3C1.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_T4 LPO_32: LPO clock 32.77 kHz, 20 pF x 3.3 V x f = 0.00216 mA; U7_T8 I3C2.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_T10 GPIO.GPIO7: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_T12 GPIO.USART6_RTS: UART static line: 0 = 0 mA; U7_T14 ETH1.CLK: RMII clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_T16 GPIO.SAI2_SCKB: SAI clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_U3 LCD_CLK: LTDC clock 33.3 MHz, 20 pF x 3.3 V x f = 2.2 mA; U7_U5 LCD_RST: resistive load, on all the time (upper bound): R2 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_U7 GPIO.SAI2_SDA: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_U9 GPIO.TIM8_CH4: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_U11 ETH1.TXD0: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_U13 MDF.CCK0: MDF clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_U15 GPIO.USART6_RX: UART input: 0 = 0 mA; U7_V1 JTCK_SWCLK: static line: 0 = 0 mA; U7_V2 JTMS_SWDIO: static line: 0 = 0 mA; U7_V3 NJTRST: static line: 0 = 0 mA; U7_V4 PWR_CPU_ON: static line: 0 = 0 mA; U7_V10 ETH1.TXD1: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_V12 ETH1.TX_EN: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_V16 USART2_RX: UART input: 0 = 0 mA; U7_W1 JTDO_SWDO: static line: 0 = 0 mA; U7_W2 JTDI: static line: 0 = 0 mA; U7_W3 PWR_LP: static line: 0 = 0 mA; U7_W4 PWR_ON: static line: 0 = 0 mA; U7_W7 MCO1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W10 GPIO.TIM13_CH1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W11 ETH1.RXD0: RMII input: 0 = 0 mA; U7_W13 GPIO.TIM11_CH1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W14 ETH1.NRST: resistive load, on all the time (upper bound): R38 10k to GND: V/R 0.33 mA = 0.33 mA; U7_W15 ETH1.CRS_DV: RMII input: 0 = 0 mA; U7_W16 GPIO.SAI2_FSB: SAI static line: 0 = 0 mA; U7_W17 I3C1.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_Y6 PA0_INT: static line: 0 = 0 mA; U7_Y7 I3C2.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_Y10 GPIO.TIM8_CH2: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_Y11 ETH1.MDC: MDIO clock 2.5 MHz, 20 pF x 3.3 V x f = 0.165 mA; U7_Y12 ETH1.RXD1: RMII input: 0 = 0 mA; U7_Y14 ETH1.MDINT: RMII input: 0 = 0 mA; U7_Y15 UART4_RX: UART input: 0 = 0 mA; U7_Y16 USART2_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; 6 input-only x 0 - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U7 [VDDIO1] on VDDIO: I/O current 5.775 mA ESTIMATED, not a data-sheet figure (7 of 10 VDDIO1 bank pins connected (not connected: U7_B15, U7_C14, U…

  pdn.json: U7 [VDDIO1] on VDDIO: I/O current 5.775 mA ESTIMATED, not a data-sheet figure (7 of 10 VDDIO1 bank pins connected (not connected: U7_B15, U7_C14, U7_E13): U7_A11 SD.SDMMC1_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_B12 SD.SDMMC1_CMD: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C11 SD.SDMMC1_D3: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C12 SD.SDMMC1_CK: SDMMC clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_C13 M2.SDMMC2_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D10 SD.SDMMC1_D1: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D12 SD.SDMMC1_D0: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: Not fitted, solved as open (5e+08 Ohm): R14, R39, R31, R105, R89, R3
• WARN
  Design · pdn.json: Not fitted, left out: C46, U19
• WARN
  Design · pdn.json: Temperature: the board's maximum ambient is 40 °C; the board temperature is set to it
• WARN
  Design · pdn.json: Via plating from the file (ipc6012_class2_min): through 20 um, blind 20 um, buried 13 um, microvia 12 um; set on the Settings tab
• WARN
  NetC130_2 · U7#3: only 16 mV above PDN_MIN_V 1.710 V

  Margin is under 1 % of the 1.728 V nominal. Drop 2 mV from the 1.728 V setpoint (0.538 mV of it in the return path). Lowest pin U7-F12 on Top Layer.
• WARN
  NetC130_2 · U7#4: only 16 mV above PDN_MIN_V 1.710 V

  Margin is under 1 % of the 1.728 V nominal. Drop 2 mV from the 1.728 V setpoint (0.538 mV of it in the return path). Lowest pin U7-F12 on Top Layer.
• WARN
  VDDA1V8_AON · U7#5: only 17.1 mV above PDN_MIN_V 1.710 V

  Margin is under 1 % of the 1.728 V nominal. Drop 0.872 mV from the 1.728 V setpoint (0.538 mV of it in the return path). Lowest pin U7-L1 on Top Layer.

2 · Power tree

3 · NetC130_2

WARN 1 uncheckedU9#3 (LDO, from VBUS) · nets NetC130_2, VDDA1V8 · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.725 V

U21#2 · min 0.900 V

Worst drop

2.8 mV

0.16 % of 1.728 V

Load

41 mA

11 loads

Max via current

41 mA

17 vias

Copper loss

0.0779 mW

Bottom Layer 0.0447 mW · Top Layer 0.0249 mW

Peak |J|

5.92 A/mm²

current density

3.1Findings

• WARN
  U7#3: only 16 mV above PDN_MIN_V 1.710 V

  Margin is under 1 % of the 1.728 V nominal. Drop 2 mV from the 1.728 V setpoint (0.538 mV of it in the return path). Lowest pin U7-F12 on Top Layer.
• WARN
  U7#4: only 16 mV above PDN_MIN_V 1.710 V

  Margin is under 1 % of the 1.728 V nominal. Drop 2 mV from the 1.728 V setpoint (0.538 mV of it in the return path). Lowest pin U7-F12 on Top Layer.
• UNCHECKED
  No PDN_MIN_V on 6 of 11 sinks

  The drop at R9#1, R82#1, R80#1, R16#1 and 2 more was calculated but not compared against a limit.

3.2Power path

3.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#2	VDDA1V8	1	0.415 mA	1.727 V	1.37 mV	0.538 mV	1.620 V	+107 mV	PASS
U7#3	VDDA1V8	6	3.4 mA	1.726 V	2 mV	0.538 mV	1.710 V	+16 mV	WARN
U7#4	VDDA1V8	1	2.7 mA	1.726 V	2 mV	0.538 mV	1.710 V	+16 mV	WARN
U22#2	VDDA1V8	1	17.1 mA	1.726 V	2.45 mV	0.406 mV	0.900 V	+826 mV	PASS
U21#2	VDDA1V8	1	17.1 mA	1.725 V	2.8 mV	0.493 mV	0.900 V	+825 mV	PASS
R9#1	VDDA1V8	1	0.0383 mA	1.725 V	2.7 mV	0.493 mV	—	no limit	UNCHECKED
R82#1	VDDA1V8	1	0.0383 mA	1.726 V	2.26 mV	0.538 mV	—	no limit	UNCHECKED
R80#1	VDDA1V8	1	0.0383 mA	1.726 V	2.26 mV	0.538 mV	—	no limit	UNCHECKED
R16#1	VDDA1V8	1	0.0383 mA	1.726 V	1.98 mV	0.538 mV	—	no limit	UNCHECKED
R79#1	VDDA1V8	1	0.0383 mA	1.726 V	2.26 mV	0.538 mV	—	no limit	UNCHECKED
R19#1	VDDA1V8	1	0.0383 mA	1.726 V	1.98 mV	0.538 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.728 V setpoint. Every pin is listed in the appendix.

3.4Heatmaps

3.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDDA1V8	1.1 oz	2.21 mV	5.92 A/mm²	(30.42, 28.67)	0.0249 mW	32%
Signal Layer 1	VDDA1V8	1 oz	1.6 mV	1.18e-08 A/mm²	(57.73, 29.68)	3.62e-21 mW	0%
Signal Layer 2	VDDA1V8	1 oz	1.54 mV	1.17 A/mm²	(32.62, 48.19)	0.00824 mW	11%
Bottom Layer	VDDA1V8	1.1 oz	1.64 mV	2.78 A/mm²	(76.69, 51.37)	0.0447 mW	57%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

3.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(34.10, 29.50)	Top Layer → Bottom Layer	0.30 mm · —	41 mA	0.0658 mV	0.00267 mW	PASS
(61.55, 46.62)	Top Layer → Bottom Layer	0.30 mm · —	34.4 mA	0.00364 mV	0.000129 mW	PASS
(32.40, 48.05)	Top Layer → Bottom Layer	0.30 mm · —	33.5 mA	0.00365 mV	0.000122 mW	PASS
(63.75, 26.00)	Top Layer → Bottom Layer	0.30 mm · —	7.15 mA	0.00078 mV	5.58e-06 mW	PASS
(62.16, 31.95)	Top Layer → Bottom Layer	0.20 mm · —	3.63 mA	0.00917 mV	3.32e-05 mW	PASS

Showing 5 of 17 vias, highest current first. Limit 1 A per via.

3.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#3	LDO	VBUS → NetC130_2	1.728 V	4.487 V	41 mA	41 mA	113 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

3.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

3.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

4 · VDDA1V8_AON

WARNU9#4 (LDO, from VBUS) · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.727 V

U7#5 · min 1.710 V

Worst drop

0.872 mV

0.05 % of 1.728 V

Load

5.3 mA

1 load

Max via current

5.3 mA

3 vias

Copper loss

0.00166 mW

Signal Layer 2 0.000844 mW · Top Layer 0.000817 mW

Peak |J|

2.23 A/mm²

current density

4.1Findings

• WARN
  U7#5: only 17.1 mV above PDN_MIN_V 1.710 V

  Margin is under 1 % of the 1.728 V nominal. Drop 0.872 mV from the 1.728 V setpoint (0.538 mV of it in the return path). Lowest pin U7-L1 on Top Layer.

4.2Power path

4.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#5	VDDA1V8_AON	1	5.3 mA	1.727 V	0.872 mV	0.538 mV	1.710 V	+17.1 mV	WARN

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.728 V setpoint. Every pin is listed in the appendix.

4.4Heatmaps

4.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDDA1V8_AON	1.1 oz	0.334 mV	2.23 A/mm²	(53.93, 35.60)	0.000817 mW	49%
Signal Layer 1	VDDA1V8_AON	1 oz	0.178 mV	1.14e-08 A/mm²	(51.83, 35.60)	8.46e-22 mW	0%
Signal Layer 2	VDDA1V8_AON	1 oz	0.159 mV	0.576 A/mm²	(52.05, 34.82)	0.000844 mW	51%
Bottom Layer	VDDA1V8_AON	1.1 oz	0.159 mV	1.25e-08 A/mm²	(53.43, 33.92)	1.25e-21 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

4.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(36.15, 31.05)	Top Layer → Bottom Layer	0.30 mm · —	5.3 mA	0.00803 mV	4.26e-05 mW	PASS
(51.88, 35.41)	Top Layer → Bottom Layer	0.20 mm · —	5.3 mA	0.0125 mV	6.62e-05 mW	PASS
(53.25, 33.89)	Top Layer → Bottom Layer	0.20 mm · —	2.85e-07 mA	5.04e−10 mV	1.02e-19 mW	PASS

Showing 3 of 3 vias, highest current first. Limit 1 A per via.

4.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#4	LDO	VBUS → VDDA1V8_AON	1.728 V	4.487 V	5.3 mA	5.3 mA	14.6 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

4.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

4.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

5 · VBUS

PASS 1 uncheckedCN10#1 (source) · nets 5V_VIN, VBUS · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

4.487 V

U9#1 → VDD3V3_USB

Worst drop

60.3 mV

1.3 % of 4.547 V

Load

0.865 A

12 loads

Max via current

0.372 A

23 vias

Copper loss

13.9 mW

Signal Layer 2 8.74 mW · Top Layer 5.16 mW

Peak |J|

92.4 A/mm²

current density

5.1Findings

• UNCHECKED
  No PDN_MIN_V on any sink

  The drop at U12#1, U14#2 was calculated but not compared against a limit.

5.2Power path

5.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U23#1 → NetL6_1 (regulator input)	5V_VIN	2	0.213 A	4.487 V	59.3 mV	0.099 mV	—	no limit	UNCHECKED
U9#1 → VDD3V3_USB (regulator input)	5V_VIN	7	0.001 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#2 → VDD1_DDR (regulator input)	5V_VIN	7	23 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#3 → NetC130_2 (regulator input)	5V_VIN	7	41 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#4 → VDDA1V8_AON (regulator input)	5V_VIN	7	5.3 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#5 → NetL3_1 (regulator input)	5V_VIN	7	0.197 A	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#6 → NetL2_1 (regulator input)	5V_VIN	7	90 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#7 → NetL1_1 (regulator input)	5V_VIN	7	42.8 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#8 → VDDIO (regulator input)	5V_VIN	7	52 mA	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U9#9 → VDD_FLASH (regulator input)	5V_VIN	7	0.201 A	4.487 V	60.3 mV	−0.0685 mV	—	no limit	UNCHECKED
U12#1	VBUS	1	0.0002 mA	4.544 V	2.74 mV	0.0739 mV	—	no limit	UNCHECKED
U14#2	VBUS	2	0.37 mA	4.542 V	5.27 mV	0.0628 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 4.547 V setpoint. Every pin is listed in the appendix.

5.4Heatmaps

5.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	5V_VIN, VBUS	1.1 oz	60.3 mV	92.4 A/mm²	(94.73, 23.23)	5.16 mW	37%
Signal Layer 1	5V_VIN, VBUS	1 oz	60 mV	1.04e-08 A/mm²	(96.81, 26.44)	1.75e-20 mW	0%
Signal Layer 2	5V_VIN, VBUS	1 oz	59.8 mV	13.1 A/mm²	(71.44, 67.28)	8.74 mW	63%
Bottom Layer	5V_VIN, VBUS	1.1 oz	59.8 mV	8.79 A/mm²	(11.95, 40.93)	0.0297 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

5.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(98.00, 19.58)	Top Layer → Bottom Layer	0.30 mm · —	0.372 A	0.563 mV	0.209 mW	PASS
(99.77, 19.58)	Top Layer → Bottom Layer	0.30 mm · —	0.265 A	0.401 mV	0.106 mW	PASS
(101.25, 19.58)	Top Layer → Bottom Layer	0.30 mm · —	0.228 A	0.346 mV	0.0789 mW	PASS
(95.31, 24.09)	Top Layer → Bottom Layer	0.30 mm · —	0.133 A	0.202 mV	0.027 mW	PASS
(10.05, 46.25)	Top Layer → Bottom Layer	0.30 mm · —	0.107 A	0.0117 mV	0.00125 mW	PASS

Showing 5 of 23 vias, highest current first. Limit 1 A per via.

5.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
U14#1	Series part	VBUS → 5V_VIN	50 mΩ	0.864 A	43.2 mV	37.4 mW

5.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

5.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

6 · VDD3V3_USB

PASSU9#1 (LDO, from VBUS) · nets NetC128_2, VDD3V3_USB · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.229 V

U7#1 · min 3.070 V

Worst drop

0.538 mV

0.017 % of 3.230 V

Load

0.001 mA

1 load

Max via current

0.00101 mA

3 vias

Copper loss

7.43e-11 mW

Signal Layer 2 3.93e-11 mW · Top Layer 2.71e-11 mW

Peak |J|

0.000433 A/mm²

current density

6.1Findings

No issues on this rail.

6.2Power path

6.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#1	NetC128_2	1	0.001 mA	3.229 V	0.538 mV	0.538 mV	3.070 V	+159 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.230 V setpoint. Every pin is listed in the appendix.

6.4Heatmaps

6.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetC128_2	1.1 oz	7.85e−05 mV	0.000433 A/mm²	(63.12, 31.39)	2.71e-11 mW	36%
Signal Layer 1	NetC128_2	1 oz	5.13e−05 mV	1.75e-08 A/mm²	(63.85, 29.44)	2.26e-21 mW	0%
Signal Layer 2	NetC128_2	1 oz	4.76e−05 mV	0.000108 A/mm²	(55.55, 25.86)	3.93e-11 mW	53%
Bottom Layer	NetC128_2	1.1 oz	4.75e−05 mV	0.000379 A/mm²	(64.76, 27.41)	7.93e-12 mW	11%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

6.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(36.05, 29.02)	Top Layer → Bottom Layer	0.30 mm · —	0.00101 mA	1.53e−06 mV	1.54e-12 mW	PASS
(64.03, 29.53)	Top Layer → Bottom Layer	0.20 mm · —	0.00101 mA	2.54e−06 mV	2.56e-12 mW	PASS
(64.75, 26.00)	Top Layer → Bottom Layer	0.30 mm · —	0.00101 mA	1.09e−07 mV	1.11e-13 mW	PASS

Showing 3 of 3 vias, highest current first. Limit 1 A per via.

6.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#1	LDO	VBUS → VDD3V3_USB	3.230 V	4.487 V	0.001 mA	0.001 mA	0.00126 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

6.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

6.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

7 · VDDIO

PASS 1 uncheckedU9#8 (LDO, from VBUS) · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.228 V

U7#10 · min 2.700 V

Worst drop

1.93 mV

0.06 % of 3.230 V

Load

52 mA

11 loads

Max via current

27.1 mA

31 vias

Copper loss

0.0645 mW

Top Layer 0.0399 mW · Signal Layer 2 0.0245 mW

Peak |J|

5.89 A/mm²

current density

7.1Findings

• UNCHECKED
  No PDN_MIN_V on 7 of 11 sinks

  The drop at R93#1, R92#1, R73#1, R72#1 and 3 more was calculated but not compared against a limit.

7.2Power path

7.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
R93#1	VDDIO	1	2.2 mA	3.228 V	1.73 mV	0.538 mV	—	no limit	UNCHECKED
R92#1	VDDIO	1	2.2 mA	3.228 V	1.73 mV	0.538 mV	—	no limit	UNCHECKED
R73#1	VDDIO	1	0.33 mA	3.228 V	1.64 mV	0.538 mV	—	no limit	UNCHECKED
R72#1	VDDIO	1	0.33 mA	3.228 V	1.65 mV	0.538 mV	—	no limit	UNCHECKED
R83#1	VDDIO	1	2.2 mA	3.228 V	1.59 mV	0.538 mV	—	no limit	UNCHECKED
R84#1	VDDIO	1	2.2 mA	3.228 V	1.59 mV	0.538 mV	—	no limit	UNCHECKED
U7#10	VDDIO	4	2.9 mA	3.228 V	1.93 mV	0.538 mV	2.700 V	+528 mV	PASS
U7#11	VDDIO	2	0.913 mA	3.228 V	1.65 mV	0.538 mV	2.700 V	+528 mV	PASS
U7#12	VDDIO	4	32.6 mA	3.228 V	1.93 mV	0.538 mV	2.700 V	+528 mV	PASS
U7#13	VDDIO	1	5.77 mA	3.228 V	1.64 mV	0.538 mV	2.700 V	+528 mV	PASS
R107#1	VDDIO	1	0.33 mA	3.228 V	1.62 mV	0.538 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.230 V setpoint. Every pin is listed in the appendix.

7.4Heatmaps

7.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDDIO	1.1 oz	1.4 mV	5.89 A/mm²	(26.07, 31.25)	0.0399 mW	62%
Signal Layer 1	VDDIO	1 oz	0.623 mV	1.88e-08 A/mm²	(57.83, 37.97)	1.63e-20 mW	0%
Signal Layer 2	VDDIO	1 oz	0.558 mV	1.58 A/mm²	(56.81, 33.12)	0.0245 mW	38%
Bottom Layer	VDDIO	1.1 oz	0.558 mV	0.396 A/mm²	(45.73, 35.32)	5.09e-05 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

7.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(19.90, 31.33)	Top Layer → Bottom Layer	0.30 mm · —	27.1 mA	0.041 mV	0.00111 mW	PASS
(19.45, 31.98)	Top Layer → Bottom Layer	0.30 mm · —	24.9 mA	0.0377 mV	0.000939 mW	PASS
(57.33, 33.62)	Top Layer → Bottom Layer	0.20 mm · —	13.6 mA	0.0319 mV	0.000438 mW	PASS
(58.33, 33.62)	Top Layer → Bottom Layer	0.20 mm · —	12.4 mA	0.0295 mV	0.000365 mW	PASS
(59.15, 33.44)	Top Layer → Bottom Layer	0.20 mm · —	9.41 mA	0.0222 mV	0.000209 mW	PASS

Showing 5 of 31 vias, highest current first. Limit 1 A per via.

7.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#8	LDO	VBUS → VDDIO	3.230 V	4.487 V	52 mA	52 mA	65.3 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

7.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

7.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

8 · VDD_FLASH

PASS 1 uncheckedU9#9 (LDO, from VBUS) · nets VDD_FLASH, VDD_SDCARD · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.221 V

CN7#1

Worst drop

9.33 mV

0.29 % of 3.230 V

Load

0.201 A

7 loads

Max via current

0.201 A

5 vias

Copper loss

1.56 mW

Top Layer 0.738 mW · Bottom Layer 0.418 mW

Peak |J|

67 A/mm²

current density

8.1Findings

• UNCHECKED
  No PDN_MIN_V on any sink

  The drop at R6#1, R8#1, R77#1, R10#1 and 3 more was calculated but not compared against a limit.

8.2Power path

8.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
R6#1	VDD_SDCARD	1	0.0702 mA	3.222 V	8.36 mV	0.177 mV	—	no limit	UNCHECKED
R8#1	VDD_SDCARD	1	0.0702 mA	3.221 V	9.16 mV	0.177 mV	—	no limit	UNCHECKED
R77#1	VDD_SDCARD	1	0.0702 mA	3.221 V	8.83 mV	0.173 mV	—	no limit	UNCHECKED
R10#1	VDD_SDCARD	1	0.0702 mA	3.221 V	9.16 mV	0.177 mV	—	no limit	UNCHECKED
R13#1	VDD_SDCARD	1	0.0702 mA	3.224 V	6.28 mV	0.177 mV	—	no limit	UNCHECKED
R78#1	VDD_SDCARD	1	0.33 mA	3.221 V	8.83 mV	0.173 mV	—	no limit	UNCHECKED
CN7#1	VDD_SDCARD	1	0.2 A	3.221 V	9.33 mV	0.205 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.230 V setpoint. Every pin is listed in the appendix.

8.4Heatmaps

8.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDD_SDCARD	1.1 oz	9.13 mV	67 A/mm²	(20.26, 47.56)	0.738 mW	47%
Signal Layer 1	VDD_SDCARD	1 oz	6.16 mV	5.54e-09 A/mm²	(17.26, 54.70)	1.69e-21 mW	0%
Signal Layer 2	VDD_SDCARD	1 oz	5.6 mV	11.6 A/mm²	(17.20, 32.77)	0.403 mW	26%
Bottom Layer	VDD_SDCARD	1.1 oz	5.57 mV	25.5 A/mm²	(16.21, 54.46)	0.418 mW	27%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

8.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(17.37, 32.70)	Top Layer → Bottom Layer	0.30 mm · —	0.201 A	0.304 mV	0.061 mW	PASS
(20.25, 46.77)	Top Layer → Bottom Layer	0.30 mm · —	0.201 A	0.304 mV	0.061 mW	PASS
(17.25, 48.45)	Top Layer → Bottom Layer	0.30 mm · —	0.201 A	0.326 mV	0.0654 mW	PASS
(17.13, 54.80)	Top Layer → Bottom Layer	0.30 mm · —	0.2 A	0.325 mV	0.0651 mW	PASS
(17.15, 58.85)	Top Layer → Bottom Layer	0.30 mm · —	0.0702 mA	0.000114 mV	8.01e-09 mW	PASS

Showing 5 of 5 vias, highest current first. Limit 1 A per via.

8.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
R14#1	Resistor	VDD_SDCARD → 3V3	5e+08 Ω	1.42e-07 mA	70.9 mV	1.01e-08 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#9	LDO	VBUS → VDD_FLASH	3.230 V	4.487 V	0.201 A	0.201 A	252 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

8.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

8.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

9 · NetL6_1

PASS 1 uncheckedU23#1 (SMPS, from VBUS), remote sense at R88 · nets 3V3, NetC53_2, NetL6_1 · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.104 V

U15#2 · min 3.000 V

Worst drop

48.8 mV

1.5 % of 3.153 V

Load

0.214 A

19 loads

Max via current

92.7 mA

38 vias

Copper loss

0.48 mW

Signal Layer 2 0.239 mW · Bottom Layer 0.181 mW

Peak |J|

20.1 A/mm²

current density

9.1Findings

• UNCHECKED
  No PDN_MIN_V on 13 of 19 sinks

  The drop at R88#1, R81#1, U13#1, R41#1 and 9 more was calculated but not compared against a limit.

9.2Power path

9.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
R88#1	3V3	1	0.0333 mA	3.153 V	−8.38e−05 mV	−0.000155 mV	—	no limit	UNCHECKED
R81#1	3V3	1	5.89 mA	3.153 V	−0.00048 mV	3.1e−06 mV	—	no limit	UNCHECKED
U13#1	NetC53_2	1	0.00015 mA	3.105 V	48.2 mV	0.00514 mV	—	no limit	UNCHECKED
R41#1	3V3	1	0.33 mA	3.152 V	1.3 mV	0.0725 mV	—	no limit	UNCHECKED
R43#1	3V3	1	2.2 mA	3.151 V	1.59 mV	0.371 mV	—	no limit	UNCHECKED
R44#1	3V3	1	0.33 mA	3.152 V	1.3 mV	0.0725 mV	—	no limit	UNCHECKED
R54#1	3V3	1	0.33 mA	3.152 V	1.28 mV	0.0725 mV	—	no limit	UNCHECKED
R60#1	3V3	1	0.33 mA	3.152 V	1.28 mV	0.0725 mV	—	no limit	UNCHECKED
U15#1	3V3	1	46.3 mA	3.152 V	1.46 mV	0.0725 mV	1.620 V	+1.53e+03 mV	PASS
U15#2	NetC53_2	2	92.7 mA	3.104 V	48.8 mV	0.0725 mV	3.000 V	+104 mV	PASS
R61#1	3V3	1	0.33 mA	3.152 V	1.07 mV	0.0215 mV	—	no limit	UNCHECKED
U16#1	3V3	1	0.75 mA	3.152 V	1.08 mV	0.0215 mV	1.600 V	+1.55e+03 mV	PASS
U17#1	3V3	1	0.75 mA	3.152 V	1.04 mV	−0.00961 mV	1.600 V	+1.55e+03 mV	PASS
U22#1	3V3	1	31.4 mA	3.152 V	1.04 mV	0.238 mV	0.900 V	+2.25e+03 mV	PASS
U21#1	3V3	1	31.4 mA	3.152 V	1.16 mV	0.325 mV	0.900 V	+2.25e+03 mV	PASS
R7#1	3V3	1	0.033 mA	3.152 V	0.981 mV	0.325 mV	—	no limit	UNCHECKED
R5#1	3V3	1	0.0702 mA	3.152 V	1.02 mV	0.371 mV	—	no limit	UNCHECKED
R12#1	3V3	1	0.33 mA	3.152 V	1.05 mV	0.371 mV	—	no limit	UNCHECKED
R4#1	3V3	1	0.0702 mA	3.152 V	1.02 mV	0.371 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.153 V setpoint. Every pin is listed in the appendix.

9.4Heatmaps

9.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	3V3, NetC53_2	1.1 oz	48.8 mV	14.3 A/mm²	(41.20, 10.87)	0.0613 mW	13%
Signal Layer 1	3V3, NetC53_2	1 oz	48.3 mV	5.62e-09 A/mm²	(71.68, 55.97)	1.4e-20 mW	0%
Signal Layer 2	3V3, NetC53_2	1 oz	48.2 mV	2.62 A/mm²	(19.08, 46.92)	0.239 mW	50%
Bottom Layer	3V3, NetC53_2, NetL6_1	1.1 oz	49.2 mV	20.1 A/mm²	(11.49, 45.28)	0.181 mW	38%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

9.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(38.75, 9.95)	Top Layer → Bottom Layer	0.30 mm · —	92.7 mA	0.14 mV	0.013 mW	PASS
(15.78, 46.75)	Top Layer → Bottom Layer	0.30 mm · —	88.1 mA	0.00962 mV	0.000847 mW	PASS
(48.43, 15.50)	Top Layer → Bottom Layer	0.30 mm · —	46.3 mA	0.0702 mV	0.00325 mW	PASS
(40.43, 11.32)	Top Layer → Bottom Layer	0.30 mm · —	44.6 mA	0.0676 mV	0.00301 mW	PASS
(41.20, 18.50)	Top Layer → Bottom Layer	0.30 mm · —	44.6 mA	0.0676 mV	0.00301 mW	PASS

Showing 5 of 38 vias, highest current first. Limit 1 A per via.

9.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L6#1	Inductor	NetL6_1 → 3V3	1 mΩ	0.214 A	0.214 mV	0.0456 mW
L4#1	Inductor	3V3 → NetC53_2	500 mΩ	92.7 mA	46.3 mV	4.29 mW
R39#1	Resistor	NetR40_2 → 3V3	5e+08 Ω	-4.37e-06 mA	−2.19e+03 mV	9.57e-06 mW
R14#1	Resistor	VDD_SDCARD → 3V3	5e+08 Ω	1.42e-07 mA	70.9 mV	1.01e-08 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U23#1	SMPS · remote sense at R88	VBUS → NetL6_1	3.153 V	4.488 V	0.214 A	0.213 A	280 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

9.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

9.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

10 · VDD1_DDR

PASSU9#2 (LDO, from VBUS) · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.727 V

U8#1 · min 1.700 V

Worst drop

0.902 mV

0.052 % of 1.728 V

Load

23 mA

1 load

Max via current

23 mA

5 vias

Copper loss

0.00953 mW

Top Layer 0.00447 mW · Signal Layer 2 0.0035 mW

Peak |J|

2.62 A/mm²

current density

10.1Findings

No issues on this rail.

10.2Power path

10.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U8#1	VDD1_DDR	8	23 mA	1.727 V	0.902 mV	0.298 mV	1.700 V	+27.1 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.728 V setpoint. Every pin is listed in the appendix.

10.4Heatmaps

10.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDD1_DDR	1.1 oz	0.604 mV	2.62 A/mm²	(76.64, 29.34)	0.00447 mW	47%
Signal Layer 1	VDD1_DDR	1 oz	0.488 mV	9.12e-09 A/mm²	(76.63, 35.69)	7.66e-22 mW	0%
Signal Layer 2	VDD1_DDR	1 oz	0.456 mV	0.849 A/mm²	(47.52, 25.90)	0.0035 mW	37%
Bottom Layer	VDD1_DDR	1.1 oz	0.453 mV	1.26 A/mm²	(35.36, 29.12)	0.00156 mW	16%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

10.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(33.18, 33.10)	Top Layer → Bottom Layer	0.30 mm · —	23 mA	0.0374 mV	0.000859 mW	PASS
(77.02, 28.64)	Top Layer → Bottom Layer	0.30 mm · —	23 mA	0.0348 mV	0.000801 mW	PASS
(35.30, 28.75)	Top Layer → Bottom Layer	0.30 mm · —	12.5 mA	0.00136 mV	1.69e-05 mW	PASS
(34.55, 28.72)	Top Layer → Bottom Layer	0.30 mm · —	10.5 mA	0.00115 mV	1.21e-05 mW	PASS
(76.45, 35.61)	Top Layer → Bottom Layer	0.20 mm · —	8.96e-07 mA	1.4e−09 mV	8.23e-19 mW	PASS

Showing 5 of 5 vias, highest current first. Limit 1 A per via.

10.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#2	LDO	VBUS → VDD1_DDR	1.728 V	4.487 V	23 mA	23 mA	63.4 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

10.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

10.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

11 · NetL3_1

PASS 1 uncheckedU9#5 (SMPS, from VBUS), remote sense at LNK3 · nets NetL3_1, VDD2_DDR · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.079 V

U7#6 · min 1.060 V

Worst drop

4.02 mV

0.37 % of 1.083 V

Load

0.637 A

4 loads

Max via current

0.172 A

50 vias

Copper loss

2.72 mW

Signal Layer 2 1.85 mW · Top Layer 0.879 mW

Peak |J|

63.3 A/mm²

current density

11.1Findings

• UNCHECKED
  No PDN_MIN_V on 1 of 4 sinks

  The drop at R94#1 was calculated but not compared against a limit.

11.2Power path

11.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#6	VDD2_DDR	4	0.275 A	1.079 V	4.02 mV	0.538 mV	1.060 V	+19.5 mV	PASS
U7#7	VDD2_DDR	4	58.4 mA	1.079 V	4.02 mV	0.538 mV	1.060 V	+19.5 mV	PASS
R94#1	VDD2_DDR	1	4.58 mA	1.080 V	3.44 mV	0.298 mV	—	no limit	UNCHECKED
U8#2	VDD2_DDR	45	0.299 A	1.080 V	3.56 mV	0.298 mV	1.060 V	+19.9 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.083 V setpoint. Every pin is listed in the appendix.

11.4Heatmaps

11.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetL3_1, VDD2_DDR	1.1 oz	32.2 mV	63.3 A/mm²	(31.97, 35.68)	0.879 mW	32%
Signal Layer 1	VDD2_DDR	1 oz	3.37 mV	8.32e-09 A/mm²	(73.29, 38.30)	7.31e-21 mW	0%
Signal Layer 2	VDD2_DDR	1 oz	2.95 mV	11.5 A/mm²	(47.43, 30.03)	1.85 mW	68%
Bottom Layer	VDD2_DDR	1.1 oz	2.95 mV	1.31 A/mm²	(61.59, 34.72)	0.0002 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

11.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(39.68, 34.80)	Top Layer → Bottom Layer	0.30 mm · —	0.172 A	0.26 mV	0.0447 mW	PASS
(39.68, 35.50)	Top Layer → Bottom Layer	0.30 mm · —	0.167 A	0.254 mV	0.0425 mW	PASS
(40.40, 34.80)	Top Layer → Bottom Layer	0.30 mm · —	0.153 A	0.231 mV	0.0353 mW	PASS
(40.40, 35.50)	Top Layer → Bottom Layer	0.30 mm · —	0.145 A	0.22 mV	0.032 mW	PASS
(61.67, 34.44)	Top Layer → Bottom Layer	0.20 mm · —	0.102 A	0.238 mV	0.0243 mW	PASS

Showing 5 of 50 vias, highest current first. Limit 1 A per via.

11.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L3#1	Inductor	NetL3_1 → VDD2_DDR	43 mΩ	0.637 A	27.4 mV	17.4 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#5	SMPS · remote sense at LNK3	VBUS → NetL3_1	1.083 V	4.487 V	0.637 A	0.197 A	176 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

11.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

11.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

12 · NetL2_1

PASSU9#6 (SMPS, from VBUS), remote sense at LNK1 · nets NetL2_1, VDDCORE · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

0.803 V

U7#8 · min 0.792 V

Worst drop

4.31 mV

0.53 % of 0.808 V

Load

0.39 A

1 load

Max via current

0.116 A

11 vias

Copper loss

1.67 mW

Signal Layer 2 1.29 mW · Top Layer 0.382 mW

Peak |J|

47 A/mm²

current density

12.1Findings

No issues on this rail.

12.2Power path

12.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#8	VDDCORE	7	0.39 A	0.803 V	4.31 mV	0.538 mV	0.792 V	+11.4 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 0.808 V setpoint. Every pin is listed in the appendix.

12.4Heatmaps

12.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetL2_1, VDDCORE	1.1 oz	21.5 mV	47 A/mm²	(28.74, 38.60)	0.382 mW	23%
Signal Layer 1	VDDCORE	1 oz	3.74 mV	5.41e-09 A/mm²	(57.22, 35.75)	7.64e-22 mW	0%
Signal Layer 2	VDDCORE	1 oz	3.48 mV	13.6 A/mm²	(59.26, 33.93)	1.29 mW	77%
Bottom Layer	VDDCORE	1.1 oz	3.48 mV	3.72 A/mm²	(57.59, 35.67)	0.000857 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

12.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(26.50, 45.50)	Top Layer → Bottom Layer	0.30 mm · —	0.116 A	0.176 mV	0.0204 mW	PASS
(25.43, 45.50)	Top Layer → Bottom Layer	0.30 mm · —	0.1 A	0.152 mV	0.0152 mW	PASS
(26.45, 46.43)	Top Layer → Bottom Layer	0.30 mm · —	94.6 mA	0.143 mV	0.0135 mW	PASS
(57.41, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	82.8 mA	0.191 mV	0.0162 mW	PASS
(58.33, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	82.3 mA	0.195 mV	0.016 mW	PASS

Showing 5 of 11 vias, highest current first. Limit 1 A per via.

12.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L2#1	Inductor	NetL2_1 → VDDCORE	43 mΩ	0.39 A	16.8 mV	6.54 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#6	SMPS · remote sense at LNK1	VBUS → NetL2_1	0.808 V	4.487 V	0.39 A	90 mA	81.8 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

12.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

12.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

13 · NetL1_1

PASSU9#7 (SMPS, from VBUS), remote sense at LNK2 · nets NetL1_1, VDDCPU · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

0.786 V

U7#9 · min 0.768 V

Worst drop

1.92 mV

0.24 % of 0.788 V

Load

0.19 A

1 load

Max via current

56.3 mA

8 vias

Copper loss

0.306 mW

Signal Layer 2 0.207 mW · Top Layer 0.0985 mW

Peak |J|

22.8 A/mm²

current density

13.1Findings

No issues on this rail.

13.2Power path

13.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#9	VDDCPU	5	0.19 A	0.786 V	1.92 mV	0.538 mV	0.768 V	+18.1 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 0.788 V setpoint. Every pin is listed in the appendix.

13.4Heatmaps

13.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetL1_1, VDDCPU	1.1 oz	9.99 mV	22.8 A/mm²	(30.27, 38.60)	0.0985 mW	32%
Signal Layer 1	VDDCPU	1 oz	1.3 mV	5.69e-09 A/mm²	(60.13, 35.76)	4.08e-22 mW	0%
Signal Layer 2	VDDCPU	1 oz	1.12 mV	8.52 A/mm²	(59.34, 38.22)	0.207 mW	68%
Bottom Layer	VDDCPU	1.1 oz	1.12 mV	0.608 A/mm²	(60.13, 35.75)	2.5e-05 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

13.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(36.95, 43.80)	Top Layer → Bottom Layer	0.30 mm · —	56.3 mA	0.0853 mV	0.00481 mW	PASS
(36.15, 43.80)	Top Layer → Bottom Layer	0.30 mm · —	54.5 mA	0.0826 mV	0.0045 mW	PASS
(59.83, 37.25)	Top Layer → Bottom Layer	0.20 mm · —	51.6 mA	0.122 mV	0.00628 mW	PASS
(60.33, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	50.4 mA	0.119 mV	0.00598 mW	PASS
(59.33, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	49.1 mA	0.115 mV	0.00568 mW	PASS

Showing 5 of 8 vias, highest current first. Limit 1 A per via.

13.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L1#1	Inductor	NetL1_1 → VDDCPU	43 mΩ	0.19 A	8.17 mV	1.55 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#7	SMPS · remote sense at LNK2	VBUS → NetL1_1	0.788 V	4.487 V	0.19 A	42.8 mA	40.5 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

13.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

13.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

A · Setup & assumptions

Stackup

All load pins

Review

FYPA is a design aid. Validate results against measurement.