MB2059

1 · Executive summary

Rails with failures come first, then warnings, then by nominal voltage. Grey “no limit” and “not analysed” cells were not checked against anything, so they are not passes. Drop is measured from the setpoint and includes the return path.

Issues to resolve

• WARN
  Design · U7: appears in multiple schdocs with PDN_ROLE

  Only the first occurrence is used
• WARN
  Design · U8: appears in multiple schdocs with PDN_ROLE

  Only the first occurrence is used
• WARN
  Design · REGULATOR on U23#1: Vin=5 V was inferred 1 SERIES hop(s) upstream of PDN1_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN1_GAIN explicitly
• WARN
  Design · SERIES on R89#1: auto-inferred PDN1_P_NET='EXT_EN5', PDN1_N_NET='EXT_EN1' from 2-pin connectivity
• WARN
  Design · REGULATOR on U9#5: Vin=5 V was inferred 1 SERIES hop(s) upstream of PDN5_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN5_GAIN explicitly
• WARN
  Design · REGULATOR on U9#6: Vin=5 V was inferred 1 SERIES hop(s) upstream of PDN6_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN6_GAIN explicitly
• WARN
  Design · REGULATOR on U9#7: Vin=5 V was inferred 1 SERIES hop(s) upstream of PDN7_IN_P_NET='5V_VIN', not from a rail declared on that net

  Confirm that chain is the power path, or set PDN7_GAIN explicitly
• WARN
  Design · SERIES on R39#1: auto-inferred PDN1_P_NET='NetR40_2', PDN1_N_NET='3V3' from 2-pin connectivity
• WARN
  Design · SERIES on R31#1: auto-inferred PDN1_P_NET='GND', PDN1_N_NET='NetCN11_12' from 2-pin connectivity
• WARN
  Design · SERIES on R3#1: auto-inferred PDN1_P_NET='GND', PDN1_N_NET='LCD_INT' from 2-pin connectivity
• WARN
  Design · SERIES on R14#1: auto-inferred PDN1_P_NET='VDD_SDCARD', PDN1_N_NET='3V3' from 2-pin connectivity
• WARN
  Design · SERIES on R105#1: auto-inferred PDN1_P_NET='BUTTON.TAMP', PDN1_N_NET='VBAT' from 2-pin connectivity
• WARN
  Design · 0R link on R90 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging EXT_EN1 / NetR89_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R90 (Power_PMIC.SchDoc): auto-bridged EXT_EN1 ↔ NetR89_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R91 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VDDIO / NetD2_1. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R91 (Power_MPU.SchDoc): auto-bridged VDDIO ↔ NetD2_1 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R102 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VREF+ / VDDA1V8. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R102 (Power_MPU.SchDoc): auto-bridged VREF+ ↔ VDDA1V8 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R103 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VDDA1V8 / NetC130_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R103 (Power_MPU.SchDoc): auto-bridged VDDA1V8 ↔ NetC130_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R29 (MP215_11x11.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetC35_1 / OSC32_OUT. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R29 (MP215_11x11.SchDoc): auto-bridged NetC35_1 ↔ OSC32_OUT as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R18 (SDcard.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging SD.uSD_DETECT / NetCN7_10. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R18 (SDcard.SchDoc): auto-bridged SD.uSD_DETECT ↔ NetCN7_10 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R30 (MP215_11x11.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging HSE_OUT / NetC48_1. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R30 (MP215_11x11.SchDoc): auto-bridged HSE_OUT ↔ NetC48_1 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R101 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetR101_2 / NRST. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R101 (Power_PMIC.SchDoc): auto-bridged NetR101_2 ↔ NRST as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R74 (LCD_connector.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetR74_2 / LCD_BL. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R74 (LCD_connector.SchDoc): auto-bridged NetR74_2 ↔ LCD_BL as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R68 (LCD_connector.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging 5V_VIN / VL. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R68 (LCD_connector.SchDoc): auto-bridged 5V_VIN ↔ VL as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R15 (SDcard.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging VDD_SDCARD / VDD_FLASH. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R15 (SDcard.SchDoc): auto-bridged VDD_SDCARD ↔ VDD_FLASH as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R71 (LCD_connector.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging LCD_BL_A / VH. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R71 (LCD_connector.SchDoc): auto-bridged LCD_BL_A ↔ VH as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R42 (Ethernet_RMII.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging ETH1.MDINT / NetR41_1. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R42 (Ethernet_RMII.SchDoc): auto-bridged ETH1.MDINT ↔ NetR41_1 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R40 (Ethernet_RMII.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging ETH1.NRST / NetR40_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R40 (Ethernet_RMII.SchDoc): auto-bridged ETH1.NRST ↔ NetR40_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R98 (Power_MPU.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NetC128_2 / VDD3V3_USB. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R98 (Power_MPU.SchDoc): auto-bridged NetC128_2 ↔ VDD3V3_USB as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R26 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging PWR_ON / NetR26_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R26 (Power_PMIC.SchDoc): auto-bridged PWR_ON ↔ NetR26_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R24 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging PWR_CPU_ON / NetR24_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R24 (Power_PMIC.SchDoc): auto-bridged PWR_CPU_ON ↔ NetR24_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · 0R link on R22 (Power_PMIC.SchDoc): auto-bridged as SERIES (0.5 mΩ) because value '0R' reads as a 0 Ω link

  Bridging NRSTC1MS / NetR22_2. Add PDN_ROLE=SERIES with a real PDN_R to override.
• WARN
  Design · 0R link on R22 (Power_PMIC.SchDoc): auto-bridged NRSTC1MS ↔ NetR22_2 as low-Ω NetTie short (0.5 mΩ)
• WARN
  Design · pdn.json: Rail VBAT: no source traced in the schematic
• WARN
  Design · pdn.json: U23 (3V3): regulated at its feedback point, R88_2 on 3V3
• WARN
  Design · pdn.json: U9 (VDD2_DDR): regulated at its feedback point, LNK3_2 on VDD2_DDR
• WARN
  Design · pdn.json: U18 (LCD_BL_A): no stated voltage; no REGULATOR, so LCD_BL_A is not driven
• WARN
  Design · pdn.json: U9 (VDDCORE): regulated at its feedback point, LNK1_2 on VDDCORE
• WARN
  Design · pdn.json: U9 (VDDCPU): regulated at its feedback point, LNK2_2 on VDDCPU
• WARN
  Design · pdn.json: U14: load switch, a SERIES of 0.048 Ohm from VBUS to 5V_VIN (not a regulator)
• WARN
  Design · pdn.json: U14: load switch, a SERIES of 0.048 Ohm from VBUS to 5V_VIN (not a regulator)
• WARN
  Design · pdn.json: L6: inside U23's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: L6: DC resistance not in the file; bridged at 1 mOhm
• WARN
  Design · pdn.json: L3: inside U9's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: L2: inside U9's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: L1: inside U9's regulation loop, before its feedback point; its own DC resistance, made up by the loop
• WARN
  Design · pdn.json: R46 on 5V_VIN: its current is counted in U14's figure; no SINK
• WARN
  Design · pdn.json: U17: only a maximum current is known; 0.75 mA is used
• WARN
  Design · pdn.json: U16: only a maximum current is known; 0.75 mA is used
• WARN
  Design · pdn.json: U15 on 3V3: 2 die supplies, none named as the current's; drawn at all its pins
• WARN
  Design · pdn.json: R47 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: R49 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: R50 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: R53 on 3V3: its current is counted in U13's figure; no SINK
• WARN
  Design · pdn.json: U7 on VDDA1V8: 6 die supplies, none named as the current's; drawn at all its pins
• WARN
  Design · pdn.json: U7 [VDDIO2] on VDDA1V8: I/O current 2.7 mA ESTIMATED, not a data-sheet figure (5 of 6 VDDIO2 bank pins connected (not connected: U7_C15): U7_A14 M2…

  pdn.json: U7 [VDDIO2] on VDDA1V8: I/O current 2.7 mA ESTIMATED, not a data-sheet figure (5 of 6 VDDIO2 bank pins connected (not connected: U7_C15): U7_A14 M2.SDMMC2_D0: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_A15 M2.SDMMC2_D3: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_B14 M2.SDMMC2_D1: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_D14 M2.SDMMC2_CK: SDMMC clock 50 MHz, 20 pF x 1.8 V x f = 1.8 mA; U7_E11 M2.SDMMC2_CMD: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U7 on VDDA1V8_AON: its current is VDDA18AON's, drawn at those pins; PDR_ON draw none stated (no SINK)
• WARN
  Design · pdn.json: U7 on VREF+: current not known; no SINK, so VREF+'s drop is a lower bound
• WARN
  Design · pdn.json: U7 [VDDQDDR] on VDD2_DDR: I/O current 58.4 mA ESTIMATED, not a data-sheet figure (32 of 52 VDDQDDR bank pins connected (not connected: U7_F18, U7_F…

  pdn.json: U7 [VDDQDDR] on VDD2_DDR: I/O current 58.4 mA ESTIMATED, not a data-sheet figure (32 of 52 VDDQDDR bank pins connected (not connected: U7_F18, U7_F21, U7_G19, U7_G21, U7_H18, U7_H20, U7_J17, U7_K18, U7_K19, U7_K20, U7_K21, U7_L17, U7_L19, U7_M19, U7_M20, U7_N19, U7_P18, U7_P19, U7_P20, U7_P21): 32 LPDDR4 LVSTL x 7.3 mA x 25 % - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U8 on VDD2_DDR: 3 die supplies, none named as the current's; drawn at all its pins
• WARN
  Design · pdn.json: Rail VBAT: nothing in the file drives it; its loads are left out: U7
• WARN
  Design · pdn.json: U7 on VDDCORE: its current is VDDCORE's, drawn at those pins; VDDCSI draw none stated (no SINK)
• WARN
  Design · pdn.json: U7: draws what it drives (figure is with all peripherals disabled; VDD/VDDIO1/VDDIO3 I/O current follows pin activity and loads); its own current 2…

  pdn.json: U7: draws what it drives (figure is with all peripherals disabled; VDD/VDDIO1/VDDIO3 I/O current follows pin activity and loads); its own current 2350 uA is used, so the rail's drop is a lower bound
• WARN
  Design · pdn.json: U7 on VDDIO: its current is VDD's, drawn at those pins
• WARN
  Design · pdn.json: U7 [VDDIO3] on VDDIO: I/O current 0.91344 mA ESTIMATED, not a data-sheet figure (11 of 12 VDDIO3 bank pins connected (not connected: U7_E15): U7_A6…

  pdn.json: U7 [VDDIO3] on VDDIO: I/O current 0.91344 mA ESTIMATED, not a data-sheet figure (11 of 12 VDDIO3 bank pins connected (not connected: U7_E15): U7_A6 SD.uSD_DETECT: static line: 0 = 0 mA; U7_B4 M2.SAI1_SCKA: SAI clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_B6 M2.SAI1_SDB: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_B7 M2.SAI1_FSA: SAI static line: 0 = 0 mA; U7_B11 BT_HOST_WAKE: static line: 0 = 0 mA; U7_C4 GPIO.SPI1_NSS: SPI static line: 0 = 0 mA; U7_C7 GPIO.SPI1_MISO: SPI input: 0 = 0 mA; U7_C9 M2.SAI1_SDA: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_C10 CAM_RESET: static line: 0 = 0 mA; U7_D4 GPIO.SPI1_SCK: SPI clock 10 MHz, 20 pF x 3.3 V x f = 0.66 mA; U7_D8 CAM_ENABLE: static line: 0 = 0 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U7 [VDD] on VDDIO: I/O current 32.5774 mA ESTIMATED, not a data-sheet figure (102 of 110 VDD bank pins connected (not connected: U7_A10, U7_AA10, U…

  pdn.json: U7 [VDD] on VDDIO: I/O current 32.5774 mA ESTIMATED, not a data-sheet figure (102 of 110 VDD bank pins connected (not connected: U7_A10, U7_AA10, U7_D6, U7_K2, U7_V6, U7_V14, U7_W12, U7_Y18): U7_A7 I2C2.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_A18 GPIO.SDMMC3_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_A19 GPIO.SDMMC3_D1: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_AA6 LED2: resistive load, on all the time (upper bound): R57 100k to GND: V/R 0.033 mA = 0.033 mA; U7_AA7 LCD_BL: resistive load, on all the time (upper bound): R75 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_AA11 ETH1.MDIO: MDIO data 2.5 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0206 mA; U7_AA14 LED3: resistive load, on all the time (upper bound): R56 100k to GND: V/R 0.033 mA = 0.033 mA; U7_AA15 UART4_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_AA18 LED1: static line: 0 = 0 mA; U7_B8 USART1_RTS: UART static line: 0 = 0 mA; U7_B10 MDF.SDI3: MDF input: 0 = 0 mA; U7_B16 GPIO.SDMMC3_D0: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_B18 GPIO.SDMMC3_CMD: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C5 BT_REG_ON: static line: 0 = 0 mA; U7_C6 USART1_CTS: UART static line: 0 = 0 mA; U7_C8 USART1_RX: UART input: 0 = 0 mA; U7_C16 GPIO.SDMMC3_CK: SDMMC clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_C17 GPIO.SDMMC3_D3: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D3 LCD_VSYNC: LTDC static line: 0 = 0 mA; U7_E3 LCD_HSYNC: LTDC static line: 0 = 0 mA; U7_E4 LCD_DE: LTDC static line: 0 = 0 mA; U7_E5 GPIO.SPI1_MOSI: SPI data 10 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.165 mA; U7_E7 I2C2.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_E9 WL_REG_ON: static line: 0 = 0 mA; U7_F1 LCD_B4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F2 LCD_B5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F3 LCD_B6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F4 LCD_B3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_G1 USART1_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_G2 LCD_B2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_G3 BUTTON.TAMP: static line: 0 = 0 mA; U7_G5 LCD_B7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H2 LCD_G6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H3 LCD_G5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H4 LCD_G4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_J3 LCD_G3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_J5 LCD_G7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_K1 GPIO.SAI2_SDB: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_K3 LCD_G2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_K4 I2C3.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_K6 LED4: resistive load, on all the time (upper bound): R55 100k to GND: V/R 0.033 mA = 0.033 mA; U7_L3 LCD_R7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_L5 I2C3.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_M2 LCD_R6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_M3 LCD_INT: LTDC input: 0 = 0 mA; U7_M4 LCD_R5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_N3 LCD_R4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_N5 LCD_R3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_P1 GPIO.USART6_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_P2 GPIO.USART6_CTS: UART static line: 0 = 0 mA; U7_P3 LCD_R2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_P4 BUTTON.USER2: static line: 0 = 0 mA; U7_P6 LCD_DISP: resistive load, on all the time (upper bound): R1 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_R5 BUTTON.USER1: static line: 0 = 0 mA; U7_T2 NRSTC1MS: static line: 0 = 0 mA; U7_T3 I3C1.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_T4 LPO_32: LPO clock 32.77 kHz, 20 pF x 3.3 V x f = 0.00216 mA; U7_T8 I3C2.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_T10 GPIO.GPIO7: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_T12 GPIO.USART6_RTS: UART static line: 0 = 0 mA; U7_T14 ETH1.CLK: RMII clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_T16 GPIO.SAI2_SCKB: SAI clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_U3 LCD_CLK: LTDC clock 33.3 MHz, 20 pF x 3.3 V x f = 2.2 mA; U7_U5 LCD_RST: resistive load, on all the time (upper bound): R2 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_U7 GPIO.SAI2_SDA: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_U9 GPIO.TIM8_CH4: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_U11 ETH1.TXD0: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_U13 MDF.CCK0: MDF clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_U15 GPIO.USART6_RX: UART input: 0 = 0 mA; U7_V1 JTCK_SWCLK: static line: 0 = 0 mA; U7_V2 JTMS_SWDIO: static line: 0 = 0 mA; U7_V3 NJTRST: static line: 0 = 0 mA; U7_V4 PWR_CPU_ON: static line: 0 = 0 mA; U7_V10 ETH1.TXD1: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_V12 ETH1.TX_EN: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_V16 USART2_RX: UART input: 0 = 0 mA; U7_W1 JTDO_SWDO: static line: 0 = 0 mA; U7_W2 JTDI: static line: 0 = 0 mA; U7_W3 PWR_LP: static line: 0 = 0 mA; U7_W4 PWR_ON: static line: 0 = 0 mA; U7_W7 MCO1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W10 GPIO.TIM13_CH1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W11 ETH1.RXD0: RMII input: 0 = 0 mA; U7_W13 GPIO.TIM11_CH1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W14 ETH1.NRST: resistive load, on all the time (upper bound): R38 10k to GND: V/R 0.33 mA = 0.33 mA; U7_W15 ETH1.CRS_DV: RMII input: 0 = 0 mA; U7_W16 GPIO.SAI2_FSB: SAI static line: 0 = 0 mA; U7_W17 I3C1.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_Y6 PA0_INT: static line: 0 = 0 mA; U7_Y7 I3C2.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_Y10 GPIO.TIM8_CH2: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_Y11 ETH1.MDC: MDIO clock 2.5 MHz, 20 pF x 3.3 V x f = 0.165 mA; U7_Y12 ETH1.RXD1: RMII input: 0 = 0 mA; U7_Y14 ETH1.MDINT: RMII input: 0 = 0 mA; U7_Y15 UART4_RX: UART input: 0 = 0 mA; U7_Y16 USART2_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; 6 input-only x 0 - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: U7 [VDDIO1] on VDDIO: I/O current 5.775 mA ESTIMATED, not a data-sheet figure (7 of 10 VDDIO1 bank pins connected (not connected: U7_B15, U7_C14, U…

  pdn.json: U7 [VDDIO1] on VDDIO: I/O current 5.775 mA ESTIMATED, not a data-sheet figure (7 of 10 VDDIO1 bank pins connected (not connected: U7_B15, U7_C14, U7_E13): U7_A11 SD.SDMMC1_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_B12 SD.SDMMC1_CMD: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C11 SD.SDMMC1_D3: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C12 SD.SDMMC1_CK: SDMMC clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_C13 M2.SDMMC2_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D10 SD.SDMMC1_D1: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D12 SD.SDMMC1_D0: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• WARN
  Design · pdn.json: Not fitted, solved as open (5e+08 Ohm): R14, R39, R31, R105, R89, R3
• WARN
  Design · pdn.json: Not fitted, left out: C46, U19
• WARN
  Design · pdn.json: Temperature: the board's maximum ambient is 40 °C; the board temperature is set to it
• WARN
  Design · pdn.json: Via plating from the file (ipc6012_class2_min): through 20 um, blind 20 um, buried 13 um, microvia 12 um; set on the Settings tab

2 · Power tree

3 · VBUS

PASS 1 uncheckedCN10#1 (source) · nets 5V_VIN, VBUS · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

4.976 V

U9#1 → VDD3V3_USB

Worst drop

24.3 mV

0.49 % of 5.000 V

Load

0.36 A

12 loads

Max via current

0.155 A

23 vias

Copper loss

2.38 mW

Signal Layer 2 1.48 mW · Top Layer 0.885 mW

Peak |J|

38.4 A/mm²

current density

3.1Findings

• UNCHECKED
  No PDN_MIN_V on any sink

  The drop at U12#1, U14#2 was calculated but not compared against a limit.

3.2Power path

3.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U23#1 → NetL6_1 (regulator input)	5V_VIN	2	0.138 A	4.976 V	24 mV	0.0977 mV	—	no limit	UNCHECKED
U9#1 → VDD3V3_USB (regulator input)	5V_VIN	7	0.001 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#2 → VDD1_DDR (regulator input)	5V_VIN	7	3.4 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#3 → NetC130_2 (regulator input)	5V_VIN	7	5.38 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#4 → VDDA1V8_AON (regulator input)	5V_VIN	7	3.15 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#5 → NetL3_1 (regulator input)	5V_VIN	7	32.7 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#6 → NetL2_1 (regulator input)	5V_VIN	7	18 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#7 → NetL1_1 (regulator input)	5V_VIN	7	11.8 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#8 → VDDIO (regulator input)	5V_VIN	7	46.5 mA	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U9#9 → VDD_FLASH (regulator input)	5V_VIN	7	0.1 A	4.976 V	24.3 mV	0.0592 mV	—	no limit	UNCHECKED
U12#1	VBUS	1	0.0002 mA	4.999 V	1.14 mV	0.0319 mV	—	no limit	UNCHECKED
U14#2	VBUS	2	0.37 mA	4.998 V	2.2 mV	0.0282 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 5.000 V setpoint. Every pin is listed in the appendix.

3.4Heatmaps

3.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	5V_VIN, VBUS	1.1 oz	24.3 mV	38.4 A/mm²	(94.73, 23.23)	0.885 mW	37%
Signal Layer 1	5V_VIN, VBUS	1 oz	24.2 mV	9.09e-09 A/mm²	(51.75, 9.85)	2.12e-20 mW	0%
Signal Layer 2	5V_VIN, VBUS	1 oz	24.1 mV	5.46 A/mm²	(71.44, 67.28)	1.48 mW	62%
Bottom Layer	5V_VIN, VBUS	1.1 oz	24.1 mV	5.71 A/mm²	(10.24, 46.27)	0.0125 mW	1%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

3.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(98.00, 19.58)	Top Layer → Bottom Layer	0.30 mm · —	0.155 A	0.234 mV	0.0362 mW	PASS
(99.77, 19.58)	Top Layer → Bottom Layer	0.30 mm · —	0.11 A	0.167 mV	0.0184 mW	PASS
(101.25, 19.58)	Top Layer → Bottom Layer	0.30 mm · —	94.9 mA	0.144 mV	0.0136 mW	PASS
(10.05, 46.25)	Top Layer → Bottom Layer	0.30 mm · —	69.4 mA	0.00758 mV	0.000526 mW	PASS
(11.63, 40.75)	Top Layer → Bottom Layer	0.30 mm · —	68.8 mA	0.00751 mV	0.000516 mW	PASS

Showing 5 of 23 vias, highest current first. Limit 1 A per via.

3.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
U14#1	Series part	VBUS → 5V_VIN	48 mΩ	0.36 A	17.3 mV	6.2 mW

3.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

3.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

4 · NetL6_1

PASS 1 uncheckedU23#1 (SMPS, from VBUS), remote sense at R88 · nets 3V3, NetC53_2, NetL6_1 · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.251 V

U15#2 · min 3.000 V

Worst drop

48.6 mV

1.5 % of 3.300 V

Load

0.146 A

19 loads

Max via current

92.7 mA

38 vias

Copper loss

0.303 mW

Signal Layer 2 0.162 mW · Bottom Layer 0.0795 mW

Peak |J|

14.3 A/mm²

current density

4.1Findings

• UNCHECKED
  No PDN_MIN_V on 13 of 19 sinks

  The drop at R88#1, R81#1, U13#1, R41#1 and 9 more was calculated but not compared against a limit.

4.2Power path

4.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
R88#1	3V3	1	0.0333 mA	3.300 V	0.000331 mV	0.000283 mV	—	no limit	UNCHECKED
R81#1	3V3	1	2.95 mA	3.300 V	−0.000504 mV	1.35e−06 mV	—	no limit	UNCHECKED
U13#1	NetC53_2	1	1e-05 mA	3.252 V	48 mV	0.00286 mV	—	no limit	UNCHECKED
R41#1	3V3	1	0.165 mA	3.299 V	1.07 mV	0.0352 mV	—	no limit	UNCHECKED
R43#1	3V3	1	1.1 mA	3.299 V	1.11 mV	0.0799 mV	—	no limit	UNCHECKED
R44#1	3V3	1	0.165 mA	3.299 V	1.06 mV	0.0352 mV	—	no limit	UNCHECKED
R54#1	3V3	1	0.165 mA	3.299 V	1.06 mV	0.0352 mV	—	no limit	UNCHECKED
R60#1	3V3	1	0.165 mA	3.299 V	1.05 mV	0.0352 mV	—	no limit	UNCHECKED
U15#1	3V3	1	46.3 mA	3.299 V	1.23 mV	0.0352 mV	1.620 V	+1.68e+03 mV	PASS
U15#2	NetC53_2	2	92.7 mA	3.251 V	48.6 mV	0.0352 mV	3.000 V	+251 mV	PASS
R61#1	3V3	1	0.165 mA	3.299 V	0.817 mV	−0.041 mV	—	no limit	UNCHECKED
U16#1	3V3	1	0.75 mA	3.299 V	0.824 mV	−0.041 mV	1.600 V	+1.7e+03 mV	PASS
U17#1	3V3	1	0.75 mA	3.299 V	0.802 mV	−0.0569 mV	1.600 V	+1.7e+03 mV	PASS
U22#1	3V3	1	0.005 mA	3.300 V	0.455 mV	−0.022 mV	0.900 V	+2.4e+03 mV	PASS
U21#1	3V3	1	0.005 mA	3.300 V	0.435 mV	−0.0209 mV	0.900 V	+2.4e+03 mV	PASS
R7#1	3V3	1	0.0165 mA	3.300 V	0.456 mV	−0.0209 mV	—	no limit	UNCHECKED
R5#1	3V3	1	0.0351 mA	3.299 V	0.552 mV	0.0799 mV	—	no limit	UNCHECKED
R12#1	3V3	1	0.165 mA	3.299 V	0.574 mV	0.0799 mV	—	no limit	UNCHECKED
R4#1	3V3	1	0.0351 mA	3.299 V	0.551 mV	0.0799 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.300 V setpoint. Every pin is listed in the appendix.

4.4Heatmaps

4.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	3V3, NetC53_2	1.1 oz	48.5 mV	14.3 A/mm²	(41.20, 10.87)	0.0613 mW	20%
Signal Layer 1	3V3, NetC53_2	1 oz	48.1 mV	5.57e-09 A/mm²	(46.71, 20.83)	1.35e-20 mW	0%
Signal Layer 2	3V3, NetC53_2	1 oz	48 mV	2.26 A/mm²	(15.71, 46.93)	0.162 mW	54%
Bottom Layer	3V3, NetC53_2, NetL6_1	1.1 oz	48.7 mV	13.7 A/mm²	(11.49, 45.28)	0.0795 mW	26%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

4.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(38.75, 9.95)	Top Layer → Bottom Layer	0.30 mm · —	92.7 mA	0.14 mV	0.013 mW	PASS
(15.78, 46.75)	Top Layer → Bottom Layer	0.30 mm · —	60.5 mA	0.00661 mV	0.0004 mW	PASS
(48.43, 15.50)	Top Layer → Bottom Layer	0.30 mm · —	46.3 mA	0.0702 mV	0.00325 mW	PASS
(40.43, 11.32)	Top Layer → Bottom Layer	0.30 mm · —	44.6 mA	0.0676 mV	0.00301 mW	PASS
(41.20, 18.50)	Top Layer → Bottom Layer	0.30 mm · —	44.6 mA	0.0676 mV	0.00301 mW	PASS

Showing 5 of 38 vias, highest current first. Limit 1 A per via.

4.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L6#1	Inductor	NetL6_1 → 3V3	1 mΩ	0.146 A	0.146 mV	0.0212 mW
L4#1	Inductor	3V3 → NetC53_2	500 mΩ	92.7 mA	46.3 mV	4.29 mW
R39#1	Resistor	NetR40_2 → 3V3	5e+08 Ω	-5.08e-06 mA	−2.54e+03 mV	1.29e-05 mW
R14#1	Resistor	VDD_SDCARD → 3V3	5e+08 Ω	-5.99e-09 mA	−2.99 mV	1.79e-11 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U23#1	SMPS · remote sense at R88	VBUS → NetL6_1	3.300 V	4.976 V	0.146 A	0.138 A	207 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

4.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

4.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

5 · VDD3V3_USB

PASSU9#1 (LDO, from VBUS) · nets NetC128_2, VDD3V3_USB · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.300 V

U7#1 · min 3.070 V

Worst drop

0.119 mV

0.0036 % of 3.300 V

Load

0.001 mA

1 load

Max via current

0.00101 mA

3 vias

Copper loss

7.43e-11 mW

Signal Layer 2 3.93e-11 mW · Top Layer 2.71e-11 mW

Peak |J|

0.000433 A/mm²

current density

5.1Findings

No issues on this rail.

5.2Power path

5.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#1	NetC128_2	1	0.001 mA	3.300 V	0.119 mV	0.119 mV	3.070 V	+230 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.300 V setpoint. Every pin is listed in the appendix.

5.4Heatmaps

5.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetC128_2	1.1 oz	7.85e−05 mV	0.000433 A/mm²	(63.12, 31.39)	2.71e-11 mW	36%
Signal Layer 1	NetC128_2	1 oz	5.13e−05 mV	2.05e-08 A/mm²	(63.83, 29.50)	2.79e-21 mW	0%
Signal Layer 2	NetC128_2	1 oz	4.77e−05 mV	0.000108 A/mm²	(55.55, 25.86)	3.93e-11 mW	53%
Bottom Layer	NetC128_2	1.1 oz	4.75e−05 mV	0.000379 A/mm²	(64.76, 27.41)	7.93e-12 mW	11%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

5.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(36.05, 29.02)	Top Layer → Bottom Layer	0.30 mm · —	0.00101 mA	1.53e−06 mV	1.54e-12 mW	PASS
(64.03, 29.53)	Top Layer → Bottom Layer	0.20 mm · —	0.00101 mA	2.54e−06 mV	2.56e-12 mW	PASS
(64.75, 26.00)	Top Layer → Bottom Layer	0.30 mm · —	0.00101 mA	1.09e−07 mV	1.11e-13 mW	PASS

Showing 3 of 3 vias, highest current first. Limit 1 A per via.

5.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#1	LDO	VBUS → VDD3V3_USB	3.300 V	4.976 V	0.001 mA	0.001 mA	0.00168 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

5.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

5.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

6 · VDDIO

PASS 1 uncheckedU9#8 (LDO, from VBUS) · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.299 V

U7#10 · min 2.700 V

Worst drop

1.4 mV

0.042 % of 3.300 V

Load

46.5 mA

11 loads

Max via current

24.2 mA

31 vias

Copper loss

0.0532 mW

Top Layer 0.032 mW · Signal Layer 2 0.0211 mW

Peak |J|

5.27 A/mm²

current density

6.1Findings

• UNCHECKED
  No PDN_MIN_V on 7 of 11 sinks

  The drop at R93#1, R92#1, R73#1, R72#1 and 3 more was calculated but not compared against a limit.

6.2Power path

6.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
R93#1	VDDIO	1	1.1 mA	3.299 V	1.19 mV	0.119 mV	—	no limit	UNCHECKED
R92#1	VDDIO	1	1.1 mA	3.299 V	1.19 mV	0.119 mV	—	no limit	UNCHECKED
R73#1	VDDIO	1	0.165 mA	3.299 V	1.07 mV	0.119 mV	—	no limit	UNCHECKED
R72#1	VDDIO	1	0.165 mA	3.299 V	1.07 mV	0.119 mV	—	no limit	UNCHECKED
R83#1	VDDIO	1	1.1 mA	3.299 V	1.04 mV	0.119 mV	—	no limit	UNCHECKED
R84#1	VDDIO	1	1.1 mA	3.299 V	1.04 mV	0.119 mV	—	no limit	UNCHECKED
U7#10	VDDIO	4	2.35 mA	3.299 V	1.4 mV	0.119 mV	2.700 V	+599 mV	PASS
U7#11	VDDIO	2	0.913 mA	3.299 V	1.1 mV	0.119 mV	2.700 V	+599 mV	PASS
U7#12	VDDIO	4	32.6 mA	3.299 V	1.4 mV	0.119 mV	2.700 V	+599 mV	PASS
U7#13	VDDIO	1	5.77 mA	3.299 V	1.1 mV	0.119 mV	2.700 V	+599 mV	PASS
R107#1	VDDIO	1	0.165 mA	3.299 V	1.09 mV	0.119 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.300 V setpoint. Every pin is listed in the appendix.

6.4Heatmaps

6.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDDIO	1.1 oz	1.28 mV	5.27 A/mm²	(26.07, 31.25)	0.032 mW	60%
Signal Layer 1	VDDIO	1 oz	0.585 mV	2.04e-08 A/mm²	(58.97, 33.52)	1.6e-20 mW	0%
Signal Layer 2	VDDIO	1 oz	0.525 mV	1.49 A/mm²	(55.79, 33.77)	0.0211 mW	40%
Bottom Layer	VDDIO	1.1 oz	0.525 mV	0.306 A/mm²	(36.08, 38.14)	2.43e-05 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

6.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(19.90, 31.33)	Top Layer → Bottom Layer	0.30 mm · —	24.2 mA	0.0367 mV	0.000889 mW	PASS
(19.45, 31.98)	Top Layer → Bottom Layer	0.30 mm · —	22.3 mA	0.0338 mV	0.000752 mW	PASS
(57.33, 33.62)	Top Layer → Bottom Layer	0.20 mm · —	13.4 mA	0.0314 mV	0.000425 mW	PASS
(58.33, 33.62)	Top Layer → Bottom Layer	0.20 mm · —	12.2 mA	0.029 mV	0.000353 mW	PASS
(59.15, 33.44)	Top Layer → Bottom Layer	0.20 mm · —	9.27 mA	0.0219 mV	0.000202 mW	PASS

Showing 5 of 31 vias, highest current first. Limit 1 A per via.

6.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#8	LDO	VBUS → VDDIO	3.300 V	4.976 V	46.5 mA	46.5 mA	77.9 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

6.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

6.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

7 · VDD_FLASH

PASS 1 uncheckedU9#9 (LDO, from VBUS) · nets VDD_FLASH, VDD_SDCARD · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

3.295 V

CN7#1

Worst drop

4.62 mV

0.14 % of 3.300 V

Load

0.1 A

7 loads

Max via current

0.1 A

5 vias

Copper loss

0.39 mW

Top Layer 0.184 mW · Bottom Layer 0.104 mW

Peak |J|

33.5 A/mm²

current density

7.1Findings

• UNCHECKED
  No PDN_MIN_V on any sink

  The drop at R6#1, R8#1, R77#1, R10#1 and 3 more was calculated but not compared against a limit.

7.2Power path

7.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
R6#1	VDD_SDCARD	1	0.0351 mA	3.296 V	4.13 mV	0.0405 mV	—	no limit	UNCHECKED
R8#1	VDD_SDCARD	1	0.0351 mA	3.295 V	4.53 mV	0.0405 mV	—	no limit	UNCHECKED
R77#1	VDD_SDCARD	1	0.0351 mA	3.296 V	4.37 mV	0.0398 mV	—	no limit	UNCHECKED
R10#1	VDD_SDCARD	1	0.0351 mA	3.295 V	4.53 mV	0.0405 mV	—	no limit	UNCHECKED
R13#1	VDD_SDCARD	1	0.0351 mA	3.297 V	3.09 mV	0.0405 mV	—	no limit	UNCHECKED
R78#1	VDD_SDCARD	1	0.165 mA	3.296 V	4.37 mV	0.0398 mV	—	no limit	UNCHECKED
CN7#1	VDD_SDCARD	1	0.1 A	3.295 V	4.62 mV	0.0549 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 3.300 V setpoint. Every pin is listed in the appendix.

7.4Heatmaps

7.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDD_SDCARD	1.1 oz	4.56 mV	33.5 A/mm²	(20.26, 47.56)	0.184 mW	47%
Signal Layer 1	VDD_SDCARD	1 oz	3.08 mV	4.29e-09 A/mm²	(17.17, 54.63)	1.44e-21 mW	0%
Signal Layer 2	VDD_SDCARD	1 oz	2.8 mV	5.82 A/mm²	(17.20, 32.77)	0.101 mW	26%
Bottom Layer	VDD_SDCARD	1.1 oz	2.79 mV	12.7 A/mm²	(16.21, 54.46)	0.104 mW	27%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

7.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(17.37, 32.70)	Top Layer → Bottom Layer	0.30 mm · —	0.1 A	0.152 mV	0.0153 mW	PASS
(20.25, 46.77)	Top Layer → Bottom Layer	0.30 mm · —	0.1 A	0.152 mV	0.0153 mW	PASS
(17.25, 48.45)	Top Layer → Bottom Layer	0.30 mm · —	0.1 A	0.163 mV	0.0163 mW	PASS
(17.13, 54.80)	Top Layer → Bottom Layer	0.30 mm · —	0.1 A	0.163 mV	0.0163 mW	PASS
(17.15, 58.85)	Top Layer → Bottom Layer	0.30 mm · —	0.0351 mA	5.7e−05 mV	2e-09 mW	PASS

Showing 5 of 5 vias, highest current first. Limit 1 A per via.

7.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
R14#1	Resistor	VDD_SDCARD → 3V3	5e+08 Ω	-5.99e-09 mA	−2.99 mV	1.79e-11 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#9	LDO	VBUS → VDD_FLASH	3.300 V	4.976 V	0.1 A	0.1 A	168 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

7.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

7.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

8 · NetC130_2

PASS 1 uncheckedU9#3 (LDO, from VBUS) · nets NetC130_2, VDDA1V8 · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.800 V

U7#3 · min 1.710 V

Worst drop

0.346 mV

0.019 % of 1.800 V

Load

5.38 mA

11 loads

Max via current

5.38 mA

17 vias

Copper loss

0.000957 mW

Top Layer 0.00044 mW · Bottom Layer 0.00037 mW

Peak |J|

0.783 A/mm²

current density

8.1Findings

• UNCHECKED
  No PDN_MIN_V on 6 of 11 sinks

  The drop at R9#1, R82#1, R80#1, R16#1 and 2 more was calculated but not compared against a limit.

8.2Power path

8.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#2	VDDA1V8	1	0.355 mA	1.800 V	0.249 mV	0.119 mV	1.620 V	+180 mV	PASS
U7#3	VDDA1V8	6	2.2 mA	1.800 V	0.346 mV	0.119 mV	1.710 V	+89.7 mV	PASS
U7#4	VDDA1V8	1	2.7 mA	1.800 V	0.346 mV	0.119 mV	1.710 V	+89.7 mV	PASS
U22#2	VDDA1V8	1	0.005 mA	1.800 V	0.19 mV	0.0166 mV	0.900 V	+900 mV	PASS
U21#2	VDDA1V8	1	0.005 mA	1.800 V	0.191 mV	0.0176 mV	0.900 V	+900 mV	PASS
R9#1	VDDA1V8	1	0.0191 mA	1.800 V	0.191 mV	0.0176 mV	—	no limit	UNCHECKED
R82#1	VDDA1V8	1	0.0191 mA	1.800 V	0.291 mV	0.119 mV	—	no limit	UNCHECKED
R80#1	VDDA1V8	1	0.0191 mA	1.800 V	0.292 mV	0.119 mV	—	no limit	UNCHECKED
R16#1	VDDA1V8	1	0.0191 mA	1.800 V	0.291 mV	0.119 mV	—	no limit	UNCHECKED
R79#1	VDDA1V8	1	0.0191 mA	1.800 V	0.292 mV	0.119 mV	—	no limit	UNCHECKED
R19#1	VDDA1V8	1	0.0191 mA	1.800 V	0.291 mV	0.119 mV	—	no limit	UNCHECKED

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.800 V setpoint. Every pin is listed in the appendix.

8.4Heatmaps

8.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDDA1V8	1.1 oz	0.227 mV	0.783 A/mm²	(29.62, 32.81)	0.00044 mW	46%
Signal Layer 1	VDDA1V8	1 oz	0.144 mV	1.41e-08 A/mm²	(58.83, 38.11)	4.2e-21 mW	0%
Signal Layer 2	VDDA1V8	1 oz	0.13 mV	0.134 A/mm²	(34.52, 29.51)	0.000147 mW	15%
Bottom Layer	VDDA1V8	1.1 oz	0.13 mV	0.493 A/mm²	(59.41, 38.99)	0.00037 mW	39%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

8.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(34.10, 29.50)	Top Layer → Bottom Layer	0.30 mm · —	5.38 mA	0.00856 mV	4.54e-05 mW	PASS
(32.40, 48.05)	Top Layer → Bottom Layer	0.30 mm · —	3.72 mA	0.000406 mV	1.51e-06 mW	PASS
(59.03, 38.08)	Top Layer → Bottom Layer	0.20 mm · —	2.56 mA	0.00646 mV	1.65e-05 mW	PASS
(60.85, 44.45)	Top Layer → Bottom Layer	0.30 mm · —	2.56 mA	0.000279 mV	7.13e-07 mW	PASS
(63.75, 26.00)	Top Layer → Bottom Layer	0.30 mm · —	1.3 mA	0.000142 mV	1.85e-07 mW	PASS

Showing 5 of 17 vias, highest current first. Limit 1 A per via.

8.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#3	LDO	VBUS → NetC130_2	1.800 V	4.976 V	5.38 mA	5.38 mA	17.1 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

8.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

8.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

9 · VDD1_DDR

PASSU9#2 (LDO, from VBUS) · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.800 V

U8#1 · min 1.700 V

Worst drop

0.117 mV

0.0065 % of 1.800 V

Load

3.4 mA

1 load

Max via current

3.4 mA

5 vias

Copper loss

0.000208 mW

Top Layer 9.78e-05 mW · Signal Layer 2 7.64e-05 mW

Peak |J|

0.387 A/mm²

current density

9.1Findings

No issues on this rail.

9.2Power path

9.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U8#1	VDD1_DDR	8	3.4 mA	1.800 V	0.117 mV	0.0278 mV	1.700 V	+99.9 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.800 V setpoint. Every pin is listed in the appendix.

9.4Heatmaps

9.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDD1_DDR	1.1 oz	0.0893 mV	0.387 A/mm²	(76.64, 29.34)	9.78e-05 mW	47%
Signal Layer 1	VDD1_DDR	1 oz	0.0722 mV	1.02e-08 A/mm²	(76.64, 35.64)	7.57e-22 mW	0%
Signal Layer 2	VDD1_DDR	1 oz	0.0674 mV	0.126 A/mm²	(47.52, 25.90)	7.64e-05 mW	37%
Bottom Layer	VDD1_DDR	1.1 oz	0.067 mV	0.186 A/mm²	(35.36, 29.12)	3.41e-05 mW	16%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

9.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(33.18, 33.10)	Top Layer → Bottom Layer	0.30 mm · —	3.4 mA	0.00552 mV	1.88e-05 mW	PASS
(77.02, 28.64)	Top Layer → Bottom Layer	0.30 mm · —	3.4 mA	0.00515 mV	1.75e-05 mW	PASS
(35.30, 28.75)	Top Layer → Bottom Layer	0.30 mm · —	1.84 mA	0.000201 mV	3.7e-07 mW	PASS
(34.55, 28.72)	Top Layer → Bottom Layer	0.30 mm · —	1.56 mA	0.00017 mV	2.65e-07 mW	PASS
(76.45, 35.61)	Top Layer → Bottom Layer	0.20 mm · —	8.97e-07 mA	1.35e−09 mV	7.79e-19 mW	PASS

Showing 5 of 5 vias, highest current first. Limit 1 A per via.

9.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#2	LDO	VBUS → VDD1_DDR	1.800 V	4.976 V	3.4 mA	3.4 mA	10.8 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

9.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

9.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

10 · VDDA1V8_AON

PASSU9#4 (LDO, from VBUS) · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.800 V

U7#5 · min 1.710 V

Worst drop

0.317 mV

0.018 % of 1.800 V

Load

3.15 mA

1 load

Max via current

3.15 mA

3 vias

Copper loss

0.000587 mW

Signal Layer 2 0.000298 mW · Top Layer 0.000288 mW

Peak |J|

1.33 A/mm²

current density

10.1Findings

No issues on this rail.

10.2Power path

10.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#5	VDDA1V8_AON	1	3.15 mA	1.800 V	0.317 mV	0.119 mV	1.710 V	+89.7 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.800 V setpoint. Every pin is listed in the appendix.

10.4Heatmaps

10.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	VDDA1V8_AON	1.1 oz	0.198 mV	1.33 A/mm²	(53.93, 35.60)	0.000288 mW	49%
Signal Layer 1	VDDA1V8_AON	1 oz	0.106 mV	1.17e-08 A/mm²	(51.69, 35.38)	9.23e-22 mW	0%
Signal Layer 2	VDDA1V8_AON	1 oz	0.0947 mV	0.343 A/mm²	(52.05, 34.82)	0.000298 mW	51%
Bottom Layer	VDDA1V8_AON	1.1 oz	0.0947 mV	1.13e-08 A/mm²	(53.05, 33.86)	1.62e-21 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

10.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(36.15, 31.05)	Top Layer → Bottom Layer	0.30 mm · —	3.15 mA	0.00477 mV	1.5e-05 mW	PASS
(51.88, 35.41)	Top Layer → Bottom Layer	0.20 mm · —	3.15 mA	0.00742 mV	2.34e-05 mW	PASS
(53.25, 33.89)	Top Layer → Bottom Layer	0.20 mm · —	2.76e-07 mA	4.02e−10 mV	6.66e-20 mW	PASS

Showing 3 of 3 vias, highest current first. Limit 1 A per via.

10.7Series elements & regulators

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#4	LDO	VBUS → VDDA1V8_AON	1.800 V	4.976 V	3.15 mA	3.15 mA	10 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

10.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

10.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

11 · NetL3_1

PASS 1 uncheckedU9#5 (SMPS, from VBUS), remote sense at LNK3 · nets NetL3_1, VDD2_DDR · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

1.099 V

U7#6 · min 1.060 V

Worst drop

0.79 mV

0.072 % of 1.100 V

Load

0.114 A

4 loads

Max via current

30.8 mA

50 vias

Copper loss

0.0899 mW

Signal Layer 2 0.0609 mW · Top Layer 0.029 mW

Peak |J|

11.4 A/mm²

current density

11.1Findings

• UNCHECKED
  No PDN_MIN_V on 1 of 4 sinks

  The drop at R94#1 was calculated but not compared against a limit.

11.2Power path

11.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#6	VDD2_DDR	4	37 mA	1.099 V	0.79 mV	0.119 mV	1.060 V	+39.2 mV	PASS
U7#7	VDD2_DDR	4	58.4 mA	1.099 V	0.79 mV	0.119 mV	1.060 V	+39.2 mV	PASS
R94#1	VDD2_DDR	1	2.29 mA	1.099 V	0.587 mV	0.0278 mV	—	no limit	UNCHECKED
U8#2	VDD2_DDR	45	16.8 mA	1.099 V	0.591 mV	0.0278 mV	1.060 V	+39.4 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 1.100 V setpoint. Every pin is listed in the appendix.

11.4Heatmaps

11.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetL3_1, VDD2_DDR	1.1 oz	5.82 mV	11.4 A/mm²	(31.97, 35.68)	0.029 mW	32%
Signal Layer 1	VDD2_DDR	1 oz	0.643 mV	8.31e-09 A/mm²	(80.32, 38.99)	7.73e-21 mW	0%
Signal Layer 2	VDD2_DDR	1 oz	0.543 mV	2.14 A/mm²	(61.71, 34.34)	0.0609 mW	68%
Bottom Layer	VDD2_DDR	1.1 oz	0.543 mV	0.411 A/mm²	(70.04, 34.98)	1.06e-05 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

11.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(39.68, 34.80)	Top Layer → Bottom Layer	0.30 mm · —	30.8 mA	0.0467 mV	0.00144 mW	PASS
(39.68, 35.50)	Top Layer → Bottom Layer	0.30 mm · —	30.1 mA	0.0456 mV	0.00137 mW	PASS
(61.67, 34.44)	Top Layer → Bottom Layer	0.20 mm · —	28.7 mA	0.0673 mV	0.00194 mW	PASS
(40.40, 34.80)	Top Layer → Bottom Layer	0.30 mm · —	27.4 mA	0.0415 mV	0.00114 mW	PASS
(40.40, 35.50)	Top Layer → Bottom Layer	0.30 mm · —	26.1 mA	0.0396 mV	0.00103 mW	PASS

Showing 5 of 50 vias, highest current first. Limit 1 A per via.

11.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L3#1	Inductor	NetL3_1 → VDD2_DDR	43 mΩ	0.114 A	4.92 mV	0.563 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#5	SMPS · remote sense at LNK3	VBUS → NetL3_1	1.100 V	4.976 V	0.114 A	32.7 mA	36.2 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

11.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

11.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

12 · NetL2_1

PASSU9#6 (SMPS, from VBUS), remote sense at LNK1 · nets NetL2_1, VDDCORE · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

0.819 V

U7#8 · min 0.792 V

Worst drop

0.935 mV

0.11 % of 0.820 V

Load

84.5 mA

1 load

Max via current

25.1 mA

11 vias

Copper loss

0.0786 mW

Signal Layer 2 0.0606 mW · Top Layer 0.018 mW

Peak |J|

10.2 A/mm²

current density

12.1Findings

No issues on this rail.

12.2Power path

12.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#8	VDDCORE	7	84.5 mA	0.819 V	0.935 mV	0.119 mV	0.792 V	+27.1 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 0.820 V setpoint. Every pin is listed in the appendix.

12.4Heatmaps

12.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetL2_1, VDDCORE	1.1 oz	4.66 mV	10.2 A/mm²	(28.74, 38.60)	0.018 mW	23%
Signal Layer 1	VDDCORE	1 oz	0.81 mV	5.67e-09 A/mm²	(60.88, 33.47)	7.6e-22 mW	0%
Signal Layer 2	VDDCORE	1 oz	0.755 mV	2.95 A/mm²	(59.26, 33.93)	0.0606 mW	77%
Bottom Layer	VDDCORE	1.1 oz	0.755 mV	0.805 A/mm²	(57.59, 35.67)	4.02e-05 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

12.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(26.50, 45.50)	Top Layer → Bottom Layer	0.30 mm · —	25.1 mA	0.0381 mV	0.000956 mW	PASS
(25.43, 45.50)	Top Layer → Bottom Layer	0.30 mm · —	21.7 mA	0.0329 mV	0.000713 mW	PASS
(26.45, 46.43)	Top Layer → Bottom Layer	0.30 mm · —	20.5 mA	0.031 mV	0.000636 mW	PASS
(57.41, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	17.9 mA	0.0415 mV	0.000762 mW	PASS
(58.33, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	17.8 mA	0.0423 mV	0.00075 mW	PASS

Showing 5 of 11 vias, highest current first. Limit 1 A per via.

12.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L2#1	Inductor	NetL2_1 → VDDCORE	43 mΩ	84.5 mA	3.63 mV	0.307 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#6	SMPS · remote sense at LNK1	VBUS → NetL2_1	0.820 V	4.976 V	84.5 mA	18 mA	19.9 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

12.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

12.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

13 · NetL1_1

PASSU9#7 (SMPS, from VBUS), remote sense at LNK2 · nets NetL1_1, VDDCPU · copper on Top Layer, Signal Layer 1, Signal Layer 2, Bottom Layer

Lowest load

0.799 V

U7#9 · min 0.768 V

Worst drop

0.534 mV

0.067 % of 0.800 V

Load

57 mA

1 load

Max via current

16.9 mA

8 vias

Copper loss

0.0275 mW

Signal Layer 2 0.0187 mW · Top Layer 0.00887 mW

Peak |J|

6.85 A/mm²

current density

13.1Findings

No issues on this rail.

13.2Power path

13.3DC voltage at loads

Load	Net	Pins	Current	V at load	Drop	in return	Min V	Margin	Status
U7#9	VDDCPU	5	57 mA	0.799 V	0.534 mV	0.119 mV	0.768 V	+31.5 mV	PASS

V at load is the lowest supply pin minus the highest return pin. Drop is measured from the 0.800 V setpoint. Every pin is listed in the appendix.

13.4Heatmaps

13.5Copper by layer

Layer	Nets	Copper	V spread	Peak |J|	at (mm)	Loss	Share
Top Layer	NetL1_1, VDDCPU	1.1 oz	3 mV	6.85 A/mm²	(30.27, 38.60)	0.00887 mW	32%
Signal Layer 1	VDDCPU	1 oz	0.389 mV	5.3e-09 A/mm²	(59.14, 35.76)	5.48e-22 mW	0%
Signal Layer 2	VDDCPU	1 oz	0.337 mV	2.56 A/mm²	(59.34, 38.22)	0.0187 mW	68%
Bottom Layer	VDDCPU	1.1 oz	0.337 mV	0.183 A/mm²	(60.13, 35.75)	2.25e-06 mW	0%

V spread is the highest minus the lowest voltage on the layer's rail copper. Peak |J| is the 99.9th percentile of the mesh, so single-vertex pin singularities are ignored.

13.6Vias

Location (mm)	Span	Drill · fill	|I|	ΔV	Power	Status
(36.95, 43.80)	Top Layer → Bottom Layer	0.30 mm · —	16.9 mA	0.0256 mV	0.000432 mW	PASS
(36.15, 43.80)	Top Layer → Bottom Layer	0.30 mm · —	16.4 mA	0.0248 mV	0.000405 mW	PASS
(59.83, 37.25)	Top Layer → Bottom Layer	0.20 mm · —	15.5 mA	0.0365 mV	0.000565 mW	PASS
(60.33, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	15.1 mA	0.0356 mV	0.000538 mW	PASS
(59.33, 35.78)	Top Layer → Bottom Layer	0.20 mm · —	14.7 mA	0.0346 mV	0.000512 mW	PASS

Showing 5 of 8 vias, highest current first. Limit 1 A per via.

13.7Series elements & regulators

Part	Kind	Nets	R	I	ΔV	Loss
L1#1	Inductor	NetL1_1 → VDDCPU	43 mΩ	57 mA	2.45 mV	0.14 mW

Regulator	Kind	Rails	V out	V in	I out	I in (est.)	Loss
U9#7	SMPS · remote sense at LNK2	VBUS → NetL1_1	0.800 V	4.976 V	57 mA	11.8 mA	13.2 mW

V in is measured at the input pins. I in is estimated as gain × I out + quiescent current.

13.8Decoupling & PDN impedance

Not analysed. Capacitor and impedance analysis runs in the viewer (File > Export > Report…), not from the command line.

13.9Thermal

Not analysed. Electrothermal coupling was off for this solve.

A · Setup & assumptions

Stackup

All load pins

Review

FYPA is a design aid. Validate results against measurement.