KiPI power-integrity report

Voltages: mV from target% from targetVolts From the target voltage, negative is a drop below it and positive a boost above it.

Mesh: max edge 0.5 mm, via grading 0.2, copper resistivity 1.724e-08 Ω·m at 20 °C (TCR 0.00393/°C); copper solved at 40 °C, the board's ambient. Via plating, first matching rule (drill = hole in the laminate, plated inward): micro any drill: 12 um, if filled: non-conductive epoxy; buried any drill: 13 um, if filled: non-conductive epoxy; blind any drill: 20 um, if filled: non-conductive epoxy; blind_buried any drill: 20 um, if filled: non-conductive epoxy; through any drill: 20 um, if filled: non-conductive epoxy; pth any drill: 20 um, if filled: non-conductive epoxy; any any drill: 20 um, if filled: non-conductive epoxy.

Stackup, top to bottom: top silkscreen 2.54 µm, top solder mask 24.99 µm, TOP_LAYER 37 µm, dielectric 70 µm εr 3.8, SIGNAL_LAYER_1 35 µm, dielectric 1330 µm εr 4.3, SIGNAL_LAYER_2 35 µm, dielectric 70 µm εr 3.8, BOTTOM_LAYER 37 µm, bottom solder mask 24.99 µm, bottom silkscreen 2.54 µm; 1.614 mm in all.

Power-tree import

What the imported power-tree file could not place, or what was assumed:

• Thermal: load power is included (Thermal settings tab), from the loads' currents and stated heat
• Temperature: every solve at the board's maximum ambient, 40 °C: copper resistivity, parts with a temperature model, capacitor dielectrics (Thermal and AC settings)
• Via plating from the file (ipc6012_class2_min): through 20 um, blind 20 um, buried 13 um, microvia 12 um; change it in Via rules
• Each load's pads are one node (KiPI's default without the file: current shared equally over the pads)
• Rail VBAT: no source traced; its loads are not imported
• U14: several DC-resistance figures printed; the highest of each is used
• U14 (5V_VIN): load switch, imported as a DC connection from VBUS to 5V_VIN, not a regulator
• U23 3V3: remote sense at R88[2] (FB) on 3V3
• L6: inside U23's regulation loop, so its DC resistance lowers nothing (its loss is in the efficiency); modeled as a short
• U9 VDD2_DDR: remote sense at LNK3[2] (VOUT2) on VDD2_DDR
• L3: inside U9's regulation loop, so its DC resistance lowers nothing (its loss is in the efficiency); modeled as a short
• Rail LCD_BL_A: voltage not stated, so it has no source; its loads are not imported
• U9 VDDCORE: remote sense at LNK1[2] (VOUT1) on VDDCORE
• L2: inside U9's regulation loop, so its DC resistance lowers nothing (its loss is in the efficiency); modeled as a short
• U9 VDDCPU: remote sense at LNK2[2] (VOUT3) on VDDCPU
• L1: inside U9's regulation loop, so its DC resistance lowers nothing (its loss is in the efficiency); modeled as a short
• U17: only a maximum current is known; 750 µA is used
• U16: only a maximum current is known; 750 µA is used
• U15 (3V3): 2 die supplies, but the file names none as the current's; solved as one node
• U7: package resistance per ball is its terminal's times its ball count (an equal share) for VDD33USB
• U7 (NetC130_2): package resistance per ball is its terminal's times its ball count (an equal share) for VDDA18ADC
• U7 (VDDA1V8): package resistance per ball is its terminal's times its ball count (an equal share) for VDDA18DDR, VDDIO2, VDDA18USB, VDDA18PLL1, VDDA18CSI, VDDA18PLL2
• U7 (VDDA1V8) [VDDIO2]: I/O current 2.7 mA ESTIMATED, not a data-sheet figure (5 of 6 VDDIO2 bank pins connected (not connected: U7_C15): U7_A14 M2.SDMMC2_D0: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_A15 M2.SDMMC2_D3: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_B14 M2.SDMMC2_D1: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA; U7_D14 M2.SDMMC2_CK: SDMMC clock 50 MHz, 20 pF x 1.8 V x f = 1.8 mA; U7_E11 M2.SDMMC2_CMD: SDMMC data 50 Mb/s, 20 pF x 1.8 V x rate/4 x 0.5 driven by this ball = 0.225 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• U7 (VDDA1V8): 6 die supplies, but the file names none as the current's; solved as one node with the I/O currents (2.7 mA) added
• U7 (VDDA1V8_AON): package resistance per ball is its terminal's times its ball count (an equal share) for PDR_ON, VDDA18AON
• U7 (VDDA1V8_AON): its current is VDDA18AON's; PDR_ON draws none stated (0 A solved)
• U7 (VREF+): package resistance per ball is its terminal's times its ball count (an equal share) for VREFP
• U7 (VDD2_DDR): package resistance per ball is its terminal's times its ball count (an equal share) for VDDQDDR
• U7 (VDD2_DDR) [VDDQDDR]: I/O current 58.4 mA ESTIMATED, not a data-sheet figure (32 of 52 VDDQDDR bank pins connected (not connected: U7_F18, U7_F21, U7_G19, U7_G21, U7_H18, U7_H20, U7_J17, U7_K18, U7_K19, U7_K20, U7_K21, U7_L17, U7_L19, U7_M19, U7_M20, U7_N19, U7_P18, U7_P19, U7_P20, U7_P21): 32 LPDDR4 LVSTL x 7.3 mA x 25 % - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• U8 (VDD2_DDR): 3 die supplies, but the file names none as the current's; solved as one node
• U7 (VDDCORE): package resistance per ball is its terminal's times its ball count (an equal share) for VDDCORE, VDDCSI
• U7 (VDDCORE): its current is VDDCORE's; VDDCSI draws none stated (0 A solved)
• U7 (VDDCPU): package resistance per ball is its terminal's times its ball count (an equal share) for VDDCPU
• U7 on VDDIO: draws what it drives (figure is with all peripherals disabled; VDD/VDDIO1/VDDIO3 I/O current follows pin activity and loads)
• U7 (VDDIO): package resistance per ball is its terminal's times its ball count (an equal share) for VDDIO3, VDD, VDDIO1
• U7 (VDDIO) [VDDIO3]: I/O current 913.4 µA ESTIMATED, not a data-sheet figure (11 of 12 VDDIO3 bank pins connected (not connected: U7_E15): U7_A6 SD.uSD_DETECT: static line: 0 = 0 mA; U7_B4 M2.SAI1_SCKA: SAI clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_B6 M2.SAI1_SDB: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_B7 M2.SAI1_FSA: SAI static line: 0 = 0 mA; U7_B11 BT_HOST_WAKE: static line: 0 = 0 mA; U7_C4 GPIO.SPI1_NSS: SPI static line: 0 = 0 mA; U7_C7 GPIO.SPI1_MISO: SPI input: 0 = 0 mA; U7_C9 M2.SAI1_SDA: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_C10 CAM_RESET: static line: 0 = 0 mA; U7_D4 GPIO.SPI1_SCK: SPI clock 10 MHz, 20 pF x 3.3 V x f = 0.66 mA; U7_D8 CAM_ENABLE: static line: 0 = 0 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• U7 (VDDIO) [VDD]: I/O current 32.58 mA ESTIMATED, not a data-sheet figure (102 of 110 VDD bank pins connected (not connected: U7_A10, U7_AA10, U7_D6, U7_K2, U7_V6, U7_V14, U7_W12, U7_Y18): U7_A7 I2C2.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_A18 GPIO.SDMMC3_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_A19 GPIO.SDMMC3_D1: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_AA6 LED2: resistive load, on all the time (upper bound): R57 100k to GND: V/R 0.033 mA = 0.033 mA; U7_AA7 LCD_BL: resistive load, on all the time (upper bound): R75 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_AA11 ETH1.MDIO: MDIO data 2.5 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0206 mA; U7_AA14 LED3: resistive load, on all the time (upper bound): R56 100k to GND: V/R 0.033 mA = 0.033 mA; U7_AA15 UART4_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_AA18 LED1: static line: 0 = 0 mA; U7_B8 USART1_RTS: UART static line: 0 = 0 mA; U7_B10 MDF.SDI3: MDF input: 0 = 0 mA; U7_B16 GPIO.SDMMC3_D0: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_B18 GPIO.SDMMC3_CMD: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C5 BT_REG_ON: static line: 0 = 0 mA; U7_C6 USART1_CTS: UART static line: 0 = 0 mA; U7_C8 USART1_RX: UART input: 0 = 0 mA; U7_C16 GPIO.SDMMC3_CK: SDMMC clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_C17 GPIO.SDMMC3_D3: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D3 LCD_VSYNC: LTDC static line: 0 = 0 mA; U7_E3 LCD_HSYNC: LTDC static line: 0 = 0 mA; U7_E4 LCD_DE: LTDC static line: 0 = 0 mA; U7_E5 GPIO.SPI1_MOSI: SPI data 10 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.165 mA; U7_E7 I2C2.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_E9 WL_REG_ON: static line: 0 = 0 mA; U7_F1 LCD_B4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F2 LCD_B5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F3 LCD_B6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_F4 LCD_B3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_G1 USART1_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_G2 LCD_B2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_G3 BUTTON.TAMP: static line: 0 = 0 mA; U7_G5 LCD_B7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H2 LCD_G6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H3 LCD_G5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_H4 LCD_G4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_J3 LCD_G3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_J5 LCD_G7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_K1 GPIO.SAI2_SDB: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_K3 LCD_G2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_K4 I2C3.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_K6 LED4: resistive load, on all the time (upper bound): R55 100k to GND: V/R 0.033 mA = 0.033 mA; U7_L3 LCD_R7: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_L5 I2C3.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_M2 LCD_R6: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_M3 LCD_INT: LTDC input: 0 = 0 mA; U7_M4 LCD_R5: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_N3 LCD_R4: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_N5 LCD_R3: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_P1 GPIO.USART6_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; U7_P2 GPIO.USART6_CTS: UART static line: 0 = 0 mA; U7_P3 LCD_R2: LTDC data 33.3 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.549 mA; U7_P4 BUTTON.USER2: static line: 0 = 0 mA; U7_P6 LCD_DISP: resistive load, on all the time (upper bound): R1 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_R5 BUTTON.USER1: static line: 0 = 0 mA; U7_T2 NRSTC1MS: static line: 0 = 0 mA; U7_T3 I3C1.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_T4 LPO_32: LPO clock 32.77 kHz, 20 pF x 3.3 V x f = 0.00216 mA; U7_T8 I3C2.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_T10 GPIO.GPIO7: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_T12 GPIO.USART6_RTS: UART static line: 0 = 0 mA; U7_T14 ETH1.CLK: RMII clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_T16 GPIO.SAI2_SCKB: SAI clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_U3 LCD_CLK: LTDC clock 33.3 MHz, 20 pF x 3.3 V x f = 2.2 mA; U7_U5 LCD_RST: resistive load, on all the time (upper bound): R2 4.7k to GND: V/R 0.702 mA = 0.702 mA; U7_U7 GPIO.SAI2_SDA: SAI data 3.07 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.0253 mA; U7_U9 GPIO.TIM8_CH4: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_U11 ETH1.TXD0: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_U13 MDF.CCK0: MDF clock 3.07 MHz, 20 pF x 3.3 V x f = 0.203 mA; U7_U15 GPIO.USART6_RX: UART input: 0 = 0 mA; U7_V1 JTCK_SWCLK: static line: 0 = 0 mA; U7_V2 JTMS_SWDIO: static line: 0 = 0 mA; U7_V3 NJTRST: static line: 0 = 0 mA; U7_V4 PWR_CPU_ON: static line: 0 = 0 mA; U7_V10 ETH1.TXD1: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_V12 ETH1.TX_EN: RMII data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.825 mA; U7_V16 USART2_RX: UART input: 0 = 0 mA; U7_W1 JTDO_SWDO: static line: 0 = 0 mA; U7_W2 JTDI: static line: 0 = 0 mA; U7_W3 PWR_LP: static line: 0 = 0 mA; U7_W4 PWR_ON: static line: 0 = 0 mA; U7_W7 MCO1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W10 GPIO.TIM13_CH1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W11 ETH1.RXD0: RMII input: 0 = 0 mA; U7_W13 GPIO.TIM11_CH1: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_W14 ETH1.NRST: resistive load, on all the time (upper bound): R38 10k to GND: V/R 0.33 mA = 0.33 mA; U7_W15 ETH1.CRS_DV: RMII input: 0 = 0 mA; U7_W16 GPIO.SAI2_FSB: SAI static line: 0 = 0 mA; U7_W17 I3C1.SDA: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_Y6 PA0_INT: static line: 0 = 0 mA; U7_Y7 I3C2.SCL: I2C open drain: 0 at the bank (the pull-up's current is its rail's) = 0 mA; U7_Y10 GPIO.TIM8_CH2: function not shown: 2 mA x 50 % (upper bound) = 1 mA; U7_Y11 ETH1.MDC: MDIO clock 2.5 MHz, 20 pF x 3.3 V x f = 0.165 mA; U7_Y12 ETH1.RXD1: RMII input: 0 = 0 mA; U7_Y14 ETH1.MDINT: RMII input: 0 = 0 mA; U7_Y15 UART4_RX: UART input: 0 = 0 mA; U7_Y16 USART2_TX: UART data 115.2 kb/s, 20 pF x 3.3 V x rate/4 x 1 driven by this ball = 0.0019 mA; 6 input-only x 0 - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• U7 (VDDIO) [VDDIO1]: I/O current 5.775 mA ESTIMATED, not a data-sheet figure (7 of 10 VDDIO1 bank pins connected (not connected: U7_B15, U7_C14, U7_E13): U7_A11 SD.SDMMC1_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_B12 SD.SDMMC1_CMD: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C11 SD.SDMMC1_D3: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_C12 SD.SDMMC1_CK: SDMMC clock 50 MHz, 20 pF x 3.3 V x f = 3.3 mA; U7_C13 M2.SDMMC2_D2: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D10 SD.SDMMC1_D1: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA; U7_D12 SD.SDMMC1_D0: SDMMC data 50 Mb/s, 20 pF x 3.3 V x rate/4 x 0.5 driven by this ball = 0.412 mA - assumed activity, not data-sheet figures, for the designer to replace with the bank's real current in the PI tool); change it to the bank's real current
• U7 (VDDIO): its current is VDD's
• Capacitor models (AC): 14 added and 0 filled in by part number (by value and ESL where none is given), with their ESL; 14 have no ESR in the file, to be entered before an AC sweep
• Draw what they drive: their own (static) current from the datasheet is solved, what they drive is on top and not known, the Headroom results say how much that may add: U7 (VDDIO) (2.35 mA)
• No supply voltage range is stated for these ICs, so they are not judged PASS / FAIL; enter it on the Loads tab when known: U12, U13, U7 (VREF+)
• Current not known, imported as 0 A and marked not known (the Headroom results say how much they may add together); enter it on the Loads tab when known: U7 (VREF+)
• Output accuracy from the datasheets (a worst-case solve runs each VRM at its low end): U23 3V3 3.153 to 3.451 V at 40 C; U9 VDD3V3_USB 3.23 to 3.4 V at 40 C; U9 VDD1_DDR 1.728 to 1.872 V at 40 C; U9 VDDA1V8 1.728 to 1.872 V at 40 C; U9 VDDA1V8_AON 1.728 to 1.872 V at 40 C; U9 VDD2_DDR 1.084 to 1.117 V at 40 C; U9 VDDCORE 0.8077 to 0.8323 V at 40 C; U9 VDDCPU 0.788 to 0.812 V at 40 C; U9 VDDIO 3.23 to 3.4 V at 40 C; U9 VDD_FLASH 3.23 to 3.4 V at 40 C
• Maximum currents and resistances are kept for a worst-case solve (beside Solve): 46 loads, 1 DC connections

Headroom: what the currents not known may add

A rail with a load whose current is not known (a header, what a translator drives) is solved at the known currents; the room is how much those loads may draw together before the tightest load leaves its tolerance, a bound however the current is shared (worst case, all of it at the costliest unknown), its ground return counted where it has ground pins. The VRM holds what it held.

• VDDA1V8 (+2 nets): 41 mA known. Not known: U7 (VREF+). Together they must stay under 475 mA, or U7 (VDDA1V8) (16.1 mV above its minimum) leaves its tolerance (worst case, all of it at U7 (VREF+): 33.88 mV per A). Through U9 VDDA1V8 the same current also loads 5V_VIN (+2 nets); not counted there.
• VDDIO: 52 mA known. Not known: U7 (VDDIO). Together they must stay under 15.5 A, or U7 (VDDIO) (528.1 mV above its minimum) leaves its tolerance (worst case, all of it at U7 (VDDIO): 34.12 mV per A). Through U9 VDDIO the same current also loads 5V_VIN (+2 nets); not counted there.

3V3 (+2 nets)

driven by U23 3V3; nets: 3V3, NetC53_2, NetL6_1.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

NetC128_2 (+1 net)

driven by U9 VDD3V3_USB; nets: NetC128_2, VDD3V3_USB.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDD1_DDR

driven by U9 VDD1_DDR; nets: VDD1_DDR.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDDA1V8 (+2 nets)

driven by U9 VDDA1V8; nets: NetC130_2, VDDA1V8, VREF+.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDDA1V8_AON

driven by U9 VDDA1V8_AON; nets: VDDA1V8_AON.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDD2_DDR (+1 net)

driven by U9 VDD2_DDR; nets: NetL3_1, VDD2_DDR.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDDCORE (+1 net)

driven by U9 VDDCORE; nets: NetL2_1, VDDCORE.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDDCPU (+1 net)

driven by U9 VDDCPU; nets: NetL1_1, VDDCPU.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDDIO

driven by U9 VDDIO; nets: VDDIO.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

VDD_SDCARD (+1 net)

driven by U9 VDD_FLASH; nets: VDD_FLASH, VDD_SDCARD.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

5V_VIN (+2 nets)

driven by CN10 VBUS; nets: 5V_VIN, VBUS, VL.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

GND

ground, referenced at CN10 VBUS; nets: GND.

Current-density maps clip at the 99.5th percentile; pad corners are singular and would otherwise wash out the map.

Loads

60 loads solved: 18 in range, 0 out of range, 42 with no voltage window to check against. Series parts: 5 within their rated current, 0 above, 6 with no rating to check. 2 rails with currents not known (VDDA1V8 (+2 nets), VDDIO): the Headroom tab says how much they may add.

Each load's mean voltage and its lowest and highest supply pins (less the ground pins), From the target, negative is a drop below it and positive a boost above it, e.g. near a remote-sensed VRM's output pins. The margin is how far the pins are inside the tolerance, negative when outside. A load passes when every pin is within its tolerance; in range at known currents when a load on the same rail has a current not known. Pre-layout margin: what the copper could take, worked out from the datasheets before layout (imported). Unknowns may add: what the rail's loads whose current is not known may draw together before this load leaves its tolerance.

Load pin groups

VRMs

Rail lowest: the lowest voltage anywhere on the copper of the rail the VRM drives. V out and it are from the rail's target voltage, the target V set less the load line's droop, above the ground the VRM regulates against: its ground sense pins (V gnd sense), else its own ground pins (V gnd). P out and P in are across the VRM, from its ground pins.

DC connections

Pins