PSU-EXT power supply board: power tree

Drawn by Tomachie from the KiCad schematic.

This diagram shows how power flows on this board, from the schematic: where it enters, each regulator, each rail, the parts it passes through and the loads on each rail. A large tree is split into several figures; a rail that continues in another figure names that figure.

Power Control / bias supply (EN, VCTRL) SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 10 loads, at least 4.4 mA R10 → U5_4 165 µA R11 → U5_5 165 µA R12 → U5_6 351 µA R13 → U5_7 351 µA R18 → U5_3 165 µA R5 → U2_4 250 µA R6 → U5_39 351 µA R7 → U5_38 351 µA U1 1 µA U5 draws what it drives U7 2.5 mA J2_4 leaves the board +5V 5 V V3.3 3.3 V V3.3-F Fig. 3 3.3 V V5-F 5 V VUSB 5 V SMPS PS1 5 V out efficiency 26 % U2 load switch LDO U3 3.3 V out LDO U4 3.3 V out SOURCE J1 5 V out Figure 2 J1 V3.3-F SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 9 loads, at least 5.28 mA R26 → U7_7 351 µA R27 → U7_6 351 µA R28 → U8_2 165 µA R30 → R31 → GNDS 138 µA R42 → U11_1 165 µA R43 → U11_6 165 µA U10 1.8 mA U11 draws what it drives U7 1.9 mA U8 150 µA U9 425 µA -3V3 -3.3 V V3.3-F Fig. 2 3.3 V SMPS U12 -3.3 V out Figure 3 V3.3-F V3.3-F SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) R29 0R PGND GNDS Figure 4 PGND SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) TERMINAL H8 H9 external load 10 V DC, up to 2.5 A K1 HF49FD_005-1H12T R25 10mR LOAD_P PSU_P SNT_N Figure 5 H8
Figure 1: Power tree overview
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 10 loads, at least 4.4 mA R10 → U5_4 165 µA R11 → U5_5 165 µA R12 → U5_6 351 µA R13 → U5_7 351 µA R18 → U5_3 165 µA R5 → U2_4 250 µA R6 → U5_39 351 µA R7 → U5_38 351 µA U1 1 µA U5 draws what it drives U7 2.5 mA J2_4 leaves the board +5V 5 V V3.3 3.3 V V3.3-F Fig. 3 3.3 V V5-F 5 V VUSB 5 V SMPS PS1 5 V out efficiency 26 % U2 load switch LDO U3 3.3 V out LDO U4 3.3 V out SOURCE J1 5 V out
Figure 2: power entering at J1
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) 9 loads, at least 5.28 mA R26 → U7_7 351 µA R27 → U7_6 351 µA R28 → U8_2 165 µA R30 → R31 → GNDS 138 µA R42 → U11_1 165 µA R43 → U11_6 165 µA U10 1.8 mA U11 draws what it drives U7 1.9 mA U8 150 µA U9 425 µA -3V3 -3.3 V V3.3-F Fig. 2 3.3 V SMPS U12 -3.3 V out
Figure 3: V3.3-F rail
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) R29 0R PGND GNDS
Figure 4: Chassis and shield connections
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SOURCE LDO SMPS MAKES A SUPPLY Rail Load Current unknown Power Control / bias supply (EN, VCTRL) TERMINAL H8 H9 external load 10 V DC, up to 2.5 A K1 HF49FD_005-1H12T R25 10mR LOAD_P PSU_P SNT_N
Figure 5: power carried through K1