More than schematic ERC - Reveals what first-pass review and ERC cannot.

Tomachie analyzes your Altium, KiCad, or OrCAD schematic files and extracts what's implicit: connectivity issues, ERC misses, interface validation, library quality grades, test coverage gaps, and documents the artifacts ready for formal review.¹

Upload ZIP → Parse Schematics → Analyze & Check → Render HTML → Email Link

Try it yourself: Download FPGA1394V3.zip — Xilinx FPGA PCB design with Firewire, multi-sheet hierarchy. Upload below to receive a full analysis report. (more PCB design reviews)
Design Review Pre-generated — see what the output looks like without uploading.

Submit Schematic for ERC, DFT and auto-documentation

No account needed — just enter your email to receive results. Links are valid for two weeks.

Email Address

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Schematic Files (ZIP)

Drop ZIP here or click to browse

ZIP containing schematic files: Altium (.SchDoc + .PrjPcb), KiCad (.kicad_sch + .kicad_pro), or OrCAD (coming soon). Add BSDL files for Boundary Scan analysis. KiCad users: include .kicad_dru if available for HSSI analysis.

Variant (optional)

0 = base (all components), 1+ = named variants

Top Level Sheet (optional)

Leave blank if .PrjPcb or .kicad_pro is included.

▸ Advanced Options

Test Point Insertion

Insert test points on:

Exclude BSCAN-testable nets

Tester Styles

Optical:

AXI (Automated X-ray Inspection)

ATE:

Test Access

LSSI connector IO connectors Bed of nails

Loopback:

Test Types

BSCAN:

NVM Programming

Default method:

Environment

Test environment:

Stats

Exclude footprints from public stats Exclude part numbers from public stats

Need extended privacy?

¹ Altium is a registered trademark of Altium Limited. KiCad is a trademark of the KiCad project. OrCAD is a registered trademark of Cadence Design Systems. Trademarks are used under fair use doctrine, solely to identify compatible file formats. No endorsement or affiliation is claimed.