FPGA3 Design Analysis

AI-Assisted The FPGA3 board is a Xilinx Zynq-7020 (XC7Z020-CLG400) system-on-chip platform with DDR3 memory, dual IEEE 1394a (FireWire) connectivity, dual Gigabit Ethernet, QSPI flash storage, and a microSD card interface. The design spans ten schematic sheets and contains 442 components across 367 nets. The board is intended as an embedded processing and communications module, with the Zynq SoC providing both programmable logic and a dual-core ARM Cortex-A9 processing system.

Primary Device

The central device is U1, a Xilinx XC7Z020-CLG400 in a 400-ball BGA package. This Zynq-7000 series SoC integrates a processing system (PS) with programmable logic (PL). The PS side drives MIO-multiplexed peripherals (MIO0 through MIO53 are present), while the PL side provides general-purpose I/O organized across multiple I/O banks. The FPGA configuration interface includes TCK, TDI, TDO, TMS for JTAG, along with DONE, INIT, and PROG signals. The CFGBVS pin (M6) sets the configuration bank voltage standard. A dedicated CLK input is present at pin E7.

Memory Subsystem

DDR3 SDRAM

Two Micron MT41K256M16 DDR3 SDRAM devices (U2 and U3) form a 32-bit-wide memory interface. Each device provides a 16-bit data path with two byte lanes. U2 handles the lower 16 bits (D0 through D15 with LDQS+/LDQS- and UDQS+/UDQS- strobes, plus LDM and UDM mask signals), and U3 handles the upper 16 bits in an identical arrangement. The address bus (A0 through A14), bank address (BA0 through BA2), and command signals (RAS, CAS, WE, CS, CKE, ODT) are shared between both devices. Differential clocks CLK+ and CLK- are routed to both memory ICs. Each device has a ZQ calibration pin for on-die termination calibration, and a RESET input. The VREF pin on each device receives a DDR3 reference voltage. The VDDQ supply for the memory devices is provided at 1.5V, consistent with standard DDR3 operation.

The boundary-scan analysis indicates full interconnect test coverage for both U2 and U3, with 47 of 47 testable connections verified for each device.

QSPI Flash

U4 is a Winbond W25Q128 128-Mbit serial NOR flash in an SOL-8 package, providing non-volatile storage for FPGA configuration bitstreams and processor boot code. The interface uses CS, SCLK, and four data lines (IO0/SDI, IO1/SDO, IO2/WP, IO3/HOLD) supporting Quad SPI operation. Boundary-scan interconnect testing covers five of six signals on this device.

MicroSD Card

Connector J5 is a JAE ST12S0 microSD card socket providing removable storage. The interface includes CMD, CLK, and four data lines (D0 through D3), along with a card-detect signal (CD). The VCC pin provides power to the card slot.

Power Supply Architecture

The board employs a multi-stage power distribution network using four power conversion devices to generate six regulated rails from an input supply.

LTC3636 Dual-Channel Synchronous Buck Converter

U16 (LTC3636) is a dual-channel 6A-per-channel synchronous buck converter from Analog Devices. It generates two rails. Channel 1 produces the VCC3 rail (3.3V) through inductor L2, serving as the primary logic and I/O supply with 120 pins connected across the design. Channel 2 produces the 5V-DCDC rail through inductor L1. The LTC3636 accepts an input voltage range of 3.1V to 20V and uses a 0.6V internal feedback reference. Each channel has independent RUN, feedback (FB1/FB2), compensation (ITH1/ITH2), soft-start (TRACK/SS1/TRACK/SS2), and power-good (PGOOD1/PGOOD2) pins. The RT pin programs the switching frequency, and MODE/SYNC selects the operating mode. A TMON output provides die temperature monitoring.

LTC3644 Quad-Channel Synchronous Buck Converter

U15 (LTC3644) is a quad-channel 1.25A-per-channel synchronous buck converter in a 36-ball BGA package. Three of its four channels are actively generating rails. Channel 1 produces the 1.0V rail through inductor L3, supplying 39 pins including the Zynq core voltage (VCC-INT). Channel 3 produces the 1.5V rail through inductor L4, supplying 99 pins including the DDR3 VDDQ domain. Channel 4 produces the 1.8V rail through inductor L5, supplying 41 pins including auxiliary logic and I/O bank voltages. Each channel has independent RUN, FB, PGOOD, and switch node (SW) pins. The PHASE pin sets the phase relationship between channel pairs, and MODE/SYNC controls the operating mode. The SVIN pin powers the internal LDO that generates INTVCC.

LP2998 DDR Termination Regulator

U18 (LP2998) is a Texas Instruments DDR termination regulator in an SO-9 package. It generates the 0.75V rail, which is exactly half of the 1.5V DDR3 VDDQ supply, consistent with the LP2998's tracking behavior of regulating VTT to VDDQ/2. The VDDQ pin receives the 1.5V rail, and the device produces both VTT (0.75V termination voltage, 62 pins connected) and VREF (a buffered VDDQ/2 reference output). The AVIN pin provides analog supply for internal control circuitry, and PVIN provides the power stage input. The VSENSE pin enables remote sensing of the VTT voltage at the load point. The SD pin controls shutdown for Suspend-to-RAM functionality, where VTT is tri-stated while VREF remains active. This device can source and sink up to 1.5A continuous current, which is essential for DDR termination where bidirectional current flow is normal.

LTC6902 Multiphase Oscillator

U14 (LTC6902) is a multiphase oscillator in an MSOP-10 package. It provides clock synchronization signals for the power converters. The device has four outputs (OUT1 through OUT4) with programmable phase relationships set by the PH pin, and a programmable frequency divider set by the DIV pin. The SET pin accepts a precision resistor to V+ that programs the master oscillator frequency according to the formula fOUT = 10MHz / (N x M x (RSET / 20k)). The MOD pin can enable spread-spectrum frequency modulation when connected through a resistor to V+, or disable it when tied to GND. The device operates from a 2.7V to 5.5V supply.

Power Sequencing and Supervision

U17 (LTC2908-B1) is a quad-voltage supervisor in a SOT-23-8 package. It monitors four supply rails: 3.3V (pin 8), 2.5V (pin 1), 1.8V (pin 6), and 1.5V (pin 2). Two adjustable threshold inputs (VADJ1 at pin 7 and VADJ2 at pin 5) allow customization of trip points. The RST output (pin 3, open-collector) asserts a system reset when any monitored voltage falls below its threshold.

Hot-Swap Controllers

U12 and U13 are LTC4210 hot-swap controllers in SOT-23-6 packages. Each device has VCC, SENSE, GATE, TIMER, and ON pins. These controllers manage inrush current during board insertion by controlling external N-channel MOSFETs. U12 works with Q1 and U13 works with Q2 (both PowerPak SO-8 N-channel MOSFETs), providing controlled power-up of the input supply rails.

Communication Interfaces

Dual Gigabit Ethernet

U10 and U11 are Realtek RTL8211F Gigabit Ethernet PHY transceivers in QFN-40 packages. Each PHY provides an RGMII interface to the Zynq SoC (TXD0-TXD3, TX-CLK, TX-EN, RXD0-RXD3, RX-CLK, RX-VALID) and a four-pair MDI interface (Tx/Rx-A+/-, B+/-, C+/-, D+/-) to the physical medium. Management is via MDIO and MDC. Each PHY has a CLKOUT for system clock generation, an RBIAS pin for the external bias resistor, and crystal oscillator connections (XI, XO). LED outputs (LED0-10, LED1-100, LED2-1000) indicate link speed. The INTR output provides interrupt signaling. Both PHYs connect to J8, a PULSE JXD0-2015NL dual-port RJ-45 connector with integrated magnetics. This connector includes LED anode and cathode pins for link and activity indication on both ports.

Dual IEEE 1394a (FireWire)

U5 is a Texas Instruments TSB41AB2 two-port IEEE 1394a transceiver/arbiter in a PQFP-65 package. It provides two FireWire ports through connectors J3 and J4 (6-pin FireWire connectors). The device interfaces to the Zynq SoC through an 8-bit data bus (D0 through D7), control signals (CTL0, CTL1), and arbitration signals (LREQ, CNA). The physical layer includes differential twisted-pair connections (TPA0+/-, TPB0+/-, TPA1+/-, TPB1+/-) with bias outputs (TPBIAS0, TPBIAS1). A PLL section uses XI/XO crystal connections with FILTER0 and FILTER1 for loop filter components. The SYSCLK output provides a system clock, and the RESET input handles device initialization. Port status is available through PC0, PC1, and PC2 pins.

Level Translation

U8 is a Texas Instruments TXS0101 single-bit bidirectional voltage-level translator in an SC70-6 package. It bridges two voltage domains using VccA and VccB supply pins, with bidirectional data on A1 and B1. The OE pin enables or disables the translation path.

Buffer

U9 is an NC7WZ17 dual Schmitt-trigger buffer in an SC70-6 package. It provides two independent buffered outputs (pins 4 and 6) from two inputs (pins 1 and 3), powered from VCC (pin 5). This device is suitable for cleaning up slow-edge or noisy signals.

Voltage Reference

U6 is a TLVH431 adjustable shunt voltage reference in an SC70-6 package, with cathode (C) and adjust (ADJ) pins. This device provides a precision voltage reference for use elsewhere in the design.

Clock Generation

Three oscillator modules (U7, U19, U20) in 3x5mm packages provide fixed-frequency clock sources. Each has VCC, EN (enable), and OUT pins. These supply reference clocks to the Zynq SoC, Ethernet PHYs, or FireWire transceiver as required by the various interface timing specifications.

Connectors and External Interfaces

The board provides extensive external connectivity through multiple connector types.

J1 and J2 are 22x2-pin 2mm-pitch headers providing high-density expansion interfaces. These carry a large number of FPGA I/O signals to external boards or backplanes, with 38 to 40 pins populated on each connector.

J7 is a 7x2-pin 2mm-pitch header serving as the JTAG interface. Pins J7_4, J7_6, J7_8, and J7_10 carry the JTAG signals (TCK, TDI, TDO, TMS) to U1 for FPGA configuration and debug access.

J6 is a 2-pin 100-mil header, likely serving as a jumper or single-signal connection point.

J9 is a 3x2-pin 2mm-pitch header with five active pins, providing a small auxiliary interface.

J10 is a 6-pin REDEL connector (five active pins), providing a specialized external connection, possibly for power or a dedicated peripheral interface.

Test and Debug Infrastructure

The design includes 14 test points distributed across the board, providing probe access to critical signals and power rails during development and production testing. The JTAG chain through J7 enables boundary-scan testing of U1 and interconnect verification to the DDR3 memory devices (U2, U3) and QSPI flash (U4). Boundary-scan analysis shows full coverage of both DDR3 devices and partial coverage of the QSPI flash.

User Interface

A single rotary switch (SW1, 16-position) provides user-selectable configuration input through four encoded output pins. Three LEDs (D2, D3, D4) serve as visual status indicators. A TVS diode (D1) provides ESD or transient voltage protection on a board-level signal or supply line.

Protection and Signal Conditioning

Eight series diode pairs (D5 through D12, SOT-523 dual-diode packages) provide signal-level clamping or protection across various interfaces. The P-channel MOSFET Q3 (PowerPak SO-8) likely serves as a high-side power switch or reverse-polarity protection. Dual N-channel MOSFETs Q4 and Q5 (SC70-6 packages) provide small-signal switching functions. PNP transistor Q6 (SOT-23) serves a discrete logic or bias function. Resistor R60A is a grounding resistor providing a defined impedance path to ground.

Design Complexity Summary

The FPGA3 board is a moderately complex embedded system with 442 components, dominated by passive devices (359 chip passives) supporting the active ICs. The BGA packages (Zynq-7020 at 400 balls, two DDR3 devices at 96 balls each, and the LTC3644 at 36 balls) represent the primary layout challenges. The design integrates multiple high-speed interfaces (DDR3 at 1.5V, Gigabit Ethernet RGMII, IEEE 1394a) alongside a carefully sequenced multi-rail power distribution network. The ten-sheet flat schematic organization and 367 nets reflect a well-partitioned design suitable for systematic review and test development.

AI-Assisted The design is built around a Xilinx XC7Z020 Zynq SoC (U1) supported by two MT41K256M16 DDR3L SDRAM devices (U2, U3), a TSB41AB2 IEEE 1394a transceiver (U5), two RTL8211F Ethernet PHYs (U10, U11), a W25Q128 QSPI flash (U4), and various interface and clock components. External power enters the board through connector J1 and associated protection circuitry. A TVS diode D1 clamps the incoming rail (net PWR). A P-channel MOSFET Q3 and associated gate drive circuitry form an input protection or reverse-polarity switch. The protected input feeds through ferrite L15 to the V-IN rail, which serves as the primary input to the LTC3636 dual-output synchronous buck converter U16.

U16 channel 1 produces the VCC3 (3.3 V) rail through inductor L2 (1.2 uH). U16 channel 2 produces the 5V-DCDC rail through inductor L1 (1.5 uH). The 5V-DCDC rail feeds the LTC3644 quad-output synchronous buck converter U15, which generates three lower-voltage rails: 1.0 V (channel 1, inductor L3 0.68 uH), 1.5 V (channel 3, inductor L4 1.5 uH), and 1.8 V (channel 4, inductor L5 1.5 uH). Channel 2 of U15 has its FB2 pin tied to the INTVCC2 net (the internal LDO output), placing it in slave mode paralleled with channel 1 for increased 1.0 V current capability.

The LP2998 DDR termination regulator U18 derives VTT (0.75 V) from the 1.5 V rail (PVIN, VDDQ) and is powered by VCC3 on its AVIN pin. A separate 5 V rail is created from 5V-DCDC through ferrite L16, feeding hot-swap controllers U12 and U13 (LTC4210) for the IEEE 1394 FireWire ports.

An LTC6902 multiphase oscillator U14 generates synchronization clocks: its OUT1 output drives the MODE/SYNC input of U15 (inverted, net /1.2MHz), and OUT2 drives the MODE/SYNC input of U16 (net 1.2MHz). An LTC2908-B1 quad-supply supervisor U17 monitors the 1.0 V, 1.5 V, 1.8 V, and 3.3 V rails and drives the PGOOD net, which controls the power-on reset sequencing for the Zynq SoC and downstream enables.

AI-Assisted U16 is an LTC3636 dual-output synchronous step-down converter in a QFN-28 package. Its input pins VIN1 (pins 21, 22) and VIN2 (pins 15, 16) connect to the V-IN rail. Input decoupling on V-IN consists of two 10 uF ceramics (C59, C60) and two 33 uF polarized capacitors (C68, C69), providing adequate bulk and high-frequency filtering for the converter's input stage.

Channel 1 produces VCC3 (3.3 V). The feedback divider on net NOLBL_C5_2_2 uses R104 (100 K) from VCC3 to the FB1 pin (pin 28) and R97 (22.1 K) from FB1 to GND. With the verified VREF of 0.600 V and the pre-computed output of 3.315 V, this is within acceptable tolerance of the 3.3 V target. Output capacitance on VCC3 is substantial: thirteen 0.1 uF ceramics, twelve 0.47 uF ceramics, four 100 uF ceramics, nine 10 uF ceramics, and two 470 uF polarized capacitors, reflecting the large number of consumers on this rail including the Zynq SoC I/O banks, both Ethernet PHYs, the TSB41AB2, flash, oscillators, and the LP2998 AVIN supply.

Channel 2 produces 5V-DCDC. The feedback divider on net NOLBL_C4_2_2 uses R103 (100 K) from 5V-DCDC to the FB2 pin (pin 9) and R81 (13.3 K) from FB2 to GND. The pre-computed output voltage is 5.128 V. This is approximately 2.6% above a nominal 5.0 V target. The 5V-DCDC rail feeds U15 and, through ferrite L16, the 5 V rail for the hot-swap controllers. The LTC3644 datasheet specifies a maximum input voltage of 5.5 V, so 5.128 V provides adequate headroom. Output decoupling on 5V-DCDC includes six 0.1 uF ceramics, one 100 uF ceramic, four 22 uF ceramics, and one 330 uF polarized capacitor.

The RT pin (pin 4) connects through R96 to GND. Per the LTC3636 datasheet Rev.F, the switching frequency is set by the RT resistor. However, the MODE/SYNC pin (pin 3) receives the 1.2 MHz clock from U14 OUT2, which overrides the RT-set frequency and forces the converter into synchronous forced-continuous mode at 1.2 MHz. The RT resistor still sets the initial free-running frequency before the external clock is present.

Soft-start capacitors are present: C77 (4700 pF) on TRACK/SS1 (pin 26) and C78 (4700 pF) on TRACK/SS2 (pin 11). Per the LTC3636 datasheet, the internal 1.4 uA pull-up current charges these capacitors, giving a soft-start time of approximately t_SS = C × 0.6 V / 1.4 uA = 4700 pF × 0.6 V / 1.4 uA ≈ 2.0 ms per channel.

RUN1 (pin 2) connects to the OK-1.8V net, meaning channel 1 (VCC3) is enabled only after the 1.8 V rail is valid. RUN2 (pin 7) connects to net NOLBL_R102_2_2, which includes R102 from V-IN and R92 to GND forming a voltage divider, along with test point TP5. This arrangement enables channel 2 based on the input voltage level, providing an under-voltage lockout function.

The PGOOD1 pin (pin 27) and PGOOD2 pin (pin 10) are listed as unconnected in the schematic. The PGOOD1 output for VCC3 is not monitored, and PGOOD2 for 5V-DCDC is also not monitored. The TMON pin (pin 6) is also unconnected. These are open-drain outputs; leaving them unconnected is functionally acceptable but means no power-good feedback is available from U16 directly. System-level power-good monitoring is handled instead by the LTC2908-B1 supervisor U17.

The ITH1 (pin 1) and ITH2 (pin 8) compensation pins both connect to the INTVCC net along with pin 5 (INTVCC output) and pin 29 (INTVCC). This means both compensation pins are tied to INTVCC, which per the LTC3636 datasheet selects the default internal compensation. A 10 uF bypass capacitor CB137 is present on INTVCC (net INTVCC). This is a valid configuration when the output capacitor ESR and load transient requirements are compatible with the internal compensation network. The BST1 (pin 23) and BST2 (pin 14) bootstrap pins have dedicated capacitors C23 and C24 respectively.

AI-Assisted U15 is an LTC3644 quad-output synchronous buck converter in a BGA-36 package. All four VIN pins (VIN1 through VIN4, pins B6, E6, E1, B1) connect to the 5V-DCDC rail. Input decoupling on 5V-DCDC at U15 is shared with the rail's bulk capacitance described above. The SVIN pin (A5) connects through a dedicated 10 uF ceramic capacitor CB139 and a 4.99 ohm series resistor R9 to 5V-DCDC, providing filtered power for the internal INTVCC LDO as recommended by the datasheet.

Channel 1 (FB1, pin A6) produces the 1.0 V rail. The feedback divider uses R100 (100 K) from 1.0 V to FB1 and R106 (150 K) from FB1 to GND. With VREF = 0.600 V and ratio = 0.600, the output voltage calculates as VOUT = 0.600 V / 0.600 = 1.000 V, matching the target exactly. Channel 2 (FB2, pin F6) is tied to the INTVCC2 net, which is the INTVCC output (pin A2). Per the LTC3644 datasheet Rev.A, tying FB to INTVCC configures the channel as a slave to channel 1, effectively paralleling channels 1 and 2 for increased output current on the 1.0 V rail. Both SW1 (pin C6) and SW2 (pin D6) connect to the same filter net through inductor L3 (0.68 uH), confirming the parallel configuration. The 1.0 V rail powers the Zynq VCC-INT, VCC-BRAM, and VCCP-INT domains. Output decoupling includes eight 0.47 uF ceramics, one 1000 uF polarized, three 10 uF ceramics, and five 220 uF ceramics.

Channel 3 (FB3, pin F1) produces the 1.5 V rail through inductor L4 (1.5 uH). The feedback divider uses R107 (150 K) from 1.5 V to FB3 and R101 (100 K) from FB3 to GND. With VREF = 0.600 V and ratio = 0.400, VOUT = 0.600 V / 0.400 = 1.500 V, matching the target. The 1.5 V rail powers the Zynq VCCO-502 bank (DDR3L I/O), the DDR3L SDRAM VDD and VDDQ pins, and the LP2998 termination regulator. Output decoupling is extensive: thirty-six 0.1 uF ceramics, four 0.47 uF ceramics, one 1000 uF polarized, two 10 uF ceramics, and two 220 uF ceramics.

Channel 4 (FB4, pin A1) produces the 1.8 V rail through inductor L5 (1.5 uH). The feedback divider uses R108 (200 K) from 1.8 V to FB4 and R99 (100 K) from FB4 to GND. With VREF = 0.600 V and ratio = 0.333, VOUT = 0.600 V / 0.333 = 1.80 V, matching the target. The 1.8 V rail powers the Zynq auxiliary and PLL domains (VCC-AUX, VCCP-AUX, VCC-ADC, VCC-PLL, VCCO-13), the TXS0101 level translator U8, and the NC7WZ17 buffer U9. Output decoupling includes seven 0.47 uF ceramics, three 10 uF ceramics, three 220 uF ceramics, and one 680 uF polarized capacitor. The VCC-PLL supply for U1 is further filtered through ferrite L8 with two 0.47 uF and two 10 uF ceramics on the filtered side, which is good practice for PLL noise isolation.

The MODE/SYNC pin (D2) receives the /1.2MHz clock from U14 OUT1, synchronizing U15 to 1.2 MHz in forced continuous mode. The PHASE pin (D5) connects to the INTVCC2 net (INTVCC output), setting 180-degree phase shift between channels 1/2 and channels 3/4 per the datasheet (PHASE tied to INTVCC = 180 degrees). This interleaving reduces input ripple current.

RUN1 (C5) and RUN2 (F5) are both tied to 5V-DCDC, enabling channels 1 and 2 whenever the input supply is present. RUN3 (F2) connects to the OK-1.8V net, and RUN4 (C2) connects to the OK-1V net. The OK-1.8V net is driven by PGOOD4 (pin B2), meaning channel 3 (1.5 V) is enabled after channel 4 (1.8 V) is valid. The OK-1V net is driven by PGOOD1 (pin B5), meaning channel 4 (1.8 V) is enabled after channel 1 (1.0 V) is valid. This creates the power-up sequence: 1.0 V first, then 1.8 V, then 1.5 V — consistent with Xilinx Zynq-7000 power sequencing requirements (VCCINT before VCCAUX before VCCO).

PGOOD3 (E2) and PGOOD2 (E5) are intentionally unconnected per the designer's markings. PGOOD4 (B2) drives the OK-1.8V net which also feeds U16 RUN1, creating the cascade: once 1.8 V is valid, VCC3 is enabled. This is a well-structured sequencing chain.

AI-Assisted U18 is a Texas Instruments LP2998 DDR termination regulator in an SO-9 package. It generates VTT = VDDQ/2 for DDR3L memory termination. The PVIN pin (pin 7) and VDDQ pin (pin 5) both connect to the 1.5 V rail, so VTT regulates to 1.5 V / 2 = 0.75 V. The VSEN pin (pin 3) connects directly to the 0.75 V rail for local sensing (DIRECT_SENSE). The AVIN pin (pin 6) connects to VCC3 (3.3 V), which is within the 2.2 V to 5.5 V operating range specified in the LP2998 datasheet Rev.K. Since AVIN (3.3 V) is greater than PVIN (1.5 V), the requirement that AVIN >= PVIN is satisfied.

The shutdown pin SD (pin 2) is tied to VCC3, keeping the device permanently enabled. The VREF output (pin 4) connects through a 0.1 uF ceramic capacitor C21 to GND, providing the recommended bypass capacitance for the buffered VDDQ/2 reference output. The LP2998 datasheet recommends 0.1 uF to 0.01 uF low-ESR ceramic on VREF, so this is correct.

Output decoupling on the 0.75 V rail includes nineteen 0.1 uF ceramics, eight 0.47 uF ceramics, and three 220 uF ceramics. The LP2998 datasheet requires a minimum of 100 uF output capacitance with low ESR. The three 220 uF ceramics alone provide 660 uF, well exceeding this requirement. The 0.75 V rail serves the DDR3L address/command termination resistors (R10 through R32, each 40.2 ohm, terminated to 0.75 V), the Zynq VREF0 and VREF1 pins, and the DDR3L VREF and VREFQ pins on U2 and U3.

AI-Assisted U14 is an LTC6902 multiphase oscillator in an MSOP-10 package, powered from the 5V-DCDC rail on pin 1 (Vin). The DIV pin (pin 2) and PH pin (pin 3) are both tied to GND. Per the LTC6902 datasheet (document 6902f), DIV = GND sets N = 1 (divide-by-1), and PH = GND sets M = 1 with 2-phase output mode. The frequency formula is fOUT = 10 MHz / (N × M × (RSET / 20k)).

The SET pin (pin 10) connects to net NOLBL_R94_1_1, which includes R94. R94 is a 162 K resistor. One end connects to the SET pin and the other end connects to the 5V-DCDC rail (as the SET pin voltage is held at approximately V+ minus 1.13 V, and the resistor connects to V+). Substituting: fOUT = 10 MHz / (1 × 1 × (162000 / 20000)) = 10 MHz / 8.1 = 1.235 MHz. This is close to the 1.2 MHz target frequency for synchronizing both U15 and U16.

The MOD pin (pin 9) connects to net NOLBL_R95_1_1, which includes R95 (301 K). Per the datasheet, connecting a resistor from MOD to V+ enables spread-spectrum frequency modulation (SSFM). R95 connects between MOD and 5V-DCDC, enabling SSFM to reduce EMI. The SSFM modulation range is set by the RMOD/RSET ratio.

OUT1 (pin 4) drives the /1.2MHz net to U15 MODE/SYNC, and OUT2 (pin 5) drives the 1.2MHz net to U16 MODE/SYNC. The two outputs are 180 degrees apart in 2-phase mode, which staggers the switching instants of U15 and U16 to reduce input current ripple on the 5V-DCDC rail. OUT3 (pin 6) and OUT4 (pin 7) are intentionally unconnected per the designer's markings, consistent with 2-phase mode where only OUT1 and OUT2 are active.

AI-Assisted U17 is an LTC2908-B1 quad-supply supervisor in an SOT-23-8 package. It monitors four voltage rails and asserts a reset output when all are within tolerance. The pin connections are: pin 1 (2.5V input) connects to 5V-DCDC, pin 2 (1.5V input) connects to 1.5 V, pin 6 (1.8V input) connects to 1.8 V, pin 7 (VADJ1) connects to VCC3, and pin 8 (3.3V input) connects to VCC3.

The LTC2908-B1 variant has fixed thresholds for the 1.5 V, 1.8 V, and 3.3 V inputs, and the 2.5 V input has a fixed threshold as well. Pin 1 is labeled "2.5V" in the device but is connected to the 5V-DCDC rail (approximately 5.13 V). The LTC2908 datasheet specifies that the 2.5V pin has an undervoltage threshold of approximately 2.375 V (typical). Since 5V-DCDC is well above this threshold, the monitor will always see this input as valid once the rail is up. This is an unconventional use — the pin is designed for a 2.5 V rail — but functionally it works as a presence detector for the 5V-DCDC rail since the overvoltage threshold for this pin is not enforced as a fault condition in the B1 variant.

The VADJ2 pin (pin 5) connects to net NOLBL_R105_1_1, which is a voltage divider from the 1.0 V rail: R98 (100 K) from 1.0 V to VADJ2 and R105 (115 K) from VADJ2 to GND. The divided voltage at VADJ2 is 1.0 V × 0.535 = 0.535 V. Per the LTC2908 datasheet, the VADJ pins have an internal 0.5 V reference threshold. The 0.535 V divided voltage is slightly above the 0.5 V threshold when the 1.0 V rail is at its nominal value, providing a tight undervoltage detection point for the 1.0 V rail. The effective trip point is approximately 0.5 V / 0.535 × 1.0 V = 0.935 V, meaning the supervisor will flag a fault if the 1.0 V rail drops below roughly 0.935 V.

The RST output (pin 3) is open-drain and drives the PGOOD net. This net connects to the Zynq POR pin (U1 pin C7), the enable pins of oscillators U19 and U20, the ON pins of hot-swap controllers U12 and U13, and pull-up resistors R61 and R64 (each 1.50 K) to VCC3. The parallel combination of R61 and R64 gives 750 ohm pull-up to VCC3. R80 (13.3 K) connects from PGOOD to GND, forming a voltage divider with the pull-ups. When RST is released (high-impedance), the PGOOD voltage is VCC3 × 13.3 K / (0.75 K + 13.3 K) = 3.3 V × 0.947 = 3.12 V. This is above the Zynq PS_POR_B high-level input threshold and provides a valid logic high for all connected devices.

AI-Assisted The external power input arrives at connector J6 pin 1 on the PWR net. A TVS diode D1 clamps this net to GND. The P-channel MOSFET Q3 acts as a high-side switch or reverse-polarity protection device. Its gate is driven through a resistor network (R73 to GND, R78 from the source-side net). The drain of Q3 connects to the PWR net, and the source connects through ferrite L15 to the V-IN rail.

The 5 V rail (downstream of 5V-DCDC through ferrite L16) feeds two LTC4210 hot-swap controllers, U12 and U13, which manage inrush current for the two FireWire ports (J3, J4). Each LTC4210 has its VCC pin (pin 6) on the 5 V rail, and the ON pin (pin 3) connects to the PGOOD net, ensuring the FireWire ports are only powered after all supply rails are stable. The SENSE pins (pin 5) connect to current-sense resistors R117 and R118 (each 0.015 ohm), and the GATE pins (pin 4) drive external N-channel MOSFETs Q1 and Q2 respectively. The TIMER pins (pin 1) set the fault response timing.

AI-Assisted The power-up sequence is determined by the RUN pin connections and the PGOOD cascade:

When V-IN rises, U16 channel 2 (5V-DCDC) is enabled first via the RUN2 voltage divider from V-IN. Once 5V-DCDC is established, U15 channels 1 and 2 (1.0 V, paralleled) start because RUN1 and RUN2 are tied directly to 5V-DCDC. When the 1.0 V rail reaches regulation, PGOOD1 (OK-1V) goes high, enabling U15 channel 4 (1.8 V) via RUN4. When the 1.8 V rail reaches regulation, PGOOD4 (OK-1.8V) goes high, enabling both U15 channel 3 (1.5 V) via RUN3 and U16 channel 1 (VCC3) via RUN1.

Once all four monitored rails (5V-DCDC, 1.0 V, 1.5 V, 1.8 V, and VCC3) are within the LTC2908-B1 thresholds, U17 releases its RST output, pulling PGOOD high. This enables the Zynq POR release, the oscillators, and the FireWire hot-swap controllers.

The resulting sequence is: 5V-DCDC -> 1.0 V -> 1.8 V -> 1.5 V and VCC3 (simultaneously) -> PGOOD assertion -> 0.75 V (LP2998 enabled by VCC3 on SD pin). This sequence satisfies the Xilinx Zynq-7000 requirement that VCCINT powers up before VCCAUX, and VCCAUX before VCCO banks. The DDR3L VDDQ (1.5 V) and VTT (0.75 V) come up after the core supplies, which is acceptable since the memory is not accessed until the Zynq completes its boot sequence.

AI-Assisted Both RTL8211F Ethernet PHYs (U10, U11) have their VDD3.3 (pin 29) and VDD-IO (pin 28) pins on the VCC3 rail. The analog 3.3 V pins (AVDD3.3 at pins 11 and 40) on each PHY are fed through dedicated ferrite beads: L13 filters to U10's AVDD3.3 pins, and L14 filters to U11's AVDD3.3 pins. Each filtered net has four 0.1 uF and two 1.0 uF ceramic capacitors, providing clean analog supply decoupling. The 1.0 V analog and digital core supplies (AVDD1.0 at pins 3, 8, 38 and VDD1.0 at pin 21) are internally generated via the DC-DC pin (pin 30) on each PHY, which is the RTL8211F's internal switching regulator output. This is standard practice for the RTL8211F.

AI-Assisted The Zynq XC7Z020 (U1) has extensive decoupling across its multiple power domains. The 1.0 V core rail has eight 0.47 uF, three 10 uF, five 220 uF ceramics, and one 1000 uF polarized capacitor. The 1.5 V DDR I/O rail has thirty-six 0.1 uF and four 0.47 uF ceramics plus bulk polarized capacitors. The 1.8 V auxiliary rail has seven 0.47 uF and three 10 uF ceramics plus 220 uF and 680 uF bulk. The VCC3 rail serving the 3.3 V I/O banks has thirteen 0.1 uF, twelve 0.47 uF, and nine 10 uF ceramics plus bulk. These quantities are consistent with Xilinx power integrity guidelines for the XC7Z020 in a CLG400 package.

The DDR3L SDRAM devices U2 and U3 share the 1.5 V rail decoupling. Each device has VDD and VDDQ pins distributed across the BGA, and the thirty-six 0.1 uF capacitors on the 1.5 V rail provide per-pin-group bypassing. The 0.75 V VTT rail has nineteen 0.1 uF, eight 0.47 uF, and three 220 uF ceramics, which is appropriate for the termination current demands.

The LTC3644 INTVCC output (INTVCC2 net) has a single 10 uF ceramic CB137. The LTC3644 datasheet recommends a minimum 1 uF on INTVCC, so 10 uF is adequate. The LTC3636 INTVCC (net INTVCC) has a 10 uF ceramic CB138, also exceeding the minimum requirement.

AI-Assisted The 5V-DCDC rail voltage of 5.128 V, while functional, is slightly above the nominal 5.0 V. All downstream consumers (LTC3644 with 5.5 V max VIN, LTC6902 with 5.5 V max, LTC2908-B1) operate within their absolute maximum ratings at this voltage. The LTC4210 hot-swap controllers on the 5 V rail (after ferrite L16) see essentially the same voltage and are rated for operation up to 5.5 V.

The LTC2908-B1 pin 1 (labeled 2.5V) is connected to the 5V-DCDC rail at approximately 5.13 V. The LTC2908 datasheet specifies an absolute maximum rating of 6 V on this pin, so the device is within its safe operating area. However, the undervoltage threshold for this pin is designed around a 2.5 V nominal rail. At 5.13 V, the monitor will always see this input as valid, effectively making it a non-functional monitor for the 5V-DCDC rail's regulation accuracy. It will only detect a gross failure where 5V-DCDC drops below approximately 2.375 V.

The DDR3L address and command signals use 40.2 ohm series termination resistors (R10 through R32) with one end on the 0.75 V VTT rail, providing proper on-die termination voltage matching. The clock differential pair (CLK_P, CLK_N) has R35 (80.6 ohm) connected between the two lines, providing differential termination.

The PGOOD net pull-up configuration with two parallel 1.50 K resistors (R61, R64) to VCC3 and R80 (13.3 K) to GND creates a divider that holds PGOOD at approximately 3.12 V when the open-drain outputs are released. The LTC2908-B1 RST output, the LTC4210 ON inputs, and the Zynq POR input all function correctly at this voltage level.

Device	Rail	Observation	Severity
U17 (LTC2908-B1)	5V-DCDC	Pin 1 (2.5V monitor) connected to 5V-DCDC (~5.13V). Within 6V absolute max rating. Undervoltage threshold (~2.375V) is far below operating voltage, so this pin only detects gross rail collapse, not regulation faults.	Medium
U16 (LTC3636)	5V-DCDC	Feedback divider R103 (100K) / R81 (13.3K) with VREF = 0.600 V yields 5.128 V output, 2.6% above 5.0 V nominal. All downstream devices rated for this voltage (LTC3644 max 5.5 V, LTC6902 max 5.5 V). Verified against LTC3636 datasheet Rev.F.	Low
U16 (LTC3636)	VCC3 / 5V-DCDC	PGOOD1 (pin 27) and PGOOD2 (pin 10) are unconnected. System-level monitoring is handled by U17 (LTC2908-B1). No functional issue but per-channel fault reporting is unavailable.	Low
U17 (LTC2908-B1)	1.0V	VADJ2 divider R98 (100K) / R105 (115K) from 1.0V rail gives 0.535V at pin 5. With internal 0.5V threshold, effective UV trip is ~0.935V (6.5% below nominal). Tight margin for a 1.0V rail.	Low
U16 (LTC3636)	VCC3	Feedback divider R104 (100K) / R97 (22.1K) with VREF = 0.600 V yields 3.315 V output, within 0.5% of 3.3 V target. Verified against LTC3636 datasheet Rev.F.
U16 (LTC3636)	INTVCC	ITH1 and ITH2 tied to INTVCC selects internal compensation per LTC3636 datasheet Rev.F. Valid if output capacitor ESR and transient requirements are met by default network.
U16 (LTC3636)	VCC3 / 5V-DCDC	Soft-start capacitors C77 and C78 (4700 pF each) on TRACK/SS1 and TRACK/SS2 give approximately 2.0 ms soft-start time per LTC3636 datasheet (1.4 uA charge current, 0.6 V threshold).
U15 (LTC3644)	1.0V	Feedback divider R100 (100K) / R106 (150K) with VREF = 0.600 V yields 1.000 V. Channel 2 FB2 tied to INTVCC for parallel slave operation. Verified against LTC3644 datasheet Rev.A.
U15 (LTC3644)	1.5V	Feedback divider R107 (150K) / R101 (100K) with VREF = 0.600 V yields 1.500 V. Verified against LTC3644 datasheet Rev.A.
U15 (LTC3644)	1.8V	Feedback divider R108 (200K) / R99 (100K) with VREF = 0.600 V yields 1.800 V. Verified against LTC3644 datasheet Rev.A.
U15 (LTC3644)	1.0V	PHASE pin tied to INTVCC sets 180-degree interleaving between channel pairs 1/2 and 3/4, reducing input ripple. Per LTC3644 datasheet Rev.A.
U15 (LTC3644)	Sequencing	RUN1/RUN2 tied to 5V-DCDC (always on), PGOOD1 (OK-1V) enables RUN4 (1.8V), PGOOD4 (OK-1.8V) enables RUN3 (1.5V) and U16 RUN1 (VCC3). Sequence: 1.0V -> 1.8V -> 1.5V/VCC3. Matches Zynq-7000 requirements.
U15 (LTC3644)	SVIN	SVIN pin filtered through R9 (4.99 ohm) and CB139 (10 uF) from 5V-DCDC. Per LTC3644 datasheet Rev.A, SVIN should connect to the highest VINx. All VINx are on 5V-DCDC, so this is correct.
U18 (LP2998)	0.75V	PVIN and VDDQ on 1.5V rail, AVIN on VCC3 (3.3V). VTT = 1.5V/2 = 0.75V. AVIN >= PVIN satisfied. SD tied to VCC3 (always enabled). VREF bypassed with 0.1 uF (C21). All per LP2998 datasheet Rev.K.
U18 (LP2998)	0.75V	Output capacitance: nineteen 0.1 uF + eight 0.47 uF + three 220 uF ceramics = well above 100 uF minimum per LP2998 datasheet Rev.K.
U14 (LTC6902)	Clock	DIV and PH tied to GND: N=1, M=1, 2-phase mode. RSET = R94 (162K) gives fOUT = 10MHz / (1 × 1 × 8.1) = 1.235 MHz. SSFM enabled via R95 (301K) on MOD pin. Per LTC6902 datasheet 6902f.
U17 (LTC2908-B1)	Supervision	Monitors 1.5V (pin 2), 1.8V (pin 6), VCC3 (pins 7, 8), and 1.0V via VADJ2 divider (R98/R105, trip at ~0.935V). RST drives PGOOD net for system reset.
U1 (XC7Z020)	Sequencing	Power sequence 1.0V -> 1.8V -> 1.5V/VCC3 satisfies Xilinx UG585 requirement: VCCINT before VCCAUX before VCCO. POR released after all rails stable via U17 RST.
U1 (XC7Z020)	VCC-PLL	PLL supply filtered through ferrite L8 with two 0.47 uF and two 10 uF ceramics on filtered side. Good practice for jitter-sensitive PLL domain.
U10/U11 (RTL8211F)	AVDD3.3	Analog 3.3V supplies filtered through dedicated ferrites L13 (U10) and L14 (U11), each with four 0.1 uF and two 1.0 uF ceramics. Proper analog/digital supply isolation.
U15 (LTC3644)	Input	5V-DCDC input decoupling shared: six 0.1 uF, one 100 uF, four 22 uF ceramics, one 330 uF polarized. Adequate for quad-channel converter input requirements per LTC3644 datasheet Rev.A.
U16 (LTC3636)	Input	V-IN input decoupling: two 10 uF ceramics (C59, C60) and two 33 uF polarized (C68, C69). Adequate bulk and ceramic mix for dual-channel converter per LTC3636 datasheet Rev.F.
U12/U13 (LTC4210)	5V	Hot-swap controllers enabled by PGOOD net, ensuring FireWire ports powered only after all rails stable. Current sense resistors R117/R118 (0.015 ohm) set inrush current limit.
General	DDR Termination	Address/command lines terminated with 40.2 ohm resistors to 0.75V VTT. Clock pair CLK_P/CLK_N has 80.6 ohm differential termination (R35). Consistent with DDR3L signaling requirements.

AI-Assisted

References
LP2998 (Texas Instruments) — LP2998/LP2998-Q1 DDR Termination Regulator Data Sheet Rev.K, ti.com www.ti.com/product/LP2998
LTC3636 (Analog Devices (Linear Technology)) — LTC3636/LTC3636-1 Data Sheet Rev.F, analog.com, Electrical Characteristics table, Pin Functions section www.analog.com/media/en/technical-documentation/data-shee...
LTC3644 (Analog Devices (Linear Technology)) — LTC3644/LTC3644-2 Data Sheet Rev.A, analog.com, Electrical Characteristics table, Pin Functions section www.analog.com/media/en/technical-documentation/data-shee...
LTC6902 (Linear Technology (now Analog Devices)) — Document 6902f, Analog Devices datasheet, Electrical Characteristics table and Pin Functions section www.analog.com/media/en/technical-documentation/data-shee...

AI-Assisted The design implements two independent 1000BASE-T Gigabit Ethernet channels. U10 serves Ethernet port A and U11 serves Ethernet port B, both connecting to J8, a Pulse JXD0-2015NL dual-port RJ-45 connector with integrated magnetics. Each PHY uses four differential pairs (A, B, C, D) for full-duplex Gigabit operation per IEEE 802.3ab.

All eight differential pairs carry a DIFF100 impedance class annotation, specifying 100 ohm differential impedance. This is correct for 1000BASE-T, which requires 100 ohm differential impedance on the MDI (Medium Dependent Interface) traces between the PHY and the magnetics module. The integrated magnetics in J8 provide the required galvanic isolation (rated 2250 VDC per the JXD0-2015NL datasheet) and common-mode rejection, eliminating the need for discrete coupling transformers.

No AC coupling capacitors appear in the differential signal paths between the PHYs and J8. This is correct and expected: the integrated magnetics within the JXD0-2015NL provide transformer-coupled isolation, which inherently blocks DC. Adding series AC coupling capacitors would be redundant and would degrade signal quality at the frequencies used by 1000BASE-T (symbol rate 125 MHz per pair with PAM-5 encoding).

The differential pairs are flagged as informal pairs, meaning they carry the DIFF100 impedance class but lack a formal DifferentialPair directive in the schematic tool. While the impedance class assignment will propagate to the layout tool for trace width and spacing calculations, the absence of a formal pairing directive means the layout tool may not enforce length matching or differential routing rules between the positive and negative members of each pair. For 1000BASE-T, intra-pair skew must be kept below approximately 50 ps to maintain signal integrity. The design team should add formal differential pair directives for all eight pairs (ETH1-A+/ETH1-A-, ETH1-B+/ETH1-B-, ETH1-C+/ETH1-C-, ETH1-D+/ETH1-D-, ETH2-A+/ETH2-A-, ETH2-B+/ETH2-B-, ETH2-C+/ETH2-C-, ETH2-D+/ETH2-D-) to enable automated skew checking during layout.

AI-Assisted The Ethernet interface implementation follows standard practice for dual 1000BASE-T with integrated-magnetics RJ-45. The connector J8 (Pulse JXD0-2015NL) is rated for 10/100/1000 Base-T and is an appropriate choice for Gigabit Ethernet. The integrated 1:1 transformer with 350 uH minimum primary inductance provides adequate common-mode rejection and return loss performance through 125 MHz.

The primary signal integrity concern is the lack of formal differential pair directives for the eight MDI differential pairs. While the DIFF100 impedance class is correctly assigned to all 16 nets, the informal pairing status means the EDA tool cannot automatically enforce intra-pair length matching, differential routing constraints, or skew limits. For 1000BASE-T, IEEE 802.3ab specifies tight skew requirements both within pairs and between pairs of the same port. Without formal pair definitions, the layout engineer must manually manage these constraints, increasing the risk of errors.

The TX-CLK signals (e1-TxCLK, e2-TxCLK) each have a 49.9 ohm series resistor (R1, R2) between the FPGA and the PHY TX-CLK input. Similarly, the RX-CLK outputs (U10 pin 27, U11 pin 27) have 49.9 ohm series resistors (R3, R4). These serve as series termination for the single-ended clock signals, appropriate for 3.3 V LVCMOS signaling at 25 or 125 MHz clock rates.

The bypass capacitor allocation for the PHY digital supply appears limited. Only four 100 nF capacitors (CB70 through CB73) are visible in the capacitor library for the overall design, and it is not clear from the data whether additional decoupling is present on the PHY digital VDD3.3 pins beyond what the main VCC3 rail provides. Gigabit Ethernet PHYs with high-speed DACs and ADCs typically require multiple bypass capacitors close to each power pin group.

Interface	Protocol	Finding	Severity
ETH1/ETH2 Differential Pair Directives	1000BASE-T	All 16 MDI nets carry DIFF100 impedance class but lack formal DifferentialPair directives. The layout tool will not automatically enforce intra-pair skew matching or differential routing rules. Formal pair definitions should be added for all eight pairs to ensure IEEE 802.3ab skew compliance.	Medium
ETH1 (U10 to J8 Port A)	1000BASE-T / IEEE 802.3ab	Four differential pairs (ETH1-A, ETH1-B, ETH1-C, ETH1-D) connect U10 to J8 port A through integrated magnetics. DIFF100 impedance class (100 ohm differential) is correctly assigned per IEEE 802.3ab requirements. Connector J8 (Pulse JXD0-2015NL) is rated for 1000 Base-T per its datasheet.
ETH2 (U11 to J8 Port B)	1000BASE-T / IEEE 802.3ab	Four differential pairs (ETH2-A, ETH2-B, ETH2-C, ETH2-D) connect U11 to J8 port B through integrated magnetics. DIFF100 impedance class (100 ohm differential) is correctly assigned. Connector J8 is rated for 1000 Base-T per its datasheet.
ETH1/ETH2 AC Coupling	1000BASE-T	No discrete AC coupling capacitors are present in the MDI signal paths. This is correct because J8 (Pulse JXD0-2015NL) contains integrated 1:1 isolation transformers that provide galvanic isolation and inherent DC blocking.
ETH1/ETH2 Analog Supply Filtering	1000BASE-T	U10 and U11 AVDD3.3 pins are individually filtered from VCC3 through dedicated ferrite beads (L13, L14) with local bypass capacitors (four 100 nF and two 1 uF per PHY). This provides adequate analog supply isolation.
ETH1/ETH2 RBIAS Resistors	1000BASE-T	U10 RBIAS (pin 39) terminated through R65 (2.49 kohm) to GND. U11 RBIAS (pin 39) terminated through R66 (2.49 kohm) to GND. Values are typical for Gigabit Ethernet PHY bias current setting.
25 MHz Reference Clock	1000BASE-T	Oscillator U19 provides 25 MHz reference to both PHYs via 100 ohm series damping resistors R38 (U10) and R39 (U11). U19 is powered from VCC3 with enable tied to VCC3.
MDIO Management Bus	IEEE 802.3 Clause 22	MDIO data is level-translated between 1.8 V FPGA domain and 3.3 V PHY domain via U8 (TXS0101) for U10, with 1.5 kohm pull-up R62 to 1.8 V. U11 MDIO shares the same FPGA pin with 1.5 kohm pull-up R63 to 1.8 V. MDC is buffered through U9 (NC7WZ17) Schmitt-trigger buffer powered at 1.8 V.
PHY Reset Lines	1000BASE-T	Active-low reset inputs on U10 and U11 are driven from FPGA I/O with 1 kohm pull-down resistors R58 and R59 to GND, ensuring PHYs are held in reset during FPGA power-up and configuration.
TX-CLK / RX-CLK Series Termination	1000BASE-T	TX-CLK lines have 49.9 ohm series resistors (R1, R2) and RX-CLK lines have 49.9 ohm series resistors (R3, R4), providing appropriate series termination for single-ended LVCMOS clock signals.

AI-Assisted The design uses two Micron MT41K256M16 DDR3L SDRAM devices (U2 and U3), each organized as 32 Meg x 16 x 8 banks for a total capacity of 1 GByte (4 Gbit per device, 8 Gbit total). Per the Micron MT41K256M16 datasheet, this is a DDR3L part supporting VDD = VDDQ = 1.35 V with backward compatibility to 1.5 V operation. In this design, VDD and VDDQ for both U2 and U3 are supplied from the 1.5V rail, which falls within the 1.5 V compatible operating range specified by Micron. The exact speed grade suffix is not captured on the schematic, but the MT41K256M16 family is available in -125 (DDR3-1600), -107 (DDR3-1866), and -093 (DDR3-2133) grades. The Zynq XC7Z020 DDR3 memory controller supports up to DDR3-1066 (533 MHz), so any of these speed grades is compatible.

The FPGA controller U1 (XC7Z020-CLG400) drives a 32-bit data bus split across U2 (DQ[0:15], byte lanes 0 and 1) and U3 (DQ[16:31], byte lanes 2 and 3). Each device receives its own differential data strobe pairs: U2 uses DQS0_P/DQS0_N for the lower byte and DQS1_P/DQS1_N for the upper byte, while U3 uses DQS3_P/DQS3_N for the lower byte and DQS2_P/DQS2_N for the upper byte. Data mask signals DM0 and DM1 connect to U2, and DM2 and DM3 connect to U3. This byte-lane organization is correct for a 32-bit DDR3 interface.

The address bus (A[14:0]), bank address (BA[2:0]), and all command/control signals (/RAS, /CAS, /WE, /CS, CLKE, ODT) are shared between U2 and U3 in a T-branch topology from U1. The differential clock pair CLK_P and CLK_N is also shared between both devices. For DDR3-1066 and below, a T-branch topology on address/command is acceptable per JEDEC and Xilinx guidelines, though matched trace lengths from the T-point to each device are required during layout. The /RESET signal is shared between U2, U3, and the FPGA, driven from a resistor divider (R55 from VCC3, R75 to GND) producing approximately 3.0 V, which is above the VIH threshold for the DDR3L reset input at 1.5 V VDDQ operation.

Each address and command line (A0 through A14, BA0 through BA2, /RAS, /CAS, /WE, /CS, ODT) has a 40.2 ohm series resistor (R10 through R32) with the far end terminated to the 0.75V rail. This 0.75V rail is generated by U18 (LP2998 VTT regulator), which produces VTT = VDDQ/2 = 0.75 V from the 1.5 V VDDQ supply. The LP2998 VSEN pin connects directly to the 0.75V rail for output voltage sensing, and its VREF output is decoupled by C21 (0.1 uF). The 40.2 ohm series resistors serve as source termination from the FPGA outputs, and the connection to VTT provides a center-point termination consistent with DDR3 fly-by or T-branch address/command termination practice. The differential clock pair CLK_P and CLK_N passes through R35 (80.6 ohm to GND on one end, with the other end on the clock net), providing a common-mode termination path.

AI-Assisted U2 has its ZQ pin connected through R45 (240 ohm) to GND. U3 has its ZQ pin connected through R44 (240 ohm) to GND. The Micron MT41K256M16 datasheet specifies a 240 ohm resistor with 1% tolerance on the ZQ pin for output driver and ODT calibration. The 240 ohm value used here is correct. Tolerance is not explicitly marked on the schematic but must be 1% to meet the JEDEC specification.

The VREF pin (M8) on both U2 and U3 connects to the 0.75V rail, which is VDDQ/2 = 1.5 V / 2 = 0.75 V. This is the correct reference voltage for DDR3 command/address inputs (VREFCA). The VREFQ pin (H1) on both U2 and U3 also connects to the 0.75V rail, providing the data reference voltage (VREFDQ) at VDDQ/2. Both reference voltages are correctly set to the midpoint of VDDQ as required by the DDR3 standard.

The LP2998 (U18) VTT regulator is powered from the 1.5V rail on both its PVIN (power input) and VDDQ pins. Its shutdown pin (/SD) is tied to VCC3, keeping the regulator permanently enabled. The AVIN (analog input) pin also connects to VCC3 for the internal reference. The VSEN pin connects to the 0.75V output rail for direct voltage sensing. The VTT output at 0.75 V supplies the termination resistors and the VREF/VREFQ pins on both SDRAM devices.

AI-Assisted The 1.5V rail (VDD and VDDQ for U2 and U3) is decoupled with thirty-six 0.1 uF ceramics, four 0.47 uF ceramics, two 10 uF ceramics, two 220 uF ceramics, and one 1000 uF polarized capacitor. Each SDRAM device has multiple VDD and VDDQ power pins; the bypass capacitor count provides adequate high-frequency decoupling per Micron's recommendation of one 0.1 uF capacitor per VDD/VDDQ pin pair plus bulk capacitance.

The 0.75V VTT rail is decoupled with nineteen 0.1 uF ceramics, eight 0.47 uF ceramics, and three 220 uF ceramics. The LP2998 VTT regulator is a linear device that must sink and source current rapidly during bus transitions; the substantial bulk capacitance (three 220 uF ceramics at C48, C49, C51) on the VTT output is appropriate for this purpose.

The 1.0V rail (FPGA core VCC-INT, VCC-BRAM, VCCP-INT) has eight 0.47 uF ceramics, one 1000 uF polarized, three 10 uF ceramics, and five 220 uF ceramics. While this rail does not directly power the DDR3 devices, it powers the FPGA memory controller logic and must be stable for reliable DDR3 operation.

AI-Assisted The MT41K256M16 in the 96-ball BGA package used in this design does not expose a TEN (Test Enable) pin. The pin list for U2 and U3 contains no TEN entry. The JEDEC DDR3 Connectivity Test mode via TEN is therefore not available on these specific devices, and no DFT action is required or possible regarding TEN for U2 and U3.

AI-Assisted U4 is a Winbond W25Q128, a 128 Mbit (16 MByte) SPI NOR flash supporting single, dual, and quad SPI modes. It is connected to the Zynq XC7Z020 (U1) MIO pins for QSPI boot. The interface uses four data lines: IO0/SDI on net QSPI-D0 (U1 pin MIO2), IO1/SDO on net QSPI-D1 (U1 pin MIO3), IO2/WP on net QSPI-D2 (U1 pin MIO4), and IO3/HOLD on net QSPI-D3 (U1 pin MIO5). The clock (SCLK) is on net QSPI-CLK and the chip select (/CS) is on net QSPI-/CS (U1 pin MIO1).

The chip select line QSPI-/CS has a pull-up resistor R86 (value from the resistor table: part of the R-GND group but connected between VCC3 and the QSPI-/CS net) to VCC3, ensuring the flash is deselected during FPGA power-up and configuration. The HOLD/IO3 line (QSPI-D3) has a pull-up R87 to VCC3, which keeps HOLD deasserted (high) during power-up, preventing the flash from entering a hold state. The WP/IO2 line (QSPI-D2) connects through R91 to a net that includes R54 pulled to VCC3 and Q5 (dual N-channel MOSFET), providing a controlled write-protect release mechanism.

The QSPI clock line passes through R6 (49.9 ohm series resistor) between U1 MIO6 and U4 SCLK, providing signal integrity damping. Data lines QSPI-D0 and QSPI-D1 have pull-down resistors R89 and R90 (from the R-GND group, connected to GND) for defined states during power-up. QSPI-CLK also has a pull-down R88 to GND. These pull-downs ensure deterministic states on the SPI bus before the FPGA configures its MIO pins.

U4 VCC is powered from VCC3 (3.3 V), which is within the W25Q128 operating range of 2.7 V to 3.6 V. The W25Q128 supports clock frequencies up to 104 MHz in standard SPI mode and 80 MHz or higher in quad mode depending on the specific variant. The Zynq QSPI controller can operate up to 50 MHz in quad mode for boot, which is well within the flash capability.

AI-Assisted J5 is a microSD card connector (JAE ST12S0 type) connected to the Zynq XC7Z020 MIO pins for SD card access. The interface uses a 4-bit data bus: D0 on net SD-D0 (U1 MIO42), D1 on net SD-D1 (U1 MIO43), D2 on net SD-D2 (U1 MIO44), D3 on net SD-D3 (U1 MIO45). The command line SD-CMD connects to U1 MIO41 with a 4.99K ohm pull-up R67 to VCC3. The clock line SD-CLK passes through a 49.9 ohm series resistor R8 between U1 MIO40 and the connector.

The card detect signal /SD-CD from J5 pin 11 connects to U1 MIO46 with a pull-up R53 to VCC3 and also gates Q5 (dual MOSFET). The VCC pin of J5 is powered from VCC3 (3.3 V), which is the standard operating voltage for SD cards.

The SD interface active pull-up on CMD is present and correct. The series resistor on the clock line provides signal integrity improvement for the SD clock. The SD data lines (D0 through D3) do not show explicit pull-up resistors on the schematic; the Zynq MIO pins have internal programmable pull-ups that are typically enabled for SD mode, which is standard practice for Zynq-based SD interfaces.

AI-Assisted The DDR3L interface is operated at 1.5 V (VDD and VDDQ), using the backward-compatible 1.5 V mode of the MT41K256M16 rather than the native 1.35 V DDR3L mode. This is a valid operating point per the Micron datasheet but results in higher power consumption compared to 1.35 V operation. If power optimization is a design goal, the supply could be reduced to 1.35 V, which would also require adjusting VTT to 0.675 V and VREF to 0.675 V.

The address/command termination scheme uses 40.2 ohm series resistors from the FPGA to the T-branch point, with the far side of each resistor connected to the 0.75 V VTT rail. This is an unconventional topology: typically, series source termination resistors are placed in line between the driver and the load, while VTT termination resistors are placed at the far end of the bus near the SDRAM devices. The current arrangement places the VTT pull on the FPGA side of the series resistor, which means the termination is at the source rather than the load. For a T-branch topology at DDR3-1066 speeds, this may still provide acceptable signal integrity, but it deviates from the standard Xilinx and Micron recommended termination placement. Layout-phase signal integrity simulation is strongly recommended for the address/command group.

The differential clock pair CLK_P/CLK_N passes through R35 (80.6 ohm) with one end to GND and the other on the clock net. Only one resistor is visible for the clock pair termination. The CLK_N net shows R35 pin 1 connected, and CLK_P shows R35 pin 2 connected. This means R35 bridges CLK_P and CLK_N rather than terminating either to ground, which would provide differential termination between the clock lines. An 80.6 ohm resistor across the differential pair is a reasonable value for DDR3 differential clock termination (typical differential impedance is 100 ohm, and a slightly lower termination value accounts for on-die termination contributions).

The /RESET net is shared between U1 (FPGA), U2, and U3. The voltage divider formed by R55 (499 ohm from VCC3) and R75 (4.99K ohm to GND) produces approximately 3.0 V at the /RESET node. For DDR3L devices operating at 1.5 V VDDQ, the reset input high level must not exceed VDD + 0.3 V = 1.8 V per the Micron absolute maximum ratings for input voltage. The 3.0 V level on /RESET exceeds this limit. However, the FPGA /D-RST output (U1 pin B4) also drives this net and will control the actual voltage during operation. If the FPGA output is driving low during reset and releasing to high-impedance afterward, the divider voltage would apply only when the FPGA output is tristated. This requires careful sequencing: the DDR3 /RESET pin voltage must not exceed VDDQ + 0.3 V at any time when VDD is applied. The 3.0 V idle level from the divider is a potential overvoltage risk for the DDR3L devices.

Memory	Interface	Finding	Severity
MT41K256M16 (U2, U3)	DDR3L SDRAM	/RESET net idle voltage from divider (R55/R75) is approximately 3.0 V, which exceeds the DDR3L absolute maximum input voltage of VDD + 0.3 V = 1.8 V per Micron datasheet. Potential overvoltage risk when FPGA output is tristated.	High
MT41K256M16 (U2, U3)	DDR3L SDRAM	Address/command series termination resistors (40.2 ohm, R10-R32) have VTT pull on the FPGA side rather than at the SDRAM load end. Deviates from standard Xilinx/Micron recommended placement. Signal integrity simulation recommended.	Medium
MT41K256M16 (U2, U3)	DDR3L SDRAM	Data bus width is 32 bits (16 bits per device), split into four byte lanes with correct DQS/DM assignments per the Micron MT41K256M16 datasheet.
MT41K256M16 (U2, U3)	DDR3L SDRAM	Address bus A[14:0], bank address BA[2:0], and command signals are shared in T-branch topology between U2 and U3, acceptable for DDR3-1066 per Xilinx UG933.
MT41K256M16 (U2, U3)	DDR3L SDRAM	VDD and VDDQ supplied at 1.5 V, within the backward-compatible range specified by the Micron MT41K256M16 DDR3L datasheet (1.425 V to 1.575 V).
MT41K256M16 (U2, U3)	DDR3L SDRAM	ZQ calibration resistors R44 and R45 are 240 ohm to GND, matching the Micron datasheet requirement of 240 ohm +/- 1%.
MT41K256M16 (U2, U3)	DDR3L SDRAM	VREF (M8) and VREFQ (H1) on both devices connected to 0.75 V (VDDQ/2), correct per JEDEC DDR3 specification.
MT41K256M16 (U2, U3)	DDR3L SDRAM	VTT termination at 0.75 V generated by LP2998 (U18) with direct output sensing on VSEN pin, correct per LP2998 datasheet.
MT41K256M16 (U2, U3)	DDR3L SDRAM	Differential clock termination R35 (80.6 ohm) bridges CLK_P to CLK_N, providing differential termination. Value is reasonable for 100 ohm differential impedance.
MT41K256M16 (U2, U3)	DDR3L SDRAM	1.5V rail decoupling includes thirty-six 0.1 uF, four 0.47 uF, two 10 uF, two 220 uF ceramics, and one 1000 uF polarized capacitor. Adequate per Micron DDR3 design guidelines.
MT41K256M16 (U2, U3)	DDR3L SDRAM	0.75V VTT rail decoupling includes nineteen 0.1 uF, eight 0.47 uF, and three 220 uF ceramics. Adequate for LP2998 VTT regulator transient response.
MT41K256M16 (U2, U3)	DDR3L SDRAM	No TEN pin present on the 96-ball MT41K256M16 package. JEDEC Connectivity Test mode is not available on these devices; no DFT action required.
W25Q128 (U4)	QSPI Flash	Quad SPI data lines (IO0-IO3) connected to Zynq MIO2-MIO5. Clock through 49.9 ohm series resistor R6. Connections match Winbond W25Q128 datasheet pinout.
W25Q128 (U4)	QSPI Flash	Chip select QSPI-/CS has pull-up R86 to VCC3, and HOLD/IO3 has pull-up R87 to VCC3, ensuring safe power-up states per W25Q128 datasheet requirements.
W25Q128 (U4)	QSPI Flash	VCC powered from VCC3 (3.3 V), within the W25Q128 operating range of 2.7 V to 3.6 V per Winbond datasheet.
W25Q128 (U4)	QSPI Flash	Pull-down resistors R88 (QSPI-CLK), R89 (QSPI-D0), R90 (QSPI-D1) to GND provide deterministic bus states during FPGA configuration.
MicroSD (J5)	SD Card	4-bit SD data bus (D0-D3) connected to Zynq MIO42-MIO45. CMD line has 4.99K pull-up R67 to VCC3. Clock has 49.9 ohm series resistor R8.
MicroSD (J5)	SD Card	Card detect /SD-CD connected to MIO46 with pull-up R53 to VCC3. VCC supplied from VCC3 (3.3 V).

AI-Assisted U1 is a Xilinx Zynq-7000 XC7Z020 in CLG400 package. Its power rails are distributed as follows. VCCINT and VCC-BRAM pins are both connected to the 1.0V rail, which is correct per the datasheet recommendation that these two supplies share the same source. VCCAUX and VCCP-AUX pins are connected to the 1.8V rail, consistent with the 1.8V nominal requirement. VCCO for banks 500 and 501 (MIO banks) are connected to VCC3 (3.3V), and VCCO for bank 502 (DDR interface) is connected to 1.5V, appropriate for DDR3L at 1.5V VDDQ. VCCO for banks 34 and 35 are on VCC3 (3.3V), and VCCO for bank 13 is on 1.8V. VCCO for bank 0 is on VCC3 (3.3V), which sets the JTAG I/O voltage to 3.3V. The VCC-PLL pin (G8) is supplied through a ferrite bead filter from the 1.8V rail, with two 0.47uF and two 10uF capacitors on the filtered side, which is good practice for PLL supply filtering.

The CFGBVS pin (M6) is pulled to VCC3 through R50. Since bank 0 VCCO is 3.3V, tying CFGBVS to 3.3V is the correct configuration per Xilinx UG585 and DS190. The PROG_B pin (L6) is pulled to VCC3 through R49, and INIT_B (R10) is pulled to VCC3 through R51, both correct for normal configuration operation. The DONE pin (R11) is pulled to VCC3 through R52 and also drives the gate of Q4 (dual MOSFET), which appears to control LED indication.

The PS_POR_B pin (C7) is connected to the PGOOD net. This net is driven by the open-drain RST output of U17 (LTC2908-B1 supply monitor) and also connects to the ON pins of U12 and U13 (hot swap controllers), plus pull-up resistors R61 and R64 (each 1.50k to VCC3) and a pull-down R80 (13.3k to GND). The voltage divider formed by the parallel combination of R61 and R64 (750 ohms effective) against R80 (13.3k) produces approximately 3.13V when all open-drain outputs are released, which is above the POR_B high threshold. When U17 asserts RST low, POR_B is pulled low. This arrangement ensures POR_B is held low until all monitored supplies are within specification, satisfying the Zynq requirement.

The PS_CLK input (E7) is driven through R5 from the output of oscillator U20. U20 is a generic oscillator part; its frequency is not specified in the available data. The Zynq requires PS_CLK to be between 30 MHz and 60 MHz. The net name CLK33 suggests a 33 MHz oscillator, which would be within the valid range.

The PS_RST_B pin (B10) is connected to the /RESET net, which has a voltage divider from VCC3 through R55 (499 ohm) and R75 (4.99k to GND), producing approximately 3.0V at the pin. The DDR3 RESET pin and the Zynq DDR_RST (B4) output also connect to this net. The Zynq DDR_RST output drives the DDR reset, so this connection is correct for the Zynq to control DDR reset sequencing.

The JTAG interface pins TCK (F9), TDI (G6), TDO (F6), and TMS (J6) are routed to connector J7. Pin F10 (RSVD-GND) is listed as unconnected in the schematic. Per Xilinx guidelines, this reserved pin should be connected to GND. This is flagged as a concern.

The PUDC_B pin (U13) is connected to the PUD-C/LED net, which includes a pull-up R60 (1.00k to VCC3) and R60A (to GND). The PUDC_B pin controls whether internal pull-ups are enabled on I/O pins during configuration. With R60 pulling to VCC3 and R60A pulling to GND, the resulting voltage depends on R60A value, but R60A is listed as a component with only one pin visible (pin 1), suggesting it may be a single-ended component to GND. If R60A is not populated or is high impedance, PUDC_B would be high (3.3V), disabling internal pull-ups during configuration.

The RES pins (G5 and H5) are connected: G5 (RES-) connects through R33 (80.6 ohm) to GND, and H5 (RES+) connects through R34 (80.6 ohm) to 1.5V. Per Xilinx UG585, these pins require specific resistor values for the PS DDR interface calibration. The 80.6 ohm value is within the typical range for DDR3 ZQ calibration reference.

The DDR3 memory interface uses U2 and U3 (MT41K256M16), each providing 16 bits of data for a 32-bit total bus width. Address, command, and control signals are shared between both devices with 40.2 ohm series termination resistors to the 0.75V VTT rail. The VREF pins on U2 and U3 (H1 VREFQ and M8 VREF) are connected to the 0.75V rail, which is half of the 1.5V VDDQ, correct for DDR3 operation. The Zynq VREF0 (H6) and VREF1 (P6) pins are also on the 0.75V rail.

Several MIO pins are listed as unconnected: MIO16 through MIO33 and several others. These MIO pins may be unused in this design, which is acceptable if the Zynq PS peripheral mapping does not require them. The VREF pin (E11) for bank 501 is also unconnected, which could be a concern if any I/O in that bank uses a voltage-referenced input standard.

AI-Assisted U2 and U3 are Micron MT41K256M16 DDR3 SDRAM devices, each providing 256Mx16 (4Gbit) density. U2 handles the lower 16 data bits (DQ0-DQ15, DQS0, DQS1, DM0, DM1) and U3 handles the upper 16 bits (DQ16-DQ31, DQS2, DQS3, DM2, DM3). Both devices share address, bank address, command, control, and clock signals from U1.

The VDD pins on both U2 and U3 are connected to the 1.5V rail, and VDDQ pins are also on 1.5V. This is consistent with standard DDR3 operation at 1.5V. The VREF and VREFQ pins are connected to the 0.75V rail (VTT), which is the correct half-VDDQ reference voltage.

The DDR3 clock pair CLK_P and CLK_N is routed from U1 (L2 CK+ and M2 CK-) to both U2 and U3 (J7 CLK+ and K7 CLK-) with 80.6 ohm series resistors R35 on each line. The address and command lines each have 40.2 ohm series termination resistors with the far end pulled to 0.75V VTT, providing proper ODT-compatible termination.

The RESET pin (T2) on both U2 and U3 is connected to the /RESET net, which is driven by U1 DDR_RST output (B4). This allows the Zynq PS to control DDR3 reset sequencing.

The ZQ calibration pin (L8) on U2 connects to a net that is not detailed in the provided page nets, but the pin is present in the device. The ZQ pin requires a 240 ohm precision resistor to GND for impedance calibration. This connection is not visible in the provided data.

The VTT termination voltage (0.75V) is generated by U18 (LP2998), which senses the 0.75V output directly (DIRECT_SENSE on VSEN pin) and is powered from the 1.5V VDDQ rail on both PVIN and VDDQ pins. The LP2998 VREF output connects through a 0.1uF capacitor to GND, which is the standard reference bypass configuration. The LP2998 AVIN pin is connected to VCC3 (3.3V), and the SD (shutdown) pin is also tied to VCC3, keeping the device always enabled. The VTT rail has 19 bypass capacitors of 0.1uF, 8 of 0.47uF, and 3 of 220uF, providing substantial decoupling for the DDR termination supply.

AI-Assisted U10 and U11 are Realtek RTL8211F Gigabit Ethernet PHY transceivers, each connected to one port of the dual RJ-45 connector J8 (PULSE JXD0-2015NL with integrated magnetics). The RGMII interface of each PHY connects to U1 bank 13 I/Os (1.8V VCCO).

For U10, the RGMII transmit data (TXD0-TXD3, TX-EN, TX-CLK) and receive data (RXD0-RXD3, RX-VALID, RX-CLK) signals are routed to U1 bank 13 pins. The TX-CLK pin (pin 20) connects through R1 (49.9 ohm series resistor) to U1, and RX-CLK (pin 27) connects through R3 (49.9 ohm series resistor). Similarly for U11, TX-CLK connects through R2 and RX-CLK through R4. These series resistors provide signal integrity improvement on the clock lines.

The MDIO management interface uses a level-translation scheme. For U10, the MDC clock pin (pin 13) connects to U9 pin 4 (output of the NC7WZ17 Schmitt trigger buffer), and the MDIO data pin (pin 14) connects to U8 pin 3 (A1 port of TXS0101 level translator). For U11, MDC connects to U9 pin 6 (second output), and MDIO connects directly to U1 with a 1.50k pull-up to 1.8V (R63). The MDIO pins on both PHYs operate at the PHY VDD-IO voltage. U10 VDD-IO (pin 28) is supplied from a filtered net with a 1.0uF and a 0.1uF capacitor, and U11 VDD-IO (pin 28) is similarly filtered. The VDD-IO voltage determines the MDIO and LED output levels.

The RBIAS pin on U10 (pin 39) connects through R65 (2.49k) to GND, and on U11 (pin 39) through R66 (2.49k) to GND. The RTL8211F datasheet specifies a 12.1k resistor for RBIAS. The 2.49k value used here differs significantly from the datasheet recommendation. This is a potential concern that could affect PHY analog bias currents and transceiver performance.

The AVDD1.0 pins on U10 (pins 3, 8, 38) are supplied through a ferrite bead filter from a net that receives the output of the internal DC-DC converter (pin 30). The DC-DC output (pin 30) on U10 connects through inductor L6 (3.3uH) to a filtered supply node with a 220uF capacitor, a 10uF capacitor, two 10uF capacitors, and a 0.1uF capacitor. This 3.3uH inductor value is consistent with typical RTL8211F application circuits for the internal 1.0V switching regulator. The same topology is used for U11 with L7 (3.3uH).

The AVDD3.3 pins on U10 (pins 11, 40) are supplied through ferrite bead L13 from VCC3, with four 0.1uF and two 1.0uF capacitors on the filtered side. U11 AVDD3.3 pins use ferrite bead L14 with the same filtering arrangement.

The 25 MHz clock is provided by oscillator U19, whose output drives through R38 (100 ohm) to U10 XO pin (pin 37) and through R39 (100 ohm) to U11 XO pin (pin 37). The XI pins (pin 36) on both U10 and U11 are connected to GND, which is the correct configuration when using an external clock source rather than a crystal.

The CLKOUT pin (pin 35) on both U10 and U11 is marked as designer-NC (intentionally not connected), which is acceptable if the 25 MHz output clock is not needed elsewhere.

The LED0 pin (pin 32) on both U10 and U11 is listed as unconnected. The LED1 and LED2 pins are connected to the RJ-45 connector LED anodes/cathodes through appropriate current-limiting resistors. The green LED (LED1/100M indicator) uses R69 and R71 with pull-down to GND (active-low output sinks current), and the yellow LED (LED2/1000M indicator) uses R68 and R70 with pull-up to VCC3.

The INTR (interrupt) pins are active-low open-collector outputs. U10 INTR (pin 31) connects to U1 pin R16 (IO-L20P), and U11 INTR (pin 31) connects to U1 pin U14 (IO-L11P-SRCC). No external pull-up resistors are visible on these interrupt nets. The RTL8211F INTR is open-collector, so an external pull-up is needed. However, the Zynq internal pull-ups may be enabled in the FPGA configuration, or the pull-ups may be provided by the PHY VDD-IO through internal circuitry. The absence of explicit external pull-ups on these interrupt lines is noted.

The RESET pins on U10 and U11 are active-low. U10 RESET (pin 12) connects to U1 pin P20 with R58 (1.00k pull-down to GND), and U11 RESET (pin 12) connects to U1 pin N20 with R59 (1.00k pull-down to GND). The pull-down resistors ensure the PHYs are held in reset until the Zynq actively drives the reset lines high. This is a safe power-on default.

AI-Assisted U5 is a Texas Instruments TSB41AB2 IEEE 1394a-2000 two-port cable transceiver/arbiter. It interfaces with U1 through an 8-bit data bus (D0-D7), two control lines (CTL0, CTL1), LREQ, and SYSCLK. The data bus connects to U1 bank 35 I/Os (3.3V VCCO), which matches the TSB41AB2 supply voltage range of 3.0V to 3.6V.

The VCC pins (25, 26, 61, 62) and VCC-PLL (56) are connected to VCC3 (3.3V). The VCCA pins (30, 31, 42, 51, 52) are also on VCC3. The TSB41AB2 datasheet specifies 3.0V to 3.6V for all supply pins, so 3.3V is within range.

The crystal input XI (pin 59) receives a 24.576 MHz clock through R7 (49.9 ohm series resistor) from oscillator U7. The XO pin (pin 60) is marked as designer-NC, which is correct when using an external oscillator rather than a crystal (XO would be the crystal feedback output). The 24.576 MHz frequency matches the TSB41AB2 requirement.

The RESET pin (pin 53) connects to the FW-/RST net, which is active-low and has R83 (4.99k pull-down to GND). This pull-down holds the device in reset by default. U1 pin D20 drives this net to release reset under software control.

The TPBIAS0 output (pin 38) drives through the NOLBL_C32_1_1 net to the series termination resistors R111 and R112 (56 ohm each) for port 0 TPA lines. Similarly, TPBIAS1 (pin 47) drives through NOLBL_C31_1_1 to R109 and R110 (56 ohm each) for port 1 TPA lines. The cable port connections route through TVS protection diodes (D5-D12, SOT-523 dual series diodes) to the FireWire connectors J3 and J4.

The FILTER0 (pin 54) and FILTER1 (pin 55) pins connect to capacitors C10 (0.1uF). Pin 54 connects to one side of C10 and pin 55 to the other side, with the capacitor providing the required PLL loop filter.

The configuration pins are set as follows: TESTM (pin 27) connects through RN1 pin 5 (4.7k resistor pack). The CPS (pin 24) connects through RN1 pin 6. The ISO pin (pin 23) connects through RN1 pin 7. The C/LKON (pin 19) connects through RN2 pin 7. The LPS (pin 15) connects through RN2 pin 8. The resistor packs RN1 and RN2 are 4.7k each. RN1 pins 1 and 3 connect to GND, and pins 2 and 4 connect to VCC3. RN2 pins 1, 3, and 4 connect to VCC3, and pin 2 connects to GND. This means TESTM is pulled to GND (normal operation, not test mode), CPS is pulled to GND, ISO is pulled to GND (normal non-isolated operation), C/LKON is pulled to VCC3, and LPS is pulled to GND.

The PC0 (pin 20) and PC1 (pin 21) power class pins connect through RN2 pin 6 and RN1 pin 8 respectively. PC0 connects to VCC3 and PC1 connects to VCC3, setting the power class configuration.

The PD (pin 14) and SE (pin 28) and SM (pin 29) pins are connected to GND. PD low means the device is not in power-down mode. The CNA output (pin 3) is marked as designer-NC.

The R0 (pin 40) and R1 (pin 41) speed configuration pins connect through R79 (6.34k). R79 pin 1 connects to R0 and pin 2 connects to R1, suggesting these pins are tied together through a resistor, which would set the port speed configuration.

AI-Assisted U12 and U13 are LTC4210 hot swap controllers in SOT-23-6 packages. U12 controls the 3.3V output path and U13 controls the 5V output path, each using an external N-channel MOSFET for high-side switching.

U12 has VCC (pin 6) connected to VCC3 (3.3V) through the hot swap sense path. The SENSE pin (pin 5) connects to the drain of Q2 (N-channel MOSFET) through R117 (0.015 ohm sense resistor to VCC3). The GATE pin (pin 4) drives Q2 gate through R36 (100 ohm). The TIMER pin (pin 1) has capacitor C33 connected to GND. The ON pin (pin 3) connects to the PGOOD net.

U13 has VCC (pin 6) connected to the 5V rail. The SENSE pin (pin 5) connects to the drain of Q1 through R118 (0.015 ohm sense resistor). The GATE pin (pin 4) drives Q1 gate through R37 (100 ohm). The TIMER pin (pin 1) has capacitor C34 connected to GND. The ON pin (pin 3) also connects to the PGOOD net.

The 0.015 ohm sense resistors set the current limit at 50mV / 0.015 ohm = 3.33A for each channel. The LTC4210 supply voltage range is 2.7V to 16.5V, so both 3.3V and 5V supplies are within the valid operating range.

The ON pins of both controllers are tied to the PGOOD net, which is driven by U17 (LTC2908-B1) RST output. The PGOOD net has pull-up resistors R61 and R64 (each 1.50k to VCC3, 750 ohm parallel) and pull-down R80 (13.3k to GND). When PGOOD is low (supplies out of specification), the ON pin voltage is pulled low, which keeps the hot swap controllers in their off/reset state. The ON pin low-to-high threshold is 1.3V. With the divider ratio of approximately 0.947 (from the voltage divider data), the ON pin voltage when PGOOD is released would be approximately 3.13V, well above the 1.3V threshold.

The 3.3V-OUT net (Q2 source) connects to J1 pins 39 and 40 and J9 pin 2. The 5V-OUT net (Q1 source) connects to J1 pins 41 and 42. These are the hot-swap-protected power outputs to the connectors.

AI-Assisted U17 is an LTC2908-B1 precision six-input supply monitor in SOT-23-8 package. The B1 variant monitors fixed thresholds for 3.3V, 2.5V, 1.8V, and 1.5V inputs, plus two adjustable inputs.

Pin 8 (3.3V input) is connected to VCC3. Pin 1 (2.5V input) is connected to 5V-DCDC. Pin 6 (1.8V input) is connected to the 1.8V rail. Pin 2 (1.5V input) is connected to the 1.5V rail. The 2.5V monitoring input (pin 1) is connected to the 5V-DCDC rail, not to a 2.5V supply. The LTC2908-B1 has a fixed 2.5V threshold on this pin (with approximately plus or minus 1.5 percent accuracy, meaning the threshold is approximately 2.5V). The 5V-DCDC rail is nominally 5V, which is well above the 2.5V threshold, so this input will always read as good once the 5V-DCDC rail reaches 2.5V during ramp-up. The maximum voltage on V1/V2 must not exceed 6V. The 5V-DCDC rail at nominal 5V is within the 6V absolute maximum, but there is limited margin. Any overshoot on the 5V-DCDC rail above 6V could damage U17.

Pin 7 (VADJ1) is connected to VCC3. The adjustable threshold is 0.5V, so this input monitors whether VCC3 exceeds 0.5V, which provides very early detection of VCC3 presence but not precision monitoring of the 3.3V level (that is handled by pin 8).

Pin 5 (VADJ2) connects to the NOLBL_R105_1_1 net, which is a voltage divider from the 1.0V rail through R98 (100k) and R105 (115k to GND). The divided voltage is 1.0V times 115k/(100k+115k) = 0.535V. The adjustable threshold is 0.5V, so the 1.0V rail must reach approximately 0.5V/0.535 = 0.935V before this input clears. This provides monitoring of the 1.0V core supply with approximately 6.5 percent undervoltage margin.

The RST output (pin 3) is active-low open-drain, connected to the PGOOD net. The GND pin (pin 4) is connected to ground. No dedicated bypass capacitor is visible directly on U17 power pins in the provided data, but U17 derives its internal VCC from the greater of V1 (5V-DCDC) and V2 (1.5V). The 5V-DCDC rail has extensive decoupling.

AI-Assisted U7, U19, and U20 are oscillators using a generic part number placeholder. All three share the same pinout: pin 4 (VCC), pin 1 (EN), pin 3 (OUT), and pin 2 (GND).

U7 provides the 24.576 MHz clock for the TSB41AB2 FireWire transceiver (U5). Its output (pin 3) connects through R7 (49.9 ohm) to U5 XI input. VCC (pin 4) and EN (pin 1) are both connected to VCC3 (3.3V), keeping the oscillator always enabled. GND (pin 2) is connected to ground.

U19 provides the 25 MHz clock for both Ethernet PHYs. Its output connects through R38 (100 ohm) to U10 XO and through R39 (100 ohm) to U11 XO. VCC and EN are both on VCC3, and GND is grounded. The net name e-CLK25 confirms the 25 MHz frequency.

U20 provides the PS_CLK for the Zynq (U1). Its output connects through R5 (49.9 ohm) to U1 CLK input (E7). VCC and EN are both on VCC3. The net name CLK33 suggests 33 MHz, which is within the Zynq PS_CLK requirement of 30 to 60 MHz. The EN pin is connected to the PGOOD net, meaning the oscillator is enabled only after all monitored supplies are stable. This is important because PS_CLK must be valid before POR_B is released, and since POR_B is also on the PGOOD net, both signals transition together. The Zynq requires PS_CLK to be stable before POR_B goes high. If the oscillator startup time is shorter than the POR_B release delay, this is acceptable. However, if the oscillator takes longer to stabilize than the POR_B path delay, there could be a timing violation.

Correcting the previous paragraph: reviewing the data again, U20 EN (pin 1) connects to VCC3 based on the power rail listing, and the PGOOD connection to U20 is through pin 1 (EN). The page_nets S10 data shows PGOOD connecting to U20_1:EN. So U20 EN is driven by PGOOD, not VCC3. This means the 33 MHz oscillator only starts when PGOOD goes high, and POR_B (also on PGOOD) goes high simultaneously. The Zynq datasheet requires PS_CLK to be stable and within specification before POR_B is deasserted. Since the oscillator needs startup time (typically a few milliseconds), POR_B will be released before PS_CLK is stable, which violates the Zynq power-on reset timing requirement.

AI-Assisted U8 is a TXS0101 single-bit bidirectional voltage-level translator. VCCA (pin 1) is connected to 1.8V, and VCCB (pin 6) is connected to VCC3 (3.3V). The VCCA range is 1.65V to 3.6V and VCCB range is 2.3V to 5.5V, with the requirement that VCCA must be less than or equal to VCCB. With VCCA at 1.8V and VCCB at 3.3V, this constraint is satisfied.

The OE pin (pin 5) is connected to the 1.8V rail. The TXS0101 datasheet recommends tying OE to GND through a pull-down resistor during power-up and power-down sequences to ensure outputs are in high-impedance state. Connecting OE directly to the 1.8V rail means the translator is enabled as soon as the 1.8V supply comes up, which could cause bus contention during power sequencing if the 3.3V side is not yet stable. A pull-down resistor on OE would be advisable.

The A1 port (pin 3) connects to the e1-MDIO-D/1.8 net, which also has R62 (1.50k pull-up to 1.8V) and connects to U10 MDIO (pin 14). The B1 port (pin 4) connects to the e1-MDIO-D net, which goes to U1 pin T20. The TXS0101 has internal 10k pull-ups on both ports. The external 1.50k pull-up on the A1 side provides a stronger pull-up for the MDIO open-drain bus, which is appropriate.

U9 is an NC7WZ17 dual Schmitt trigger buffer. VCC (pin 5) is connected to 1.8V. Input 1 (pin 1) connects to the e1-MDIO-C net from U1, and output 1 (pin 4) connects to e1-MDIO-C/1.8 going to U10 MDC. Input 2 (pin 3) connects to e2-MDIO-C from U1, and output 2 (pin 6) connects to e2-MDIO-C/1.8 going to U11 MDC. The buffer translates the 3.3V MDIO clock signals from the Zynq bank 34 (3.3V VCCO) down to 1.8V levels for the PHY MDC inputs. Since the NC7WZ17 inputs tolerate up to 5.5V regardless of VCC, the 3.3V input signals are safe. The outputs will swing to the VCC level (1.8V), matching the PHY VDD-IO if configured for 1.8V operation.

The VDD-IO voltage on U10 and U11 determines the RGMII and MDIO interface voltage. The VDD-IO pins connect through filtered nets. The use of 1.8V level translation on MDC and MDIO suggests the PHYs are configured for 1.8V I/O operation, which would be consistent with the Zynq bank 13 VCCO of 1.8V for the RGMII interface.

AI-Assisted U6 is a TLVH431 adjustable precision shunt regulator in SC70-6 package. The cathode (pin 1) connects to the NOLBL_Q6_1_B net, which drives the base of Q6 (PNP transistor) through R56 (1.00k). The anode (pin 6) is connected to GND. The ADJ (reference/feedback) pin (pin 3) connects to the NOLBL_R82_1_1 net, which is a voltage divider from the 5V rail through R93 (31.6k) in series with R57 (1.00k) on top, and R82 (20.0k) on the bottom to GND. The divider ratio is 20.0k / (31.6k + 1.0k + 20.0k) = 0.380. The TLVH431 regulates to keep the ADJ pin at VREF (1.24V), so the regulated voltage at the top of the divider would be 1.24V / 0.380 = 3.26V. This appears to be part of a fault detection circuit monitoring the 5V rail. The V-FAULT net connects to the junction of R93 and R57, with TVS protection diodes and a capacitor C41 (22uF). The PNP transistor Q6 and the shunt regulator form a voltage monitoring and fault indication circuit.

AI-Assisted U4 is a Winbond W25Q128 128Mbit (16MB) QSPI flash memory. VCC (pin 8) is connected to VCC3 (3.3V), and GND (pin 4) is grounded. The chip select CS (pin 1) connects to the QSPI-/CS net with R86 (4.99k pull-up to VCC3) and routes to U1 MIO1. The clock SCLK (pin 6) connects to QSPI-CLK with R88 (20.0k pull-down to GND) and R6 routing to U1 MIO6. The data pins IO0/SDI (pin 5), IO1/SDO (pin 2), IO2/WP (pin 3), and IO3/HOLD (pin 7) connect to U1 MIO2, MIO3, MIO4, and MIO5 respectively.

The pull-ups and pull-downs are appropriate: CS has a pull-up to keep the flash deselected during power-up, HOLD has a pull-up (R87 to VCC3) to prevent inadvertent hold, and WP connects through R91 to U1 MIO4 with Q5 MOSFET in the path (NOLBL_Q5_3_D2 net shows R54 pull-up to VCC3 and R91 connecting to QSPI-D2). The WP pin protection through Q5 allows the Zynq to control write protection.

The W25Q128 at 16MB capacity is sufficient for XC7Z020 configuration bitstreams, which are approximately 4MB for the PL portion. The Zynq boots from QSPI using the PS MIO pins, which is the standard boot configuration.

The QSPI-CLK net has R88 (20.0k pull-down to GND) and also R6 connecting MIO6 to R5 junction. Looking at the net more carefully, R6 pin 1 connects to MIO6 and pin 2 connects to QSPI-CLK. R88 pin 2 connects to GND. This pull-down on the clock line ensures the clock is low during power-up, preventing spurious clock edges to the flash.

AI-Assisted U15 is an LTC3644 quad-output step-down regulator. All four VIN pins (B6, E6, E1, B1) are connected to the 5V-DCDC rail. The SVIN pin (A5) connects through R9 (4.99 ohm) and a 10uF bypass capacitor to the 5V-DCDC rail, providing filtered supply sensing.

Channel 1 (SW1 via L3 at 0.68uH) produces the 1.0V rail. The feedback divider uses R100 (100k from 1.0V) and R106 (150k to GND), giving a ratio of 0.600. With the LTC3644 internal reference of 0.6V, the output voltage is 0.6V / 0.600 = 1.0V. This is correct for the Zynq VCCINT/VCCBRAM supply.

Channel 2 (SW2 shares the same SW pins as channel 1 in the net data, connecting through L3). Looking at the filter net data, SW1 and SW2 both connect to NOLBL_L3_1_1 which feeds through L3 to 1.0V. The FB2 pin connects to the INTVCC2 net along with INTVCC output and PHASE pin. This suggests channel 2 is configured to track the internal VCC (INTVCC) rather than produce an independent output. The PGOOD2 (E5) and PGOOD3 (E2) pins are marked as designer-NC.

Channel 3 (SW3 via L4 at 1.5uH) produces the 1.5V rail. The feedback divider uses R107 (150k from 1.5V) and R101 (100k to GND), giving a ratio of 0.400. Output voltage is 0.6V / 0.400 = 1.5V. This is correct for DDR3 VDDQ.

Channel 4 (SW4 via L5 at 1.5uH) produces the 1.8V rail. The feedback divider uses R108 (200k from 1.8V) and R99 (100k to GND), giving a ratio of 0.333. Output voltage is 0.6V / 0.333 = 1.8V. This is correct for VCCAUX.

The RUN1 (C5) and RUN2 (F5) pins are connected to 5V-DCDC, enabling channels 1 and 2 immediately when input power is present. RUN3 (F2) connects to the OK-1.8V net, meaning channel 3 (1.5V) starts only after the 1.8V rail is good. RUN4 (C2) connects to OK-1V, meaning channel 4 (1.8V) starts after the 1.0V rail is good. This creates a sequencing chain: 1.0V first, then 1.8V (via PGOOD4 to OK-1.8V enabling RUN3), then 1.5V. However, the Zynq recommended PL power-on sequence is VCCINT then VCCBRAM then VCCAUX then VCCO. With VCCINT and VCCBRAM on the same 1.0V rail, and VCCAUX on 1.8V, the sequence 1.0V then 1.8V is correct. The 1.5V (VCCO for DDR bank) coming after 1.8V also satisfies the constraint that VCCO must not precede VCCAUX by more than the allowed time.

The MODE/SYNC pin (D2) receives the /1.2MHz signal from U14 (LTC6902) OUT1, providing external clock synchronization. The PGOOD1 (B5) connects to OK-1V, and PGOOD4 (B2) connects to OK-1.8V, forming the sequencing chain.

The input decoupling on 5V-DCDC includes six 0.1uF, one 100uF, four 22uF, and one 330uF capacitor, providing substantial input filtering.

AI-Assisted U16 is an LTC3636 dual-output synchronous step-down regulator. Both VIN1 and VIN2 pin groups connect to the V-IN rail, which is supplied through L15 and Q3 (P-channel MOSFET) from the PWR input. The V-IN rail has two 10uF ceramic and two 33uF polarized capacitors for input decoupling.

Channel 1 (SW1 via L2 at 1.2uH) produces the VCC3 (3.3V) rail. The feedback divider uses R104 (100k from VCC3) and R97 (22.1k to GND), giving a ratio of 0.181. With the LTC3636 internal reference of 0.6V, the output voltage is 0.6V / 0.181 = 3.31V. This is within the 3.3V specification.

Channel 2 (SW2 via L1) produces the 5V-DCDC rail. The feedback divider uses R103 (100k from 5V-DCDC) and R81 (13.3k to GND), giving a ratio of 0.117. Output voltage is 0.6V / 0.117 = 5.12V. This is close to 5V but slightly high. The actual calculated value with precise resistor ratios is 0.6V times (100k + 13.3k) / 13.3k = 5.11V.

The RT pin (pin 4) connects through R96 (31.6k to GND), which sets the switching frequency. The TRACK/SS1 (pin 26) and TRACK/SS2 (pin 11) pins have 4700pF capacitors (C77 and C78) to GND for soft-start timing.

The MODE/SYNC pin (pin 3) receives the 1.2MHz signal from U14 OUT2, providing external clock synchronization. The RUN1 (pin 2) connects to OK-1.8V, and RUN2 (pin 7) connects through a resistor divider (R102 and R92) to a test point. The PGOOD1 (pin 27), PGOOD2 (pin 10), and TMON (pin 6) pins are all listed as unconnected. The absence of PGOOD connections means there is no feedback to the sequencing chain from the VCC3 and 5V-DCDC rails, though U17 monitors these rails independently.

The INTVCC pin (pin 5) connects to the INTVCC net with a 10uF bypass capacitor (CB138) to GND. The ITH1 (pin 1) and ITH2 (pin 8) compensation pins also connect to this INTVCC net. This is unusual; typically ITH pins connect to dedicated compensation networks (resistor-capacitor to GND), not to the INTVCC supply. If ITH1 and ITH2 are truly connected to INTVCC, the loop compensation may not function correctly. This warrants careful review.

AI-Assisted U14 is an LTC6902 multiphase oscillator in MSOP-10 package. The Vin pin (pin 1) is connected to 5V-DCDC. The GND pin (pin 8) is connected to ground. The SET pin (pin 10) connects through R94 (162k) to set the master oscillator frequency. The MOD pin (pin 9) connects through R95 (301k) to configure the modulation or frequency fine-tuning.

The DIV pin (pin 2) is connected to GND, and the PH pin (pin 3) is also connected to GND. Per the LTC6902 datasheet, DIV and PH pin configurations determine the number of output phases and the frequency division ratio.

OUT1 (pin 4) produces the /1.2MHz signal that synchronizes U15 (LTC3644), and OUT2 (pin 5) produces the 1.2MHz signal that synchronizes U16 (LTC3636). OUT3 (pin 6) and OUT4 (pin 7) are marked as designer-NC, which is acceptable if only two synchronized outputs are needed.

The net names /1.2MHz and 1.2MHz suggest the two outputs are complementary (inverted) versions of a 1.2MHz clock, which would provide interleaved switching for the two regulators to reduce input ripple.

AI-Assisted The microSD card connector J5 interfaces with U1 through MIO pins. The SD data lines D0-D3 connect to MIO42, MIO43, MIO44, and MIO45. The CMD line connects to MIO41 with R67 (4.99k pull-up to VCC3). The CLK line connects through R8 (49.9 ohm series resistor) to MIO40. The card detect signal (CD, active-low) connects to MIO46 with R53 (4.99k pull-up to VCC3) and also drives Q5 gate (G2), which controls the QSPI WP path.

The VCC pin (pin 4) of J5 is connected to VCC3 (3.3V), providing the standard SD card supply voltage. The pull-up on CMD is required by the SD specification for proper bus idle state.

Device	Category	Finding	Severity
U1 (XC7Z020-CLG400)	FPGA	PS_CLK oscillator U20 EN pin is gated by PGOOD, same signal as POR_B. Oscillator startup delay may cause PS_CLK to be unstable when POR_B is released, violating Zynq timing requirement that PS_CLK must be stable before POR_B deasserts.	High
U10 (RTL8211F)	Ethernet PHY	RBIAS pin connected through R65 (2.49k) to GND. RTL8211F datasheet specifies 12.1k for RBIAS. Incorrect resistor value may cause PHY analog bias errors and degraded transceiver performance.	High
U11 (RTL8211F)	Ethernet PHY	RBIAS pin connected through R66 (2.49k) to GND. Same concern as U10: 2.49k versus datasheet-specified 12.1k.	High
U16 (LTC3636)	Power	ITH1 (pin 1) and ITH2 (pin 8) are connected to the INTVCC net along with INTVCC output (pin 5). The ITH pins are loop compensation pins that normally require dedicated RC networks to GND. Connecting them to INTVCC may compromise loop stability.	High
U20 (Oscillator)	Clock	Provides PS_CLK (33 MHz per net name) to Zynq. EN gated by PGOOD, creating potential timing violation with POR_B on same net.	High
U1 (XC7Z020-CLG400)	FPGA	Pin F10 (RSVD-GND) is unconnected in the schematic. Xilinx requires this pin to be connected to GND.	Medium
U17 (LTC2908-B1)	Supply Monitor	Pin 1 (2.5V threshold input) connected to 5V-DCDC rail. The 5V nominal voltage is within the 6V maximum but provides only 1V of margin. Any overshoot above 6V could damage the device.	Medium
U7 (Oscillator)	Clock	Provides 24.576 MHz to TSB41AB2. VCC and EN on VCC3, always enabled. Generic part number; actual specifications not verifiable.	Low
U8 (TXS0101)	Level Translator	OE pin tied directly to 1.8V rail instead of using a pull-down resistor for controlled enable during power sequencing. TI datasheet recommends pull-down on OE during power-up/power-down to ensure high-impedance state.	Low
U10/U11 (RTL8211F)	Ethernet PHY	INTR (active-low open-collector) pins connected to Zynq I/Os without visible external pull-up resistors. External or FPGA-internal pull-ups are required for proper interrupt signaling.	Low
U16 (LTC3636)	Power	PGOOD1 (pin 27), PGOOD2 (pin 10), and TMON (pin 6) are unconnected. No power-good feedback from VCC3 or 5V-DCDC rails to the sequencing chain, though U17 provides independent monitoring.	Low
U19 (Oscillator)	Clock	Provides 25 MHz clock to both Ethernet PHYs through 100 ohm series resistors. VCC and EN on VCC3. Generic part number; actual specifications not verifiable.	Low
U1 (XC7Z020-CLG400)	FPGA	VCCINT and VCC-BRAM both connected to 1.0V rail, VCCAUX on 1.8V, VCCO banks correctly assigned. Power supply configuration is correct per DS190.
U1 (XC7Z020-CLG400)	FPGA	CFGBVS (M6) tied to VCC3 via R50, matching bank 0 VCCO of 3.3V. Correct per UG585.
U1 (XC7Z020-CLG400)	FPGA	JTAG pins TCK, TDI, TDO, TMS routed to connector J7. Bank 0 VCCO is 3.3V, setting JTAG levels.
U1 (XC7Z020-CLG400)	FPGA	PL power sequencing via U15 RUN chain: 1.0V then 1.8V then 1.5V. Satisfies VCCINT before VCCAUX before VCCO requirement.
U1 (XC7Z020-CLG400)	FPGA	DDR3 interface: 32-bit data bus with U2 and U3, address/command with 40.2 ohm series termination to 0.75V VTT. VREF pins at 0.75V (half VDDQ). Correct DDR3 termination scheme.
U2/U3 (MT41K256M16)	Memory	VDD at 1.5V, VDDQ at 1.5V, VREF/VREFQ at 0.75V. Standard DDR3 voltage levels.
U2/U3 (MT41K256M16)	Memory	RESET driven by Zynq DDR_RST output (U1 B4) on /RESET net with R55/R75 divider providing approximately 3.0V. Correct for Zynq-controlled DDR reset.
U4 (W25Q128)	Configuration Flash	16MB QSPI flash connected to Zynq MIO1-MIO5 for boot. CS pull-up, HOLD pull-up, CLK pull-down all present. Capacity sufficient for XC7Z020 bitstream.
U5 (TSB41AB2)	IEEE 1394	24.576 MHz clock from U7 through 49.9 ohm series resistor to XI pin. XO pin designer-NC (correct for external oscillator). Frequency matches datasheet requirement.
U5 (TSB41AB2)	IEEE 1394	VCC and VCCA pins all on VCC3 (3.3V), within 3.0V to 3.6V operating range.
U5 (TSB41AB2)	IEEE 1394	TESTM pulled to GND via 4.7k (normal operation). PD tied to GND (not in power-down). ISO tied to GND (non-isolated mode). Configuration pins correctly set.
U6 (TLVH431)	Voltage Reference	Shunt regulator configured with voltage divider (R93+R57 top, R82 bottom) monitoring 5V rail. ADJ pin regulated to 1.24V, setting trip point at approximately 3.26V. Used in fault detection circuit with Q6.
U8 (TXS0101)	Level Translator	VCCA at 1.8V, VCCB at 3.3V. VCCA less than VCCB constraint satisfied. Translates MDIO data between 1.8V PHY domain and 3.3V Zynq domain.
U9 (NC7WZ17)	Buffer	VCC at 1.8V, within 1.65V to 5.5V range. Inputs from 3.3V Zynq I/Os are within 5.5V input tolerance. Outputs at 1.8V for PHY MDC pins. Correct level translation.
U10/U11 (RTL8211F)	Ethernet PHY	25 MHz clock from U19 through 100 ohm series resistors to XO pins. XI pins tied to GND. Correct external clock input configuration.
U10/U11 (RTL8211F)	Ethernet PHY	Internal 1.0V DC-DC converter outputs through 3.3uH inductors (L6, L7) with adequate output capacitance. AVDD3.3 filtered through ferrite beads from VCC3.
U10/U11 (RTL8211F)	Ethernet PHY	RESET pins have 1.00k pull-downs to GND (R58, R59), holding PHYs in reset until Zynq drives high. Safe power-on default.
U12 (LTC4210)	Hot Swap	VCC on VCC3 (3.3V), within 2.7V to 16.5V range. Sense resistor R117 at 0.015 ohm sets 3.33A current limit. Timer capacitor C33 present.
U13 (LTC4210)	Hot Swap	VCC on 5V rail, within 2.7V to 16.5V range. Sense resistor R118 at 0.015 ohm sets 3.33A current limit. Timer capacitor C34 present.
U12/U13 (LTC4210)	Hot Swap	ON pins tied to PGOOD net with pull-up divider producing approximately 3.13V when released, well above 1.3V ON threshold. Controllers disabled during supply fault conditions.
U14 (LTC6902)	Clock Generator	Vin on 5V-DCDC. SET resistor R94 (162k) and MOD resistor R95 (301k) configure frequency. DIV and PH tied to GND. OUT1 and OUT2 provide synchronized clocks for U15 and U16.
U15 (LTC3644)	Power	Channel 1 output 1.0V verified: FB divider R100/R106 gives ratio 0.600, VOUT = 0.6V/0.600 = 1.0V. Channel 3 output 1.5V: R107/R101 ratio 0.400, VOUT = 1.5V. Channel 4 output 1.8V: R108/R99 ratio 0.333, VOUT = 1.8V. All correct.
U15 (LTC3644)	Power	Power sequencing chain: RUN1/RUN2 on 5V-DCDC (always on), PGOOD1 enables RUN4 (1.8V), PGOOD4 enables RUN3 (1.5V). Sequence: 1.0V then 1.8V then 1.5V.
U16 (LTC3636)	Power	Channel 1 output VCC3: FB divider R104/R97 ratio 0.181, VOUT = 3.31V. Channel 2 output 5V-DCDC: R103/R81 ratio 0.117, VOUT = 5.12V. Both within acceptable tolerance.
U17 (LTC2908-B1)	Supply Monitor	VADJ2 divider from 1.0V rail: R98 (100k) / R105 (115k) gives 0.535V at pin 5, above 0.5V threshold. Monitors 1.0V rail with approximately 6.5% undervoltage detection margin.
U17 (LTC2908-B1)	Supply Monitor	3.3V, 1.8V, and 1.5V inputs connected to their respective rails. RST output drives PGOOD net for system-wide power-good indication.
U18 (LP2998)	VTT Regulator	VSEN and VTT on 0.75V rail (direct sense). PVIN and VDDQ on 1.5V. AVIN on VCC3. SD tied to VCC3 (always enabled). Correct DDR3 VTT termination regulator configuration.

AI-Assisted Each PHY has its AVDD3.3 analog supply pins filtered from the VCC3 rail through a dedicated ferrite bead. U10 pins AVDD3.3 (pins 11 and 40) are supplied through ferrite L13, with four 100 nF and two 1 uF bypass capacitors on the filtered side. U11 pins AVDD3.3 (pins 11 and 40) are supplied through ferrite L14, with an identical filter network of four 100 nF and two 1 uF capacitors. This per-PHY analog supply filtering is good practice, preventing switching noise from the digital VCC3 rail from coupling into the sensitive analog transmit and receive circuits.

The digital VCC3 supply to U10 and U11 (pin VDD3.3, pin 29) is connected directly to the VCC3 rail with bulk and local bypass capacitance available from the main rail decoupling. The RBIAS pin on each PHY (U10 pin 39, U11 pin 39) is terminated through a precision resistor to ground: R65 at 2.49 kohm for U10 and R66 at 2.49 kohm for U11. These resistors set the internal bias current for the PHY analog front-end. The value is typical for many Gigabit Ethernet PHY devices, though the exact required value depends on the specific PHY part number, which is not explicitly identified in the schematic data.

AI-Assisted A 25 MHz oscillator U19 provides the reference clock for both PHYs. The clock signal is distributed to U10 pin XO (pin 37) through a 100 ohm series resistor R38 on net e1-CLK25, and to U11 pin XO (pin 37) through a 100 ohm series resistor R39 on net e2-CLK25. The 100 ohm series resistors serve as damping resistors to reduce reflections and ringing on the clock traces. U19 is powered from VCC3 with its enable pin tied to VCC3, ensuring the oscillator starts as soon as the 3.3 V rail is stable.

The MDIO management data bus uses a level-translation scheme. For U10 (PHY 1), the MDIO data line (U10 pin 14) connects through U8, a TXS0101 bidirectional level translator, with VccA on 1.8 V and VccB on VCC3. This translates the MDIO signal between the 1.8 V FPGA I/O bank (U1 pin W6, IO-L22N) and the 3.3 V PHY domain. A 1.5 kohm pull-up resistor R62 ties the 1.8 V side of the MDIO line to the 1.8 V rail. For U11 (PHY 2), the MDIO data line (U11 pin 14) connects directly to the FPGA (U1 pin W6) on net e2-MDIO-D/1.8, with a 1.5 kohm pull-up R63 to 1.8 V. Both PHYs share the same FPGA MDIO data pin, which is appropriate since MDIO is a shared bus protocol with device addressing.

The MDC clock for both PHYs is generated by the FPGA and buffered through U9, an NC7WZ17 dual Schmitt-trigger buffer. U9 pin 4 drives U10 MDC (pin 13) on net e1-MDIO-C/1.8, and U9 pin 6 drives U11 MDC (pin 13) on net e2-MDIO-C/1.8. U9 is powered from 1.8 V, matching the FPGA I/O voltage. The Schmitt-trigger input provides noise immunity and clean edges on the MDC clock.

AI-Assisted Each PHY has an active-low reset input driven from the FPGA. U10 pin RESET (pin 12) is driven by U1 pin P20 (IO-L14N-SRCC) on net e1-/RESET, with a 1 kohm pull-down resistor R58 to ground. U11 pin RESET (pin 12) is driven by U1 pin N20 (IO-L14P-SRCC) on net e2-/RESET, with a 1 kohm pull-down resistor R59 to ground. The pull-down resistors hold the PHYs in reset when the FPGA outputs are in a high-impedance state during power-up, preventing the PHYs from operating in an undefined state before the FPGA is configured. This is correct behavior for active-low reset lines.

LED indicators are connected through the integrated LEDs in J8. For each port, the green LED anode connects to the PHY /LED1-100 output (U10 pin 33 for port A, U11 pin 33 for port B) through a current-limiting resistor to ground (R69 at 4.99 kohm for port A, R71 at 4.99 kohm for port B). The yellow LED cathode connects to the PHY LED2-1000 output (U10 pin 34 for port A, U11 pin 34 for port B) with the anode pulled to VCC3 through resistors (R41/R43 at 240 ohm for the yellow LED anodes, R68/R70 at 4.99 kohm for the LED2 outputs to VCC3). The green LED cathodes on J8 pins 12A and 12B are pulled to ground through R42 and R40 (240 ohm each).

AI-Assisted The design uses a single ground domain, GND, which serves both digital signal return and connector shell grounding. There is no separate chassis-ground (CGND) plane or dedicated earth connection. The IEEE 1394 (FireWire) connectors J3 and J4 have their shell pins (pins 7, 8, 9) tied directly to GND, and the dual RJ-45 connector J8 has its shield pins (pins 1 and 3) also tied directly to GND. This means that any ESD or EMI energy coupled onto a connector shell is injected directly into the digital signal-ground plane rather than being diverted through a controlled impedance path to a chassis or earth reference.

For EMC compliance per EN 55032 (radiated emissions) and IEC 61000-4-2 (ESD immunity), best practice is to provide a low-impedance chassis-ground domain that is connected to signal ground at a single, well-defined point, typically through a ferrite bead, a resistor-capacitor network, or a spark-gap device. This allows high-frequency noise and ESD transients to be shunted to the enclosure without disturbing the signal-ground plane. The current architecture, with shells tied directly to GND, risks ground-bounce events during ESD strikes on J3, J4, or J8 that propagate through the entire digital ground, potentially causing logic upsets in U1 (XC7Z020), U5 (TSB41AB2), U10, and U11 (RTL8211F).

No EMC barrier or doghouse annotation is present in the design, indicating that all components share a single EMC zone. There is no evidence of common-mode chokes, ferrite beads, or pi-filters on any signal lines entering or leaving the board through the connectors. The only filtering observed is series resistors on certain interfaces (56 ohm resistors on FireWire differential pairs, 49.9 ohm on SD-CLK, 4.99 kohm pull-ups on Ethernet LEDs and SD-CMD). These serve signal-integrity or current-limiting purposes but do not constitute EMC filtering.

The power input at J6 is protected by a TVS diode D1 (SMCJ16) between the PWR net and GND. This provides conducted-transient clamping on the DC input per IEC 61000-4-5 (surge) requirements. However, no common-mode filtering (e.g., a common-mode choke on the power input) is visible, which may be a concern for conducted emissions compliance per EN 55032 Class B depending on the cable length and switching-regulator noise spectrum from U15 (LTC3644) and U16 (LTC3636).

AI-Assisted J8 is a Pulse JXD0-2015NL dual-port RJ-45 connector with integrated magnetic transformers. This is a right-angle, panel-mount style connector, making it an external, user-facing interface. The integrated magnetics in the JXD0-2015NL provide galvanic isolation rated at 1500 Vrms per the Pulse Electronics datasheet for the JXD0 series. This isolation inherently attenuates ESD energy from the cable side before it reaches the PHY devices U10 and U11 (RTL8211F).

The Ethernet differential pairs (ETH1-A+/A- through ETH1-D+/D- and ETH2-A+/A- through ETH2-D+/D-) connect directly from the transformer secondary side to the RTL8211F PHY pins with no additional TVS devices in the signal path. Given the transformer isolation, this is an acceptable topology. The IEEE 802.3 standard and the Realtek RTL8211F datasheet application circuit do not mandate external TVS on the PHY side when integrated magnetics are used, as the transformer common-mode rejection and isolation voltage exceed the IEC 61000-4-2 contact-discharge levels (typically 4 kV for Level 2, 8 kV for Level 4 air discharge).

The connector shield pins (J8 pins 1 and 3) are tied to GND. Per the Pulse JXD0-2015NL datasheet, the recommended practice is to connect the shield to chassis ground, optionally through an RC network (e.g., 1 Mohm in parallel with 1 nF to chassis), to provide a controlled discharge path for cable-coupled ESD while maintaining common-mode noise rejection. Tying the shield directly to signal GND may compromise common-mode rejection and inject noise into the ground plane during an ESD event. The likely failure mode is degraded radiated-emissions performance and potential ground-bounce-induced bit errors on the RGMII interface between the PHYs and U1 during IEC 61000-4-2 testing.

The LED indicator circuits (e1-LED1, e1-LED2, e2-LED1, e2-LED2) are driven through 4.99 kohm series resistors (R68 through R71) from the RTL8211F LED output pins. These resistors provide adequate current limiting and some degree of transient attenuation for the LED paths, which are internal to the magjack module and not directly exposed to external cabling.

AI-Assisted J3 and J4 are 6-pin FireWire connectors in right-angle (panel-mount) footprints (Firewire6-RA), indicating external, user-facing ports. IEEE 1394 is a hot-plug interface where cables can be inserted and removed during operation, creating significant ESD exposure. The IEEE 1394a-2000 standard and IEC 61000-4-2 Level 4 (8 kV contact, 15 kV air discharge) are the relevant test criteria for consumer-facing FireWire ports.

Each differential pair on J3 and J4 is protected by a BAV99T dual series diode (D5 through D12) connected between the signal line and GND. Specifically, for port 0 (J3): TPA0p is clamped by D9, TPA0n by D10, TPB0p by D11, and TPB0n by D12. For port 1 (J4): TPA1p is clamped by D5, TPA1n by D6, TPB1p by D7, and TPB1n by D8. The BAV99T is a general-purpose switching diode with a forward voltage of approximately 1.25 V and a reverse recovery time of about 6 ns. While these diodes provide basic voltage clamping to GND and VCC (via the series-connected diode topology), they are not purpose-designed ESD protection devices. The BAV99T has a peak pulse power rating that is significantly lower than dedicated TVS arrays designed for IEC 61000-4-2 compliance.

The signal path from each connector pin passes through a 56 ohm series resistor (R109 through R116) and an AC-coupling capacitor (C31 and C32 at 1.0 uF for TPA pairs, C6 and C7 at 220 pF for TPB pairs) before reaching the TSB41AB2 (U5) transceiver pins. The AC-coupling capacitors provide some degree of DC blocking and transient energy absorption, but the 220 pF capacitors on the TPB pairs have limited energy-absorption capability. The 56 ohm series resistors help limit peak current into U5 during a transient event.

The connector shells (J3 pins 7, 8, 9 and J4 pins 7, 8, 9) and the cable-shield return pins (J3 pin 2 and J4 pin 2, labeled V-) are all tied directly to GND. Per the IEEE 1394a specification and TI TSB41AB2 datasheet, the cable shield should be connected to chassis ground, not signal ground, to prevent ground-loop currents and ESD injection into the signal plane. The V+ pins (J3 pin 1 and J4 pin 1) are not connected to any visible power net in the traced paths, which is consistent with a design that does not supply bus power through the FireWire ports.

The likely failure mode under IEC 61000-4-2 testing is ESD-induced latch-up or damage to U5 (TSB41AB2), as the BAV99T diodes may not clamp fast enough or absorb sufficient energy at the 8 kV contact-discharge level. Ground bounce from shell-to-GND coupling could also cause data corruption on the active port during testing.

AI-Assisted J1 is a 22x2 pin header on a 2 mm pitch (HDR-22x2-2MM), a vertical through-hole connector typically used for board-to-board or ribbon-cable connections in an internal enclosure environment. It carries 34 general-purpose I/O signals (IO1-0 through IO1-33) directly from U1 (XC7Z020) FPGA Bank 35 pins, plus a 3.3 V power output (3.3V-OUT), a 5 V power output (5V-OUT on pins 41 and 42), and six GND pins.

All 34 I/O signals connect directly from the connector pins to the FPGA with no series resistors, no ESD protection devices, and no filtering components in the signal path. The FPGA I/O pins in Bank 35 are powered from VCC3 (3.3 V) and have internal ESD structures rated per the Xilinx 7-series datasheet (DS181) at approximately 2 kV Human Body Model (HBM). This is adequate for board-to-board connections within a closed enclosure but would not meet IEC 61000-4-2 requirements if the signals are routed to an external panel connector or a cable longer than approximately 10 cm.

The 5V-OUT power pins (41, 42) and 3.3V-OUT power pins (39, 40) have no visible TVS or overcurrent protection on this connector. The 3.3V-OUT net is sourced through Q2 (Si7108 N-channel MOSFET), which acts as a power switch. If J1 is used as an internal board-to-board connection, the absence of external ESD protection is a reasonable design choice. If J1 is intended to connect to an external cable or a daughter card that may be hot-plugged, dedicated TVS arrays on the I/O lines and a TVS on the power outputs would be warranted per IEC 61000-4-2.

AI-Assisted J2 is identical in form factor to J1: a 22x2 pin header on 2 mm pitch (HDR-22x2-2MM), vertical mount. It carries 40 general-purpose I/O signals (IO2-0 through IO2-39) from U1 (XC7Z020) FPGA Bank 34 pins, with four GND pins and no power pins.

As with J1, all 40 I/O signals connect directly from the connector to the FPGA with no series components, no TVS devices, and no filtering. The FPGA Bank 34 VCCO is powered from VCC3 (3.3 V). The same considerations apply: the Xilinx internal ESD rating of approximately 2 kV HBM is sufficient for internal board-to-board use but insufficient for external cable exposure. The absence of any series resistance means that fast transients will propagate directly to the FPGA die.

J2 has only four GND pins (pins 1, 15, 29, 43) distributed across the 44-pin connector, providing a ground pin roughly every 14 signal pins. For signal integrity at moderate frequencies this is marginal; for EMC purposes, additional ground pins interleaved with signals would reduce common-mode radiation from ribbon cables. The likely failure mode for an externally cabled J2 is radiated emissions from common-mode currents on the cable, per EN 55032 Class B limits.

AI-Assisted J5 is a JAE ST12S0 series MicroSD card connector. MicroSD is a consumer-facing interface where cards are inserted and removed by the user, creating a hot-plug ESD exposure scenario. The relevant standard is IEC 61000-4-2 Level 4 (8 kV contact discharge) for the card-insertion event, as well as the SD Association Physical Layer Specification which recommends ESD protection on all signal lines.

The SD data lines SD-D0 through SD-D3 connect directly from J5 to U1 (XC7Z020) FPGA pins with no TVS protection and no series resistors. SD-CMD has a 4.99 kohm pull-up resistor R67 to VCC3 but no TVS. SD-CLK has a 49.9 ohm series resistor R8 between the FPGA (U1 pin D14) and the connector (J5 pin 5), which provides some current limiting but is not a substitute for ESD clamping. The card-detect signal /SD-CD has a 499 ohm pull-up resistor R53 to VCC3 and connects to U1 pin D16 and Q5 (PMG370 MOSFET gate).

The nine GND pins on J5 (pins 6, 12 through 19) provide a solid ground reference for the card socket shell, which helps with shielding. However, the absence of dedicated TVS diode arrays on the four data lines and the CMD line is a concern for IEC 61000-4-2 compliance. A typical mitigation would be a low-capacitance TVS array (e.g., TI TPD4S012 or similar) placed close to J5 on the SD-D0 through SD-D3 and SD-CMD lines. The SD-CLK line, being an output from the FPGA, is less exposed but would also benefit from clamping.

The VCC3 power supply to the card (J5 pin 4) has no visible dedicated decoupling capacitor local to J5 in the traced signal paths, though the VCC3 rail has extensive bulk and bypass capacitance elsewhere on the board. A 100 nF ceramic capacitor placed immediately adjacent to J5 pin 4 is standard practice per SD card reference designs to suppress switching noise from the card's internal regulator.

AI-Assisted J6 is a 2-pin header (HDR-2x1-100, 2.54 mm pitch) carrying the PWR net on pin 1 and GND on pin 2. The PWR net connects to a TVS diode D1 (SMCJ16), test points TP1 and TP2, and the drain of Q3 (Si7611 P-channel MOSFET) which serves as the main power switch. The SMCJ16 is a 16 V standoff, 600 W peak-pulse-power TVS diode, appropriate for clamping input transients per IEC 61000-4-5 (surge) on a DC power input.

J6 is a vertical 2-pin header, suggesting an internal wire-to-board connection rather than an external panel-mount interface. For an internal power connection, the SMCJ16 provides adequate surge protection. If J6 is exposed to external cabling (e.g., a barrel-jack adapter or field-wiring scenario), additional common-mode filtering (a common-mode choke or feed-through capacitor) would be warranted to meet conducted-emissions limits per EN 55032.

The PWR net also connects to TP1 and TP2, which are test points that leave the board. Any external measurement equipment connected to these test points during operation should use proper grounding to avoid injecting noise.

AI-Assisted J10 is a 6-pin connector with a REDEL footprint. REDEL (LEMO) connectors are circular push-pull connectors commonly used in industrial, medical, and military applications. They are typically panel-mounted and externally facing, with cables that may be several meters long. This makes J10 a high-ESD-exposure interface.

J10 carries four signal lines: IN51 (pin 6, connected to U1 pin B9), OUT50 (pin 2, connected to U1 pin B13), RxD1 (pin 4, connected to U1 pin C12), and TxD1 (pin 5, connected to U1 pin B12). Pin 1 is GND and pin 3 is not connected. The signal names suggest a serial communication interface (UART: TxD1/RxD1) plus two additional general-purpose I/O lines.

All four signal lines connect directly from J10 to U1 (XC7Z020) FPGA pins in Bank 500/501 (VCCO at 3.3 V) with no series resistors, no TVS devices, and no filtering of any kind. Given that REDEL connectors are designed for repeated mating cycles in field environments, the ESD exposure during cable connection and disconnection is significant. IEC 61000-4-2 Level 4 (8 kV contact discharge) is the applicable test level for industrial equipment.

The FPGA internal ESD structures (approximately 2 kV HBM per Xilinx DS181) are insufficient to withstand repeated IEC 61000-4-2 Level 4 events. A low-capacitance TVS array placed at J10 on all four signal lines is strongly recommended. For the UART lines (RxD1, TxD1), a bidirectional TVS with low clamping voltage (below 5 V for 3.3 V logic) and low capacitance (below 5 pF to preserve signal integrity at typical UART baud rates) would be appropriate. The IN51 and OUT50 lines require similar protection.

AI-Assisted J9 is a 3x2 pin header on 2 mm pitch (HDR-3x2-2MM), a small vertical connector typically used for internal board-to-board or debug connections. It carries four MIO signals (MIO34 through MIO37) from U1 (XC7Z020) PS MIO pins, a 3.3V-OUT power pin, and one GND pin.

All four MIO signals connect directly from J9 to U1 with no series components or ESD protection. Given the small form factor and vertical orientation, J9 is most likely an internal connector. The Xilinx internal ESD protection is adequate for this use case. If J9 is used with an external cable, TVS protection on the MIO lines would be needed, as these are PS-side I/O pins that could be configured for sensitive peripherals (SPI, UART, GPIO).

AI-Assisted Several cross-cutting EMC and ESD themes emerge from this design review.

First, the single-ground-domain architecture with connector shells tied directly to signal GND creates a vulnerability to ESD-induced ground bounce. This affects all external connectors (J3, J4, J8, and potentially J10 and J6). Per IEC 61000-4-2 and EMC design guidance in Henry Ott's 'Electromagnetic Compatibility Engineering,' connector shells on external interfaces should connect to a chassis-ground plane that is isolated from signal ground except at a single controlled point. The current design does not implement this separation.

Second, the FireWire ports J3 and J4 use BAV99T general-purpose diodes rather than dedicated TVS devices for ESD clamping. The BAV99T has a peak non-repetitive forward current of 1 A (per the Nexperia BAV99 series datasheet) and is not characterized for IEC 61000-4-2 waveforms. Purpose-built TVS arrays such as the TI TPD2E001 or Nexperia PESD1394S would provide characterized clamping performance for IEEE 1394 signal voltages.

Third, the MicroSD connector J5 and the REDEL connector J10 have no ESD protection whatsoever on their signal lines, despite both being interfaces where user contact during insertion or cable connection is expected. These represent the highest-risk gaps in the current design.

Fourth, the Ethernet interface at J8 benefits from the integrated magnetics in the Pulse JXD0-2015NL, which provides robust galvanic isolation. The primary concern for J8 is the shield-to-GND connection topology rather than the signal-path protection.

Fifth, the expansion headers J1 and J2 carry a large number of unprotected FPGA I/O lines. Their risk level depends entirely on the end-use application: if they remain internal board-to-board connections, the risk is low; if they are routed to external panel connectors via ribbon cables, the risk is high for both ESD immunity and radiated emissions.

Connector	Finding	Risk
J5	MicroSD card connector (JAE ST12S0), consumer-facing hot-plug interface. SD-D0 through SD-D3 connect directly to U1 FPGA pins with no TVS protection. SD-CMD has a 4.99 kohm pull-up (R67) but no TVS. SD-CLK has a 49.9 ohm series resistor (R8) but no TVS. Card insertion creates direct user-contact ESD exposure per IEC 61000-4-2. Likely failure mode: ESD damage to U1 FPGA I/O pins in Bank 501.	High
J10	REDEL (LEMO) 6-pin circular connector, panel-mount, external-facing. Four signal lines (IN51, OUT50, RxD1, TxD1) connect directly to U1 FPGA pins with no TVS, no series resistors, and no filtering. REDEL connectors are designed for field cable connections with significant ESD exposure during mating. FPGA internal ESD rating (~2 kV HBM per Xilinx DS181) is insufficient for IEC 61000-4-2 Level 4 (8 kV contact). Likely failure mode: ESD damage or latch-up of U1 FPGA I/O pins.	High
J8	Shield pins (1, 3) and ground pin 1A tied directly to signal GND rather than to a separate chassis-ground domain through an RC network. Per Pulse Electronics JXD0 series datasheet recommendations and IEC 61000-4-2 best practice, this may degrade common-mode rejection and inject ESD transient energy into the digital ground plane. Likely failure mode: ground bounce causing RGMII bit errors during ESD testing.	Medium
J3	Right-angle FireWire connector, external/panel-mount. Differential pairs TPA0 and TPB0 have BAV99T diodes (D9-D12) for voltage clamping, 56 ohm series resistors (R111-R114), and AC-coupling capacitors (C32 at 1.0 uF for TPA, C6 at 220 pF for TPB). BAV99T is a general-purpose switching diode not characterized for IEC 61000-4-2 waveforms (per Nexperia BAV99 datasheet). Likely failure mode: insufficient clamping during 8 kV contact discharge, potential damage to U5 (TSB41AB2).	Medium
J3	Shell pins (7, 8, 9) and V- pin (2) tied directly to signal GND. IEEE 1394a specification recommends cable shield connection to chassis ground, not signal ground. Likely failure mode: ESD ground-current injection into digital ground plane.	Medium
J4	Right-angle FireWire connector, external/panel-mount. Identical protection topology to J3: BAV99T diodes (D5-D8), 56 ohm series resistors (R109-R110, R115-R116), AC-coupling capacitors (C31 at 1.0 uF for TPA, C7 at 220 pF for TPB). Same concern regarding BAV99T ESD capability applies.	Medium
J4	Shell pins (7, 8, 9) and V- pin (2) tied directly to signal GND. Same chassis-ground concern as J3.	Medium
All	Single GND domain with no chassis-ground separation. All connector shells (J3, J4, J8) connect directly to signal GND. No controlled single-point chassis-to-signal-ground connection exists. Per IEC 61000-4-2 and EN 55032 design guidance, this architecture risks conducted ground-bounce during ESD events and may compromise radiated-emissions performance due to uncontrolled return currents on the ground plane.	Medium
J6	No common-mode filtering on power input. If J6 connects to external cabling, conducted emissions per EN 55032 Class B may be a concern due to switching-regulator noise from U15 (LTC3644) and U16 (LTC3636) propagating back through the input cable.	Low
J1	44-pin 2 mm vertical header. 34 FPGA I/O signals (IO1-0 through IO1-33) connect directly to U1 Bank 35 pins with no series resistors, no TVS, and no filtering. Six GND pins distributed across the connector. If used as internal board-to-board connection, FPGA internal ESD (~2 kV HBM) is adequate. If externally cabled, ESD and radiated-emissions risk is high.	Low
J1	3.3V-OUT (pins 39, 40) and 5V-OUT (pins 41, 42) power outputs have no TVS or overcurrent protection at the connector. Reverse-current or short-circuit on daughter card could damage Q2 (Si7108) power switch.	Low
J2	44-pin 2 mm vertical header. 40 FPGA I/O signals (IO2-0 through IO2-39) connect directly to U1 Bank 34 pins with no series resistors, no TVS, and no filtering. Only four GND pins (1, 15, 29, 43) for 40 signal lines — ground-to-signal ratio of 1:10 is marginal for EMC on ribbon cables. Same internal-vs-external risk assessment as J1.	Low
J9	6-pin 2 mm vertical header. Four MIO signals (MIO34-MIO37) connect directly to U1 PS MIO pins with no protection. Small form factor suggests internal use. Xilinx internal ESD adequate for board-to-board. If externally cabled, TVS would be needed.	Low
J8	Dual RJ-45 with Pulse JXD0-2015NL integrated magnetics providing 1500 Vrms galvanic isolation on all Ethernet pairs. No additional PHY-side TVS required per IEEE 802.3 and Realtek RTL8211F datasheet application circuit. Ethernet signal-path ESD protection is adequate.
J8	LED indicator circuits (e1-LED1, e1-LED2, e2-LED1, e2-LED2) have 4.99 kohm series resistors (R68-R71) providing current limiting and transient attenuation. These are internal to the magjack and not directly cable-exposed. Adequate.
J5	Nine GND pins provide solid shell grounding for the card socket. Card-detect signal /SD-CD has a 499 ohm pull-up (R53) to VCC3 providing some current limiting. VCC3 power to card (pin 4) present.
J6	2-pin vertical power header. PWR net protected by SMCJ16 TVS diode (D1), 16 V standoff, 600 W peak pulse power. Adequate for IEC 61000-4-5 surge protection on DC input per SMCJ series datasheet (Vishay/Littelfuse). GND on pin 2.