S01 Design Analysis

Executive Summary

1) Design Overview

The S01 is a 10-sheet flat schematic comprising 442 components, 1871 pins, and 369 nets. At its core is a Xilinx XC7Z020-CLG400 Zynq-7000 SoC (U1) in a 400-ball BGA, integrating a dual-core ARM Cortex-A9 processor with Artix-7 programmable logic. The design provides two 34-pin FPGA I/O expansion headers (J1, J2) exposing 74 general-purpose I/Os across PL banks 34 and 35, dual Gigabit Ethernet via two RTL8211F PHYs (U10, U11) connected through a Pulse JXD0-2015NL dual-port RJ-45 with integrated magnetics (J8), IEEE 1394a FireWire through a TSB41AB2 two-port transceiver/arbiter (U5) with two 6-pin FireWire connectors (J3, J4), 1 GB of DDR3L memory via two MT41K256M16 SDRAM devices (U2, U3) on a 32-bit bus, QSPI boot flash using a W25Q128 128Mbit SPI NOR (U4), a microSD card slot (J5), UART (J10), and a JTAG debug port (J7). A rotary switch (SW1) provides 4-bit board ID selection. The design includes 14 test points and 3 LEDs for status indication.

2) Power Supply Design

The board operates from an external DC input via connector J6, protected by a TVS diode (D1) and dual hot-swap controllers — two LTC4210 (U12, U13) managing inrush current through N-channel MOSFET power switches (Q1, Q2) with 15mΩ sense resistors (R117, R118). A P-channel MOSFET (Q3) provides reverse-polarity protection. The main 5V DC-DC rail feeds a multi-output power tree: an LTC3644 quad-output buck converter (U15) generates the 1.8V I/O rail and 1.0V core rail (among others), synchronized to 1.2MHz from an LTC6902 oscillator (U14); an LTC3636 dual-output buck converter (U16) generates the 1.5V DDR3L rail and additional regulators; and an LP2998 (U18) provides DDR VTT termination at 0.75V. A voltage sequencing/supervisory IC (LTC2908-B1, U17) monitors 3.3V, 2.5V, 1.8V, and 1.5V rails with adjustable thresholds, driving a combined PGOOD signal that gates the system oscillator (U20) and other functions. The design has 6 power rails (3.3V, 1.8V, 1.5V, 1.0V, 0.75V, GND) with extensive decoupling — over 140 bypass capacitors and ferrite beads isolating analog supplies for the Ethernet PHYs. Five of 6 rails have test points; the VCC3 (3.3V) rail is missing a test point. LTC3636 PGOOD1/PGOOD2 outputs are unconnected, reducing power fault diagnostic coverage.

3) Design Review Findings

Connector Shell Grounding (EMC): Both FireWire connectors (J3, J4) have their chassis/shield pins connected directly to digital GND. This is an EMC risk — shield current from cable connections will couple directly into the logic ground plane. The report recommends either a dedicated CHASSIS_GND net or routing shell pins through a 0Ω resistor to GND, which forces trace routing rather than via-to-plane connections, giving layout explicit control over the shell current return path. This is standard EMC practice for IEEE 1394 connectors where cable shield currents can be significant.

Switch Design-for-Test: The rotary switch SW1 drives 4 board-ID select lines (SEL1, SEL2, SEL4, SEL8) directly to Zynq MIO pins with no isolation resistors and no test points. In production, the switch creates a hard short to GND (when closed) that prevents ATE from overriding the signal state. The report flags all 4 signals — each needs a series isolation resistor (Rs) between the switch and the IC pin, plus a test point on the IC side. Without this, every board requires manual switch positioning during test, which is a production show-stopper for fixture-based ICT. The BOM cost is four 0402 resistors and four test pads.

Boundary Scan Issues: The JTAG chain contains a single device (U1, XC7Z020) with an IEEE 1149.1-2001 BSDL model. Several issues were identified: (a) BSDL package mismatch — 3 boundary scan pins (N6, R6, T6) marked as I/O in the BSDL are actually connected to VCC3 power in the schematic, indicating the IC supplier repurposed I/O pads as package power pins without updating the BSDL; these cells will capture floating zeros. (b) No 1149.6 AC-capable pins — while the BSDL declares EXTEST_PULSE/EXTEST_TRAIN instructions, no cells actually support AC-coupled testing, so differential Ethernet pairs cannot be tested via 1149.6. (c) Test coverage stands at 63% opens / 64% shorts — 221 nets get Class 2 (shorts-only through series components) coverage, but 130 nets (36%) have zero boundary scan coverage, primarily the Ethernet PHY-to-magnetics nets and FireWire transceiver signals which are beyond the Zynq's scan chain. (d) Non-BSCAN driver management identifies 5 constrained nets requiring 65 obstacle pins to be managed (e.g., holding DDR CS# high to tristate memory outputs during scan). (e) JTAG signals (TCK, TMS, TDI, TDO) have no test points — while accessible via J7, dedicated test pads would allow ATE access without requiring a mating connector.

Fault Coverage Class Definitions

Fault Coverage Class 1: Full opens and shorts fault coverage on the nets listed in this class.

Fault Coverage Class 2: Shorts fault coverage on the nets listed in this class. Opens coverage is provided on the boundary scan portion of each net through series components.

Fault Coverage Class 3: No opens coverage on the nets listed in this class. Shorts will be detected between the nets listed in this class and the nets listed in the following classes:

• Fault Coverage Class 1
• Fault Coverage Class 2

Fault Coverage Class 4: Opens will be detected on the nets listed in this class only if they cause a boundary scan input or tester pin to float to a logic state that is different from the net's constant state. Shorts will be detected between the nets listed in this class and the nets listed in the following classes:

• Fault Coverage Class 1
• Fault Coverage Class 2

Fault Coverage Class 5: The nets listed in this class are Test Access Port data and control nets. Fault coverage is provided on these nets by executing the Test Access Port Integrity Test (TAPIT).

Fault Coverage Class 6: No fault coverage on the nets listed in this class.

General Notes

The above discussion about opens coverage does not apply to any connector leads that might be on each net. Opens are not covered on any connector leads unless a tester pin is connected to that lead with a mating connector. Connector leads are listed in the net descriptions and are marked with asterisks (*).

Shorts will never be detected between two nets of any class that are connected together with transparent series components.

Nets that are described as "resistively isolated" may not have the shorts detection described for their class above. This is because these nets are tested through transparent series components whose impedance might be high enough to isolate the effect of a short so that it causes no failure.

Differential nets may not have the shorts detection described for their class above. This is because the redundancy inherent in differential signalling can make some shorts undetectable, such as a short to a logic level between 0 and 1.

Opens coverage on pull-ups and pull-downs is described as "possible" because opens on these leads can be detected only if the affected inputs float to the complement of their pulled state.