OPi_CM5_Carrier Design Analysis

Job bf031906

1 Design Summary

out of 100

Depth of review, as a baseline: 208 verified datasheet parameters applied and 342 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

Active Variant	Base (all components)
Design Type	Flat (2 sheets)
Total Components	117
Total Pins	811
Total Nets	213
Total Test Points	0
Project Variants	1
Analyzed variant	001

Improve your score:

Improve fault coverage (opens/shorts) +4
Add test points on power rails +1
Add test points on switch signals +1
Move component values to VALUE property +1
Add ordering part numbers to resistors, inductors and capacitors +1
Use IPC-compliant footprint names +1

Points deducted for open High/Medium AI findings:

0 High, 5 Medium -2.5

AI findings to review:

Power findings — 1 Medium, 1 Low, 12 Review
HSSI findings — 1 Medium, 17 Review
Memory findings — 8 Review
Functional findings — 2 Medium, 2 Low, 7 Review
EMC/ESD findings — 1 Medium, 11 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 21 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — This board is a two-sheet carrier for the Orange Pi CM5 compute module (U1). The module mates through Hirose DF40C-100DS-0.4V board-to-board receptacles with a 0.4 mm pitch, rated 0.3 A and 30 V per contact (Hirose datasheet, page 6, Datasheet). The module provides all processing, memory and I/O control. The carrier adds the physical interfaces, a gigabit Ethernet PHY and the local power conversion. Three tactile switches (S1–S3) provide user and boot-control inputs.

Ethernet

A Texas Instruments DP83867IRRGZR gigabit PHY (U2) connects to the module's GMAC1 MAC interface. The module manages it as controller over the MDIO bus. The PHY drives four MDI pairs into J1, a Bel L834-1G1T-S7 RJ45 jack with integrated magnetics and two status LEDs. Its reference clock comes from Y1, a Raltron 25 MHz fundamental-mode crystal. The ordering code decodes to 20 pF load and 30 ppm tolerance with 30 ppm stability (Raltron datasheet). Per the Texas Instruments DP83867 datasheet (page 7, source: Tomachie), the PHY's XI input requires a 25 MHz crystal of 50 ppm, which this crystal satisfies.

USB, Storage and Expansion

J2 is a GCT USB4056-03-A USB Type-C receptacle. It carries both SuperSpeed lane pairs, USB 2.0, CC and SBU signals. A Molex 1040310811 microSD socket (J4) provides a 4-bit SD interface from the module. J10 is a JAE SM3ZS067U410AER1000 M.2 socket, which carries a UART interface among its signals. Two Hirose FFC connectors serve display and camera connections: a 22-position FH12-22S (J8) and a 15-position FH12-15S (J9), with J9 also carrying an I2C control bus. J5 is a SameSky SJ3-35063BG 3.5 mm audio jack. In total the schematic defines 72 differential pairs, comprising 12 USB, 8 HDMI, 8 Ethernet, 2 MIPI and 42 further high-speed pairs.

Power Tree

The 5 V system rail VCC5V0_SYS is the board's main distribution rail. U3, a Texas Instruments TPS62914-Q1 low-noise synchronous buck converter, generates VCC3V3_REG. The TPS62914-Q1 accepts 3.0 V to 17 V input, delivers up to 4.5 A, and switches at a selectable 1 MHz, 1.4 MHz or 2.2 MHz with optional spread spectrum (Texas Instruments TPS62914-Q1 datasheet, pages 4 and 6, Datasheet). U5, an XPS62442 dual synchronous buck converter, generates two rails through 0.47 µH Murata DFE201610E-R47M inductors (rated 3.6 A Irms):

P06_VDD1P0 is produced through L3. It serves the PHY's 1.0 V core supply, whose range is 0.95 V to 1.155 V (DP83867 datasheet, page 10).

VDD_2P5 is produced through L4. It serves the PHY's 2.5 V analog supply, whose range is 2.375 V to 2.625 V (DP83867 datasheet, page 10).

Two further rails, VCC_3V3_S3 and VCC_1V8_S3, distribute 3.3 V and 1.8 V across the board. A 1 µH Würth 74439324010 power inductor (L2), rated 11.1 A and 125 °C, is fitted in the power section. Bulk and decoupling capacitance uses X5R and X7R MLCCs in 0402 to 1206 cases.

Temperature Ratings

The TPS62914-Q1 is AEC-Q100 Grade 1 qualified for −40 °C to 125 °C ambient. The DP83867IR PHY operates from −40 °C to 85 °C. The DF40C module connector is rated −35 °C to +85 °C, including contact self-heating. The X5R capacitors are rated to 85 °C. Together these set the carrier's practical operating envelope at −35 °C to 85 °C.

1.2 Processed Sheets

#	Sheet Name
1	OPi_CM5_Carrier.kicad_sch
2	opi_cm5_carrier(page_2).kicad_sch

1.3 Variants

#	Variant	DNP	ALT
0	Base (all components)	-	-
1	001 (analyzed)	0	0

1.3.1 001

Status	RefDes	Part Type	Alt Part	Footprint
	(No component variations in this variant)

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
4 of 26 unique footprints are IPC-7351B or IPC-7251	✓
14 SMT footprints do not follow IPC-7351B naming
7 footprints (connectors, specialty) — compliance unknown
1 footprints could not be classified for inspection

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	VALUE holds the manufacturer part number instead of the electrical value, so the schematic states no Capacitance to check the part number against; the value the other checks use is decoded from the part number itself. VALUE should hold the magnitude and units (e.g. 10uH, 100nF, 10k) or a =Property formula, and the part number belongs in its own MPN / Part Number property - a symbol can carry as many properties as it needs. A value written as free text beside the part is not typical of professional designs: the text is not tied to the part, so when one is changed the other can be left behind. (C7 currently has VALUE="GRM033R61E104KE14D")	49	C7, C8, C15, C6, C2, C5, C10, C9 (+41 more)
Capacitors	A magnitude value for this part was not found, some other text notation was found. Set VALUE to just the magnitude and units (e.g. 10k, 100nF, 10uH) or a =Property formula; keep wattage, current, tolerance and voltage ratings in their own named properties (Power, Current, Tolerance, Voltage). (C30 currently has VALUE="MA0805XF106K160")	3	C30, C31, C32
Resistors	VALUE holds the manufacturer part number instead of the electrical value, so the schematic states no Resistance to check the part number against; the value the other checks use is decoded from the part number itself. VALUE should hold the magnitude and units (e.g. 10uH, 100nF, 10k) or a =Property formula, and the part number belongs in its own MPN / Part Number property - a symbol can carry as many properties as it needs. A value written as free text beside the part is not typical of professional designs: the text is not tied to the part, so when one is changed the other can be left behind. (R47 currently has VALUE="RC1206FR-072K2L")	44	R47, R11, R6, R14, R3, R50, R15, R9 (+36 more)
Inductors	Values in VALUE or Inductance	1	L2	✓
Inductors	VALUE holds the manufacturer part number instead of the electrical value, so the schematic states no Inductance to check the part number against; the value the other checks use is decoded from the part number itself. VALUE should hold the magnitude and units (e.g. 10uH, 100nF, 10k) or a =Property formula, and the part number belongs in its own MPN / Part Number property - a symbol can carry as many properties as it needs. A value written as free text beside the part is not typical of professional designs: the text is not tied to the part, so when one is changed the other can be left behind. (L4 currently has VALUE="DFE201610E-R47M=P2")	2	L4, L3
Crystals	Values in VALUE or Frequency	1	Y1	✓

2.1 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the MANUFACTURER part number. This check decodes the manufacturer part number and compares the two. A distributor catalogue number is a different thing and cannot be used here - an LCSC C-number or a Digi-Key -ND number identifies a stock item, it encodes no capacitance, voltage or tolerance, so there is nothing in it to check against. Where the two readings disagree both are shown and neither is assumed correct: if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose numbering scheme is not recognized are reported as not checked rather than passed.

99 of 99 fitted resistor/inductor/capacitor part(s) carry no ordering part number: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C19, C20, C21, C22, C23 (+79 more). Without a part number the BOM cannot state what to buy, and none of the part-number cross-checks in this section can run for these parts. Add a manufacturer part number to each part in the library.

2.2 Capacitor Derating Check

Derating profile	Benign (controlled office)
Maximum ambient	40 °C
Checks performed	31
Over-specified	14

A capacitor is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Every other derating check - for capacitors and for every other part class - is applied by the AI analysis within its report sections.

Derating applied: 30% (capacitor_voltage_pct = 70)

Status key: ↓ = Over-specified ✓ = Adequately rated

Derating is how much is taken off a part's catalogue rating. What remains is the most of that rating the part may be worked at - a 16 V capacitor derated 15% has a maximum permitted value of 13.6 V - and the part is correctly sized when the voltage its position applies stays within it, taken at the worst case of the rail's stated range. This judges DC working voltage only; ripple and switching transients are not included in the compared value.

Review: 14 part(s) carry a voltage rating far higher than needed. A lower-cost part can be used, down to the voltage indicated.

3 part(s) sit across a resolved power rail with no stated voltage rating and could not be checked: C30, C31, C32. Record each rating in a Voltage property.

Part Voltage Rating vs Design Voltage
RefDes	Net Name	Rated Voltage	Max Permitted	Design Voltage	% of Rating	Sufficient Rating	Status
C6	VCC_3V3_S3	25.00 V (pn)	17.50 V	3.30 V	13.2%	16.00 V	↓
C11	VCC5V0_SYS	50.00 V (pn)	35.00 V	5.50 V (USB-C ceiling)	11.0%	16.00 V	↓
C43	VDD_2P5	50.00 V (pn)	35.00 V	2.50 V	5.0%	16.00 V	↓
C41	VDD_2P5	50.00 V (pn)	35.00 V	2.50 V	5.0%	16.00 V	↓
C45	VDD_2P5	50.00 V (pn)	35.00 V	2.50 V	5.0%	16.00 V	↓
C37	VCC_1V8_S3	50.00 V (pn)	35.00 V	1.80 V	3.6%	16.00 V	↓
C35	VCC_1V8_S3	50.00 V (pn)	35.00 V	1.80 V	3.6%	16.00 V	↓
C23	VCC_1V8_S3	50.00 V (pn)	35.00 V	1.80 V	3.6%	16.00 V	↓
C24	VCC_1V8_S3	50.00 V (pn)	35.00 V	1.80 V	3.6%	16.00 V	↓
C47	P06_VDD1P0	50.00 V (pn)	35.00 V	1.00 V	2.0%	16.00 V	↓
C55	P06_VDD1P0	50.00 V (pn)	35.00 V	1.00 V	2.0%	16.00 V	↓
C51	P06_VDD1P0	50.00 V (pn)	35.00 V	1.00 V	2.0%	16.00 V	↓
C49	P06_VDD1P0	50.00 V (pn)	35.00 V	1.00 V	2.0%	16.00 V	↓
C53	P06_VDD1P0	50.00 V (pn)	35.00 V	1.00 V	2.0%	16.00 V	↓
C40	VDD_2P5	6.30 V (pn)	4.41 V	2.50 V	39.7%		✓
C21	VDD_2P5	6.30 V (pn)	4.41 V	2.50 V	39.7%		✓
C27	VCC5V0_SYS	16.00 V (pn)	11.20 V	5.50 V (USB-C ceiling)	34.4%		✓
C38	VCC5V0_SYS	16.00 V (pn)	11.20 V	5.50 V (USB-C ceiling)	34.4%		✓
C12	VCC3V3_REG	10.00 V (pn)	7.00 V	3.30 V	33.0%		✓
C25	VCC_1V8_S3	6.30 V (pn)	4.41 V	1.80 V	28.6%		✓
C46	P06_VDD1P0	6.30 V (pn)	4.41 V	1.00 V	15.9%		✓
C42	VDD_2P5	16.00 V (pn)	11.20 V	2.50 V	15.6%		✓
C44	VDD_2P5	16.00 V (pn)	11.20 V	2.50 V	15.6%		✓
C36	VCC_1V8_S3	16.00 V (pn)	11.20 V	1.80 V	11.2%		✓
C34	VCC_1V8_S3	16.00 V (pn)	11.20 V	1.80 V	11.2%		✓
C22	VCC_1V8_S3	16.00 V (pn)	11.20 V	1.80 V	11.2%		✓
C39	P06_VDD1P0	10.00 V (pn)	7.00 V	1.00 V	10.0%		✓
C50	P06_VDD1P0	16.00 V (pn)	11.20 V	1.00 V	6.2%		✓
C54	P06_VDD1P0	16.00 V (pn)	11.20 V	1.00 V	6.2%		✓
C48	P06_VDD1P0	16.00 V (pn)	11.20 V	1.00 V	6.2%		✓
C52	P06_VDD1P0	16.00 V (pn)	11.20 V	1.00 V	6.2%		✓

Derating Settings Used in This Analysis
Parameter	Value	Source	Applied
capacitor_voltage_pct	30% (70)	Quanterion 2nd ed. Table 2.3-1 p37 / Table 3.1-4 p49 - ceramic film mica glass	Checked in the table above (31 part(s))
capacitor_aluminum_voltage_pct	20% (80)	Quanterion 2nd ed. Table 2.3-1 p37	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_mno2_voltage_pct	50% (50)	Quanterion 2nd ed. Table 2.3-1 p37 standard-process MnO2	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	20% (80)	Quanterion 2nd ed. Table 2.3-1 p37 polymer / enhanced MnO2 / niobium	Applied by the AI analysis where the rating is in evidence
capacitor_ripple_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	not stated by this scheme	Not applied - the AI is not given this parameter
capacitor_temperature_margin_c	10 °C	Quanterion 2nd ed. Table 2.3-1 p37 Tmax-10 (ceramic film)	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_temperature_margin_c	20 °C	Quanterion 2nd ed. Table 2.3-1 p37 Tmax-20	Applied by the AI analysis where the rating is in evidence
resistor_power_pct	30% (70)	Quanterion 2nd ed. Table 2.3-1 p41 film chip	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	not stated by this scheme	Not applied - the AI is not given this parameter
resistor_temperature_margin_c	24 °C	Quanterion 2nd ed. Table 2.3-1 p41 film chip Tmax-24	Applied by the AI analysis where the rating is in evidence
inductor_continuous_current_pct	10% (90)	Quanterion 2nd ed. Table 3.12-3 p113 inductor current (DC) 90 % (Severe); s3.12.4 p113 90 % for all magnetics when the hot-spot temperature is not known	Applied by the AI analysis where the rating is in evidence
inductor_surge_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 magnetics surge <100 %	Not applied - the AI is not given this parameter
inductor_continuous_voltage_pct	10% (90)	Quanterion 2nd ed. s3.12.4 p113 90 % for all magnetics when the hot-spot temperature is not known	Applied by the AI analysis where the rating is in evidence
inductor_surge_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 voltage surge <100 %	Not applied - the AI is not given this parameter
inductor_dielectric_withstand_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	not stated by this scheme	Not applied - the AI is not given this parameter
inductor_temperature_margin_c	25 °C	Quanterion 2nd ed. Table 2.3-1 p39 hot spot Tmax-25	Applied by the AI analysis where the rating is in evidence
regulator_input_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - microcircuits carry no supply-voltage row	Not applied - the AI is not given this parameter
regulator_output_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 linear microcircuits output current <100 %	Not applied - the AI is not given this parameter
regulator_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 linear PD <100 %	Not applied - the AI is not given this parameter
regulator_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. Table 2.3-1 p39 Tj 115 C (150 C part)	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. Table 2.3-1 p39	Applied by the AI analysis where the rating is in evidence
ic_output_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 output / drive current <100 %	Not applied - the AI is not given this parameter
ic_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 linear PD <100 %	Not applied - the AI is not given this parameter
ic_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. Table 2.3-1 p39 Tj 115 C (VHLSI 85 C)	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. Table 2.3-1 p39	Applied by the AI analysis where the rating is in evidence
connector_current_per_contact_pct	15% (85)	Quanterion 2nd ed. Table 2.3-1 p37	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - stated as % of dielectric withstand (80 %) not of working voltage	Not applied - the AI is not given this parameter
connector_temperature_margin_c	25 °C	Quanterion 2nd ed. Table 2.3-1 p37 insert Tmax-25	Applied by the AI analysis where the rating is in evidence
switch_contact_current_resistive_pct	10% (90)	Quanterion 2nd ed. Table 2.3-1 p41 resistive	Applied by the AI analysis where the rating is in evidence

2.3 Part Lifecycle and Silicon Errata

Status as found on the manufacturer's website by the AI enrichment run, on the date shown; the page read is linked. Silicon errata: whether the manufacturer publishes an errata sheet for the part - its presence only. No errata document is read or analysed, and no action is implied by its existence.

Item	Lifecycle	Silicon errata	Status
C27, C38 (CL31B475KOHNFNE), U5 (XPS62442QWRQRRQ1)	Datasheet could not be obtained, so the lifecycle status (NRND / obsolete) could not be determined	Not determined	Review
L3, L4 (DFE201610E-R47M)	Lifecycle status (NRND / obsolete) could not be determined	—	Review
C8, C9, C21 (CL31A476MQHNNNE)	No NRND / obsolete marking on the datasheet obtained 2026-10-01	—
C11 (CGA2B2X7R1H222K050BA)	No NRND / obsolete marking on the datasheet obtained 2026-10-01	—
C12, C39 (MSASL219LB5226MTNA01)	No NRND / obsolete marking on the datasheet obtained 2026-10-01	—
C19, C20 (C0402C100J3GACTU)	No NRND / obsolete marking on the datasheet obtained 2026-10-01	—
C22, C34, C36, C42, C44, C48, C50, C52, C54 (CL05A105KO5NNNC)	Active, as of 2026-10-01	—
C23, C35, C37, C43, C45, C49, C51, C53, C55 (GRM155R71H104KE14D)	Active, as of 2026-10-01	—
C24, C41, C47 (GCM155R71H103KA55D)	No NRND / obsolete marking on the datasheet obtained 2026-10-01	—
C25, C40, C46 (GRM155R60J106ME15D)	Active, as of 2026-10-01	—
C30, C31, C32 (MA0805XF106K160)	No NRND / obsolete marking on the datasheet obtained 2026-10-01	—
L2 (74439324010)	No NRND / obsolete marking on the datasheet obtained 2026-09-09	—
U2 (DP83867IRRGZR)	Active, as of 2026-09-09	None found on the manufacturer's website, as of 2026-09-09
U3 (TPS62914QRPYRQ1)	Active, as of 2026-09-25	None found on the manufacturer's website, as of 2026-09-25
Y1 (H130B-25.000-20-F-3030-TR)	No NRND / obsolete marking on the datasheet obtained 2026-09-08	—

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

178 unconnected pin(s) found:

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
J4_9	SW_DETECT	Unknown	1040310811	-	No net
J4_10	SW_DETECT	Unknown	1040310811	-	No net
J5_4	-	Passive	SJ3-35063BG	-	No net
J5_5	-	Passive	SJ3-35063BG	-	No net
J5_6	-	Passive	SJ3-35063BG	-	No net
J10_6	6	Unknown	SM3ZS067U410AER1000	-	No net
J10_10	10	Unknown	SM3ZS067U410AER1000	-	No net
J10_11	11	Unknown	SM3ZS067U410AER1000	-	No net
J10_13	13	Unknown	SM3ZS067U410AER1000	-	No net
J10_15	15	Unknown	SM3ZS067U410AER1000	-	No net
J10_16	16	Unknown	SM3ZS067U410AER1000	-	No net
J10_17	17	Unknown	SM3ZS067U410AER1000	-	No net
J10_19	19	Unknown	SM3ZS067U410AER1000	-	No net
J10_20	20	Unknown	SM3ZS067U410AER1000	-	No net
J10_21	21	Unknown	SM3ZS067U410AER1000	-	No net
J10_23	23	Unknown	SM3ZS067U410AER1000	-	No net
J10_38	38	Unknown	SM3ZS067U410AER1000	-	No net
J10_40	40	Unknown	SM3ZS067U410AER1000	-	No net
J10_42	42	Unknown	SM3ZS067U410AER1000	-	No net
J10_44	44	Unknown	SM3ZS067U410AER1000	-	No net
J10_46	46	Unknown	SM3ZS067U410AER1000	-	No net
J10_48	48	Unknown	SM3ZS067U410AER1000	-	No net
J10_50	50	Unknown	SM3ZS067U410AER1000	-	No net
J10_54	54	Unknown	SM3ZS067U410AER1000	-	No net
J10_56	56	Unknown	SM3ZS067U410AER1000	-	No net
J10_58	58	Unknown	SM3ZS067U410AER1000	-	No net
J10_59	59	Unknown	SM3ZS067U410AER1000	-	No net
J10_60	60	Unknown	SM3ZS067U410AER1000	-	No net
J10_61	61	Unknown	SM3ZS067U410AER1000	-	No net
J10_62	62	Unknown	SM3ZS067U410AER1000	-	No net
J10_64	64	Unknown	SM3ZS067U410AER1000	-	No net
J10_65	65	Unknown	SM3ZS067U410AER1000	-	No net
J10_66	66	Unknown	SM3ZS067U410AER1000	-	No net
J10_67	67	Unknown	SM3ZS067U410AER1000	-	No net
J10_68	68	Unknown	SM3ZS067U410AER1000	-	No net
J10_70	70	Unknown	SM3ZS067U410AER1000	-	No net
J10_71	71	Unknown	SM3ZS067U410AER1000	-	No net
J10_73	73	Unknown	SM3ZS067U410AER1000	-	No net
U1_3	Ethernet_Pair3_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_4	Ethernet_Pair1_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_5	Ethernet_Pair3_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_6	Ethernet_Pair1_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_9	Ethernet_Pair2_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_10	Ethernet_Pair0_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_11	Ethernet_Pair2_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_12	Ethernet_Pair0_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_15	Ethernet_nLED3(3.3v)	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_16	Ethernet_SYNC_IN(1.8v)	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_17	Ethernet_nLED2(3.3v)	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_18	Ethernet_SYNC_OUT(1.8v)	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_19	Ethernet_nLED1(3.3v)	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_20	EEPROM_nWP	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_21	PI_nLED_Activity	Input	Hirose DF40C-100DS-0.4V	GPIO_A4
U1_24	GPIO26	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1-C0
U1_25	GPIO21	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_B0
U1_27	GPIO20	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_B1
U1_29	GPIO16	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_B2
U1_31	GPIO12	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_B3
U1_34	GPIO5	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_A4
U1_35	ID_SC	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_D6
U1_37	GPIO7	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_B4
U1_38	GPIO11	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_A5
U1_39	GPIO8	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_B5
U1_40	GPIO9	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_A6
U1_44	GPIO10	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1_A7
U1_46	GPIO22	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1-C4
U1_47	GPIO23	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO0-C2
U1_48	GPIO27	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1-C6
U1_50	GPIO17	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1-D0
U1_51	GPIO15	Output	Hirose DF40C-100DS-0.4V	UART_RX
U1_54	GPIO4	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1-D1
U1_55	GPIO14	Input	Hirose DF40C-100DS-0.4V	UART_TX
U1_56	GPIO3	Bidirectional	Hirose DF40C-100DS-0.4V	GPIO1-D2
U1_64	SD_DAT5	Passive	Hirose DF40C-100DS-0.4V	-	No net
U1_68	SD_DAT4	Passive	Hirose DF40C-100DS-0.4V	SW_RECOVERY
U1_70	SD_DAT7	Passive	Hirose DF40C-100DS-0.4V	-	No net
U1_72	SD_DAT6	Passive	Hirose DF40C-100DS-0.4V	-	No net
U1_73	SD_VDD_Override	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_75	SD_PWR_ON	Input	Hirose DF40C-100DS-0.4V	SDMMC_PWREN
U1_76	Reserved	Passive	Hirose DF40C-100DS-0.4V	SDMMC_DET_L
U1_89	WiFi_nDisable	Power In	Hirose DF40C-100DS-0.4V	-	No net
U1_91	BT_nDisable	Power In	Hirose DF40C-100DS-0.4V	-	No net
U1_94	AnalogI_In1	Input	Hirose DF40C-100DS-0.4V	SARADC_VIN3
U1_95	nPI_LED_PWR	Output	Hirose DF40C-100DS-0.4V	GPIO4_B6
U1_96	Analog_In0	Input	Hirose DF40C-100DS-0.4V	SARADC_VIN2
U1_97	Camera_GPIO	Input	Hirose DF40C-100DS-0.4V	GPIO4_A7
U1_100	nEXTRST	Input	Hirose DF40C-100DS-0.4V	GPIO4_A5
U1_101	TYPEC_USB2_OTG_ID	Input	Hirose DF40C-100DS-0.4V	TYPEC0_USB20_OTG_ID
U1_102	PCIe_CLK_nREQ	Output	Hirose DF40C-100DS-0.4V	PCIE_CLKREQN
U1_104	PCIE_WAKEN	Output	Hirose DF40C-100DS-0.4V	PCIE_WAKEN
U1_106	GPIO4A6	Output	Hirose DF40C-100DS-0.4V	GPIO4_A6
U1_109	PCIe_nRST_3V3_L	Output	Hirose DF40C-100DS-0.4V	PCIE20_PERSTn_3V3_L
U1_110	PCIe_CLK_P	Output	Hirose DF40C-100DS-0.4V	PCIE20_2_REFCLKP
U1_111	RESERVED	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_112	PCIe_CLK_N	Output	Hirose DF40C-100DS-0.4V	PCIE20_2_REFCLKN
U1_116	PCIe_RX_P	Input	Hirose DF40C-100DS-0.4V	PCIE20_2_RXP/SATA30_2_RXP
U1_118	PCIe_RX_N	Input	Hirose DF40C-100DS-0.4V	PCIE20_2_RXN/SATA30_2_RXN
U1_122	PCIe_TX_P	Output	Hirose DF40C-100DS-0.4V	PCIE20_2_TXP/SATA30_2_TXP
U1_124	PCIe_TX_N	Output	Hirose DF40C-100DS-0.4V	PCIE20_2_TXN/SATA30_2_TXN
U1_143	HDMI1_HPG	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_145	HDMI1_SDA	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_146	HDM1_TX2_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_147	HDMI1_SCL	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_148	HDMI_TX2_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_149	HDMI0_TX_ON_H	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX_ON_H
U1_151	HDMI_TX0_CEC_M0	Output	Hirose DF40C-100DS-0.4V	HDMI_TX0_CEC_M0
U1_152	HDMI_TX1_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_153	HDMI_TX0_SBDN	Input	Hirose DF40C-100DS-0.4V	HDMI0_SBDN-HPD
U1_154	HDMI_TX1_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_157	MIPI_DPHY0_TX_D0N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY0_TX_D0N
U1_158	HDMI1_TX0_SBDP	Output	Hirose DF40C-100DS-0.4V	HDMI0_SBDP
U1_159	MIPI_DPHY0_TX_D0P	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY0_TX_D0P
U1_160	HDMI1_TX0_SBDN	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_163	MIPI_DPHY0_TX_D1N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY0_TX_D1N
U1_164	HDMI1_CLK_P	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_165	MIPI_DPHY0_TX_D1P	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY0_TX_D1P
U1_166	HDMI1_CLK_N	Unknown	Hirose DF40C-100DS-0.4V	-	No net
U1_169	MIPI_DPHY0_TX_CLKN	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY0_TX_CLKN
U1_170	HDMI0_TX2_P	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX2P
U1_171	MIPI_DPHY0_TX_CLKP	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY0_TX_CLKP
U1_172	HDMI0_TX2_N	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX2N
U1_175	MIPI_DPHY1_TX_D0N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D0N
U1_176	HDMI0_TX1_P	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX1P
U1_177	MIPI_DPHY1_TX_D0P	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D0P
U1_178	HDMI0_TX1_N	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX1N
U1_181	MIPI_DPHY1_TX_D1N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D1N
U1_182	HDMI0_TX0_P	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX0P
U1_183	MIPI_DPHY1_TX_D1P	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D1P
U1_184	HDMI0_TX0_N	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX0N
U1_187	MIPI_DPHY1_TX_CLKN	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_CLKN
U1_188	HDMI0_CLK_P	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX3P
U1_189	MIPI_DPHY1_TX_CLKP	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_CLKP
U1_190	HDMI0_CLK_N	Output	Hirose DF40C-100DS-0.4V	HDMI0_TX3N
U1_193	MIPI_DPHY1_TX_D2N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D2N
U1_194	MIPI_DPHY1_TX_D3N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D3N
U1_195	MIPI_DPHY1_TX_D2N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D2P
U1_196	MIPI_DPHY1_TX_D3N	Output	Hirose DF40C-100DS-0.4V	MIPI_DPHY1_TX_D3P
U1_199	HDMI_TX0_SDA_M0	Bidirectional	Hirose DF40C-100DS-0.4V	HDMI_TX0_SDA_M0
U1_200	HDMI0_SCL	Output	Hirose DF40C-100DS-0.4V	HDMI_TX0_SCL_M0
U1_213	USB20_HOST0_DP	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_215	USB20_HOST0_DM	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_220	GPIO3_C6	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_225	MIPI_DPHY1_RX_CLKP	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_227	MIPI_DPHY1_RX_CLKN	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_231	MIPI_DPHY1_RX_D1P	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_233	MIPI_DPHY1_RX_D1N	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_234	GPIO3_B7	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_236	GPIO3_C5	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_237	MIPI_DPHY1_RX_D0P	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_238	GPIO3_C4	Passive	Hirose DF40C-100DS-0.4V	-	No net
U1_239	MIPI_DPHY1_RX_D0N	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_244	GPIO_1V8_6	Passive	Hirose DF40C-100DS-0.4V	-	No net
U1_250	GPIO3_C1	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_252	MIPI_CLK1	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_266	GPIO0_B0	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_267	REFCLK_OUT	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_268	I2S0_MCLK	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_272	GPIO3_C0	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_277	GPIO0_D5	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_279	GPIO0_C7	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_281	GPIO0_D4	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_283	GPIO0_C4	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_285	GPIO0_D3	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_289	GPIO0_D0	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_293	GPIO4_A3	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_294	GPIO0_C5	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U1_295	GPIO4_B3	Output	Hirose DF40C-100DS-0.4V	-	No net
U1_296	CLK32K_IN	Input	Hirose DF40C-100DS-0.4V	-	No net
U1_297	GPIO4_B2	Input	Hirose DF40C-100DS-0.4V	-	No net
U1_298	GPIO0_C6	Bidirectional	Hirose DF40C-100DS-0.4V	-	No net
U2_13	VDDA1P8	Power In	DP83867IRRGZR	-	No net
U2_21	JTAG_TDO	Output	DP83867IRRGZR	-	No net
U2_39	RX_ER/GPIO_0	Bidirectional	DP83867IRRGZR	-	No net
U2_40	COL/GPIO_1	Output	DP83867IRRGZR	-	No net
U2_45	LED_2	Bidirectional	DP83867IRRGZR	-	No net
U2_48	VDDA1P8	Power In	DP83867IRRGZR	-	No net
Y1_2	NC_1	Passive	H130B-25.000-20-F-3030-TR	-	No net
Y1_4	NC_2	Passive	H130B-25.000-20-F-3030-TR	-	No net

3.2 Implied/Hidden Net Connections

No components with implied/hidden net connections found.

3.3 Open-Collector Pull-up Audit

Examined 3 candidate pin(s) on 3 net(s). All OC outputs have pull-ups to a power rail. No issues found.

3.4 Checks Not Performed

Items this report did not check, with the reason. None of these is a finding against the design - an item that was not checked says nothing about it either way.

Note 3: The parameter these checks need is not yet in the datasheet model for the part, so they were not performed. This is a limitation of the analysis data, not a finding on the design.

Checks the AI review could not perform are listed at Review severity in each AI section's Findings table, each naming the input that was missing.

Item	Not checked	Notes
Part Number vs Stated Values	The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.
Capacitors and resistors (datasheets and parameter curves)	Datasheets for capacitors and resistors, and the parameter curves they carry (ripple current, derating against temperature, DC bias, a jumper's temperature rise), are obtained on the premium tier only. This standard-tier run reads a datasheet already on file and otherwise states no rating for these parts. The exception is a capacitor on a regulator's input or output rail: this tier obtains its datasheet and curves as well.
U5 (XPS62442QWRQRRQ1)	Absolute output voltages of P06_VDD1P0 and VDD_2P5 from the feedback dividers (FB1/FB2 reference voltage)	See note 3
U5 (XPS62442QWRQRRQ1)	Output capacitance adequacy and loop stability on both channels (Minimum and maximum effective output capacitance)	See note 3
U5 (XPS62442QWRQRRQ1)	Input capacitance adequacy on VIN1 and VIN2 (Minimum effective input capacitance)	See note 3
U5, R23 (XPS62442QWRQRRQ1)	Switching frequency and compensation set by R23 7.87 kΩ on COMP/FSET (COMP/FSET resistor table)	See note 3
U5 (XPS62442QWRQRRQ1)	Operating mode selected by MODE/SYNC tied to GND (MODE/SYNC pin states table)	See note 3
L3, L4 (DFE201610E-R47M)	Isat 4.8 A against the converter peak inductor current (U5 peak switch current limit)	See note 3
U5 (XPS62442QWRQRRQ1)	Predicted junction temperature (Efficiency and thermal resistance)	See note 3
U3, R1 (TPS62914QRPYRQ1)	Decode of R1 18.2 kΩ on S-CONF (switching frequency, spread spectrum, discharge, sync range) (S-CONF Table 6-1 resistor values)	See note 3
C12 (MSASL219LB5226MTNA01)	Effective capacitance at 3.3 V for the U3 COUT minimum (DC-bias characteristic)	See note 3
U1 (DF40C-100DS-0.4V)	Board-to-board socket suitability for 5 Gb/s USB and PCIe lanes (differential impedance and insertion loss at 2.5 GHz)	See note 3
U1 (DF40C-100DS-0.4V (OPi CM5 module))	Presence of AC-coupling capacitors on the module for PCIe TX (module-side PCIe TX coupling capacitance)	See note 3
U2 (DP83867IRRGZR)	Automatic MDI polarity correction on pairs B and D (auto-polarity correction support)	See note 3
Y1 (H130B-25.000-20-F-3030-TR)	Crystal ESR and drive level against the U2 XI/XO oscillator (H130B ESR and maximum drive level)	See note 3
U2 (DP83867IRRGZR)	Configuration latched by the RX_CTRL (0.302 × VDDIO) and RX_D0 (0.199 × VDDIO) strap levels (Strap voltage-level mode table)	See note 3
U1 (DF40C-100DS-0.4V)	GPIO19 high level driven into U2 R̅E̅S̅E̅T̅ (Module GPIO VOH at the 3.3 V GPIO_VREF setting)	See note 3
U1 (DF40C-100DS-0.4V)	Released level of PWRON_L, nRPIBOOT and RUN_PG (Module internal pull-up on these inputs)	See note 3
U1 (DF40C-100DS-0.4V)	ESD withstand of the module pins reached from J2, J4, J5, J8, J9 and J10, needed to judge whether clamps are required (module pin ESD rating (HBM / IEC 61000-4-2) and absolute maximum voltage)	See note 3
J1 (L834-1G1T-S7)	Isolation rating of the integrated magnetics and the presence of shield tabs (magnetics isolation withstand voltage and shield contact definition)	See note 3

3.5 Summary

Total NO_ERC markers in design	0
Pins needing attention (warnings)	178
Pins for information only	0

4 Power Overview

Power rails	7
Power management sources identified	3

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
Rail	Voltage	Source	Consumers
VCC5V0_SYS	5.00V	J2 External	U1 (DF40C-100DS-0.4V), U3 (TPS62914QRPYRQ1), U5 (XPS62442QWRQRRQ1)
VCC3V3_REG	3.30V	U3 TPS62914QRPYRQ1	-
VCC_3V3_S3	3.30V	U1 DF40C-100DS-0.4V	-
VDD_2P5	2.50V	U5 XPS62442QWRQRRQ1	U2 (DP83867IRRGZR)
VCC_1V8_S3	1.80V	U1 DF40C-100DS-0.4V	U2 (DP83867IRRGZR)
P06_VDD1P0	1.00V	U5 XPS62442QWRQRRQ1	U2 (DP83867IRRGZR)
GND	-	J1 External	-

4.2 Regulator Enable Pull Resistors

2 regulator enable pin(s) examined for what drives them and which way they are pulled. 0 pulled toward the enabling level while a power output drives the net.

	Finding	Severity
RegulatorU5 [XPS62442QWRQRRQ1] Enable pinU5_8 (EN1) NetVCC5V0_SYS Driven by- Pull-up- Pull-down-	The enable is wired to VCC5V0_SYS; the regulator is always enabled.	Information
RegulatorU5 [XPS62442QWRQRRQ1] Enable pinU5_10 (EN2) NetVCC5V0_SYS Driven by- Pull-up- Pull-down-	The enable is wired to VCC5V0_SYS; the regulator is always enabled.	Information

4.3 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.3.1 Power Tree Overview

AI-Assisted — All power enters on J2, the USB-C receptacle. Its four VBUS contacts form VCC5V0_SYS at 5.00 V. The CC contacts carry 5.1 kΩ pull-downs (R50, R51), so the board is a sink and receives whatever current the attached source advertises. VCC5V0_SYS has three consumers. The first is the Orange Pi CM5 module U1, through six +5 V input pins. The second is U3 (TPS62914-Q1), which makes VCC3V3_REG for the two camera connectors J8 and J9 and the M.2 Key E socket J10. The third is U5 (XPS62442), which makes P06_VDD1P0 and VDD_2P5 for the DP83867 Ethernet PHY U2. The module itself drives VCC_3V3_S3, which feeds the SD card J4 VDD, and VCC_1V8_S3, which feeds U2 VDDIO and the PHY strap and pull-up network.

No clamp or series protection element is drawn on VCC5V0_SYS between J2 and these loads. The input bulk on the converter sheet is C27 and C38 (4.7 µF, 16 V X7R), C31 and C32 (MA0805XF106K160, 10 µF 16 V X5R) and C11 (2.2 nF), shared by U3 and U5.

No converter enable is driven by logic, so the power-up order follows from the wiring:

VBUS rises on J2, and VCC5V0_SYS reaches U1, U3 and U5 together.
U3 EN/SYNC is tied to VCC5V0_SYS, so U3 starts once VIN crosses its UVLO and soft-starts VCC3V3_REG over about 5 ms set by C13.
U5 EN1 and EN2 are tied to VCC5V0_SYS, so P06_VDD1P0 and VDD_2P5 start with the input.
U1 brings up VCC_3V3_S3 and VCC_1V8_S3 on its own schedule, independently of U5.
U1 GPIO19 (net GPIO1-C1) releases U2 R̅E̅S̅E̅T̅.

The PHY therefore takes its core and analog supplies from U5 and its VDDIO from the module, with no sequencing link between them.

4.3.2 TPS62914-Q1 3.3 V Buck (U3)

AI-Assisted — U3 converts VCC5V0_SYS to VCC3V3_REG through L2 (Würth 74439324010, 1 µH). The feedback divider is R17 15.4 kΩ from the output to FB and R12 4.87 kΩ from FB to GND. With the 0.8 V reference (0.792 to 0.808 V), VOUT = 0.8 × (1 + 15.4/4.87) = 3.33 V, with a band of 3.30 to 3.36 V. R12 meets the datasheet rule that the lower resistor be 5 kΩ or less (Texas Instruments TPS62914-Q1 datasheet). U3 VO senses directly at the L2 output, as the datasheet asks.

The output capacitance on U3's own sheet is C12 alone, 22 µF nominal; the ceramic DC-bias loss is not applied. C30 (10 µF) sits on the module sheet as load-side decoupling. The datasheet recommended operating conditions require 80 to 200 µF effective COUT for a single L-C stage (page 4), and the noise and PSRR characterisation uses 4 × 22 µF. Even the nominal 32 µF from both capacitors is well under the minimum, which is the main power finding of this review.

The remaining support parts match the datasheet. C26 (100 nF, 25 V) bridges BOOT to SW; the 2.2 Ω series resistor the datasheet recommends on page 19 is not drawn. C13 (470 nF) on NR/SS gives the 5 ms soft-start of page 14. R1 (18.2 kΩ) sets S-CONF. PG is pulled to VCC3V3_REG by R2 (10 kΩ, 0.33 mA) and goes nowhere else, which the datasheet allows. PGND and PSNS are on GND.

For L2, the I_R,40K rating of 11.1 A covers the 4.5 A device maximum. L2 Isat,10% of 5.8 A sits below the 8.9 A maximum peak switch limit, while Isat,30% of 12 A sits above it. The VCC3V3_REG load (J8, J9, J10) is off-board and unknown, so U3 dissipation is not computed.

4.3.3 XPS62442 Dual Buck for the Ethernet PHY (U5)

AI-Assisted — U5 channel 1 makes P06_VDD1P0 through L3 and channel 2 makes VDD_2P5 through L4. Both inductors are Murata DFE201610E-R47M, 470 nH. VIN1 and VIN2 sit on VCC5V0_SYS. The designer's note on sheet opi_cm5_carrier(page_2) reads "3.3V TO 1V & 2.5V FOR ETH PHY", but the schematic feeds U5 from 5 V, not from VCC3V3_REG.

The FB1 divider is R21 34 kΩ over R19 51 kΩ, a ratio of 0.600. The FB2 divider is R22 162 kΩ over R20 51 kΩ, a ratio of 0.2394. Both dividers imply the same 0.600 V feedback reference for the labelled 1.00 V and 2.50 V outputs, so they are consistent with each other. U5's reference voltage is not available here, so the absolute outputs are not confirmed. C19 and C20 (10 pF C0G) are feed-forward capacitors across the upper resistors.

The output capacitance on U5's sheet is 36.41 µF nominal on P06_VDD1P0 and 59.21 µF on VDD_2P5, with no DC-bias loss applied. It covers the per-pin 1 µF plus 100 nF that the DP83867 asks for on every VDD1P0 and VDDA2P5 pin (page 8).

The PHY's VDDA1P8 pins are unconnected, which places it in its two-supply mode. The loads are therefore 108 mA typical on 1.0 V and 137 mA typical on 2.5 V, 450.5 mW in total (Texas Instruments DP83867 datasheet, source: Tomachie, page 12). At 137 mA the 32 mΩ DCR of L4 drops 4.4 mV, which the loop corrects. The Irms rating of 3.6 A, derated 10% to 3.24 A, covers both channels.

PG1 and PG2 are pulled to their own outputs by R7 and R18 (100 kΩ each) and are otherwise unused. EN1 and EN2 sit on the input rail. MODE/SYNC is tied to GND, and R23 (7.87 kΩ) sits on COMP/FSET.

4.3.4 Module-Supplied Rails and Load Budget

AI-Assisted — The module connector contacts are rated 0.3 A each (Hirose DF40C datasheet). With the 15% derating (connector_current_pct = 85) in the Benign (controlled office) derating selected for this schematic analysis, each contact permits 0.255 A.

VCC5V0_SYS reaches U1 through six contacts, which permit 1.53 A in total. The module's own 5 V draw is not stated, so that budget cannot be closed.

VCC_1V8_S3 leaves U1 on two contacts, which permit 0.51 A. Its known load is 24 mA typical for U2 VDDIO, plus 0.36 mA in the two GMAC strap dividers (R24 with R60, R25 with R61). The worst-case pull-up currents of R55, R57, R58 and R59 add at most 2.7 mA.

VCC_3V3_S3 leaves U1 on two contacts, which also permit 0.51 A. It feeds J4 VDD with only C6 (100 nF) on the rail, and the SD card current is off-board.

The known VCC5V0_SYS load is at least 90 mA, which is U5's 450.5 mW output divided by 5 V before conversion loss. This excludes U1 and everything behind U3.

4.4 Observations

AI-Assisted — U3's output capacitance is the one datasheet-compliance defect: 22 µF nominal against an 80 µF effective minimum leaves its internally compensated loop outside its specified operating range.

C30, C31 and C32 carry their part number, MA0805XF106K160, in the value field. As a result the 10 µF they contribute is missing from every rail total.

Fourteen capacitors rated 25 V or 50 V sit on rails of 5.5 V or below. A 16 V part would serve each of them; this is benign over-specification.

The PHY supplies come from two unsequenced sources: U5 for the core and analog rails, and the module for VDDIO. The DP83867 states a 200 ms power-up stabilisation time (T1, page 13), so the release of U2 R̅E̅S̅E̅T̅ by U1 GPIO19 governs correct start-up.

None of the three PG outputs reaches a test point. All three output rails remain probeable elsewhere.

VBUS on J2 has no transient clamp at its point of entry, and USB hot-plug transients reach U1, U3 and U5 directly.

4.5 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.5.1	U3 (TPS62914-Q1)	VCC3V3_REG	U3's own output capacitance is C12 22 µF nominal (C30 10 µF is load-side on the module sheet). The datasheet recommended operating conditions require 80 to 200 µF effective COUT (page 4). Add X5R/X7R capacitance at the L2 output on U3's sheet until the effective value at 3.3 V is at least 80 µF and below 200 µF; the datasheet characterises 4 × 22 µF.	Medium
4.5.2	C30, C31, C32 (MA0805XF106K160)	VCC3V3_REG, VCC5V0_SYS	The value field holds the part number instead of 10 µF, so the capacitance drops out of the rail totals and BOM value fields. Enter 10 µF as the value.	Low
4.5.3	U3 (TPS62914-Q1)	Net-(U3-BOOT)	No series resistor is drawn with C26. The datasheet recommends 2.2 Ω (page 19); this is a recommendation, not a requirement.	Review
4.5.4	L2 (74439324010)	VCC3V3_REG	Isat,10% is 5.8 A, below U3's 8.9 A maximum peak switch limit. Isat,30% is 12 A, above it. The datasheet asks for saturation rating with 20% margin (pages 15 and 17). Check the 10% figure against the actual peak current at the maximum load.	Review
4.5.5	U3 (TPS62914-Q1)	VCC3V3_REG	Load current for VCC3V3_REG cannot be calculated, so U3 dissipation and junction temperature are not computed. It can be stated with free text on the schematic page, as: "VCC3V3_REG load current : <value>".	Review
4.5.6	C6, C11, C23, C24, C35, C37, C41, C43, C45, C47, C49, C51, C53, C55	several	Rated 25 V or 50 V on rails of 5.5 V or below. These parts are over-specified and a 16 V rating would serve. Benign margin, not a defect.	Review
4.5.7	U5 (XPS62442)	P06_VDD1P0, VDD_2P5	The FB1 divider R21 34 kΩ / R19 51 kΩ (ratio 0.600) and the FB2 divider R22 162 kΩ / R20 51 kΩ (ratio 0.2394) both imply a 0.600 V reference for the labelled 1.00 V and 2.50 V. Check U5's feedback reference against 0.600 V.	Review
4.5.8	U5 (XPS62442)	VCC5V0_SYS	The designer's note on sheet opi_cm5_carrier(page_2) says "3.3V TO 1V & 2.5V FOR ETH PHY", but VIN1 (U5_7) and VIN2 (U5_11) are on VCC5V0_SYS at 5 V. Align the note or the connection with the intended input.	Review
4.5.9	U5 (XPS62442)	P06_VDD1P0, VDD_2P5	PG1 and PG2 are pulled to their own outputs by R7 and R18 (100 kΩ each), an acceptable arrangement. Both are unused and reach no test point.	Review
4.5.10	U1 module contacts	VCC5V0_SYS	Six +5 V contacts at 0.3 A each, derated 15% (connector_current_pct = 85), permit 1.53 A. Check that the module's 5 V draw stays below 1.53 A. Hirose DF40C datasheet.	Review
4.5.11	Power input	VCC5V0_SYS	VCC5V0_SYS load current cannot be calculated. The known part is at least 90 mA for U5 before conversion loss, excluding U1 and U3. It can be stated with free text on the schematic page, as: "VCC5V0_SYS load current : <value>".	Review
4.5.12	U1 module contacts	VCC_3V3_S3	Two contacts permit 0.51 A after the 15% derating. Check that the J4 SD card draw stays below 0.51 A.	Review
4.5.13	J2 input	VCC5V0_SYS	No transient clamp is drawn on VBUS at J2. USB hot-plug transients reach U1, U3 and U5 directly; a clamp belongs at the point of entry.	Review
4.5.14	Power sequencing	P06_VDD1P0, VDD_2P5, VCC_1V8_S3	The DP83867 requires 200 ms power-up stabilisation (T1, page 13), and its supplies come from U5 and U1 independently. Check that U1 GPIO19 holds U2 R̅E̅S̅E̅T̅ until 200 ms after the last of the three rails is stable.	Review
4.5.15	U3 (TPS62914-Q1)	VCC3V3_REG	R17 15.4 kΩ / R12 4.87 kΩ with VREF 0.8 V (0.792 to 0.808 V) gives 3.33 V (3.30 to 3.36 V). R12 ≤ 5 kΩ as required. Texas Instruments TPS62914-Q1 datasheet, pages 5 and 18.	✓
4.5.16	U3 (TPS62914-Q1)	VCC5V0_SYS	Input bulk is C27, C38, C31 and C32, 29.4 µF nominal (DC-bias loss not applied), against a 5 µF effective minimum. C11 2.2 nF is placed VIN to PGND as page 18 asks. TPS62914-Q1 datasheet.	✓
4.5.17	C11 (CGA2B2X7R1H222K050BA)	VCC5V0_SYS	The DC Bias Characteristic graph (TDK datasheet, page 1) reads +0.9% at 5.5 V, about 2.22 nF effective. This meets the 2.2 nF VIN-PGND bypass requirement.	✓
4.5.18	C26 (GRM033R61E104KE14D)	Net-(U3-BOOT)	100 nF 25 V ceramic between BOOT and SW, against the requirement of 0.1 µF rated at least 10 V. TPS62914-Q1 datasheet, page 19.	✓
4.5.19	C13 (CGA3E2X5R1A474K080AA)	Net-(U3-NR/SS)	470 nF on NR/SS gives 5 ms soft-start, within the 3.3 µF maximum. TPS62914-Q1 datasheet, pages 14 and 19.	✓
4.5.20	U3 (TPS62914-Q1)	Net-(U3-PG)	R2 10 kΩ pulls PG to VCC3V3_REG at 0.33 mA, against the 10 mA absolute-maximum sink and VOL ≤ 0.4 V at 1 mA. PG is unused, which page 11 permits.	✓
4.5.21	U3 (TPS62914-Q1)	VCC5V0_SYS	U3_7 EN/SYNC is tied to VCC5V0_SYS: 5.5 V against the 18 V absolute maximum, with a rising threshold of 1.04 V maximum. U3 starts at UVLO (3.0 V maximum). TPS62914-Q1 datasheet, pages 4 and 5.	✓
4.5.22	U3 (TPS62914-Q1)	VCC5V0_SYS	VIN pins U3_8 and U3_12 see 5.5 V at the USB-C sink limit, against a 3.0 to 17 V operating range. TPS62914-Q1 datasheet, page 4.	✓
4.5.23	U3, U5	GND	U3_9 and U3_11 PGND, U3_1 PSNS, and U5_2 and U5_9 GND are all on GND. Every supply pin is on VCC5V0_SYS.	✓
4.5.24	U3 (TPS62914-Q1)	VCC3V3_REG	U3_4 VO senses directly after L2, as the datasheet requires. TPS62914-Q1 datasheet, pin functions.	✓
4.5.25	L2 (74439324010)	VCC3V3_REG	1 µH matches the datasheet's 1 µH typical. I_R,40K of 11.1 A, derated 10% (inductor_current_pct = 90), permits 9.99 A against U3's 4.5 A maximum output. Würth datasheet.	✓
4.5.26	C30 (MA0805XF106K160)	VCC3V3_REG	16 V part derated 30% (capacitor_voltage_pct = 70) permits 11.2 V; 3.3 V applied. Correctly sized. Meritek datasheet.	✓
4.5.27	C31, C32 (MA0805XF106K160)	VCC5V0_SYS	16 V part derated 30% (capacitor_voltage_pct = 70) permits 11.2 V; 5.5 V applied at the sink limit. Correctly sized.	✓
4.5.28	C27, C38 (CL31B475KOHNFNE), C12 (MSASL219LB5226MTNA01)	VCC5V0_SYS, VCC3V3_REG	C27 and C38 are 16 V parts permitting 11.2 V with 5.5 V applied. C12 is a 10 V part permitting 7 V with 3.3 V applied. Both under the 30% derating (capacitor_voltage_pct = 70); correctly sized.	✓
4.5.29	C21, C40, C42, C44	VDD_2P5	C21 and C40 are 6.3 V parts permitting 4.41 V; C42 and C44 are 16 V parts permitting 11.2 V. 2.5 V applied, 30% derating (capacitor_voltage_pct = 70). Correctly sized.	✓
4.5.30	C22, C25, C34, C36	VCC_1V8_S3	C25 is a 6.3 V part permitting 4.41 V; C22, C34 and C36 are 16 V parts permitting 11.2 V. 1.8 V applied, 30% derating (capacitor_voltage_pct = 70). Correctly sized.	✓
4.5.31	C39, C46, C48, C50, C52, C54	P06_VDD1P0	C39 is a 10 V part permitting 7 V, C46 a 6.3 V part permitting 4.41 V, and the 1 µF parts are 16 V permitting 11.2 V. 1 V applied, 30% derating (capacitor_voltage_pct = 70). Correctly sized.	✓
4.5.32	U5 (XPS62442)	VCC5V0_SYS	EN1 and EN2 are tied to VCC5V0_SYS, so both channels run whenever the input is present.	✓
4.5.33	L3, L4 (DFE201610E-R47M)	P06_VDD1P0, VDD_2P5	Irms of 3.6 A derated 10% (inductor_current_pct = 90) permits 3.24 A, against known loads of 108 mA and 137 mA typical (DP83867 two-supply mode). Murata datasheet.	✓
4.5.34	L3, L4 (DFE201610E-R47M)	Net-(U5-SW1), Net-(U5-SW2)	Withstand voltage of 20 V DC derated 10% permits 18 V, against a switch node swinging to the 5.5 V input. Correctly sized.	✓
4.5.35	U2 supply	P06_VDD1P0	Four VDD1P0 pins each have 1 µF + 100 nF (C48 to C55) plus C39, C46 and C47 bulk, as required per pin. Texas Instruments DP83867 datasheet, source: Tomachie, page 8.	✓
4.5.36	U2 supply	VCC_1V8_S3	Three VDDIO pins each have 1 µF + 100 nF (C22, C23, C34 to C37), as required per pin. DP83867 datasheet, source: Tomachie, page 8.	✓
4.5.37	U2 supply	VDD_2P5	Two VDDA2P5 pins each have 1 µF + 100 nF (C42 to C45) plus C21 and C40 bulk, as required per pin. DP83867 datasheet, source: Tomachie, page 8.	✓
4.5.38	U2 supply	VDD_2P5, VCC_1V8_S3	2.5 V nominal lies within 2.375 to 2.625 V, and 1.8 V within 1.71 to 1.89 V. The 1.0 V rail lies within 0.95 to 1.155 V subject to U5's reference. DP83867 datasheet, source: Tomachie, page 10.	✓
4.5.39	U2 supply	NC	VDDA1P8 pins U2_13 and U2_48 are unconnected, so the 1 µF + 100 nF requirement does not apply: it covers only an external 1.8 V supply (page 8). The two-supply load figures are used.	✓
4.5.40	U1 module contacts	VCC_1V8_S3	Two contacts permit 0.51 A after the 15% derating. The known load is 24.4 mA typical, plus at most 2.7 mA of pull-ups. Within the contact rating.	✓

4.6 Citations

AI-Assisted —

References
74439324010 (Würth Elektronik eiSos) — datasheet www.we-online.com/components/products/datasheet/744393240...
C0402C100J3GACTU (KEMET Electronics Corporation) — datasheet content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf
CGA2B2X7R1H222K050BA (TDK) — datasheet product.tdk.com/system/files/dam/doc/product/capacitor/ce...
CL05A105KO5NNNC (Samsung Electro-Mechanics) — datasheet datasheet.octopart.com/CL05A105KO5NNNC-Samsung-datasheet-...
CL31A476MQHNNNE (Samsung Electro-Mechanics) — datasheet mm.digikey.com/Volume0/opasdata/d220001/medias/docus/41/C...
DF40C-100DS-0.4V (HIROSE ELECTRIC CO., LTD.) — datasheet www.marutsu.co.jp/contents/shop/marutsu/datasheet/DF40C-3...
DFE201610E-R47M (Murata Manufacturing Co., Ltd.) — datasheet search.murata.co.jp/Ceramy/image/img/P02/J(E)TE243A-0001.pdf
GCM155R71H103KA55D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/71b256f70e3bf7cf9a4379...
GRM155R60J106ME15D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/52964d1681dfbc63ce0fc5...
GRM155R71H104KE14D (Murata Manufacturing Co., Ltd.) — datasheet www.farnell.com/datasheets/3979589.pdf
H130B (Raltron Electronics Corporation) — datasheet, cited pages 2 xonstorage.z8.web.core.windows.net/pdf/2538297_H131105921...
MA0805XF106K160 (Meritek Electronics Corporation) — datasheet datasheet.lcsc.com/datasheet/pdf/52a7812796d96435f7eaf6e2...
MSASL219LB5226MTNA01 (TAIYO YUDEN) — datasheet static6.arrow.com/aropdfconversion/f469f48a48a5ac7463ef5f...
TPS62914-Q1 (Texas Instruments) — datasheet www.mouser.lt/datasheet/2/405/1/tps62914_q1-3556322.pdf

5 Connector Pinouts

Total connectors

5.1 J1 L834-1G1T-S7

J1 - L834-1G1T-S7
Pin	Pin Name	Net	Notes
1	TRCT3	Net-(J1-TRCT1)
2	TRD3-	MDI2-
3	TRD3+	MDI2+
4	TRD2+	MDI1-
5	TRD2-	MDI1+
6	TRCT2	Net-(J1-TRCT1)
7	TRCT4	Net-(J1-TRCT1)
8	TRD4+	MDI3-
9	TRD4-	MDI3+
10	TRD1-	MDI0-
11	TRD1+	MDI0+
12	TRCT1	Net-(J1-TRCT1)
13	LEDG1_A	Net-(J1-LEDG1_A)
14	LEDG1_C	GND
15	LEDG2_A	Net-(J1-LEDG2_A)
16	LEDG2_C	GND

5.2 J2 A2

J2 - A2 (A2)
Pin	Pin Name	Net	Notes
A1	GND_A	GND
A2	SSTXP1	SSTX1P
A3	SSTXN1	SSTX1N
A4	VBUS_A	VCC5V0_SYS
A5	CC1	R49CC1
A6	DP1	TYPEC0_USB20_OTG_DP
A7	DN1	TYPEC0_USB20_OTG_DN
A8	SBU1	TYPEC0_SBU1
A9	VBUS_A__1	VCC5V0_SYS
A10	SSRXN2	TYPECO_SSRX2N
A11	SSRXP2	TYPECO_SSRX2P
A12	GND_A__1	GND
B1	GND_B	GND
B2	SSTXP2	SSTX2P
B3	SSTXN2	SSTX2N
B4	VBUS_B	VCC5V0_SYS
B5	CC2	R50CC2
B6	DP2	TYPEC0_USB20_OTG_DP
B7	DN2	TYPEC0_USB20_OTG_DN
B8	SBU2	TYPEC0_SBU2
B9	VBUS_B__1	VCC5V0_SYS
B10	SSRXN1	TYPECO_SSRX1N
B11	SSRXP1	TYPECO_SSRX1P
B12	GND_B__1	GND
S1	SHELL_GND	GND
S2	SHELL_GND__1	GND
S3	SHELL_GND__2	GND
S4	SHELL_GND__3	GND

5.3 J4 1040310811

J4 - 1040310811
Pin	Pin Name	Net	Notes
1	DAT2	Net-(J4-DAT2)
2	CD/DAT3	Net-(J4-CD/DAT3)
3	CMD	Net-(J4-CMD)
4	VDD	VCC_3V3_S3
5	CLK	SDMMC_CLK
6	VSS	GND
7	DAT0	Net-(J4-DAT0)
8	DAT1	Net-(J4-DAT1)
9	SW_DETECT	NC
10	SW_DETECT	NC

5.4 J5 SJ3-35063BG

J5 - SJ3-35063BG
Pin	Pin Name	Net	Notes
1		GND
2		Net-(C9-Pad2)
3		Net-(C8-Pad2)
4		NC
5		NC
6		NC

5.5 J8 FH12-22S-0.5SH55

J8 - FH12-22S-0.5SH55
Pin	Pin Name	Net	Notes
1	1	VCC3V3_REG
2	2	I2C4_SDA_M3
3	3	GPIO1_A3
4	4	GND
5	5	GPIO1_B7
6	6	GPIO1_B6
7	7	GND
8	8	MIPI_CSI0_RX_D3P
9	9	MIPI_CSI0_RX_D3N
10	10	GND
11	11	MIPI_CSI0_RX_D2P
12	12	MIPI_CSI0_RX_D2N
13	13	GND
14	14	MIPI_CSI0_CLK0P
15	15	MIPI_CSI0_CLK0N
16	16	GND
17	17	MIPI_CSI0_RX_D1P
18	18	MIPI_CSI0_RX_D1N
19	19	GND
20	20	MIPI_CSI0_RX_D0P
21	21	MIPI_CSI0_RX_D0N
22	22	GND

5.6 J9 FH12-15S-0.5SH55

J9 - FH12-15S-0.5SH55
Pin	Pin Name	Net	Notes
1	1	GND
2	2	MIPI_DPHY0_RX_D0N
3	3	MIPI_DPHY0_RX_D0P
4	4	GND
5	5	MIPI_DPHY0_RX_D1N
6	6	MIPI_DPHY0_RX_D1P
7	7	GND
8	8	MIPI_DPHY0_RX_CLKN
9	9	MIPI_DPHY0_RX_CLKP
10	10	GND
11	11	GPIO1-D3
12	12	GPIO1_D7
13	13	I2C6_SCL_M3
14	14	I2C6_SDA_M3
15	15	VCC3V3_REG

5.7 J10 SM3ZS067U410AER1000

J10 - SM3ZS067U410AER1000
Pin	Pin Name	Net	Notes
1	1	GND
2	2	VCC3V3_REG
3	3	USB_D+
4	4	VCC3V3_REG
5	5	USB_D-
6	6	NC
7	7	GND
8	8	I2S_SCLK
9	9	I2S_LRCLK
10	10	NC
11	11	NC
12	12	I2S_SDI
13	13	NC
14	14	I2S_SDO
15	15	NC
16	16	NC
17	17	NC
18	18	GND
19	19	NC
20	20	NC
21	21	NC
22	22	UART_RXD
23	23	NC
32	32	UART_TXD
33	33	GND
34	34	UART_CTS
35	35	PCIE20_TXP
36	36	UART_RTS
37	37	PCIE20_TXN
38	38	NC
39	39	GND
40	40	NC
41	41	PCIE20_RXP
42	42	NC
43	43	PCIE20_RXN
44	44	NC
45	45	GND
46	46	NC
47	47	PCIE20_REFCLKP
48	48	NC
49	49	PCIE20_REFCLKN
50	50	NC
51	51	GND
52	52	PCIE20_PERSTn
53	53	PCIE20_CLKREQ
54	54	NC
55	55	PCIE20_WAKEn
56	56	NC
57	57	GND
58	58	NC
59	59	NC
60	60	NC
61	61	NC
62	62	NC
63	63	GND
64	64	NC
65	65	NC
66	66	NC
67	67	NC
68	68	NC
69	69	GND
70	70	NC
71	71	NC
72	72	VCC3V3_REG
73	73	NC
74	74	VCC3V3_REG
75	75	GND

6 Indicator Documentation

No indicator devices (LED*, LD*, D* LEDs) found in design.

7 Switch Documentation

3 switch(es) found in design.

7.1 Switch Configurations

S1 Contact Pairs (SWT0010-015016SSA_REVA)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	Net-(C3-Pad2)	2	GND	SIGNAL	LOW

S1 All Pins
Pin #	Pin Name	Net	Paired With	Type
1		Net-(C3-Pad2)	2	CONTACT
2		GND	1	CONTACT

S2 Contact Pairs (SWT0010-015016SSA_REVA)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	Net-(C4-Pad2)	2	GND	SIGNAL	LOW

S2 All Pins
Pin #	Pin Name	Net	Paired With	Type
1		Net-(C4-Pad2)	2	CONTACT
2		GND	1	CONTACT

S3 Contact Pairs (SWT0010-015016SSA_REVA)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	Net-(C5-Pad2)	2	GND	SIGNAL	LOW

S3 All Pins
Pin #	Pin Name	Net	Paired With	Type
1		Net-(C5-Pad2)	2	CONTACT
2		GND	1	CONTACT

7.2 Switch DFT Analysis

Switches for mode selection are useful for development and manual debug, but production test environments require electrical override capability. A latching switch (DIP, slide, toggle) holds the signal at the rail it closes onto until somebody moves it, so ATE cannot drive past the contact: it needs a test point and a series isolation resistor between the switch and that rail. A momentary switch (push button) does not hold the signal — the bias resistor sets the level again as soon as the button is released — so it needs only a test point for ATE stimulus access.

Design Rationale: Switches for mode selection are valuable for engineering development and bench debug. However, production test and field returns require electrical override capability without manual intervention. Adding test points and isolation resistors creates a lifecycle-robust design that works across development, production test, and field returns without requiring procedure documentation or specialized knowledge of switch positions. The goal is a self-documenting, procedure-proof test interface. BOM impact: One 0201/0402 resistor per controlled signal.

Switch	Signal	Function	Pullup	Rail	Issue
S3	PMIC_RESET_L	Switch-controlled signal	(not found)	GND	No test point + Existing isolation R5 — add TP on PMIC_RESET_L
S1	PWRON_L	Switch-controlled signal	(not found)	GND	No test point + Existing isolation R3 — add TP on PWRON_L
S2	BOOT_SW	Switch-controlled signal	(not found)	GND	No test point + Existing isolation R4 — add TP on BOOT_SW

8 Low-Speed Serial Interfaces (LSSI)

Detected: 1 I2C, 1 MDIO, 1 UART

8.1 I2C

I2C: U1
Topology: U1 » Targets (J9)
Signal	Net Name	Connector	Test Point	Target Pin
SCL (needs pull-up)	I2C6_SCL_M3	J9_13	(none)	U1_80 (SCL0)
SDA (needs pull-up)	I2C6_SDA_M3	J9_14	(none)	U1_82 (SDA0)

I2C Pull-up Check
Net	Component	Status
I2C6_SDA_M3		Pull-up not found on I2C6_SDA_M3. This bus is mastered on-board by U1 and its addressable targets are off-board through J9; the interface standard for the attached device determines which side supplies the pull-up - confirm it is provided there.	-
I2C6_SCL_M3		Pull-up not found on I2C6_SCL_M3. This bus is mastered on-board by U1 and its addressable targets are off-board through J9; the interface standard for the attached device determines which side supplies the pull-up - confirm it is provided there.	-

8.2 UART

UART [UART] -> U1
Topology: Access (J10) » Targets (U1)
Signal	Net Name	Connector	Test Point	Target Pin
TX	UART_TXD	J10_32	(none)	U1_226 (UART9_TX_M2_BT)
RX	UART_RXD	J10_22	(none)	U1_230 (UART9_RX_M2_BT)
Target	Industry Type	Description
U1	Hirose DF40C-100DS-0.4V	OPi CM5

8.3 MDIO

MDIO: U1 -> U2
Topology: U1 » Targets (U2)
Signal	Net Name	Connector	Test Point	Target Pin
Target	Industry Type	Description
U2	DP83867IRRGZR

8.4 LSSI DFT Analysis

17 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
SCL	GMAC_MDC	(none)	MDIO: U1 -> U2
SDA	GMAC_MDIO	(none)	MDIO: U1 -> U2
SCL	I2C6_SCL_M3	J9_13	I2C: U1
SDA	I2C6_SDA_M3	J9_14	I2C: U1
RX	UART_RXD	J10_22	UART -> U1
TX	UART_TXD	J10_32	UART -> U1
CLK	SDMMC_CLK	J4_5	SDMMC: U1
CMD	SDMMC_CMD	(none)	SDMMC: U1
DATA0	SDMMC_D0	(none)	SDMMC: U1
DATA1	SDMMC_D1	(none)	SDMMC: U1
DATA2	SDMMC_D2	(none)	SDMMC: U1
DATA3	SDMMC_D3	(none)	SDMMC: U1
CD	Net-(J4-CD/DAT3)	J4_2	SDMMC
CMD	Net-(J4-CMD)	J4_3	SDMMC
DATA0	Net-(J4-DAT0)	J4_7	SDMMC
DATA1	Net-(J4-DAT1)	J4_8	SDMMC
DATA2	Net-(J4-DAT2)	J4_1	SDMMC

9 High-Speed Serial Interfaces (HSSI)

72 differential pair(s)

Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.

3 HDMI differential pair(s) have no controlled-impedance net class assigned. Assign a 100 Ohm differential net class so the impedance intent carries into PCB layout and length tuning.

6 USB differential pair(s) have no controlled-impedance net class assigned. Assign a 90 Ohm differential net class so the impedance intent carries into PCB layout and length tuning.

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 72 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
MIPI_CSI0_CLK0N	DIFF_PAIR
MIPI_CSI0_CLK0P	DIFF_PAIR
MIPI_CSI0_RX_D0N	DIFF_PAIR
MIPI_CSI0_RX_D0P	DIFF_PAIR
MIPI_CSI0_RX_D1N	DIFF_PAIR
MIPI_CSI0_RX_D1P	DIFF_PAIR
MIPI_CSI0_RX_D2N	DIFF_PAIR
MIPI_CSI0_RX_D2P	DIFF_PAIR
MIPI_CSI0_RX_D3N	DIFF_PAIR
MIPI_CSI0_RX_D3P	DIFF_PAIR
MIPI_DPHY0_RX_CLKN	DIFF_PAIR
MIPI_DPHY0_RX_CLKP	DIFF_PAIR
MIPI_DPHY0_RX_D1N	DIFF_PAIR
MIPI_DPHY0_RX_D1P	DIFF_PAIR
MIPI_DPHY0_TX_CLKN	DIFF_PAIR
MIPI_DPHY0_TX_CLKP	DIFF_PAIR
MIPI_DPHY0_TX_D0N	DIFF_PAIR
MIPI_DPHY0_TX_D0P	DIFF_PAIR
MIPI_DPHY0_TX_D1N	DIFF_PAIR
MIPI_DPHY0_TX_D1P	DIFF_PAIR
MIPI_DPHY1_TX_CLKN	DIFF_PAIR
MIPI_DPHY1_TX_CLKP	DIFF_PAIR
MIPI_DPHY1_TX_D0N	DIFF_PAIR
MIPI_DPHY1_TX_D0P	DIFF_PAIR
MIPI_DPHY1_TX_D1N	DIFF_PAIR
MIPI_DPHY1_TX_D1P	DIFF_PAIR
MIPI_DPHY1_TX_D2N	DIFF_PAIR
MIPI_DPHY1_TX_D2P	DIFF_PAIR
MIPI_DPHY1_TX_D3N	DIFF_PAIR
MIPI_DPHY1_TX_D3P	DIFF_PAIR
PCIE20_2_REFCLKN	DIFF_PAIR
PCIE20_2_REFCLKP	DIFF_PAIR
PCIE20_REFCLKN	DIFF_PAIR
PCIE20_REFCLKP	DIFF_PAIR
PCIE20_RXN	DIFF_PAIR
PCIE20_RXP	DIFF_PAIR
PCIE20_TXN	DIFF_PAIR
PCIE20_TXP	DIFF_PAIR
TYPECO_SSTX1N	DIFF_PAIR
TYPECO_SSTX1P	DIFF_PAIR
TYPECO_SSTX2N	DIFF_PAIR
TYPECO_SSTX2P	DIFF_PAIR
MDI0+	ETH
MDI0-	ETH
MDI1+	ETH
MDI1-	ETH
MDI2+	ETH
MDI2-	ETH
MDI3+	ETH
MDI3-	ETH
HDMI0_TX0N	HDMI
HDMI0_TX0P	HDMI
HDMI0_TX1N	HDMI
HDMI0_TX1P	HDMI
HDMI0_TX2N	HDMI
HDMI0_TX2P	HDMI
HDMI0_TX3N	HDMI
HDMI0_TX3P	HDMI
MIPI_DPHY0_RX_D0N	MIPI
MIPI_DPHY0_RX_D0P	MIPI
SSTX1N	USB
SSTX1P	USB
SSTX2N	USB
SSTX2P	USB
TYPEC0_USB20_OTG_DN	USB
TYPEC0_USB20_OTG_DP	USB
TYPECO_SSRX1N	USB
TYPECO_SSRX1P	USB
TYPECO_SSRX2N	USB
TYPECO_SSRX2P	USB
USB_D+	USB
USB_D-	USB

9.2 AI-Assisted Analysis

9.2.1 USB 3.2 SuperSpeed and USB 2.0 on the Type-C Receptacle (J2)

AI-Assisted — J2 (GCT USB4056-03-A, a 24-contact Type-C receptacle) carries both SuperSpeed lane sets from the module socket U1. Both transmit pairs are AC-coupled on this board. TYPECO_SSTX1P (U1_216) passes through C2 to J2_A2 SSTXP1, and TYPECO_SSTX1N (U1_214) through C1 to J2_A3 SSTXN1. TYPECO_SSTX2P (U1_202) passes through C15 to J2_B2 SSTXP2, and TYPECO_SSTX2N (U1_204) through C14 to J2_B3 SSTXN2. All four capacitors are 100 nF (GRM033R61E104KE14D, 0201, 25 V). The USB 3.2 specification places the TX coupling capacitor at the transmitter, in a 75 to 265 nF window. At the 2.5 GHz Nyquist frequency of 5 Gb/s, 100 nF has a reactance of about 0.64 mΩ. The receive pairs run directly from J2 to the module: J2_B11 and J2_B10 go to U1_221 and U1_219, and J2_A11 and J2_A10 go to U1_208 and U1_210. Their coupling capacitors belong in the far-end transmitter. USB 2.0 is joined across both plug orientations, with J2_A6 and J2_B6 on TYPEC0_USB20_OTG_DP (U1_105) and J2_A7 and J2_B7 on TYPEC0_USB20_OTG_DN (U1_103). The SuperSpeed pairs need 90 Ω differential routing. CC1 and CC2 carry only the R51 and R50 5.1 kΩ pull-downs to GND, which is a sink-only Rd termination. Neither CC line reaches U1, and no orientation signal is drawn to the module. The SoC therefore has no hardware indication of which SuperSpeed pair set is active. Several net labels use the letter O in TYPECO where the module pins read TYPEC0.

9.2.2 PCI Express on the M.2 Key E Socket (J10)

AI-Assisted — U1 lane PCIE20_0 runs to J10, the M.2 Key E socket (JAE SM3ZS067U410AER1000). U1_282 PCIE20_0_TXP and U1_284 TXN go to J10_35 and J10_37. U1_290 RXP and U1_288 RXN go to J10_41 and J10_43. The M.2 specification names its socket signals from the card side: pins 35 and 37 (PETp0/PETn0) are the card's transmitter outputs, and pins 41 and 43 (PERp0/PERn0) are its receiver inputs. As drawn, the host transmitter therefore meets the card transmitter. The M.2 UART follows the same name-to-name pattern: U1_230 UART9_RX goes to J10_22, and U1_226 UART9_TX goes to J10_32. No series capacitor sits on the host transmit pair on this board. PCIe requires these capacitors at the transmitter, so they must either be on the module or be added on the host TX pair. The REFCLK pair runs DC-coupled from U1_276 and U1_278 to J10_47 and J10_49, which suits an HCSL clock. The sideband signals are wired as follows. PCIE20_PERSTn goes to J10_52, and PCIE20_CLKREQ goes to J10_53 with no pull-up. PCIE20_WAKEn ties J10_55 to U1_243, a module pin named GND. The data lanes need 85 to 100 Ω differential routing.

9.2.3 MIPI CSI-2 Camera Inputs (J8, J9)

AI-Assisted — Both camera ports carry MIPI CSI-2 over the MIPI D-PHY physical layer: low-voltage differential high-speed lanes plus single-ended low-power signalling on the same wires. D-PHY must be DC-coupled, so the absence of any series part on these lanes is correct. The lanes need 100 Ω differential routing. J8 (Hirose FH12-22S-0.5SH55, 22-pin) carries four data lanes and a clock to the U1 CAM1_RX pins. The order is D3P/D3N on J8_8/J8_9, D2 on J8_11/J8_12, CLK0 on J8_14/J8_15, D1 on J8_17/J8_18 and D0 on J8_20/J8_21. Every pair is separated by a GND contact (J8_4, 7, 10, 13, 16, 19 and 22), with 3.3 V on J8_1 and I2C4 on J8_2/J8_3. This is the familiar 22-pin camera order, mirrored end-to-end. I2C4 has 2.2 kΩ pull-ups (R46, R47) to VCC3V3_REG. J9 (FH12-15S-0.5SH55, 15-pin) carries two lanes and a clock to the U1 CAM0_RX pins: D0 on J9_2/J9_3, D1 on J9_5/J9_6 and CLK on J9_8/J9_9. GND is on J9_1, 4, 7 and 10, with I2C6 on J9_13/J9_14 and 3.3 V on J9_15. This matches the common 15-pin camera layout. Both 0.5 mm FFC connectors suit D-PHY rates.

9.3 Observations

AI-Assisted — The pairs are drawn as differential groups, but none carries an impedance target in the schematic. The targets that apply are 90 Ω for USB, 85 to 100 Ω for PCIe, and 100 Ω for MIPI D-PHY and the Ethernet MDI. U1 is the Hirose DF40C 0.4 mm board-to-board socket (Hirose datasheet). That datasheet gives contact resistance (90 mΩ maximum) and 0.3 A per contact, but no high-frequency figures. Several U1 symbol pins also carry names that do not match their nets, as follows. U1_201 and U1_203 are both named USB20_HOST1_DP although they carry USB_D+ and USB_D− to J10_3 and J10_5. U1_243 is named GND but carries PCIE20_WAKEn. U1_261 is named GNDGMAC1_RXD2. The module's HDMI0, MIPI DSI (DPHY0/DPHY1 TX) and second PCIe/SATA lane (PCIE20_2) pins are left unconnected, which leaves those interfaces unused. On the SD card, R6 and R8 to R11 (22 Ω) are in series with D0 to D3 and CMD, while SDMMC_CLK runs from U1_57 to J4_5 with no series part.

9.4 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.4.1	Ethernet U2	RGMII clock	R52 120 Ω pulls GMAC_MCLK to GND, behind R49 2.2 Ω from U2_18 CLK_OUT. This is a 122.2 Ω DC load, drawing 14.7 mA at 1.8 V, against the 1 mA at which VOH ≥ VDDIO − 0.2 V is guaranteed (TI DP83867 datasheet, source: Tomachie, page 11). Remove R52, or raise it to 10 kΩ or more (0.18 mA) if a defined idle level is wanted.	Medium
9.4.2	USB-C J2	USB 3.2 SuperSpeed	No CC line or orientation signal reaches U1, so the module has no hardware indication of which SuperSpeed pair set is in use after a flipped insertion. The designer should check how the module selects the lane set. A CC controller reporting orientation to U1 would provide it.	Review
9.4.3	USB-C J2	USB 3.2 SuperSpeed	Net labels TYPECO_SSTX1P/1N, TYPECO_SSTX2P/2N and TYPECO_SSRX1P/1N/2P/2N use the letter O, while the U1 pins and the other nets use TYPEC0. Rename them for consistent net classing and searching.	Review
9.4.4	M.2 Key E J10	PCIe Gen2 data	U1_282/U1_284 PCIE20_0_TXP/TXN drive J10_35/J10_37 (PETp0/PETn0), and U1_290/U1_288 RXP/RXN take J10_41/J10_43 (PERp0/PERn0). The M.2 specification names these from the card side, so this connects host TX to card TX. Swap them: host TX to J10_41/J10_43, host RX to J10_35/J10_37.	Review
9.4.5	M.2 Key E J10	PCIe Gen2 data	PCIE20_TXP/PCIE20_TXN have no AC-coupling capacitor on this board. PCIe requires 75 to 265 nF at each transmitter. Check that the capacitors are on the module; otherwise add them on the host TX pair at J10.	Review
9.4.6	M.2 Key E J10	PCIe sideband	PCIE20_WAKEn ties J10_55 (PEWAKE0#) to U1_243, a module pin named GND. If U1_243 is a ground contact, wake is held permanently asserted. The designer should check the module pinout for the intended wake input.	Review
9.4.7	M.2 Key E J10	PCIe sideband	PCIE20_CLKREQ (J10_53) and PCIE20_WAKEn (J10_55) are open-drain M.2 sideband signals with no pull-up on this board. The M.2 specification places the pull-up on the platform side; check whether the module provides it, otherwise add one to the 3.3 V rail.	Review
9.4.8	M.2 Key E J10	UART (Bluetooth)	U1_230 UART9_RX goes to J10_22 UART_RXD and U1_226 UART9_TX goes to J10_32 UART_TXD, wired name-to-name. M.2 names these from the card side, so the data lines likely need crossing. The designer should check the RTS/CTS pairing as well.	Review
9.4.9	M.2 Key E J10	USB 2.0	U1_201 and U1_203 are both named USB20_HOST1_DP in the U1 symbol, yet they carry USB_D+ (J10_3) and USB_D− (J10_5). Check the polarity against the module pinout and correct the symbol pin name.	Review
9.4.10	Ethernet J1	1000BASE-T MDI	Pairs B and D are polarity-reversed: U2_4 TD_P_B goes to J1_5 TRD2-, U2_5 to J1_4 TRD2+, U2_10 TD_P_D to J1_9 TRD4- and U2_11 to J1_8 TRD4+. 1000BASE-T polarity correction tolerates this, but the net labels MDI1± and MDI3± disagree with J1. Pairs A and C are correct.	Review
9.4.11	Ethernet Y1	25 MHz reference	Y1 is ±30 ppm tolerance plus ±30 ppm stability, ±60 ppm worst case, against the 50 ppm stated for U2 XI (TI DP83867 datasheet, source: Tomachie, page 7). A crystal with a combined tolerance and stability of ±50 ppm or better meets the requirement.	Review
9.4.12	Ethernet U2	RGMII clock	R52 (ERA-2AEB121X, a 0402-inch part) is assigned the R_01005_0402Metric footprint, which is 01005-inch. The part and the land pattern do not match.	Review
9.4.13	Ethernet U2	RGMII	R53 (GTX_CLK), R54 (RX_CLK) and R49 (CLK_OUT) are 2.2 Ω, which gives negligible series damping against the 0.75 ns maximum RGMII rise and fall time (TI DP83867 datasheet, source: Tomachie, page 14). The designer should check that this value is intended rather than 22 Ω.	Review
9.4.14	Ethernet U2	RGMII	U2 RX timing gives tskewR of 1.0 to 2.6 ns (TI DP83867 datasheet, source: Tomachie, page 13). Check that the U1 GMAC receive delay setting is compatible with the clock delay configured in U2.	Review
9.4.15	Ethernet U1	RGMII	U1_260 is named GMAC_RXCLK but sits on GMAC_RXD0, while U1_258 on GMAC_RXCLK carries the same name. Check both against the module pinout and correct the symbol.	Review
9.4.16	Ethernet J1	Link LEDs	U2 VOH at 1.8 V VDDIO is VDDIO − 0.2 V minimum (1.6 V) at −1 mA (TI DP83867 datasheet, source: Tomachie, page 11). Check that the forward voltage of the J1 LEDs, driven through R40 and R41 (470 Ω), is compatible.	Review
9.4.17	All high-speed pairs	Controlled impedance	No differential impedance class is assigned in the schematic. Assign 90 Ω for USB, 85 to 100 Ω for PCIe, and 100 Ω for MIPI D-PHY and MDI before layout.	Review
9.4.18	SD card J4	SDIO	R6 and R8 to R11 (22 Ω) are in series with SDMMC_D0 to D3 and SDMMC_CMD, while SDMMC_CLK (U1_57 to J4_5) has no series resistor. The designer should check whether clock damping is intended.	Review
9.4.19	USB-C J2	USB 3.2 SuperSpeed	C1, C2, C14 and C15 (100 nF, GRM033R61E104KE14D) sit on the TX pairs from U1_214, U1_216, U1_202 and U1_204 to J2_A3, J2_A2, J2_B2 and J2_B3. This is within the USB 3.2 specification's 75 to 265 nF transmitter coupling window.	✓
9.4.20	USB-C J2	USB 3.2 SuperSpeed	The RX pairs (J2_B11/B10 to U1_221/U1_219, J2_A11/A10 to U1_208/U1_210) have no coupling capacitor on this board. This is correct, because the USB 3.2 specification places the capacitor at the far-end transmitter.	✓
9.4.21	USB-C J2	USB 3.2 SuperSpeed	Lane set 1 (A2/A3 TX, B10/B11 RX) and lane set 2 (B2/B3 TX, A10/A11 RX) map consistently to the matching U1 TYPEC0 lane pins.	✓
9.4.22	USB-C J2	USB 2.0	J2_A6/J2_B6 join on TYPEC0_USB20_OTG_DP (U1_105) and J2_A7/J2_B7 on TYPEC0_USB20_OTG_DN (U1_103). Both plug orientations are served, as the Type-C specification requires.	✓
9.4.23	USB-C J2	USB Type-C CC	R51 and R50 (5.1 kΩ) pull CC1 (net R49CC1) and CC2 (net R50CC2) to GND. This matches the 5.1 kΩ Rd of a sink in the Type-C specification.	✓
9.4.24	M.2 Key E J10	PCIe REFCLK	PCIE20_REFCLKP/N run DC-coupled from U1_276/U1_278 to J10_47/J10_49. This is correct for an HCSL reference clock.	✓
9.4.25	Camera J8	MIPI CSI-2 / D-PHY	The 22-pin 4-lane pinout is consistent: D3 on J8_8/9, D2 on 11/12, CLK0 on 14/15, D1 on 17/18 and D0 on 20/21. Each pair is GND-separated, with 3.3 V and I2C4 on J8_1 to J8_3. This is the standard 22-pin order, mirrored.	✓
9.4.26	Camera J9	MIPI CSI-2 / D-PHY	The 15-pin 2-lane pinout is D0 on J9_2/3, D1 on 5/6 and CLK on 8/9, with GND on 1, 4, 7 and 10, I2C6 on 13/14 and 3.3 V on 15. This matches the common 15-pin camera layout.	✓
9.4.27	Camera J8, J9	MIPI CSI-2 / D-PHY	All CSI-2 lanes are DC-coupled with no series parts. This is correct, because D-PHY low-power signalling requires DC coupling. The FH12 0.5 mm FFC connectors suit D-PHY rates.	✓
9.4.28	Ethernet U2	PHY bias	R45 11 kΩ (RC0402FR-0711KL, 1%) connects U2_12 RBIAS to GND. This meets the 11 kΩ ±1% requirement, TI DP83867 datasheet, source: Tomachie, page 8.	✓
9.4.29	Ethernet U2	MDIO	R59 1.5 kΩ pulls GMAC_MDIO (U2_17, U1_253) up to VCC_1V8_S3. This meets the IEEE 1.5 kΩ value, TI DP83867 datasheet, source: Tomachie, page 7.	✓
9.4.30	Ethernet U2	PHY control	R58 2.49 kΩ pulls U2_44 INT/PWDN to VCC_1V8_S3, so the PHY is not held in power-down (tied low = power-down). The 2.2 kΩ figure is a recommendation, TI DP83867 datasheet, source: Tomachie, page 7.	✓
9.4.31	Ethernet Y1	25 MHz reference	C28 and C29 (32 pF each) give 16 pF in series, or 19 to 21 pF with 3 to 5 pF stray, against Y1's 20 pF load capacitance.	✓
9.4.32	Module U1	Unused interfaces	The HDMI0, MIPI DSI (DPHY0/DPHY1 TX) and PCIE20_2 lane pins are left unconnected. Unused outputs need no termination.	✓

9.5 Citations

AI-Assisted —

References
DF40C-100DS-0.4V (HIROSE ELECTRIC CO., LTD.) — datasheet www.marutsu.co.jp/contents/shop/marutsu/datasheet/DF40C-3...

10 Memory Interface Analysis

Found 2 complete memory interface(s)

10.1 J4 SDMMC Connector

J4 (1040310811) - SDMMC Connector Interface [4-bit]
Signal	Pin Name	Pin #	Net Name	Test Point	Source IC
CARD_DETECT	SW_DETECT	10		-	-
CLOCK	CLK	5	SDMMC_CLK	-	U1_57
CMD	CMD	3	Net-(J4-CMD)	-	-
DATA_0	DAT0	7	Net-(J4-DAT0)	-	-
DATA_1	DAT1	8	Net-(J4-DAT1)	-	-
DATA_2	DAT2	1	Net-(J4-DAT2)	-	-
DATA_3	CD/DAT3	2	Net-(J4-CD/DAT3)	-	-
Direct programming via test points is not needed since SD cards can be pre-programmed and inserted

10.2 J10 QSPI Connector

J10 (SM3ZS067U410AER1000) - QSPI Connector Interface [2-bit]
Signal	Pin Name	Pin #	Net Name	Test Point	Source IC
CLOCK	8	8	I2S_SCLK	-	U1_271
DATA_0	12	12	I2S_SDI	-	U1_273
DATA_1	14	14	I2S_SDO	-	U1_270
SELECT	-	-	-	-	-
Direct programming via test points is not needed since SD cards can be pre-programmed and inserted

10.3 Programming Access Verification

Verifies that ICs sharing the QSPI bus can be disabled during non-volatile memory programming.

J10 (SM3ZS067U410AER1000) - Programming via J10
Adjacent IC	Type	Can Disable	Control Path
U1	Hirose DF40C-100DS-0.4V	[FAIL]	No disable pins (RESET, CE#, OE#) found on component
DESIGN_WARNING:U1 (Hirose DF40C-100DS-0.4V): No disable pins (RESET, CE#, OE#) found on component

10.4 AI-Assisted Analysis

10.4.1 microSD Card Socket J4 (SDMMC, 4-bit)

AI-Assisted — J4 is a Molex 1040310811 microSD socket wired as a 4-bit SD bus to the SD controller of the OPi CM5 compute module seated in U1. The memory is the removable card. The board side consists only of contact mapping, series damping, pulls, power and detect.

The contact mapping follows the socket's own pin names. SDMMC_D0 to SDMMC_D3, SDMMC_CMD and SDMMC_CLK run from U1_63, U1_67, U1_69, U1_61, U1_62 and U1_57 to J4_7, J4_8, J4_1, J4_2, J4_3 and J4_5. The data and command lines pass through 22 Ω series resistors (R6, R8, R9, R10, R11). The absence of a clock resistor is already reported in the signal-integrity review.

No pull-up is fitted on SDMMC_CMD or on SDMMC_D0 to SDMMC_D3. Each of these nets ends at a module contact, so the pull-ups the SD bus requires must come from the module side.

The socket's card-detect contacts J4_9 and J4_10 (SW_DETECT) are not connected. SDMMC_DET_L reaches only U1_76, a module pin labelled Reserved, so the board gives the host no insertion signal.

Card power J4_4 sits directly on VCC_3V3_S3, which is the module's own 3.3 V output on U1_84 and U1_86. C6 (100 nF) is the only capacitance on that rail. SDMMC_PWREN (U1_75) drives nothing, so the card cannot be power-cycled independently of the module. This matters when a UHS-I card fails its 1.8 V signalling switch and must be reset by removing power.

The U1 symbol types U1_57 SD_CLK as an input although the module drives the clock. The board carries no test points (board total 0), so the SDMMC nets are reachable only at J4 and the module contacts.

10.5 Observations

AI-Assisted — The board carries no memory device of its own. DRAM and on-module storage reside on the OPi CM5 module plugged into U1, so this review covers only the removable microSD path at J4 and the J10 lines that were misclassed as flash.

Every J4 observation is drawn from connectivity alone. The socket has no manufacturer data in this review, so none of its rows exceeds review severity.

The items with functional consequence are the unwired card-detect switch and the uncontrolled card power. Together they mean the host can neither sense insertion nor recover a hung card without a full module power cycle.

None of the SDMMC nets carries an ESD clamp. J4 is a user-accessible socket, so these nets connect the card contacts directly to the module's SD pins.

10.6 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.6.1	microSD socket J4 (1040310811)	SDMMC 4-bit	No pull-up is fitted on SDMMC_CMD or on SDMMC_D0 to SDMMC_D3. The SD Association Physical Layer Specification requires pull-ups on CMD and DAT lines. These nets end at U1 module contacts, so check that the OPi CM5 provides them (internal or on-module); otherwise add pull-ups to VCC_3V3_S3 on this board.	Review
10.6.2	microSD socket J4 (1040310811)	Card detect	J4_9 and J4_10 SW_DETECT are unconnected, and SDMMC_DET_L reaches only U1_76 (Reserved), so card insertion is undetectable in hardware. Route the detect switch to a module GPIO input with a pull-up to VCC_3V3_S3, or document that firmware polls the card.	Review
10.6.3	microSD socket J4 (1040310811)	Card power	J4_4 VDD is fed directly from the module 3.3 V output VCC_3V3_S3, and SDMMC_PWREN (U1_75) drives nothing. The card cannot be power-cycled on its own, which is the recovery path when a UHS-I card fails its 1.8 V signalling switch. The designer should check whether UHS-I operation is intended. If it is, add a load switch on J4_4 enabled by SDMMC_PWREN.	Review
10.6.4	microSD socket J4 (1040310811)	Card power	C6 (100 nF, GRM033R61E104KE14D) is the only capacitance on VCC_3V3_S3 at J4. The rail has no bulk capacitor to absorb card-insertion inrush and write-current steps at the socket.	Review
10.6.5	microSD socket J4 (1040310811)	SDMMC ESD	None of the SDMMC_CMD, SDMMC_CLK or SDMMC_D0 to SDMMC_D3 nets carries an ESD clamp. Discharge into the user-accessible J4 contacts reaches the module SD pins directly.	Review
10.6.6	Module U1 (OPi CM5)	SDMMC clock	U1_57 SD_CLK is typed as an input in the U1 symbol, although the module drives the card clock. Correct the pin type so electrical-rule checks treat SDMMC_CLK as driven.	Review
10.6.7	M.2 Key E J10	I2S/PCM	I2S_LRCLK (U1_269) is wired to J10_9, while I2S_SCLK, I2S_SDI and I2S_SDO use J10_8, J10_12 and J10_14 and J10_10 is unconnected. Check the frame-sync contact against the M.2 Key E pin definitions.	Review
10.6.8	M.2 Key E J10	I2S/PCM	Host input I2S0_SDI0 (U1_273) goes to J10_12 and host output I2S0_SDO0 (U1_270) to J10_14, wired name-to-name. The U1 symbol also types U1_270 as an input. Check data direction against the M.2 Key E card-side naming and the module pinout.	Review
10.6.9	microSD socket J4 (1040310811)	SDMMC 4-bit	Contacts match the socket pin names. DAT2 J4_1, CD/DAT3 J4_2, CMD J4_3, VDD J4_4 (VCC_3V3_S3), CLK J4_5, VSS J4_6 (GND), DAT0 J4_7 and DAT1 J4_8 each reach the matching U1 SD pin.	✓
10.6.10	M.2 Key E J10	I2S/PCM	J10 carries the module I2S0 port (SCLK, SDI, SDO) to the Wi-Fi/Bluetooth card. It holds no flash, so chip-select, HOLD̅/R̅E̅S̅E̅T̅, series-damping and programming-access checks do not apply, and the module lacking a disable pin is not a defect.	✓

10.7 Citations

AI-Assisted —

References
CL05A105KO5NNNC (Samsung Electro-Mechanics) — datasheet datasheet.octopart.com/CL05A105KO5NNNC-Samsung-datasheet-...
CL31A476MQHNNNE (Samsung Electro-Mechanics) — datasheet mm.digikey.com/Volume0/opasdata/d220001/medias/docus/41/C...
DF40C-100DS-0.4V (HIROSE ELECTRIC CO., LTD.) — datasheet www.marutsu.co.jp/contents/shop/marutsu/datasheet/DF40C-3...
GCM155R71H103KA55D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/71b256f70e3bf7cf9a4379...
GRM155R60J106ME15D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/52964d1681dfbc63ce0fc5...
GRM155R71H104KE14D (Murata Manufacturing Co., Ltd.) — datasheet www.farnell.com/datasheets/3979589.pdf
MA0805XF106K160 (Meritek Electronics Corporation) — datasheet datasheet.lcsc.com/datasheet/pdf/52a7812796d96435f7eaf6e2...
MSASL219LB5226MTNA01 (TAIYO YUDEN) — datasheet static6.arrow.com/aropdfconversion/f469f48a48a5ac7463ef5f...

11 Functional Analysis

3 device(s) to review across 2 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
Y1	CRYSTAL	H130B-25.000-20-F-3030-TR	MHz Crystal, 25 MHz, 5 x 3.2 mm, +/-30 ppm tolerance, +/-30 ppm stability, 20 pF, -20~70C, SMD	-	-
U1	DEVICE	DF40C-100DS-0.4V	OPi CM5	I2C, MDIO, SDMMC [SDMMC], UART [UART]	-
U2	DEVICE	DP83867IRRGZR		MDIO	-

11.1 Functional Analysis

11.1.1 Ethernet PHY U2 (DP83867IRRGZR): Supplies, Thermal and Strap Pins

AI-Assisted — U2 runs in two-supply mode: VDDA1P8 is not connected, VDD1P0 is on P06_VDD1P0, VDDA2P5 is on VDD_2P5 and VDDIO is on VCC_1V8_S3. The exposed pad U2_49 is on GND. Supply levels, per-pin decoupling, RBIAS, MDIO and INT/PWDN were settled in the earlier power and signal-integrity sections and are not repeated here.

The TI DP83867 datasheet (source: Tomachie) gives 495 mW typical in 1000BASE-T two-supply operation and a θJA of 30.8 °C/W. At the design's 40 °C ambient this predicts a junction temperature of 55.2 °C. The ICs limit in the Benign (controlled office) derating selected for this schematic analysis is the lower of 115 °C and 70 °C (35 °C below the 105 °C Tj maximum), so 70 °C governs and U2 meets it.

The datasheet marks U2_38 RX_CTRL as strap-required. R25 (5.76 kΩ to VCC_1V8_S3) and R61 (2.49 kΩ to GND) define it at 0.543 V, which is 0.302 × VDDIO. U2_33 RX_D0 is strapped by R24 (10 kΩ up) and R60 (2.49 kΩ down) to 0.359 V, which is 0.199 × VDDIO. Each divider sinks at most 0.72 mA from the PHY output driving high. This is inside the 1 mA condition at which VOH ≥ VDDIO − 0.2 V is specified.

U2_45 LED_2 is also a strap pin on the RGZ package. It is unconnected in the schematic, and the datasheet does not state that it may float. That leaves its latched configuration undefined at power-up and after each reset. A pull resistor setting the intended strap level gives the PHY a deterministic configuration.

11.1.2 Ethernet PHY U2: MAC, Management and Reset Connections

AI-Assisted — All twelve RGMII signals connect U2 to the module. TX_D0 to TX_D3, TX_CTRL and GTX_CLK (through R53, 2.2 Ω) come from U1. RX_D0 to RX_D3, RX_CTRL and RX_CLK (through R54, 2.2 Ω) return to U1. GMAC_MDC runs from U1_291 to U2_16. The datasheet allows MDC up to 25 MHz.

U2_43 R̅E̅S̅E̅T̅ is on net GPIO1-C1, driven by U1_26 GPIO19. The module's GPIO bank reference U1_78 GPIO_VREF is fed from VCC_3V3_S3 through R31 (100 Ω), so GPIO19 is a 3.3 V output. The TI DP83867 datasheet gives an absolute maximum of VDDIO + 0.3 V for R̅E̅S̅E̅T̅. That is 2.1 V at 1.8 V nominal and 2.01 V at the 1.71 V VDDIO minimum, and nothing limits the current into the pin. A 3.3 V high therefore drives the pin above its absolute maximum.

The same net also feeds the J5 audio output stage: R15 (200 Ω) into C10 (100 nF) and R16 (100 Ω) to GND, coupled by C9 (47 µF) to J5_2. GPIO1-D5 drives the matching stage for J5_3, so GPIO19 is one of the two audio PWM channels. Whenever that channel plays, the PHY is reset at the audio rate. Whenever the PHY is held out of reset, the audio channel carries a DC level, and the stage loads the reset driver with 300 Ω to GND. One pin cannot serve both functions. A dedicated module output in the 1.8 V domain, or a translator characterised for a 3.3 V input and a 1.8 V output, removes both problems.

The net labels are crossed relative to the LED pins: 0_LED2 carries U2_47 LED_0 and 0_LED1 carries U2_46 LED_1.

11.1.3 Ethernet PHY U2: JTAG Test Access

AI-Assisted — R57 (4.7 kΩ) pulls U2_22 JTAG_TMS up to VCC_1V8_S3, and R55 (4.7 kΩ) pulls U2_23 JTAG_TDI up to the same rail. R56 (4.7 kΩ) pulls U2_20 JTAG_CLK down to GND, and U2_21 JTAG_TDO is unconnected in the schematic. With TCK held low and TMS high, the TAP rests in Test-Logic-Reset. The pull-up level equals VDDIO, inside the VDDIO + 0.3 V absolute maximum.

None of the four JTAG nets reaches a connector or test point, and the design summary records no test points at all. IEEE 1149.1 boundary scan of the PHY is therefore unreachable on this board. Boundary scan is the only way to check the RGMII and MDI solder joints of the QFN in production without functional Ethernet traffic. Four test points on TCK, TMS, TDI and TDO, with the existing pulls left in place, make it usable.

11.1.4 Compute Module U1 (OPi CM5, DF40C Connectors): Control Inputs and I/O Domains

AI-Assisted — U1 mates through DF40C-100DS-0.4V connectors. The Hirose DF40C datasheet (Datasheet) rates the contacts at 30 V DC, against the 5.5 V Type-C sink maximum on VCC5V0_SYS. It rates the operating range at −35 to +85 °C including self-heating, against the 40 °C ambient. Contact current was settled in the power section.

GPIO_VREF selects the 3.3 V bank level for the header-compatible GPIOs. This is a permitted configuration, and a 1.8 V reference would move those pins to the 1.8 V domain.

S1, S2 and S3 pull three module inputs to GND: PWRON_L through R3 (100 Ω), nRPIBOOT through R4 (100 Ω) and RUN_PG through R5 (200 Ω). C3, C4 and C5 (100 nF) debounce the switch nodes. The carrier fits no pull-up on any of the three nets, so their released level depends on the module.

R46 and R47 (2.2 kΩ to VCC3V3_REG) pull up I2C4 on GPIO13 and GPIO6, a 1.5 mA sink load at 3.3 V. VCC3V3_REG comes from U3, which is enabled whenever VCC5V0_SYS is present and is independent of the module's own 3.3 V output, so these pull-ups can present 3.3 V to module pins before the module's I/O supply is up. I2C6 (U1_80 SCL0, U1_82 SDA0) reaches J9 with no carrier pull-up.

11.1.5 25 MHz Crystal Y1 (H130B-25.000-20-F-3030-TR)

AI-Assisted — Y1 pin 1 is on CKXTAL1 to U2_15 XI, and pin 3 is on CKXTAL2 to U2_14 XO. Pins 2 and 4 are unconnected in the schematic. This matches the two-terminal function of the Raltron datasheet (Datasheet), although that document assigns the four-pin map only by analogy to the H13 series. The load capacitance and the ppm budget were settled in the signal-integrity section.

The ordering code decodes to fundamental mode, a 20 pF load and ±30 ppm tolerance and stability. The −20 to +70 °C range in the part description covers the 40 °C ambient. The crystal swing stays inside U2's XI absolute maximum of 2.1 V.

11.1.6 Gigabit Ethernet PHY (U2) and RJ45 with Magnetics (J1)

AI-Assisted — U2 (TI DP83867IRRGZ, datasheet, source: Tomachie) drives four 1000BASE-T MDI pairs into J1 (L834-1G1T-S7, RJ45 with integrated magnetics). The MDI pairs need 100 Ω differential routing and no AC coupling. Pairs A and C land with correct polarity. On pair B, U2_4 TD_P_B goes to J1_5 TRD2- and U2_5 TD_M_B goes to J1_4 TRD2+. On pair D, U2_10 goes to J1_9 TRD4- and U2_11 goes to J1_8 TRD4+. 1000BASE-T receivers correct polarity automatically, so this is a drawing inconsistency rather than a link failure. The four centre taps share C33, 100 nF, to GND. CLK_OUT (U2_18) feeds GMAC_MCLK through R49 (2.2 Ω), and R52 (120 Ω) pulls GMAC_MCLK to GND. The DC load on CLK_OUT is therefore 122.2 Ω. With VDDIO at 1.8 V, the high level draws 1.8 V / 122.2 Ω = 14.7 mA, against the 1 mA at which the datasheet guarantees VOH ≥ VDDIO − 0.2 V (page 11). R53 and R54, both 2.2 Ω, sit in GTX_CLK and RX_CLK. A 2.2 Ω resistor gives negligible series damping, and the RGMII rise and fall limit is 0.75 ns maximum (page 14). Y1 is a 25 MHz crystal, ±30 ppm tolerance and ±30 ppm stability, with a 20 pF load. C28 and C29 (32 pF each) give 16 pF in series, or 19 to 21 pF with 3 to 5 pF stray. The worst-case frequency error of ±60 ppm exceeds the 50 ppm stated for XI (page 7). The module pin names are inconsistent: U1_260 is named GMAC_RXCLK but sits on GMAC_RXD0, while U1_258 on GMAC_RXCLK carries the same name.

11.1.7 M.2 Key E Connector J10 (I2S/PCM Audio Lines)

AI-Assisted — J10 is the M.2 Key E socket for the Wi-Fi/Bluetooth card, as named in the designer's note on sheet OPi_CM5_Carrier. It was classed as a serial flash only because it carries a clock and two data lines. Those lines are the module's I2S0 port: I2S_SCLK runs U1_271 to J10_8, I2S_SDI runs U1_273 to J10_12, and I2S_SDO runs U1_270 to J10_14. They form a PCM audio link to the Bluetooth radio, not a memory bus. The flash checks therefore do not apply: chip select, HOLD̅/R̅E̅S̅E̅T̅ pull-ups, mode, and the programming-access note that the module has no disable pin.

Two wiring points remain. First, the I2S clock and data lines use the even contacts J10_8, J10_12 and J10_14, but I2S_LRCLK (U1_269) lands on odd contact J10_9, and J10_10 has no connection. The frame-sync line therefore breaks the pattern of the other three signals.

Second, the host data input I2S0_SDI0 is wired to the contact labelled SDI and the host output I2S0_SDO0 to the contact labelled SDO. This is name-to-name, the same pattern the signal-integrity review raised for the UART on this connector. The U1 symbol also types U1_270 I2S0_SDO0 as an input.

11.2 Findings

AI-Assisted —

#	Device	Finding	Severity
11.2.1	DP83867IRRGZR (U2)	U2_43 R̅E̅S̅E̅T̅ is driven by U1_26 GPIO19, a 3.3 V output (GPIO_VREF on VCC_3V3_S3 through R31). There is no series limiting. The TI DP83867 datasheet (source: Tomachie) gives an absolute maximum of VDDIO + 0.3 V, which is 2.01 V at the 1.71 V VDDIO minimum. Drive R̅E̅S̅E̅T̅ from a 1.8 V-domain module output, or through a translator characterised for a 3.3 V input and a 1.8 V output.	Medium
11.2.2	DP83867IRRGZR (U2)	Net GPIO1-C1 drives both U2_43 R̅E̅S̅E̅T̅ and the J5 audio stage (R15 200 Ω, C10 100 nF, R16 100 Ω, C9 47 µF to J5_2). Audio PWM on GPIO19 therefore resets the PHY repeatedly, and the stage loads the reset driver with 300 Ω to GND. Give R̅E̅S̅E̅T̅ its own module output.	Medium
11.2.3	DP83867IRRGZR (U2)	U2_45 LED_2 is an RGZ strap pin and is unconnected in the schematic. The TI DP83867 datasheet (source: Tomachie) does not state that it may float, so its latched configuration is undefined. Fit a pull resistor to the intended strap level.	Low
11.2.4	DP83867IRRGZR (U2)	None of the JTAG_CLK, JTAG_TMS, JTAG_TDI or JTAG_TDO nets reaches a connector or test point, so the PHY's IEEE 1149.1 boundary scan cannot be used. Add four test points on these nets.	Low
11.2.5	DP83867IRRGZR (U2)	U2_16 MDC is clocked from U1_291. The TI DP83867 datasheet (source: Tomachie, page 7) allows 25 MHz maximum. Check that the U1 MDC rate is configured at or below 25 MHz.	Review
11.2.6	DP83867IRRGZR (U2)	Net 0_LED2 carries U2_47 LED_0 and net 0_LED1 carries U2_46 LED_1, the reverse of the pin numbering. Rename the nets so the documentation matches the pins.	Review
11.2.7	OPi CM5 (U1)	U1_78 GPIO_VREF is fed from VCC_3V3_S3 through R31 (100 Ω), which selects 3.3 V levels for the header-compatible GPIO bank. A 1.8 V reference from VCC_1V8_S3 would select 1.8 V levels instead.	Review
11.2.8	OPi CM5 (U1)	S1, S2 and S3 pull PWRON_L (U1_99), nRPIBOOT (U1_93) and RUN_PG (U1_92) to GND through R3 (100 Ω), R4 (100 Ω) and R5 (200 Ω), with 100 nF debounce (C3, C4, C5). No pull-up is fitted on the carrier. Check that the module holds each input high when its switch is released.	Review
11.2.9	OPi CM5 (U1)	R46 and R47 (2.2 kΩ) pull I2C4 on GPIO13 and GPIO6 up to VCC3V3_REG. That rail comes from U3 and is independent of the module 3.3 V output, so it can be up before the module bank. Check that U1 GPIO13 and GPIO6 tolerate 3.3 V through 2.2 kΩ while the module is unpowered.	Review
11.2.10	OPi CM5 (U1)	I2C6 (U1_80 SCL0, U1_82 SDA0) reaches camera connector J9 with no pull-up on the carrier. The pull-ups must come from the module or the camera.	Review
11.2.11	H130B-25.000-20-F-3030-TR (Y1)	Y1 pin 1 is on XI (U2_15) and pin 3 on XO (U2_14), with pins 2 and 4 unconnected. This is consistent with the two-terminal function in the Raltron datasheet, although that document assigns the four-pin map by analogy to the H13 series.	Review
11.2.12	DP83867IRRGZR (U2)	U2_38 RX_CTRL is strap-required per the TI DP83867 datasheet (source: Tomachie), page 6. R25 (5.76 kΩ to VCC_1V8_S3) and R61 (2.49 kΩ to GND) define it at 0.543 V (0.302 × VDDIO).	✓
11.2.13	DP83867IRRGZR (U2)	U2_33 RX_D0 is strapped by R24 (10 kΩ to VCC_1V8_S3) and R60 (2.49 kΩ to GND) to 0.359 V (0.199 × VDDIO).	✓
11.2.14	DP83867IRRGZR (U2)	The RX_CTRL and RX_D0 dividers sink at most 0.72 mA when the PHY drives high. This is within the 1 mA condition for VOH ≥ VDDIO − 0.2 V. TI DP83867 datasheet, source: Tomachie, page 11.	✓
11.2.15	DP83867IRRGZR (U2)	The predicted junction temperature is 40 °C + 495 mW typical × 30.8 °C/W = 55.2 °C. The ICs limit in the Benign (controlled office) derating selected for this schematic analysis is 70 °C, the lower of 115 °C and 105 °C Tj maximum minus 35 °C. Within the limit. TI DP83867 datasheet, source: Tomachie, pages 11 and 12.	✓
11.2.16	DP83867IRRGZR (U2)	The rated operating range of −40 to +85 °C covers the 40 °C design ambient. TI DP83867 datasheet, source: Tomachie, page 10.	✓
11.2.17	DP83867IRRGZR (U2)	U2_49 PAD is on GND.	✓
11.2.18	DP83867IRRGZR (U2)	All twelve RGMII signals connect U2 to U1: TX_D0 to TX_D3, TX_CTRL, GTX_CLK (through R53, 2.2 Ω), RX_D0 to RX_D3, RX_CTRL and RX_CLK (through R54, 2.2 Ω).	✓
11.2.19	DP83867IRRGZR (U2)	JTAG idle levels: R57 and R55 (4.7 kΩ) pull U2_22 TMS and U2_23 TDI up to VCC_1V8_S3, and R56 (4.7 kΩ) pulls U2_20 TCK down to GND. The TAP rests in Test-Logic-Reset, and the levels are within the VDDIO + 0.3 V absolute maximum. TI DP83867 datasheet, source: Tomachie, page 10.	✓
11.2.20	OPi CM5 (U1)	The DF40C contacts are rated 30 V DC, against the 5.5 V maximum on VCC5V0_SYS. Hirose DF40C datasheet, page 6.	✓
11.2.21	OPi CM5 (U1)	The DF40C operating range of −35 to +85 °C, which includes self-heating, covers the 40 °C ambient. Hirose DF40C datasheet, page 6.	✓
11.2.22	OPi CM5 (U1)	The I2C4 pull-ups R46 and R47 (2.2 kΩ to VCC3V3_REG) give a 1.5 mA sink load at 3.3 V.	✓
11.2.23	H130B-25.000-20-F-3030-TR (Y1)	The −20 to +70 °C range in the part description covers the 40 °C design ambient.	✓

11.3 Citations

AI-Assisted —

References
74439324010 (Würth Elektronik eiSos) — datasheet www.we-online.com/components/products/datasheet/744393240...
C0402C100J3GACTU (KEMET Electronics Corporation) — datasheet content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf
CGA2B2X7R1H222K050BA (TDK) — datasheet product.tdk.com/system/files/dam/doc/product/capacitor/ce...
CL05A105KO5NNNC (Samsung Electro-Mechanics) — datasheet datasheet.octopart.com/CL05A105KO5NNNC-Samsung-datasheet-...
CL31A476MQHNNNE (Samsung Electro-Mechanics) — datasheet mm.digikey.com/Volume0/opasdata/d220001/medias/docus/41/C...
DF40C-100DS-0.4V (HIROSE ELECTRIC CO., LTD.) — datasheet www.marutsu.co.jp/contents/shop/marutsu/datasheet/DF40C-3...
DFE201610E-R47M (Murata Manufacturing Co., Ltd.) — datasheet search.murata.co.jp/Ceramy/image/img/P02/J(E)TE243A-0001.pdf
GCM155R71H103KA55D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/71b256f70e3bf7cf9a4379...
GRM155R60J106ME15D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/52964d1681dfbc63ce0fc5...
GRM155R71H104KE14D (Murata Manufacturing Co., Ltd.) — datasheet www.farnell.com/datasheets/3979589.pdf
H130B (Raltron Electronics Corporation) — datasheet, cited pages 2 xonstorage.z8.web.core.windows.net/pdf/2538297_H131105921...
MA0805XF106K160 (Meritek Electronics Corporation) — datasheet datasheet.lcsc.com/datasheet/pdf/52a7812796d96435f7eaf6e2...
MSASL219LB5226MTNA01 (TAIYO YUDEN) — datasheet static6.arrow.com/aropdfconversion/f469f48a48a5ac7463ef5f...
TPS62914-Q1 (Texas Instruments) — datasheet www.mouser.lt/datasheet/2/405/1/tps62914_q1-3556322.pdf

12 Designer Annotated Nets

Annotated signals

Designer-placed annotation markers on nets that are not already analyzed as HSSI differential pairs or Memory Bus signals.

Designer Annotations
Net Name	Annotation	Impedance	Notes
SDMMC_D3	Default
GMAC_MCLK	ETH
GMAC_MDC	ETH
GMAC_RXD0	ETH
GMAC_RXD1	ETH
GMAC_RXD2	ETH
GMAC_RXD3	ETH
GMAC_RXDV	ETH
GMAC_TXCLK	ETH
GMAC_TXD0	ETH
GMAC_TXD1	ETH
GMAC_TXD2	ETH
GMAC_TXD3	ETH
GMAC_TXEN	ETH
RES_RXCLK	ETH
clkout_res	ETH
HDMI0_SBDN-HPD	HDMI

13 EMC & ESD Protection Checks

Shielded connectors were not found in this design so EMC checks were not performed.

13.1 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed:14 connector-facing signal(s). 0 protected, 14 unprotected, 0 orientation issue(s).

13.1.1 Unprotected Signal Nets

Signal Net	Connector	Status
TYPECO_SSRX1P	J2	No ESD Protection
TYPEC0_USB20_OTG_DP	J2	No ESD Protection
TYPECO_SSRX2P	J2	No ESD Protection
TYPECO_SSRX1N	J2	No ESD Protection
TYPEC0_USB20_OTG_DN	J2	No ESD Protection
SSTX2P	J2	No ESD Protection
TYPEC0_SBU2	J2	No ESD Protection
R50CC2	J2	No ESD Protection
SSTX1N	J2	No ESD Protection
TYPEC0_SBU1	J2	No ESD Protection
TYPECO_SSRX2N	J2	No ESD Protection
SSTX2N	J2	No ESD Protection
R49CC1	J2	No ESD Protection
SSTX1P	J2	No ESD Protection

13.2 EMC & ESD Analysis

13.2.1 EMC Architecture

AI-Assisted — The carrier has a single logic ground, GND, and no chassis or protective-earth domain. Every connector return and every shell contact on this board lands on that net. This includes the J2 USB-C shell contacts J2_S1 to J2_S4, the J5 audio sleeve contact J5_1, the J4 card VSS contact and all interleaved ground contacts of J8, J9 and J10. One unsplit logic ground suits a computing board in a non-conductive enclosure. The only domain that comes off the plane is a cable connector's shield. J2 shows the consequence: an IEC 61000-4-2 discharge onto the shell has no designed entry point. Of the cabled connectors, only J1 has a conducted-noise barrier on its signal pairs, the magnetics inside the jack. J2, J5 and the two camera FFC connectors carry no series common-mode filtering. No transient clamp is drawn on any external signal path examined here. The power review has already reported the missing VBUS clamp at J2. The likely failure modes are radiated emissions from the SuperSpeed and camera cables against EN 55032/CISPR 32 Class B, and ESD coupling into the module pins under EN 55035 test levels (IEC 61000-4-2, 4 kV contact and 8 kV air). The ESD withstand of the module pins behind J2, J4, J5, J8, J9 and J10 is not in the data. Those paths are therefore judged on topology only.

13.2.2 Ethernet J1 (RJ45 with Integrated Magnetics)

AI-Assisted — J1 is an L834-1G1T-S7 jack with integrated magnetics, as the designer's note on sheet opi_cm5_carrier(page_2) states ("RJ45 w MAGNETICS"). The MDI pairs MDI0± to MDI3± run straight from the PHY-side windings to U2_1, U2_2, U2_4, U2_5, U2_7, U2_8, U2_10 and U2_11. The magnetics provide the galvanic barrier, so no cable-side clamp is needed. If a clamp is ever added, it belongs between the PHY-side windings and U2, terminated to GND. U2 MDI pins are rated 8000 V HBM, with a 6.5 V absolute maximum, in the Texas Instruments DP83867 datasheet (source: Tomachie), page 10. HBM is a component-level test and is not directly comparable with an IEC 61000-4-2 system discharge. All four centre taps J1_1, J1_6, J1_7 and J1_12 join on Net-(J1-TRCT1) and return to GND through C33 (100 nF). This gives common-mode current a low-impedance PHY-side return. The LED anodes J1_13 and J1_15 reach U2_47 LED_0 and U2_46 LED_1 through R41 and R40 (470 Ω), and the LED cathodes J1_14 and J1_16 sit on GND. These LED contacts sit at the panel opening and are not behind the magnetics. U2 non-MDI pins are rated 2500 V HBM (same datasheet, page 10). The J1 symbol carries no shell pin, so the jack's shield return is not drawn.

13.2.3 USB Type-C J2

AI-Assisted — J2 is a consumer-facing, hot-plug, right-angle receptacle and the most exposed entry point on the board. This review judges it at professional level: a computing product that must pass EN 55035. The shell contacts J2_S1 to J2_S4 sit on GND directly, and the GND contacts J2_A1, J2_A12, J2_B1 and J2_B12 are hard to GND as required. The J2 symbol has no mid-plate pin. No ESD array is fitted, so the arrays' ground reference cannot be checked. The USB 2.0 nets TYPEC0_USB20_OTG_DP and TYPEC0_USB20_OTG_DN, the SBU nets and the SuperSpeed receive pairs connect directly to U1 module pins. The transmit pairs pass through C1, C2, C14 and C15 (100 nF), which block DC but pass a discharge edge. CC1 and CC2 end at R51 and R50 (5.1 kΩ) to GND and reach no active pin. SBU1 (J2_A8) and SBU2 (J2_B8) are adjacent to VBUS contacts J2_A9 and J2_B9. A contact short during insertion therefore puts VBUS directly on U1_207 or U1_209. No common-mode choke is drawn on the USB 2.0 or SuperSpeed pairs. Cable common-mode current from the 5 Gbit/s-class lanes is the likely Class B radiated-emissions risk. Any choke on 10 Gbit/s-class lanes must be chosen for that rate, so its value is left to the designer.

13.2.4 microSD Socket J4

AI-Assisted — J4 is a user-accessible card socket. It has no cable and no hot-plug from a second device at another potential, so a direct low-impedance bond to GND is acceptable and the shield-net requirement does not apply. The J4 symbol carries no shell pin. The 22 Ω series resistors R6, R8, R9, R10 and R11 on DAT0 to DAT3 and CMD add some current limiting between the contacts and the module pins. SDMMC_CLK (J4_5 to U1_57) has none. The memory-bus review has already reported that none of the SDMMC nets carries an ESD clamp, and that finding is not repeated here.

13.2.5 Audio Jack J5

AI-Assisted — J5 (SJ3-35063BG, 3.5 mm) is consumer-facing. It is touched at every plug insertion, which makes it a direct IEC 61000-4-2 contact-discharge point under EN 55035. J5_1 sleeve is on GND. J5_3 couples through C8 (47 µF) to the node shared by C7, R13 and R14. J5_2 couples through C9 to the PWM audio filter, which the functional review placed on net GPIO1-C1 through R16 (100 Ω), C10 (100 nF) and R15 (200 Ω). Neither tip nor ring contact carries a clamp. C8 and C9 block DC but pass a discharge edge. The more significant EMC point is that the functional review found GPIO1-C1 also drives U2_43 R̅E̅S̅E̅T̅. A discharge into J5_2 that survives the R16/C10/R15 low-pass therefore lands on the PHY reset input as well as the module GPIO. The in-field symptom is an Ethernet link drop during an audio-plug ESD event. The RC filter gives real attenuation. However, the residual pulse at U2_43 cannot be computed without the jack-side discharge path, so this is raised for investigation.

13.2.6 Camera Connectors J8 and J9

AI-Assisted — J8 (FH12-22S, 4-lane) and J9 (FH12-15S, 2-lane) are vertical-latch FFC connectors to camera modules, as the designer's notes on sheet OPi_CM5_Carrier state. Both are internal, and their exposure is assembly handling rather than end-user contact. The board-level ESD requirement therefore applies at the enclosure boundary, not at these contacts. Each lane pair is flanked by ground contacts (seven on J8, four on J9), which gives every pair an adjacent return in the cable and limits differential-to-common-mode conversion. The camera supply J8_1 and J9_15 is VCC3V3_REG, the U3 buck output, with no series ferrite. Switching ripple therefore travels onto the FFC as common-mode current. That is a radiated-emissions contributor if the camera cable is long or leaves a shielded volume. The I2C and GPIO lines on J8_2 to J8_6 and J9_11 to J9_14 connect directly to module pins.

13.2.7 M.2 Key E Slot J10

AI-Assisted — J10 (SM3ZS067U410AER1000) is an internal card-edge socket for the Wi-Fi/Bluetooth module, as the designer's note states ("M.2 KEY E WIFI/BLUETOOTH"). It is not user-accessible during operation and is not cabled. PCIe, USB, UART and I2S signals connect directly to U1 with five ground contacts on GND, and that is appropriate for an internal slot. The radio's antenna leads are the card's own emission and immunity subject. The power, signal-integrity and memory-bus reviews already cover the J10 sideband, polarity and coupling items.

13.3 Observations

AI-Assisted — The board's ESD posture rests on the component-level ratings of U1 and U2. U2's ratings are known (8000 V HBM on MDI, 2500 V HBM elsewhere, Texas Instruments DP83867 datasheet, source: Tomachie, page 10). U1's are not in the data, and U1 terminates every J2, J4, J5, J8, J9 and J10 path. For a product that must meet EN 55035 at J2 and J5, the investigation order is: the J2 shield net and bond, then low-capacitance clamps on the J2 USB 2.0 and SBU nets referenced to GND, then the J5 tip and ring. A plastic enclosure with no chassis still lands the charge on GND. A shield RC changes the entry point and the waveform, not the destination. The single GND domain needs no change: digital, analog and power returns should not be split.

13.4 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.4.1	J2	Shell contacts J2_S1 to J2_S4 share the logic GND net, so the shield-bond strategy is not captured as design intent. Assign a dedicated SHIELD_GND_J2 net so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MΩ \|\| 4.7 nF (≥ 2 kV) from SHIELD_GND_J2 to logic GND. USB Type-C R2.5 section 3.2.1; IEC 61000-4-2.	Medium
13.4.2	J1	U2 MDI pins are rated 8000 V HBM with a 6.5 V absolute maximum (Texas Instruments DP83867 datasheet, source: Tomachie, page 10). HBM is a component-level waveform and is not directly comparable with an IEC 61000-4-2 system discharge, so the residual surge through the J1 magnetics is not quantified.	Review
13.4.3	J1	The centre taps J1_1, J1_6, J1_7 and J1_12 join on Net-(J1-TRCT1) and return to GND through C33 (100 nF). This provides a PHY-side common-mode return.	Review
13.4.4	J1	LED contacts J1_13 and J1_15 at the panel opening reach U2_47 LED_0 and U2_46 LED_1 through R41 and R40 (470 Ω), with no magnetic isolation. U2 non-MDI pins are rated 2500 V HBM (Texas Instruments DP83867 datasheet, source: Tomachie, page 10). Investigate a clamp on these nets if the product is tested to 8 kV air at the jack. IEC 61000-4-2.	Review
13.4.5	J1	The J1 symbol carries no shell pin, so the jack's shield return for the Ethernet cable is not drawn. If the jack has shield tabs, add them on a SHIELD_GND_J1 net bonded to GND through 1 MΩ \|\| 4.7 nF (≥ 2 kV). IEC 61000-4-2.	Review
13.4.6	J2	The J2 USB 2.0 contacts J2_A6, J2_B6, J2_A7 and J2_B7 (TYPEC0_USB20_OTG_DP, TYPEC0_USB20_OTG_DN) reach U1_105 and U1_103 with no transient clamp. Investigate a low-capacitance ESD array at J2 referenced to GND. IEC 61000-4-2.	Review
13.4.7	J2	The SuperSpeed receive contacts J2_A10, J2_A11, J2_B10 and J2_B11 reach U1_208, U1_210, U1_219 and U1_221 directly. The transmit contacts J2_A2, J2_A3, J2_B2 and J2_B3 pass only through C1, C2, C14 and C15 (100 nF), which pass a discharge edge. No clamp is fitted. Investigate an array characterised for the lane rate. IEC 61000-4-2.	Review
13.4.8	J2	SBU1 (J2_A8) and SBU2 (J2_B8) connect directly to U1_207 and U1_209 with no clamp. They are adjacent to VBUS contacts J2_A9 and J2_B9, so an insertion short applies VBUS to the module pins. Investigate an SBU protection device rated for VBUS. USB Type-C R2.5.	Review
13.4.9	J2	No common-mode filtering is drawn on the USB 2.0 or SuperSpeed pairs at J2. Cable common-mode current is the likely Class B radiated-emissions source. Leave a common-mode choke footprint characterised for the lane rate. EN 55032/CISPR 32.	Review
13.4.10	J5	Consumer-facing 3.5 mm jack J5 has no transient clamp on tip and ring contacts J5_2 and J5_3. C9 and C8 (47 µF) block DC but pass the discharge edge into the audio stage. Investigate a bidirectional low-capacitance TVS at J5 referenced to GND. EN 55035; IEC 61000-4-2.	Review
13.4.11	J5	A discharge into J5_2 passes through C9, R16 (100 Ω), C10 (100 nF) and R15 (200 Ω) onto net GPIO1-C1. The functional review found this net also drives U2_43 R̅E̅S̅E̅T̅. The likely field symptom is an Ethernet link drop on an audio-plug ESD event. Check the residual pulse at U2_43, or move the PHY reset off the audio net.	Review
13.4.12	J8, J9	Camera supply contacts J8_1 and J9_15 carry VCC3V3_REG from the U3 buck with no series ferrite. Switching ripple therefore reaches the FFC as common-mode current, a radiated-emissions contributor on long camera cables. EN 55032/CISPR 32.	Review
13.4.13	Board	A single logic ground, GND, with no chassis domain suits a computing board in a non-conductive enclosure. Only cable-connector shields should come off this plane. EN 55032/CISPR 32, IEC 61000-4-2.	✓
13.4.14	J1	The magnetics integrated in J1 separate the cable from U2 MDI pins U2_1 to U2_11, and no clamp sits on the cable side. This is the correct placement; any added TVS belongs between the PHY-side windings and U2, referenced to GND. IEEE 802.3 clause 40.	✓
13.4.15	J2	GND contacts J2_A1, J2_A12, J2_B1 and J2_B12 are hard to logic GND, as required for the Type-C ground return. USB Type-C R2.5.	✓
13.4.16	J2	CC1 and CC2 (R49CC1, R50CC2) end only at R51 and R50 (5.1 kΩ) to GND and reach no active pin, so a discharge on these contacts has no semiconductor to damage. USB Type-C R2.5.	✓
13.4.17	J4	J4 is a card socket with no cable and no hot-plug from a second device, so direct bonding to GND is acceptable and no shield net is required. The J4 symbol carries no shell pin. IEC 61000-4-2.	✓
13.4.18	J8, J9	J8 and J9 are internal FFC camera connectors with ground contacts flanking every MIPI pair (seven on J8, four on J9). This is adequate return structure, and no external clamp is required at an internal connector. IEC 61000-4-2.	✓
13.4.19	J10	J10 is an internal M.2 Key E card socket with five ground contacts on GND. It is not user-accessible and is not cabled, so no external ESD protection is required.	✓

13.5 Citations

AI-Assisted —

References
DF40C-100DS-0.4V (HIROSE ELECTRIC CO., LTD.) — datasheet www.marutsu.co.jp/contents/shop/marutsu/datasheet/DF40C-3...

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on LSSI buses	Yes	Place test points on every LSSI bus signal (JTAG, SWD, I2C, I3C, MDIO, SPI, QSPI, UART) that has none
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	7
Rails with TPs	1
Rails without TPs	6

Parts adjudicated as TH: J5 (SJ3-35063BG), J1 (L834-1G1T-S7). Their description and footprint do not say how they mount, so the mounting was looked up. If any is wrong, state SMT or TH/THT/THRU in the part's description.

6 power rail(s) need test points in the submitted design.

21 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
GND		J1_14, J1_16, J5_1 (through-hole)	✓
P06_VDD1P0		-	NEEDS TP
VCC3V3_REG		-	NEEDS TP
VCC5V0_SYS		-	NEEDS TP
VCC_1V8_S3		-	NEEDS TP
VCC_3V3_S3		-	NEEDS TP
VDD_2P5		-	NEEDS TP

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP3	GND	OPi_CM5_Carrier.kicad_sch
TP4	VCC5V0_SYS	OPi_CM5_Carrier.kicad_sch
TP5	VCC_3V3_S3	OPi_CM5_Carrier.kicad_sch
TP13	P06_VDD1P0	opi_cm5_carrier(page_2).kicad_sch
TP14	VCC3V3_REG	opi_cm5_carrier(page_2).kicad_sch
TP15	VCC_1V8_S3	opi_cm5_carrier(page_2).kicad_sch
TP16	VDD_2P5	opi_cm5_carrier(page_2).kicad_sch
TP17	GND	OPi_CM5_Carrier.kicad_sch
TP18	GND	opi_cm5_carrier(page_2).kicad_sch
TP19	GND	OPi_CM5_Carrier.kicad_sch
TP20	GND	opi_cm5_carrier(page_2).kicad_sch
TP21	GND	OPi_CM5_Carrier.kicad_sch

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP1	UART_TXD	OPi_CM5_Carrier.kicad_sch
TP2	UART_RXD	OPi_CM5_Carrier.kicad_sch
TP6	BOOT_SW	OPi_CM5_Carrier.kicad_sch
TP7	PMIC_RESET_L	OPi_CM5_Carrier.kicad_sch
TP8	PWRON_L	OPi_CM5_Carrier.kicad_sch
TP9	I2C6_SCL_M3	OPi_CM5_Carrier.kicad_sch
TP10	I2C6_SDA_M3	OPi_CM5_Carrier.kicad_sch
TP11	GMAC_MDC	opi_cm5_carrier(page_2).kicad_sch
TP12	GMAC_MDIO	opi_cm5_carrier(page_2).kicad_sch

14.3 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.4 Current Test Points

Total test points

No test points found in design.

14.5 Powered-off Testing

No nets with BON test points detected.

14.6 Powered-on Testing

No power rail nets have BON test points.

14.7 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.8 Inspection

Total: 117 components, 739 of 749 pins with inspection coverage.

14.8.1 AOI

IPC Compliant Footprints
Visible-joint components with IPC compliant footprints. Package type structurally verified from footprint name.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Custom_Parts
CAPC0603X33N	0.6 x 0.3		Chip Passive	IPC-7351B	12	24	C1, C10, C14, C15, C2, C26, C3, C33 ...+4 more
CAPC10555_55N_KEM			Chip Passive	IPC-7351B	26	52	C19, C20, C22, C23, C24, C25, C34, C35 ...+18 more
CAPC340180_88N_KEM			Chip Passive	IPC-7351B	8	16	C21, C27, C30, C31, C32, C38, C8, C9
RESC1508X50N	1.5 x 0.8		Chip Passive	IPC-7351B	1	2	R17
Subtotal: 47 components, 94 pins

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Custom_Parts
CAP_06031A0R6BAT2A			Chip Passive	Designator	5	10	C28, C29, R49, R50, R51
CAP_1608_TDK			Chip Passive	Designator	1	2	C13
CAP_MSAS21-9_TAY			Chip Passive	Designator	2	4	C12, C39
IND_DFE201610E_MUR			Chip Passive	Designator	2	4	L3, L4
RES_CRCW_0402			Chip Passive	Designator	30	60	C11, R1, R10, R11, R12, R18, R19, R2 ...+22 more
STA_RMCF1206_STP			Chip Passive	Designator	2	4	R46, R47
STA_RNCP1206_STP			Chip Passive	Designator	8	16	R13, R14, R15, R16, R3, R31, R4, R5
WE-XHMI_4030			Chip Passive	Designator	1	2	L2
Resistor_SMD
R_01005_0402Metric			Chip Passive	Designator	1	2	R52
Subtotal: 52 components, 104 pins
Opens only (leads visible, shorts unreliable)
Custom_Parts
RGZ0048B			SOIC/SOP	Designator	1	49	U2
OPi_CM5			SOIC/SOP	Designator	3	300	U1, U1, U1
Subtotal: 4 components, 349 pins
Presence check (manual verification)
Custom_Parts
104031-0811_MOL			Connector	Designator	1	10	J4
CONN16_L834-1G1T-S7_BEL			Connector	Designator	1	16	J1
CONN_FH12-15S-0.5SH55_HIR			Connector	Designator	1	15	J9
CONN_FH12-22S-0.5SH55_HIR			Connector	Designator	1	22	J8
CONN_SM3ZS067U410AER1000_JAE			Connector	Designator	2	67	J10, J10
GCT_USB4056-03-A_REVA2			Connector	Designator	1	28	J2
SAMESKY_SJ3-35063BG			Connector	Designator	1	6	J5
Subtotal: 8 components, 164 pins

14.8.2 AXI

Assumed Classification (Non-IPC Footprints)
Hidden-joint classification inferred from Pkg Type property or designator prefix. Footprint names are not IPC-7351B or IPC-7251.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Custom_Parts
VQFN-HR14_RPY_TEX			QFN/DFN (No-Lead)	Footprint	1	14	U3
VQFN14_RQR_TEX			QFN/DFN (No-Lead)	Footprint	1	14	U5
Subtotal: 2 components, 28 pins

14.8.3 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library symbol lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
Custom_Parts
H130B2500020F3030TR	Oscillator / Crystal	Designator	1	4	Y1
SW_SWT0010-015016SSA_REVA	Unclassified	Unknown	3	6	S1, S2, S3
Subtotal: 4 components, 10 pins

14.9 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.9.1 Fault Coverage Summary

Fault Coverage Summary (749 pins)
Test Method	Opens	Shorts
X-ray (AXI)	0 (0.0%)	0 (0.0%)
Optical (AOI)	94 (12.6%)	94 (12.6%)
Electrical
Powered-off Testing	0 (0.0%)	0 (0.0%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	30 (4.0%)	30 (4.0%)
Total	161 (21.5%)	299 (39.9%)
Total Fault Coverage	247 (33.0%)	322 (43.0%)
No coverage	502 (67.0%)	427 (57.0%)

14.9.2 Uncovered Pins (427)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
R47_2	GPIO1_A3
J4_9
J4_10
R14_2	Net-(C7-Pad2)
R3_1	PWRON_L
R3_2	Net-(C3-Pad2)
R50_1	R50CC2
R15_1	GPIO1-C1
R15_2	Net-(C10-Pad2)
R13_1	GPIO1-D5
R13_2	Net-(C7-Pad2)
J9_2	MIPI_DPHY0_RX_D0N
J9_3	MIPI_DPHY0_RX_D0P
J9_5	MIPI_DPHY0_RX_D1N
J9_6	MIPI_DPHY0_RX_D1P
J9_8	MIPI_DPHY0_RX_CLKN
J9_9	MIPI_DPHY0_RX_CLKP
J9_11	GPIO1-D3
J9_12	GPIO1_D7
J2_A2	SSTX1P
J2_A3	SSTX1N
J2_A5	R49CC1
J2_A6	TYPEC0_USB20_OTG_DP
J2_A7	TYPEC0_USB20_OTG_DN
J2_A8	TYPEC0_SBU1
J2_A10	TYPECO_SSRX2N
J2_A11	TYPECO_SSRX2P
J2_B2	SSTX2P
J2_B3	SSTX2N
J2_B5	R50CC2
J2_B6	TYPEC0_USB20_OTG_DP
J2_B7	TYPEC0_USB20_OTG_DN
J2_B8	TYPEC0_SBU2
J2_B10	TYPECO_SSRX1N
J2_B11	TYPECO_SSRX1P
U1_101	TYPEC0_USB20_OTG_ID
U1_102	PCIE_CLKREQN
U1_103	TYPEC0_USB20_OTG_DN
U1_104	PCIE_WAKEN
U1_105	TYPEC0_USB20_OTG_DP
U1_106	GPIO4_A6
U1_109	PCIE20_PERSTn_3V3_L
U1_110	PCIE20_2_REFCLKP
U1_111
U1_112	PCIE20_2_REFCLKN
U1_115	MIPI_CSI0_RX_D0N
U1_116	PCIE20_2_RXP/SATA30_2_RXP
U1_117	MIPI_CSI0_RX_D0P
U1_118	PCIE20_2_RXN/SATA30_2_RXN
U1_121	MIPI_CSI0_RX_D1N
U1_122	PCIE20_2_TXP/SATA30_2_TXP
U1_123	MIPI_CSI0_RX_D1P
U1_124	PCIE20_2_TXN/SATA30_2_TXN
U1_127	MIPI_CSI0_CLK0N
U1_128	MIPI_DPHY0_RX_D0N
U1_129	MIPI_CSI0_CLK0P
U1_130	MIPI_DPHY0_RX_D0P
U1_133	MIPI_CSI0_RX_D2N
U1_134	MIPI_DPHY0_RX_D1N
U1_135	MIPI_CSI0_RX_D2P
U1_136	MIPI_DPHY0_RX_D1P
U1_139	MIPI_CSI0_RX_D3N
U1_140	MIPI_DPHY0_RX_CLKN
U1_141	MIPI_CSI0_RX_D3P
U1_142	MIPI_DPHY0_RX_CLKP
U1_143
U1_145
U1_146
U1_147
U1_148
U1_149	HDMI0_TX_ON_H
U1_151	HDMI_TX0_CEC_M0
U1_152
U1_153	HDMI0_SBDN-HPD
U1_154
U1_157	MIPI_DPHY0_TX_D0N
U1_158	HDMI0_SBDP
U1_159	MIPI_DPHY0_TX_D0P
U1_160
U1_163	MIPI_DPHY0_TX_D1N
U1_164
U1_165	MIPI_DPHY0_TX_D1P
U1_166
U1_169	MIPI_DPHY0_TX_CLKN
U1_170	HDMI0_TX2P
U1_171	MIPI_DPHY0_TX_CLKP
U1_172	HDMI0_TX2N
U1_175	MIPI_DPHY1_TX_D0N
U1_176	HDMI0_TX1P
U1_177	MIPI_DPHY1_TX_D0P
U1_178	HDMI0_TX1N
U1_181	MIPI_DPHY1_TX_D1N
U1_182	HDMI0_TX0P
U1_183	MIPI_DPHY1_TX_D1P
U1_184	HDMI0_TX0N
U1_187	MIPI_DPHY1_TX_CLKN
U1_188	HDMI0_TX3P
U1_189	MIPI_DPHY1_TX_CLKP
U1_190	HDMI0_TX3N
U1_193	MIPI_DPHY1_TX_D2N
U1_194	MIPI_DPHY1_TX_D3N
U1_195	MIPI_DPHY1_TX_D2P
U1_196	MIPI_DPHY1_TX_D3P
U1_199	HDMI_TX0_SDA_M0
U1_200	HDMI_TX0_SCL_M0
U1_201	USB_D+
U1_202	TYPECO_SSTX2P
U1_203	USB_D-
U1_204	TYPECO_SSTX2N
U1_207	TYPEC0_SBU1
U1_208	TYPECO_SSRX2P
U1_209	TYPEC0_SBU2
U1_210	TYPECO_SSRX2N
U1_213
U1_214	TYPECO_SSTX1N
U1_215
U1_216	TYPECO_SSTX1P
U1_219	TYPECO_SSRX1N
U1_220
U1_221	TYPECO_SSRX1P
U1_222	PCIE20_CLKREQ
U1_224	PCIE20_PERSTn
U1_225
U1_227
U1_228	UART_RTS
U1_231
U1_233
U1_234
U1_236
U1_237
U1_238
U1_239
U1_240	UART_CTS
U1_242	GMAC_TXD3
U1_243	PCIE20_WAKEn
U1_244
U1_246	GMAC_TXD0
U1_247	GMAC_TXD2
U1_249	GMAC_TXD1
U1_250
U1_251	GMAC_TXEN
U1_252
U1_253	GMAC_MDIO
U1_256	GMAC_RXD1
U1_257	GMAC_MCLK
U1_258	GMAC_RXCLK
U1_259	GMAC_RXDV
U1_260	GMAC_RXD0
U1_261	GMAC_RXD2
U1_262	GMAC_TXCLK
U1_263	GMAC_RXD3
U1_266
U1_267
U1_268
U1_269	I2S_LRCLK
U1_270	I2S_SDO
U1_271	I2S_SCLK
U1_272
U1_273	I2S_SDI
U1_276	PCIE20_REFCLKP
U1_277
U1_278	PCIE20_REFCLKN
U1_279
U1_281
U1_282	PCIE20_TXP
U1_283
U1_284	PCIE20_TXN
U1_285
U1_288	PCIE20_RXN
U1_289
U1_290	PCIE20_RXP
U1_291	GMAC_MDC
U1_293
U1_294
U1_295
U1_296
U1_297
U1_298
R4_1	BOOT_SW
R4_2	Net-(C4-Pad2)
J10_43	PCIE20_RXN
J10_44
J10_46
J10_47	PCIE20_REFCLKP
J10_48
J10_49	PCIE20_REFCLKN
J10_50
J10_52	PCIE20_PERSTn
J10_53	PCIE20_CLKREQ
J10_54
J10_55	PCIE20_WAKEn
J10_56
J10_58
J10_59
J10_60
J10_61
J10_62
J10_64
J10_65
J10_66
J10_67
J10_68
J10_70
J10_71
J10_73
U1_3
U1_4
U1_5
U1_6
U1_9
U1_10
U1_11
U1_12
U1_15
U1_16
U1_17
U1_18
U1_19
U1_20
U1_21	GPIO_A4
U1_24	GPIO1-C0
U1_25	GPIO1_B0
U1_26	GPIO1-C1
U1_27	GPIO1_B1
U1_28	I2C4_SDA_M3
U1_29	GPIO1_B2
U1_30	GPIO1_A3
U1_31	GPIO1_B3
U1_34	GPIO1_A4
U1_35	GPIO1_D6
U1_36	GPIO1_D7
U1_37	GPIO1_B4
U1_38	GPIO1_A5
U1_39	GPIO1_B5
U1_40	GPIO1_A6
U1_41	GPIO1_B6
U1_44	GPIO1_A7
U1_45	GPIO1_B7
U1_46	GPIO1-C4
U1_47	GPIO0-C2
U1_48	GPIO1-C6
U1_49	GPIO1-D5
U1_50	GPIO1-D0
U1_51	UART_RX
U1_54	GPIO1-D1
U1_55	UART_TX
U1_56	GPIO1-D2
U1_58	GPIO1-D3
U1_64
U1_68	SW_RECOVERY
U1_70
U1_72
U1_73
U1_75	SDMMC_PWREN
U1_76	SDMMC_DET_L
U1_78	GPIO_VREF
U1_89
U1_91
U1_92	PMIC_RESET_L
U1_93	BOOT_SW
U1_94	SARADC_VIN3
U1_95	GPIO4_B6
U1_96	SARADC_VIN2
U1_97	GPIO4_A7
U1_99	PWRON_L
U1_100	GPIO4_A5
R16_2	Net-(C10-Pad2)
R31_1	GPIO_VREF
S3_1	Net-(C5-Pad2)
S1_1	Net-(C3-Pad2)
J8_2	I2C4_SDA_M3
J8_3	GPIO1_A3
J8_5	GPIO1_B7
J8_6	GPIO1_B6
J8_8	MIPI_CSI0_RX_D3P
J8_9	MIPI_CSI0_RX_D3N
J8_11	MIPI_CSI0_RX_D2P
J8_12	MIPI_CSI0_RX_D2N
J8_14	MIPI_CSI0_CLK0P
J8_15	MIPI_CSI0_CLK0N
J8_17	MIPI_CSI0_RX_D1P
J8_18	MIPI_CSI0_RX_D1N
J8_20	MIPI_CSI0_RX_D0P
J8_21	MIPI_CSI0_RX_D0N
R5_1	PMIC_RESET_L
R5_2	Net-(C5-Pad2)
J5_2	Net-(C9-Pad2)
J5_3	Net-(C8-Pad2)
J5_4
J5_5
J5_6
S2_1	Net-(C4-Pad2)
R51_2	R49CC1
J10_3	USB_D+
J10_5	USB_D-
J10_6
J10_8	I2S_SCLK
J10_9	I2S_LRCLK
J10_10
J10_11
J10_12	I2S_SDI
J10_13
J10_14	I2S_SDO
J10_15
J10_16
J10_17
J10_19
J10_20
J10_21
J10_23
J10_34	UART_CTS
J10_35	PCIE20_TXP
J10_36	UART_RTS
J10_37	PCIE20_TXN
J10_38
J10_40
J10_41	PCIE20_RXP
J10_42
R46_2	I2C4_SDA_M3
R40_1	0_LED1
R40_2	Net-(J1-LEDG2_A)
Y1_1	CKXTAL1
Y1_2
Y1_3	CKXTAL2
Y1_4
R19_1	Net-(U5-FB1)
L4_2	Net-(U5-SW2)
R20_1	Net-(U5-FB2)
R22_2	Net-(U5-FB2)
C28_1	CKXTAL2
U5_1	Net-(U5-FB2)
U5_3	Net-(U5-FB1)
U5_4	Net-(U5-PG1)
U5_6	Net-(U5-SW1)
U5_12	Net-(U5-SW2)
U5_13	Net-(U5-PG2)
U5_14	Net-(U5-COMP/FSET)
R56_1	Net-(U2-JTAG_CLK)
C13_2	Net-(U3-NR/SS)
R12_2	Net-(U3-FB)
U3_2	Net-(U3-NR/SS)
U3_3	Net-(U3-FB)
U3_5	Net-(U3-PG)
U3_6	Net-(U3-S-CONF)
U3_10	Net-(C26-Pad1)
U3_13	Net-(C26-Pad1)
U3_14	Net-(U3-BOOT)
R53_1	GMAC_TXCLK
R53_2	Net-(U2-GTX_CLK)
R23_1	Net-(U5-COMP/FSET)
R54_1	GMAC_RXCLK
R54_2	RES_RXCLK
R61_2	GMAC_RXDV
R45_2	Net-(U2-RBIAS)
R24_2	GMAC_RXD0
R60_2	GMAC_RXD0
R18_2	Net-(U5-PG2)
C29_2	CKXTAL1
R1_2	Net-(U3-S-CONF)
L3_2	Net-(U5-SW1)
R57_1	Net-(U2-JTAG_TMS)
R59_1	GMAC_MDIO
R55_1	Net-(U2-JTAG_TDI)
U2_1	MDI0+
U2_2	MDI0-
U2_4	MDI1+
U2_5	MDI1-
U2_7	MDI2+
U2_8	MDI2-
U2_10	MDI3+
U2_11	MDI3-
U2_12	Net-(U2-RBIAS)
U2_13
U2_14	CKXTAL2
U2_15	CKXTAL1
U2_16	GMAC_MDC
U2_17	GMAC_MDIO
U2_18	clkout_res
U2_20	Net-(U2-JTAG_CLK)
U2_21
U2_22	Net-(U2-JTAG_TMS)
U2_23	Net-(U2-JTAG_TDI)
U2_25	GMAC_TXD3
U2_26	GMAC_TXD2
U2_27	GMAC_TXD1
U2_28	GMAC_TXD0
U2_29	Net-(U2-GTX_CLK)
U2_32	RES_RXCLK
U2_33	GMAC_RXD0
U2_34	GMAC_RXD1
U2_35	GMAC_RXD2
U2_36	GMAC_RXD3
U2_37	GMAC_TXEN
U2_38	GMAC_RXDV
U2_39
U2_40
U2_43	GPIO1-C1
U2_44	Net-(U2-INT/PWDN)
U2_45
U2_46	0_LED1
U2_47	0_LED2
U2_48
R41_1	0_LED2
R41_2	Net-(J1-LEDG1_A)
R21_2	Net-(U5-FB1)
R25_2	GMAC_RXDV
R7_2	Net-(U5-PG1)
R58_1	Net-(U2-INT/PWDN)
R49_1	clkout_res
R49_2	GMAC_MCLK
J1_1	Net-(J1-TRCT1)
J1_2	MDI2-
J1_3	MDI2+
J1_4	MDI1-
J1_5	MDI1+
J1_6	Net-(J1-TRCT1)
J1_7	Net-(J1-TRCT1)
J1_8	MDI3-
J1_9	MDI3+
J1_10	MDI0-
J1_11	MDI0+
J1_12	Net-(J1-TRCT1)
J1_13	Net-(J1-LEDG1_A)
J1_15	Net-(J1-LEDG2_A)
R52_1	GMAC_MCLK
L2_1	Net-(C26-Pad1)
R2_1	Net-(U3-PG)

14.9.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
C7_1	GND	●	●	●	◐	-	-
C7_2	Net-(C7-Pad2)	-	-	●	◐	-	-
R47_1	VCC3V3_REG	●	●	-	-	-	-
R47_2	GPIO1_A3	-	-	-	-	-	-
R11_1	SDMMC_CMD	●	◐	-	-	-	-
R11_2	Net-(J4-CMD)	●	◐	-	-	-	-
C8_1	Net-(C7-Pad2)	-	-	●	◐	-	-
C8_2	Net-(C8-Pad2)	-	-	●	◐	-	-
C15_1	SSTX2P	-	-	●	◐	-	-
C15_2	TYPECO_SSTX2P	-	-	●	◐	-	-
R6_1	SDMMC_D0	●	◐	-	-	-	-
R6_2	Net-(J4-DAT0)	●	◐	-	-	-	-
J4_1	Net-(J4-DAT2)	●	◐	-	-	-	-
J4_2	Net-(J4-CD/DAT3)	●	◐	-	-	-	-
J4_3	Net-(J4-CMD)	●	◐	-	-	-	-
J4_4	VCC_3V3_S3	-	●	-	-	-	-
J4_5	SDMMC_CLK	●	◐	-	-	-	-
J4_6	GND	-	●	-	-	-	-
J4_7	Net-(J4-DAT0)	●	◐	-	-	-	-
J4_8	Net-(J4-DAT1)	●	◐	-	-	-	-
J4_9		-	-	-	-	-	-
J4_10		-	-	-	-	-	-
C6_1	GND	-	●	●	◐	-	-
C6_2	VCC_3V3_S3	-	●	●	◐	-	-
R14_1	GND	●	●	-	-	-	-
R14_2	Net-(C7-Pad2)	-	-	-	-	-	-
R3_1	PWRON_L	-	-	-	-	-	-
R3_2	Net-(C3-Pad2)	-	-	-	-	-	-
R50_1	R50CC2	-	-	-	-	-	-
R50_2	GND	-	●	-	-	-	-
C2_1	TYPECO_SSTX1P	-	-	●	◐	-	-
C2_2	SSTX1P	-	-	●	◐	-	-
C5_1	GND	●	●	●	◐	-	-
C5_2	Net-(C5-Pad2)	-	-	●	◐	-	-
R15_1	GPIO1-C1	-	-	-	-	-	-
R15_2	Net-(C10-Pad2)	-	-	-	-	-	-
R9_1	SDMMC_D2	●	◐	-	-	-	-
R9_2	Net-(J4-DAT2)	●	◐	-	-	-	-
R13_1	GPIO1-D5	-	-	-	-	-	-
R13_2	Net-(C7-Pad2)	-	-	-	-	-	-
J9_1	GND	-	●	-	-	-	-
J9_2	MIPI_DPHY0_RX_D0N	-	-	-	-	-	-
J9_3	MIPI_DPHY0_RX_D0P	-	-	-	-	-	-
J9_4	GND	-	●	-	-	-	-
J9_5	MIPI_DPHY0_RX_D1N	-	-	-	-	-	-
J9_6	MIPI_DPHY0_RX_D1P	-	-	-	-	-	-
J9_7	GND	-	●	-	-	-	-
J9_8	MIPI_DPHY0_RX_CLKN	-	-	-	-	-	-
J9_9	MIPI_DPHY0_RX_CLKP	-	-	-	-	-	-
J9_10	GND	-	●	-	-	-	-
J9_11	GPIO1-D3	-	-	-	-	-	-
J9_12	GPIO1_D7	-	-	-	-	-	-
J9_13	I2C6_SCL_M3	●	◐	-	-	-	-
J9_14	I2C6_SDA_M3	●	◐	-	-	-	-
J9_15	VCC3V3_REG	-	●	-	-	-	-
C10_1	GND	●	●	●	◐	-	-
C10_2	Net-(C10-Pad2)	-	-	●	◐	-	-
J2_A1	GND	-	●	-	-	-	-
J2_A2	SSTX1P	-	-	-	-	-	-
J2_A3	SSTX1N	-	-	-	-	-	-
J2_A4	VCC5V0_SYS	-	●	-	-	-	-
J2_A5	R49CC1	-	-	-	-	-	-
J2_A6	TYPEC0_USB20_OTG_DP	-	-	-	-	-	-
J2_A7	TYPEC0_USB20_OTG_DN	-	-	-	-	-	-
J2_A8	TYPEC0_SBU1	-	-	-	-	-	-
J2_A9	VCC5V0_SYS	-	●	-	-	-	-
J2_A10	TYPECO_SSRX2N	-	-	-	-	-	-
J2_A11	TYPECO_SSRX2P	-	-	-	-	-	-
J2_A12	GND	-	●	-	-	-	-
J2_B1	GND	-	●	-	-	-	-
J2_B2	SSTX2P	-	-	-	-	-	-
J2_B3	SSTX2N	-	-	-	-	-	-
J2_B4	VCC5V0_SYS	-	●	-	-	-	-
J2_B5	R50CC2	-	-	-	-	-	-
J2_B6	TYPEC0_USB20_OTG_DP	-	-	-	-	-	-
J2_B7	TYPEC0_USB20_OTG_DN	-	-	-	-	-	-
J2_B8	TYPEC0_SBU2	-	-	-	-	-	-
J2_B9	VCC5V0_SYS	-	●	-	-	-	-
J2_B10	TYPECO_SSRX1N	-	-	-	-	-	-
J2_B11	TYPECO_SSRX1P	-	-	-	-	-	-
J2_B12	GND	-	●	-	-	-	-
J2_S1	GND	-	●	-	-	-	-
J2_S2	GND	-	●	-	-	-	-
J2_S3	GND	-	●	-	-	-	-
J2_S4	GND	-	●	-	-	-	-
U1_101	TYPEC0_USB20_OTG_ID	-	-	-	-	-	-
U1_102	PCIE_CLKREQN	-	-	-	-	-	-
U1_103	TYPEC0_USB20_OTG_DN	-	-	-	-	-	-
U1_104	PCIE_WAKEN	-	-	-	-	-	-
U1_105	TYPEC0_USB20_OTG_DP	-	-	-	-	-	-
U1_106	GPIO4_A6	-	-	-	-	-	-
U1_107	GND	●	●	-	-	-	-
U1_108	GND	●	●	-	-	-	-
U1_109	PCIE20_PERSTn_3V3_L	-	-	-	-	-	-
U1_110	PCIE20_2_REFCLKP	-	-	-	-	-	-
U1_111		-	-	-	-	-	-
U1_112	PCIE20_2_REFCLKN	-	-	-	-	-	-
U1_113	GND	●	●	-	-	-	-
U1_114	GND	●	●	-	-	-	-
U1_115	MIPI_CSI0_RX_D0N	-	-	-	-	-	-
U1_116	PCIE20_2_RXP/SATA30_2_RXP	-	-	-	-	-	-
U1_117	MIPI_CSI0_RX_D0P	-	-	-	-	-	-
U1_118	PCIE20_2_RXN/SATA30_2_RXN	-	-	-	-	-	-
U1_119	GND	●	●	-	-	-	-
U1_120	GND	●	●	-	-	-	-
U1_121	MIPI_CSI0_RX_D1N	-	-	-	-	-	-
U1_122	PCIE20_2_TXP/SATA30_2_TXP	-	-	-	-	-	-
U1_123	MIPI_CSI0_RX_D1P	-	-	-	-	-	-
U1_124	PCIE20_2_TXN/SATA30_2_TXN	-	-	-	-	-	-
U1_125	GND	●	●	-	-	-	-
U1_126	GND	●	●	-	-	-	-
U1_127	MIPI_CSI0_CLK0N	-	-	-	-	-	-
U1_128	MIPI_DPHY0_RX_D0N	-	-	-	-	-	-
U1_129	MIPI_CSI0_CLK0P	-	-	-	-	-	-
U1_130	MIPI_DPHY0_RX_D0P	-	-	-	-	-	-
U1_131	GND	●	●	-	-	-	-
U1_132	GND	●	●	-	-	-	-
U1_133	MIPI_CSI0_RX_D2N	-	-	-	-	-	-
U1_134	MIPI_DPHY0_RX_D1N	-	-	-	-	-	-
U1_135	MIPI_CSI0_RX_D2P	-	-	-	-	-	-
U1_136	MIPI_DPHY0_RX_D1P	-	-	-	-	-	-
U1_137	GND	●	●	-	-	-	-
U1_138	GND	●	●	-	-	-	-
U1_139	MIPI_CSI0_RX_D3N	-	-	-	-	-	-
U1_140	MIPI_DPHY0_RX_CLKN	-	-	-	-	-	-
U1_141	MIPI_CSI0_RX_D3P	-	-	-	-	-	-
U1_142	MIPI_DPHY0_RX_CLKP	-	-	-	-	-	-
U1_143		-	-	-	-	-	-
U1_144	GND	●	●	-	-	-	-
U1_145		-	-	-	-	-	-
U1_146		-	-	-	-	-	-
U1_147		-	-	-	-	-	-
U1_148		-	-	-	-	-	-
U1_149	HDMI0_TX_ON_H	-	-	-	-	-	-
U1_150	GND	●	●	-	-	-	-
U1_151	HDMI_TX0_CEC_M0	-	-	-	-	-	-
U1_152		-	-	-	-	-	-
U1_153	HDMI0_SBDN-HPD	-	-	-	-	-	-
U1_154		-	-	-	-	-	-
U1_155	GND	●	●	-	-	-	-
U1_156	GND	●	●	-	-	-	-
U1_157	MIPI_DPHY0_TX_D0N	-	-	-	-	-	-
U1_158	HDMI0_SBDP	-	-	-	-	-	-
U1_159	MIPI_DPHY0_TX_D0P	-	-	-	-	-	-
U1_160		-	-	-	-	-	-
U1_161	GND	●	●	-	-	-	-
U1_162	GND	●	●	-	-	-	-
U1_163	MIPI_DPHY0_TX_D1N	-	-	-	-	-	-
U1_164		-	-	-	-	-	-
U1_165	MIPI_DPHY0_TX_D1P	-	-	-	-	-	-
U1_166		-	-	-	-	-	-
U1_167	GND	●	●	-	-	-	-
U1_168	GND	●	●	-	-	-	-
U1_169	MIPI_DPHY0_TX_CLKN	-	-	-	-	-	-
U1_170	HDMI0_TX2P	-	-	-	-	-	-
U1_171	MIPI_DPHY0_TX_CLKP	-	-	-	-	-	-
U1_172	HDMI0_TX2N	-	-	-	-	-	-
U1_173	GND	●	●	-	-	-	-
U1_174	GND	●	●	-	-	-	-
U1_175	MIPI_DPHY1_TX_D0N	-	-	-	-	-	-
U1_176	HDMI0_TX1P	-	-	-	-	-	-
U1_177	MIPI_DPHY1_TX_D0P	-	-	-	-	-	-
U1_178	HDMI0_TX1N	-	-	-	-	-	-
U1_179	GND	●	●	-	-	-	-
U1_180	GND	●	●	-	-	-	-
U1_181	MIPI_DPHY1_TX_D1N	-	-	-	-	-	-
U1_182	HDMI0_TX0P	-	-	-	-	-	-
U1_183	MIPI_DPHY1_TX_D1P	-	-	-	-	-	-
U1_184	HDMI0_TX0N	-	-	-	-	-	-
U1_185	GND	●	●	-	-	-	-
U1_186	GND	●	●	-	-	-	-
U1_187	MIPI_DPHY1_TX_CLKN	-	-	-	-	-	-
U1_188	HDMI0_TX3P	-	-	-	-	-	-
U1_189	MIPI_DPHY1_TX_CLKP	-	-	-	-	-	-
U1_190	HDMI0_TX3N	-	-	-	-	-	-
U1_191	GND	●	●	-	-	-	-
U1_192	GND	●	●	-	-	-	-
U1_193	MIPI_DPHY1_TX_D2N	-	-	-	-	-	-
U1_194	MIPI_DPHY1_TX_D3N	-	-	-	-	-	-
U1_195	MIPI_DPHY1_TX_D2P	-	-	-	-	-	-
U1_196	MIPI_DPHY1_TX_D3P	-	-	-	-	-	-
U1_197	GND	●	●	-	-	-	-
U1_198	GND	●	●	-	-	-	-
U1_199	HDMI_TX0_SDA_M0	-	-	-	-	-	-
U1_200	HDMI_TX0_SCL_M0	-	-	-	-	-	-
R8_1	SDMMC_D1	●	◐	-	-	-	-
R8_2	Net-(J4-DAT1)	●	◐	-	-	-	-
U1_201	USB_D+	-	-	-	-	-	-
U1_202	TYPECO_SSTX2P	-	-	-	-	-	-
U1_203	USB_D-	-	-	-	-	-	-
U1_204	TYPECO_SSTX2N	-	-	-	-	-	-
U1_205	GND	●	●	-	-	-	-
U1_206	GND	●	●	-	-	-	-
U1_207	TYPEC0_SBU1	-	-	-	-	-	-
U1_208	TYPECO_SSRX2P	-	-	-	-	-	-
U1_209	TYPEC0_SBU2	-	-	-	-	-	-
U1_210	TYPECO_SSRX2N	-	-	-	-	-	-
U1_211	GND	●	●	-	-	-	-
U1_212	GND	●	●	-	-	-	-
U1_213		-	-	-	-	-	-
U1_214	TYPECO_SSTX1N	-	-	-	-	-	-
U1_215		-	-	-	-	-	-
U1_216	TYPECO_SSTX1P	-	-	-	-	-	-
U1_217	GND	●	●	-	-	-	-
U1_218	GND	●	●	-	-	-	-
U1_219	TYPECO_SSRX1N	-	-	-	-	-	-
U1_220		-	-	-	-	-	-
U1_221	TYPECO_SSRX1P	-	-	-	-	-	-
U1_222	PCIE20_CLKREQ	-	-	-	-	-	-
U1_223	GND	●	●	-	-	-	-
U1_224	PCIE20_PERSTn	-	-	-	-	-	-
U1_225		-	-	-	-	-	-
U1_226	UART_TXD	●	◐	-	-	-	-
U1_227		-	-	-	-	-	-
U1_228	UART_RTS	-	-	-	-	-	-
U1_229	GND	●	●	-	-	-	-
U1_230	UART_RXD	●	◐	-	-	-	-
U1_231		-	-	-	-	-	-
U1_232	GND	●	●	-	-	-	-
U1_233		-	-	-	-	-	-
U1_234		-	-	-	-	-	-
U1_235	GND	●	●	-	-	-	-
U1_236		-	-	-	-	-	-
U1_237		-	-	-	-	-	-
U1_238		-	-	-	-	-	-
U1_239		-	-	-	-	-	-
U1_240	UART_CTS	-	-	-	-	-	-
U1_241	GND	●	●	-	-	-	-
U1_242	GMAC_TXD3	-	-	-	-	-	-
U1_243	PCIE20_WAKEn	-	-	-	-	-	-
U1_244		-	-	-	-	-	-
U1_245	GND	●	●	-	-	-	-
U1_246	GMAC_TXD0	-	-	-	-	-	-
U1_247	GMAC_TXD2	-	-	-	-	-	-
U1_248	GND	●	●	-	-	-	-
U1_249	GMAC_TXD1	-	-	-	-	-	-
U1_250		-	-	-	-	-	-
U1_251	GMAC_TXEN	-	-	-	-	-	-
U1_252		-	-	-	-	-	-
U1_253	GMAC_MDIO	-	-	-	-	-	-
U1_254	GND	●	●	-	-	-	-
U1_255	GND	●	●	-	-	-	-
U1_256	GMAC_RXD1	-	-	-	-	-	-
U1_257	GMAC_MCLK	-	-	-	-	-	-
U1_258	GMAC_RXCLK	-	-	-	-	-	-
U1_259	GMAC_RXDV	-	-	-	-	-	-
U1_260	GMAC_RXD0	-	-	-	-	-	-
U1_261	GMAC_RXD2	-	-	-	-	-	-
U1_262	GMAC_TXCLK	-	-	-	-	-	-
U1_263	GMAC_RXD3	-	-	-	-	-	-
U1_264	GND	●	●	-	-	-	-
U1_265	GND	●	●	-	-	-	-
U1_266		-	-	-	-	-	-
U1_267		-	-	-	-	-	-
U1_268		-	-	-	-	-	-
U1_269	I2S_LRCLK	-	-	-	-	-	-
U1_270	I2S_SDO	-	-	-	-	-	-
U1_271	I2S_SCLK	-	-	-	-	-	-
U1_272		-	-	-	-	-	-
U1_273	I2S_SDI	-	-	-	-	-	-
U1_274	GND	●	●	-	-	-	-
U1_275	GND	●	●	-	-	-	-
U1_276	PCIE20_REFCLKP	-	-	-	-	-	-
U1_277		-	-	-	-	-	-
U1_278	PCIE20_REFCLKN	-	-	-	-	-	-
U1_279		-	-	-	-	-	-
U1_280	GND	●	●	-	-	-	-
U1_281		-	-	-	-	-	-
U1_282	PCIE20_TXP	-	-	-	-	-	-
U1_283		-	-	-	-	-	-
U1_284	PCIE20_TXN	-	-	-	-	-	-
U1_285		-	-	-	-	-	-
U1_286	GND	●	●	-	-	-	-
U1_287	GND	●	●	-	-	-	-
U1_288	PCIE20_RXN	-	-	-	-	-	-
U1_289		-	-	-	-	-	-
U1_290	PCIE20_RXP	-	-	-	-	-	-
U1_291	GMAC_MDC	-	-	-	-	-	-
U1_292	GND	●	●	-	-	-	-
U1_293		-	-	-	-	-	-
U1_294		-	-	-	-	-	-
U1_295		-	-	-	-	-	-
U1_296		-	-	-	-	-	-
U1_297		-	-	-	-	-	-
U1_298		-	-	-	-	-	-
U1_299	GND	●	●	-	-	-	-
U1_300	GND	●	●	-	-	-	-
R4_1	BOOT_SW	-	-	-	-	-	-
R4_2	Net-(C4-Pad2)	-	-	-	-	-	-
J10_43	PCIE20_RXN	-	-	-	-	-	-
J10_44		-	-	-	-	-	-
J10_45	GND	-	●	-	-	-	-
J10_46		-	-	-	-	-	-
J10_47	PCIE20_REFCLKP	-	-	-	-	-	-
J10_48		-	-	-	-	-	-
J10_49	PCIE20_REFCLKN	-	-	-	-	-	-
J10_50		-	-	-	-	-	-
J10_51	GND	-	●	-	-	-	-
J10_52	PCIE20_PERSTn	-	-	-	-	-	-
J10_53	PCIE20_CLKREQ	-	-	-	-	-	-
J10_54		-	-	-	-	-	-
J10_55	PCIE20_WAKEn	-	-	-	-	-	-
J10_56		-	-	-	-	-	-
J10_57	GND	-	●	-	-	-	-
J10_58		-	-	-	-	-	-
J10_59		-	-	-	-	-	-
J10_60		-	-	-	-	-	-
J10_61		-	-	-	-	-	-
J10_62		-	-	-	-	-	-
J10_63	GND	-	●	-	-	-	-
J10_64		-	-	-	-	-	-
J10_65		-	-	-	-	-	-
J10_66		-	-	-	-	-	-
J10_67		-	-	-	-	-	-
J10_68		-	-	-	-	-	-
J10_69	GND	-	●	-	-	-	-
J10_70		-	-	-	-	-	-
J10_71		-	-	-	-	-	-
J10_72	VCC3V3_REG	-	●	-	-	-	-
J10_73		-	-	-	-	-	-
J10_74	VCC3V3_REG	-	●	-	-	-	-
J10_75	GND	-	●	-	-	-	-
U1_1	GND	●	●	-	-	-	-
U1_2	GND	●	●	-	-	-	-
U1_3		-	-	-	-	-	-
U1_4		-	-	-	-	-	-
U1_5		-	-	-	-	-	-
U1_6		-	-	-	-	-	-
U1_7	GND	●	●	-	-	-	-
U1_8	GND	●	●	-	-	-	-
U1_9		-	-	-	-	-	-
U1_10		-	-	-	-	-	-
U1_11		-	-	-	-	-	-
U1_12		-	-	-	-	-	-
U1_13	GND	●	●	-	-	-	-
U1_14	GND	●	●	-	-	-	-
U1_15		-	-	-	-	-	-
U1_16		-	-	-	-	-	-
U1_17		-	-	-	-	-	-
U1_18		-	-	-	-	-	-
U1_19		-	-	-	-	-	-
U1_20		-	-	-	-	-	-
U1_21	GPIO_A4	-	-	-	-	-	-
U1_22	GND	●	●	-	-	-	-
U1_23	GND	●	●	-	-	-	-
U1_24	GPIO1-C0	-	-	-	-	-	-
U1_25	GPIO1_B0	-	-	-	-	-	-
U1_26	GPIO1-C1	-	-	-	-	-	-
U1_27	GPIO1_B1	-	-	-	-	-	-
U1_28	I2C4_SDA_M3	-	-	-	-	-	-
U1_29	GPIO1_B2	-	-	-	-	-	-
U1_30	GPIO1_A3	-	-	-	-	-	-
U1_31	GPIO1_B3	-	-	-	-	-	-
U1_32	GND	●	●	-	-	-	-
U1_33	GND	●	●	-	-	-	-
U1_34	GPIO1_A4	-	-	-	-	-	-
U1_35	GPIO1_D6	-	-	-	-	-	-
U1_36	GPIO1_D7	-	-	-	-	-	-
U1_37	GPIO1_B4	-	-	-	-	-	-
U1_38	GPIO1_A5	-	-	-	-	-	-
U1_39	GPIO1_B5	-	-	-	-	-	-
U1_40	GPIO1_A6	-	-	-	-	-	-
U1_41	GPIO1_B6	-	-	-	-	-	-
U1_42	GND	●	●	-	-	-	-
U1_43	GND	●	●	-	-	-	-
U1_44	GPIO1_A7	-	-	-	-	-	-
U1_45	GPIO1_B7	-	-	-	-	-	-
U1_46	GPIO1-C4	-	-	-	-	-	-
U1_47	GPIO0-C2	-	-	-	-	-	-
U1_48	GPIO1-C6	-	-	-	-	-	-
U1_49	GPIO1-D5	-	-	-	-	-	-
U1_50	GPIO1-D0	-	-	-	-	-	-
U1_51	UART_RX	-	-	-	-	-	-
U1_52	GND	●	●	-	-	-	-
U1_53	GND	●	●	-	-	-	-
U1_54	GPIO1-D1	-	-	-	-	-	-
U1_55	UART_TX	-	-	-	-	-	-
U1_56	GPIO1-D2	-	-	-	-	-	-
U1_57	SDMMC_CLK	●	◐	-	-	-	-
U1_58	GPIO1-D3	-	-	-	-	-	-
U1_59	GND	●	●	-	-	-	-
U1_60	GND	●	●	-	-	-	-
U1_61	SDMMC_D3	●	◐	-	-	-	-
U1_62	SDMMC_CMD	●	◐	-	-	-	-
U1_63	SDMMC_D0	●	◐	-	-	-	-
U1_64		-	-	-	-	-	-
U1_65	GND	●	●	-	-	-	-
U1_66	GND	●	●	-	-	-	-
U1_67	SDMMC_D1	●	◐	-	-	-	-
U1_68	SW_RECOVERY	-	-	-	-	-	-
U1_69	SDMMC_D2	●	◐	-	-	-	-
U1_70		-	-	-	-	-	-
U1_71	GND	●	●	-	-	-	-
U1_72		-	-	-	-	-	-
U1_73		-	-	-	-	-	-
U1_74	GND	●	●	-	-	-	-
U1_75	SDMMC_PWREN	-	-	-	-	-	-
U1_76	SDMMC_DET_L	-	-	-	-	-	-
U1_77	VCC5V0_SYS	-	●	-	-	-	-
U1_78	GPIO_VREF	-	-	-	-	-	-
U1_79	VCC5V0_SYS	-	●	-	-	-	-
U1_80	I2C6_SCL_M3	●	◐	-	-	-	-
U1_81	VCC5V0_SYS	-	●	-	-	-	-
U1_82	I2C6_SDA_M3	●	◐	-	-	-	-
U1_83	VCC5V0_SYS	-	●	-	-	-	-
U1_84	VCC_3V3_S3	●	●	-	-	-	-
U1_85	VCC5V0_SYS	-	●	-	-	-	-
U1_86	VCC_3V3_S3	●	●	-	-	-	-
U1_87	VCC5V0_SYS	-	●	-	-	-	-
U1_88	VCC_1V8_S3	●	●	-	-	-	-
U1_89		-	-	-	-	-	-
U1_90	VCC_1V8_S3	●	●	-	-	-	-
U1_91		-	-	-	-	-	-
U1_92	PMIC_RESET_L	-	-	-	-	-	-
U1_93	BOOT_SW	-	-	-	-	-	-
U1_94	SARADC_VIN3	-	-	-	-	-	-
U1_95	GPIO4_B6	-	-	-	-	-	-
U1_96	SARADC_VIN2	-	-	-	-	-	-
U1_97	GPIO4_A7	-	-	-	-	-	-
U1_98	GND	●	●	-	-	-	-
U1_99	PWRON_L	-	-	-	-	-	-
U1_100	GPIO4_A5	-	-	-	-	-	-
R16_1	GND	●	●	-	-	-	-
R16_2	Net-(C10-Pad2)	-	-	-	-	-	-
C9_1	Net-(C10-Pad2)	-	-	●	◐	-	-
C9_2	Net-(C9-Pad2)	-	-	●	◐	-	-
R31_1	GPIO_VREF	-	-	-	-	-	-
R31_2	VCC_3V3_S3	●	●	-	-	-	-
S3_1	Net-(C5-Pad2)	-	-	-	-	-	-
S3_2	GND	-	●	-	-	-	-
S1_1	Net-(C3-Pad2)	-	-	-	-	-	-
S1_2	GND	-	●	-	-	-	-
C14_1	SSTX2N	-	-	●	◐	-	-
C14_2	TYPECO_SSTX2N	-	-	●	◐	-	-
C4_1	GND	●	●	●	◐	-	-
C4_2	Net-(C4-Pad2)	-	-	●	◐	-	-
C1_1	TYPECO_SSTX1N	-	-	●	◐	-	-
C1_2	SSTX1N	-	-	●	◐	-	-
J8_1	VCC3V3_REG	-	●	-	-	-	-
J8_2	I2C4_SDA_M3	-	-	-	-	-	-
J8_3	GPIO1_A3	-	-	-	-	-	-
J8_4	GND	-	●	-	-	-	-
J8_5	GPIO1_B7	-	-	-	-	-	-
J8_6	GPIO1_B6	-	-	-	-	-	-
J8_7	GND	-	●	-	-	-	-
J8_8	MIPI_CSI0_RX_D3P	-	-	-	-	-	-
J8_9	MIPI_CSI0_RX_D3N	-	-	-	-	-	-
J8_10	GND	-	●	-	-	-	-
J8_11	MIPI_CSI0_RX_D2P	-	-	-	-	-	-
J8_12	MIPI_CSI0_RX_D2N	-	-	-	-	-	-
J8_13	GND	-	●	-	-	-	-
J8_14	MIPI_CSI0_CLK0P	-	-	-	-	-	-
J8_15	MIPI_CSI0_CLK0N	-	-	-	-	-	-
J8_16	GND	-	●	-	-	-	-
J8_17	MIPI_CSI0_RX_D1P	-	-	-	-	-	-
J8_18	MIPI_CSI0_RX_D1N	-	-	-	-	-	-
J8_19	GND	-	●	-	-	-	-
J8_20	MIPI_CSI0_RX_D0P	-	-	-	-	-	-
J8_21	MIPI_CSI0_RX_D0N	-	-	-	-	-	-
J8_22	GND	-	●	-	-	-	-
C30_1	VCC3V3_REG	-	●	●	◐	-	-
C30_2	GND	-	●	●	◐	-	-
R5_1	PMIC_RESET_L	-	-	-	-	-	-
R5_2	Net-(C5-Pad2)	-	-	-	-	-	-
R10_1	SDMMC_D3	●	◐	-	-	-	-
R10_2	Net-(J4-CD/DAT3)	●	◐	-	-	-	-
J5_1	GND	-	●	-	-	-	-
J5_2	Net-(C9-Pad2)	-	-	-	-	-	-
J5_3	Net-(C8-Pad2)	-	-	-	-	-	-
J5_4		-	-	-	-	-	-
J5_5		-	-	-	-	-	-
J5_6		-	-	-	-	-	-
S2_1	Net-(C4-Pad2)	-	-	-	-	-	-
S2_2	GND	-	●	-	-	-	-
R51_1	GND	-	●	-	-	-	-
R51_2	R49CC1	-	-	-	-	-	-
J10_1	GND	-	●	-	-	-	-
J10_2	VCC3V3_REG	-	●	-	-	-	-
J10_3	USB_D+	-	-	-	-	-	-
J10_4	VCC3V3_REG	-	●	-	-	-	-
J10_5	USB_D-	-	-	-	-	-	-
J10_6		-	-	-	-	-	-
J10_7	GND	-	●	-	-	-	-
J10_8	I2S_SCLK	-	-	-	-	-	-
J10_9	I2S_LRCLK	-	-	-	-	-	-
J10_10		-	-	-	-	-	-
J10_11		-	-	-	-	-	-
J10_12	I2S_SDI	-	-	-	-	-	-
J10_13		-	-	-	-	-	-
J10_14	I2S_SDO	-	-	-	-	-	-
J10_15		-	-	-	-	-	-
J10_16		-	-	-	-	-	-
J10_17		-	-	-	-	-	-
J10_18	GND	-	●	-	-	-	-
J10_19		-	-	-	-	-	-
J10_20		-	-	-	-	-	-
J10_21		-	-	-	-	-	-
J10_22	UART_RXD	●	◐	-	-	-	-
J10_23		-	-	-	-	-	-
J10_32	UART_TXD	●	◐	-	-	-	-
J10_33	GND	-	●	-	-	-	-
J10_34	UART_CTS	-	-	-	-	-	-
J10_35	PCIE20_TXP	-	-	-	-	-	-
J10_36	UART_RTS	-	-	-	-	-	-
J10_37	PCIE20_TXN	-	-	-	-	-	-
J10_38		-	-	-	-	-	-
J10_39	GND	-	●	-	-	-	-
J10_40		-	-	-	-	-	-
J10_41	PCIE20_RXP	-	-	-	-	-	-
J10_42		-	-	-	-	-	-
R46_1	VCC3V3_REG	●	●	-	-	-	-
R46_2	I2C4_SDA_M3	-	-	-	-	-	-
C3_1	GND	●	●	●	◐	-	-
C3_2	Net-(C3-Pad2)	-	-	●	◐	-	-
R40_1	0_LED1	-	-	-	-	-	-
R40_2	Net-(J1-LEDG2_A)	-	-	-	-	-	-
Y1_1	CKXTAL1	-	-	-	-	-	-
Y1_2		-	-	-	-	-	-
Y1_3	CKXTAL2	-	-	-	-	-	-
Y1_4		-	-	-	-	-	-
R19_1	Net-(U5-FB1)	-	-	-	-	-	-
R19_2	GND	●	●	-	-	-	-
L4_1	VDD_2P5	●	●	-	-	-	-
L4_2	Net-(U5-SW2)	-	-	-	-	-	-
R20_1	Net-(U5-FB2)	-	-	-	-	-	-
R20_2	GND	●	●	-	-	-	-
C20_1	Net-(U5-FB2)	-	-	●	◐	-	-
C20_2	VDD_2P5	●	●	●	◐	-	-
R22_1	VDD_2P5	●	●	-	-	-	-
R22_2	Net-(U5-FB2)	-	-	-	-	-	-
C37_1	GND	-	●	●	◐	-	-
C37_2	VCC_1V8_S3	-	●	●	◐	-	-
C43_1	GND	-	●	●	◐	-	-
C43_2	VDD_2P5	-	●	●	◐	-	-
C28_1	CKXTAL2	-	-	-	-	-	-
C28_2	GND	●	●	-	-	-	-
U5_1	Net-(U5-FB2)	-	-	-	-	-	-
U5_2	GND	●	●	-	-	-	-
U5_3	Net-(U5-FB1)	-	-	-	-	-	-
U5_4	Net-(U5-PG1)	-	-	-	-	-	-
U5_5	GND	●	●	-	-	-	-
U5_6	Net-(U5-SW1)	-	-	-	-	-	-
U5_7	VCC5V0_SYS	-	●	-	-	-	-
U5_8	VCC5V0_SYS	-	●	-	-	-	-
U5_9	GND	●	●	-	-	-	-
U5_10	VCC5V0_SYS	-	●	-	-	-	-
U5_11	VCC5V0_SYS	-	●	-	-	-	-
U5_12	Net-(U5-SW2)	-	-	-	-	-	-
U5_13	Net-(U5-PG2)	-	-	-	-	-	-
U5_14	Net-(U5-COMP/FSET)	-	-	-	-	-	-
R56_1	Net-(U2-JTAG_CLK)	-	-	-	-	-	-
R56_2	GND	●	●	-	-	-	-
C41_1	GND	-	●	●	◐	-	-
C41_2	VDD_2P5	-	●	●	◐	-	-
C36_1	GND	-	●	●	◐	-	-
C36_2	VCC_1V8_S3	-	●	●	◐	-	-
C13_1	GND	●	●	-	-	-	-
C13_2	Net-(U3-NR/SS)	-	-	-	-	-	-
C42_1	GND	-	●	●	◐	-	-
C42_2	VDD_2P5	-	●	●	◐	-	-
R12_1	GND	●	●	-	-	-	-
R12_2	Net-(U3-FB)	-	-	-	-	-	-
C35_1	GND	-	●	●	◐	-	-
C35_2	VCC_1V8_S3	-	●	●	◐	-	-
U3_1	GND	●	●	-	-	-	-
U3_2	Net-(U3-NR/SS)	-	-	-	-	-	-
U3_3	Net-(U3-FB)	-	-	-	-	-	-
U3_4	VCC3V3_REG	●	●	-	-	-	-
U3_5	Net-(U3-PG)	-	-	-	-	-	-
U3_6	Net-(U3-S-CONF)	-	-	-	-	-	-
U3_7	VCC5V0_SYS	-	●	-	-	-	-
U3_8	VCC5V0_SYS	-	●	-	-	-	-
U3_9	GND	●	●	-	-	-	-
U3_10	Net-(C26-Pad1)	-	-	-	-	-	-
U3_11	GND	●	●	-	-	-	-
U3_12	VCC5V0_SYS	-	●	-	-	-	-
U3_13	Net-(C26-Pad1)	-	-	-	-	-	-
U3_14	Net-(U3-BOOT)	-	-	-	-	-	-
R53_1	GMAC_TXCLK	-	-	-	-	-	-
R53_2	Net-(U2-GTX_CLK)	-	-	-	-	-	-
R23_1	Net-(U5-COMP/FSET)	-	-	-	-	-	-
R23_2	GND	●	●	-	-	-	-
C31_1	VCC5V0_SYS	-	●	●	◐	-	-
C31_2	GND	-	●	●	◐	-	-
C23_1	GND	-	●	●	◐	-	-
C23_2	VCC_1V8_S3	-	●	●	◐	-	-
R54_1	GMAC_RXCLK	-	-	-	-	-	-
R54_2	RES_RXCLK	-	-	-	-	-	-
R61_1	GND	●	●	-	-	-	-
R61_2	GMAC_RXDV	-	-	-	-	-	-
R45_1	GND	●	●	-	-	-	-
R45_2	Net-(U2-RBIAS)	-	-	-	-	-	-
R24_1	VCC_1V8_S3	●	●	-	-	-	-
R24_2	GMAC_RXD0	-	-	-	-	-	-
R60_1	GND	●	●	-	-	-	-
R60_2	GMAC_RXD0	-	-	-	-	-	-
C50_1	GND	-	●	●	◐	-	-
C50_2	P06_VDD1P0	-	●	●	◐	-	-
R18_1	VDD_2P5	●	●	-	-	-	-
R18_2	Net-(U5-PG2)	-	-	-	-	-	-
C45_1	GND	-	●	●	◐	-	-
C45_2	VDD_2P5	-	●	●	◐	-	-
C29_1	GND	●	●	-	-	-	-
C29_2	CKXTAL1	-	-	-	-	-	-
C47_1	GND	-	●	●	◐	-	-
C47_2	P06_VDD1P0	-	●	●	◐	-	-
R1_1	GND	●	●	-	-	-	-
R1_2	Net-(U3-S-CONF)	-	-	-	-	-	-
C39_1	GND	-	●	-	-	-	-
C39_2	P06_VDD1P0	-	●	-	-	-	-
C34_1	GND	-	●	●	◐	-	-
C34_2	VCC_1V8_S3	-	●	●	◐	-	-
C11_1	GND	-	●	-	-	-	-
C11_2	VCC5V0_SYS	-	●	-	-	-	-
L3_1	P06_VDD1P0	●	●	-	-	-	-
L3_2	Net-(U5-SW1)	-	-	-	-	-	-
R57_1	Net-(U2-JTAG_TMS)	-	-	-	-	-	-
R57_2	VCC_1V8_S3	●	●	-	-	-	-
R17_1	Net-(U3-FB)	-	-	●	◐	-	-
R17_2	VCC3V3_REG	●	●	●	◐	-	-
C55_1	GND	-	●	●	◐	-	-
C55_2	P06_VDD1P0	-	●	●	◐	-	-
C33_1	GND	-	●	●	◐	-	-
C33_2	Net-(J1-TRCT1)	-	-	●	◐	-	-
C12_1	GND	-	●	-	-	-	-
C12_2	VCC3V3_REG	-	●	-	-	-	-
C24_1	GND	-	●	●	◐	-	-
C24_2	VCC_1V8_S3	-	●	●	◐	-	-
C54_1	GND	-	●	●	◐	-	-
C54_2	P06_VDD1P0	-	●	●	◐	-	-
R59_1	GMAC_MDIO	-	-	-	-	-	-
R59_2	VCC_1V8_S3	●	●	-	-	-	-
C48_1	GND	-	●	●	◐	-	-
C48_2	P06_VDD1P0	-	●	●	◐	-	-
C51_1	GND	-	●	●	◐	-	-
C51_2	P06_VDD1P0	-	●	●	◐	-	-
C26_1	Net-(C26-Pad1)	-	-	●	◐	-	-
C26_2	Net-(U3-BOOT)	-	-	●	◐	-	-
R55_1	Net-(U2-JTAG_TDI)	-	-	-	-	-	-
R55_2	VCC_1V8_S3	●	●	-	-	-	-
C27_1	GND	-	●	●	◐	-	-
C27_2	VCC5V0_SYS	-	●	●	◐	-	-
C25_1	GND	-	●	●	◐	-	-
C25_2	VCC_1V8_S3	-	●	●	◐	-	-
C52_1	GND	-	●	●	◐	-	-
C52_2	P06_VDD1P0	-	●	●	◐	-	-
U2_1	MDI0+	-	-	-	-	-	-
U2_2	MDI0-	-	-	-	-	-	-
U2_3	VDD_2P5	-	●	-	-	-	-
U2_4	MDI1+	-	-	-	-	-	-
U2_5	MDI1-	-	-	-	-	-	-
U2_6	P06_VDD1P0	-	●	-	-	-	-
U2_7	MDI2+	-	-	-	-	-	-
U2_8	MDI2-	-	-	-	-	-	-
U2_9	VDD_2P5	-	●	-	-	-	-
U2_10	MDI3+	-	-	-	-	-	-
U2_11	MDI3-	-	-	-	-	-	-
U2_12	Net-(U2-RBIAS)	-	-	-	-	-	-
U2_13		-	-	-	-	-	-
U2_14	CKXTAL2	-	-	-	-	-	-
U2_15	CKXTAL1	-	-	-	-	-	-
U2_16	GMAC_MDC	-	-	-	-	-	-
U2_17	GMAC_MDIO	-	-	-	-	-	-
U2_18	clkout_res	-	-	-	-	-	-
U2_19	VCC_1V8_S3	●	●	-	-	-	-
U2_20	Net-(U2-JTAG_CLK)	-	-	-	-	-	-
U2_21		-	-	-	-	-	-
U2_22	Net-(U2-JTAG_TMS)	-	-	-	-	-	-
U2_23	Net-(U2-JTAG_TDI)	-	-	-	-	-	-
U2_24	P06_VDD1P0	-	●	-	-	-	-
U2_25	GMAC_TXD3	-	-	-	-	-	-
U2_26	GMAC_TXD2	-	-	-	-	-	-
U2_27	GMAC_TXD1	-	-	-	-	-	-
U2_28	GMAC_TXD0	-	-	-	-	-	-
U2_29	Net-(U2-GTX_CLK)	-	-	-	-	-	-
U2_30	VCC_1V8_S3	●	●	-	-	-	-
U2_31	P06_VDD1P0	-	●	-	-	-	-
U2_32	RES_RXCLK	-	-	-	-	-	-
U2_33	GMAC_RXD0	-	-	-	-	-	-
U2_34	GMAC_RXD1	-	-	-	-	-	-
U2_35	GMAC_RXD2	-	-	-	-	-	-
U2_36	GMAC_RXD3	-	-	-	-	-	-
U2_37	GMAC_TXEN	-	-	-	-	-	-
U2_38	GMAC_RXDV	-	-	-	-	-	-
U2_39		-	-	-	-	-	-
U2_40		-	-	-	-	-	-
U2_41	VCC_1V8_S3	●	●	-	-	-	-
U2_42	P06_VDD1P0	-	●	-	-	-	-
U2_43	GPIO1-C1	-	-	-	-	-	-
U2_44	Net-(U2-INT/PWDN)	-	-	-	-	-	-
U2_45		-	-	-	-	-	-
U2_46	0_LED1	-	-	-	-	-	-
U2_47	0_LED2	-	-	-	-	-	-
U2_48		-	-	-	-	-	-
U2_49	GND	●	●	-	-	-	-
C40_1	GND	-	●	●	◐	-	-
C40_2	VDD_2P5	-	●	●	◐	-	-
R41_1	0_LED2	-	-	-	-	-	-
R41_2	Net-(J1-LEDG1_A)	-	-	-	-	-	-
C22_1	GND	-	●	●	◐	-	-
C22_2	VCC_1V8_S3	-	●	●	◐	-	-
R21_1	P06_VDD1P0	●	●	-	-	-	-
R21_2	Net-(U5-FB1)	-	-	-	-	-	-
C19_1	Net-(U5-FB1)	-	-	●	◐	-	-
C19_2	P06_VDD1P0	●	●	●	◐	-	-
R25_1	VCC_1V8_S3	●	●	-	-	-	-
R25_2	GMAC_RXDV	-	-	-	-	-	-
C49_1	GND	-	●	●	◐	-	-
C49_2	P06_VDD1P0	-	●	●	◐	-	-
C32_1	VCC5V0_SYS	-	●	●	◐	-	-
C32_2	GND	-	●	●	◐	-	-
R7_1	P06_VDD1P0	●	●	-	-	-	-
R7_2	Net-(U5-PG1)	-	-	-	-	-	-
C44_1	GND	-	●	●	◐	-	-
C44_2	VDD_2P5	-	●	●	◐	-	-
R58_1	Net-(U2-INT/PWDN)	-	-	-	-	-	-
R58_2	VCC_1V8_S3	●	●	-	-	-	-
R49_1	clkout_res	-	-	-	-	-	-
R49_2	GMAC_MCLK	-	-	-	-	-	-
J1_1	Net-(J1-TRCT1)	-	-	-	-	-	-
J1_2	MDI2-	-	-	-	-	-	-
J1_3	MDI2+	-	-	-	-	-	-
J1_4	MDI1-	-	-	-	-	-	-
J1_5	MDI1+	-	-	-	-	-	-
J1_6	Net-(J1-TRCT1)	-	-	-	-	-	-
J1_7	Net-(J1-TRCT1)	-	-	-	-	-	-
J1_8	MDI3-	-	-	-	-	-	-
J1_9	MDI3+	-	-	-	-	-	-
J1_10	MDI0-	-	-	-	-	-	-
J1_11	MDI0+	-	-	-	-	-	-
J1_12	Net-(J1-TRCT1)	-	-	-	-	-	-
J1_13	Net-(J1-LEDG1_A)	-	-	-	-	-	-
J1_14	GND	-	●	-	-	-	-
J1_15	Net-(J1-LEDG2_A)	-	-	-	-	-	-
J1_16	GND	-	●	-	-	-	-
C53_1	GND	-	●	●	◐	-	-
C53_2	P06_VDD1P0	-	●	●	◐	-	-
R52_1	GMAC_MCLK	-	-	-	-	-	-
R52_2	GND	●	●	-	-	-	-
C21_1	GND	-	●	●	◐	-	-
C21_2	VDD_2P5	-	●	●	◐	-	-
C38_1	GND	-	●	●	◐	-	-
C38_2	VCC5V0_SYS	-	●	●	◐	-	-
L2_1	Net-(C26-Pad1)	-	-	-	-	-	-
L2_2	VCC3V3_REG	●	●	-	-	-	-
C46_1	GND	-	●	●	◐	-	-
C46_2	P06_VDD1P0	-	●	●	◐	-	-
R2_1	Net-(U3-PG)	-	-	-	-	-	-
R2_2	VCC3V3_REG	●	●	-	-	-	-

14.10 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.10.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	42.1%	0.0%	0.0%	6.2%	0.0%	20.0%	21.5%	0.0%
Optical Inspection (AOI)	41.2%	0.9%	21.1%	0.0%	20.6%	6.3%	6.3%	6.3%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
Combined	65.8%	0.9%	21.1%	6.2%	20.6%	21.5%	27.2%	6.3%

14.10.2 PCB Device/Pin Count

Devices (PCOLA): 114
Pins (SOQ): 749

14.10.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	22917 / 100,000	22.9%
SOQ	18336 / 100,000	18.3%
Combined	20626 / 100,000	20.6%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	9671 / 100,000	13818 / 100,000
Optical/X-ray Inspection	16754 / 100,000	6275 / 100,000
Combined (max)	22917 / 100,000	18336 / 100,000

14.10.4 PCOLA (114 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
70%	R17	CRCW060315K4FKEA / RESC1508X50N	Resistor	●	●	●	—	◐	AOI, Powered_Off
40%	C7	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C41	GCM155R71H103KA55D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C4	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C8	CL31A476MQHNNNE / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI
40%	C15	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI
40%	C1	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI
40%	C35	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C6	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C30	MA0805XF106K160 / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C50	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C2	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI
40%	C5	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C34	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C14	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI
40%	C47	GCM155R71H103KA55D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C36	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C10	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C20	C0402C100J3GACTU / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C46	GRM155R60J106ME15D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C42	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C45	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C37	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C43	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C9	CL31A476MQHNNNE / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI
40%	C3	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C23	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C31	MA0805XF106K160 / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C55	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C33	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C24	GCM155R71H103KA55D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C54	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C48	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C51	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C26	GRM033R61E104KE14D / CAPC0603X33N	Capacitor	●	○	◐	—	◐	AOI
40%	C27	CL31B475KOHNFNE / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C25	GRM155R60J106ME15D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C52	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C40	GRM155R60J106ME15D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C22	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C19	C0402C100J3GACTU / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C49	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C32	MA0805XF106K160 / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C44	CL05A105KO5NNNC / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C53	GRM155R71H104KE14D / CAPC10555_55N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C21	CL31A476MQHNNNE / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C38	CL31B475KOHNFNE / CAPC340180_88N_KEM	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
20%	U1	Hirose DF40C-100DS-0.4V / OPi_CM5 *	IC	◐	○	○	◐	○	LSSI, Powered_Off
10%	R46	RC1206FR-072K2L / STA_RMCF1206_STP *	Resistor	◐	○	○	—	○	Powered_Off
10%	R19	RC0402FR-1351KL / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R20	RC0402FR-1351KL / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R22	AC0402FR-07162KL / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	C28	06031A320FAT2A / CAP_06031A0R6BAT2A *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U5	XPS62442QWRQRRQ1 / VQFN14_RQR_TEX *	IC	◐	○	○	○	○	Powered_Off
10%	R56	RC0402JR-074K7L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	C13	CGA3E2X5R1A474K080AA / CAP_1608_TDK *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R12	CRCW04024K87FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	L4	DFE201610E-R47M=P2 / IND_DFE201610E_MUR *	Inductor	◐	○	○	—	○	Powered_Off
10%	U3	TPS62914QRPYRQ1 / VQFN-HR14_RPY_TEX *	IC	◐	○	○	○	○	Powered_Off
10%	R23	RC0402FR-077K87L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R61	RC0402FR-072K49L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R45	RC0402FR-0711KL / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R24	RMCF0402FT10K0 / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R60	RC0402FR-072K49L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R18	CRCW0402100KFKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	C29	06031A320FAT2A / CAP_06031A0R6BAT2A *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R1	CRCW040218K2FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	C39	MSASL219LB5226MTNA01 / CAP_MSAS21-9_TAY *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C11	CGA2B2X7R1H222K050BA / RES_CRCW_0402 *	Capacitor	◐	○	○	—	○	Powered_Off
10%	L3	DFE201610E-R47M=P2 / IND_DFE201610E_MUR *	Inductor	◐	○	○	—	○	Powered_Off
10%	R57	RC0402JR-074K7L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R47	RC1206FR-072K2L / STA_RMCF1206_STP *	Resistor	◐	○	○	—	○	Powered_Off
10%	R11	CRCW040222R0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	C12	MSASL219LB5226MTNA01 / CAP_MSAS21-9_TAY *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R6	CRCW040222R0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	J4	1040310811 / 104031-0811_MOL *	Connector	◐	○	○	—	○	Powered_Off
10%	R59	ERJ-2RKF1501X / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R14	RNCP1206FTD100R / STA_RNCP1206_STP *	Resistor	◐	○	○	—	○	Powered_Off
10%	R50	RMCF0603FT5K10 / CAP_06031A0R6BAT2A *	Resistor	◐	○	○	—	○	Powered_Off
10%	J9	FH12-15S-0.5SH55 / CONN_FH12-15S-0.5SH55_HIR *	Connector	◐	○	○	—	○	Powered_Off
10%	R55	RC0402JR-074K7L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	J2	USB4056-03-A_REVA2 / GCT_USB4056-03-A_REVA2 *	Connector	◐	○	○	—	○	Powered_Off
10%	R8	CRCW040222R0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	J10	SM3ZS067U410AER1000 / CONN_SM3ZS067U410AER1000_JAE *	Connector	◐	○	○	—	○	Powered_Off
10%	U2	DP83867IRRGZR / RGZ0048B *	IC	◐	○	○	○	○	Powered_Off
10%	R16	RNCP1206FTD100R / STA_RNCP1206_STP *	Resistor	◐	○	○	—	○	Powered_Off
10%	R31	RNCP1206FTD100R / STA_RNCP1206_STP *	Resistor	◐	○	○	—	○	Powered_Off
10%	R21	CRCW040234K0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	S3	SWT0010-015016SSA_REVA / SW_SWT0010-015016SSA_REVA *	Switch	◐	○	○	○	○	Powered_Off
10%	R25	CRCW04025K76FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	S1	SWT0010-015016SSA_REVA / SW_SWT0010-015016SSA_REVA *	Switch	◐	○	○	○	○	Powered_Off
10%	R9	CRCW040222R0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R7	CRCW0402100KFKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	J8	FH12-22S-0.5SH55 / CONN_FH12-22S-0.5SH55_HIR *	Connector	◐	○	○	—	○	Powered_Off
10%	R58	RC0402FR-072K49L / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	J1	L834-1G1T-S7 / CONN16_L834-1G1T-S7_BEL *	Connector	◐	○	○	—	○	Powered_Off
10%	R10	CRCW040222R0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
10%	R52	ERA-2AEB121X / R_01005_0402Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	J5	SJ3-35063BG / SAMESKY_SJ3-35063BG *	Connector	◐	○	○	—	○	Powered_Off
10%	S2	SWT0010-015016SSA_REVA / SW_SWT0010-015016SSA_REVA *	Switch	◐	○	○	○	○	Powered_Off
10%	L2	74439324010 / WE-XHMI_4030 *	Inductor	◐	○	○	—	○	Powered_Off
10%	R51	RMCF0603FT5K10 / CAP_06031A0R6BAT2A *	Resistor	◐	○	○	—	○	Powered_Off
10%	R2	CRCW040210K0FKED / RES_CRCW_0402 *	Resistor	◐	○	○	—	○	Powered_Off
0%	R15	RNCP1206FTD200R / STA_RNCP1206_STP *	Resistor	○	○	○	—	○
0%	R5	RNCP1206FTD200R / STA_RNCP1206_STP *	Resistor	○	○	○	—	○
0%	R49	ERJ-2GEJ2R2X / CAP_06031A0R6BAT2A *	Resistor	○	○	○	—	○
0%	R41	RC0402FR-07470RL / RES_CRCW_0402 *	Resistor	○	○	○	—	○
0%	R53	ERJ-2GEJ2R2X / RES_CRCW_0402 *	Resistor	○	○	○	—	○
0%	R4	RNCP1206FTD100R / STA_RNCP1206_STP *	Resistor	○	○	○	—	○
0%	R3	RNCP1206FTD100R / STA_RNCP1206_STP *	Resistor	○	○	○	—	○
0%	Y1	H130B-25.000-20-F-3030-TR / H130B2500020F3030TR *	Other	○	○	○	○	○
0%	R13	RNCP1206FTD200R / STA_RNCP1206_STP *	Resistor	○	○	○	—	○
0%	R40	RC0402FR-07470RL / RES_CRCW_0402 *	Resistor	○	○	○	—	○
0%	R54	ERJ-2GEJ2R2X / RES_CRCW_0402 *	Resistor	○	○	○	—	○

14.10.5 SOQ (749 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
67%	C7_1	GND	◐	●	◐
67%	C20_2	VDD_2P5	◐	●	◐
67%	C10_1	GND	◐	●	◐
67%	C3_1	GND	◐	●	◐
67%	C5_1	GND	◐	●	◐
67%	C4_1	GND	◐	●	◐
67%	C19_2	P06_VDD1P0	◐	●	◐
67%	R17_2	VCC3V3_REG	◐	●	◐
50%	C7_2	Net-(C7-Pad2)	◐	◐	◐
50%	R47_1	VCC3V3_REG	◐	●	○
50%	C3_2	Net-(C3-Pad2)	◐	◐	◐
50%	R11_1	SDMMC_CMD	◐	●	○
50%	R11_2	Net-(J4-CMD)	◐	●	○
50%	C8_1	Net-(C7-Pad2)	◐	◐	◐
50%	C8_2	Net-(C8-Pad2)	◐	◐	◐
50%	C15_1	SSTX2P	◐	◐	◐
50%	C15_2	TYPECO_SSTX2P	◐	◐	◐
50%	R6_1	SDMMC_D0	◐	●	○
50%	R6_2	Net-(J4-DAT0)	◐	●	○
50%	J4_1	Net-(J4-DAT2)	◐	●	○
50%	J4_2	Net-(J4-CD/DAT3)	◐	●	○
50%	J4_3	Net-(J4-CMD)	◐	●	○
50%	R19_2	GND	◐	●	○
50%	J4_5	SDMMC_CLK	◐	●	○
50%	L4_1	VDD_2P5	◐	●	○
50%	J4_7	Net-(J4-DAT0)	◐	●	○
50%	J4_8	Net-(J4-DAT1)	◐	●	○
50%	R20_2	GND	◐	●	○
50%	C20_1	Net-(U5-FB2)	◐	◐	◐
50%	C6_1	GND	◐	◐	◐
50%	C6_2	VCC_3V3_S3	◐	◐	◐
50%	R14_1	GND	◐	●	○
50%	R22_1	VDD_2P5	◐	●	○
50%	C37_1	GND	◐	◐	◐
50%	C37_2	VCC_1V8_S3	◐	◐	◐
50%	U1_264	GND	◐	●	○
50%	U1_265	GND	◐	●	○
50%	C2_1	TYPECO_SSTX1P	◐	◐	◐
50%	C2_2	SSTX1P	◐	◐	◐
50%	C5_2	Net-(C5-Pad2)	◐	◐	◐
50%	C43_1	GND	◐	◐	◐
50%	C43_2	VDD_2P5	◐	◐	◐
50%	R9_1	SDMMC_D2	◐	●	○
50%	R9_2	Net-(J4-DAT2)	◐	●	○
50%	C28_2	GND	◐	●	○
50%	U5_2	GND	◐	●	○
50%	U5_5	GND	◐	●	○
50%	U5_9	GND	◐	●	○
50%	R56_2	GND	◐	●	○
50%	C41_1	GND	◐	◐	◐
50%	U1_274	GND	◐	●	○
50%	U1_275	GND	◐	●	○
50%	C41_2	VDD_2P5	◐	◐	◐
50%	C36_1	GND	◐	◐	◐
50%	C36_2	VCC_1V8_S3	◐	◐	◐
50%	C13_1	GND	◐	●	○
50%	U1_280	GND	◐	●	○
50%	C42_1	GND	◐	◐	◐
50%	J9_13	I2C6_SCL_M3	◐	●	○
50%	J9_14	I2C6_SDA_M3	◐	●	○
50%	C42_2	VDD_2P5	◐	◐	◐
50%	C10_2	Net-(C10-Pad2)	◐	◐	◐
50%	R12_1	GND	◐	●	○
50%	C35_1	GND	◐	◐	◐
50%	C35_2	VCC_1V8_S3	◐	◐	◐
50%	U1_286	GND	◐	●	○
50%	U1_287	GND	◐	●	○
50%	U3_1	GND	◐	●	○
50%	U3_4	VCC3V3_REG	◐	●	○
50%	U3_9	GND	◐	●	○
50%	U3_11	GND	◐	●	○
50%	U1_292	GND	◐	●	○
50%	R23_2	GND	◐	●	○
50%	C31_1	VCC5V0_SYS	◐	◐	◐
50%	U1_53	GND	◐	●	○
50%	C31_2	GND	◐	◐	◐
50%	C23_1	GND	◐	◐	◐
50%	C23_2	VCC_1V8_S3	◐	◐	◐
50%	U1_299	GND	◐	●	○
50%	U1_300	GND	◐	●	○
50%	R61_1	GND	◐	●	○
50%	R45_1	GND	◐	●	○
50%	R24_1	VCC_1V8_S3	◐	●	○
50%	R60_1	GND	◐	●	○
50%	C50_1	GND	◐	◐	◐
50%	C50_2	P06_VDD1P0	◐	◐	◐
50%	R18_1	VDD_2P5	◐	●	○
50%	C45_1	GND	◐	◐	◐
50%	C45_2	VDD_2P5	◐	◐	◐
50%	C29_1	GND	◐	●	○
50%	C47_1	GND	◐	◐	◐
50%	C47_2	P06_VDD1P0	◐	◐	◐
50%	R1_1	GND	◐	●	○
50%	C34_1	GND	◐	◐	◐
50%	C34_2	VCC_1V8_S3	◐	◐	◐
50%	L3_1	P06_VDD1P0	◐	●	○
50%	U1_107	GND	◐	●	○
50%	U1_108	GND	◐	●	○
50%	R8_2	Net-(J4-DAT1)	◐	●	○
50%	R57_2	VCC_1V8_S3	◐	●	○
50%	R17_1	Net-(U3-FB)	◐	◐	◐
50%	C55_1	GND	◐	◐	◐
50%	U1_113	GND	◐	●	○
50%	U1_114	GND	◐	●	○
50%	C55_2	P06_VDD1P0	◐	◐	◐
50%	C33_1	GND	◐	◐	◐
50%	C33_2	Net-(J1-TRCT1)	◐	◐	◐
50%	C24_1	GND	◐	◐	◐
50%	U1_119	GND	◐	●	○
50%	U1_120	GND	◐	●	○
50%	C24_2	VCC_1V8_S3	◐	◐	◐
50%	C54_1	GND	◐	◐	◐
50%	C54_2	P06_VDD1P0	◐	◐	◐
50%	R59_2	VCC_1V8_S3	◐	●	○
50%	U1_125	GND	◐	●	○
50%	U1_126	GND	◐	●	○
50%	C48_1	GND	◐	◐	◐
50%	C48_2	P06_VDD1P0	◐	◐	◐
50%	C51_1	GND	◐	◐	◐
50%	C51_2	P06_VDD1P0	◐	◐	◐
50%	U1_131	GND	◐	●	○
50%	U1_132	GND	◐	●	○
50%	C26_1	Net-(C26-Pad1)	◐	◐	◐
50%	C26_2	Net-(U3-BOOT)	◐	◐	◐
50%	R55_2	VCC_1V8_S3	◐	●	○
50%	C27_1	GND	◐	◐	◐
50%	U1_137	GND	◐	●	○
50%	U1_138	GND	◐	●	○
50%	U1_1	GND	◐	●	○
50%	U1_2	GND	◐	●	○
50%	C27_2	VCC5V0_SYS	◐	◐	◐
50%	C25_1	GND	◐	◐	◐
50%	C25_2	VCC_1V8_S3	◐	◐	◐
50%	U1_144	GND	◐	●	○
50%	C52_1	GND	◐	◐	◐
50%	U1_7	GND	◐	●	○
50%	U1_8	GND	◐	●	○
50%	C52_2	P06_VDD1P0	◐	◐	◐
50%	U2_19	VCC_1V8_S3	◐	●	○
50%	U1_150	GND	◐	●	○
50%	U2_30	VCC_1V8_S3	◐	●	○
50%	U2_41	VCC_1V8_S3	◐	●	○
50%	U1_13	GND	◐	●	○
50%	U1_14	GND	◐	●	○
50%	U1_155	GND	◐	●	○
50%	U1_156	GND	◐	●	○
50%	U2_49	GND	◐	●	○
50%	C40_1	GND	◐	◐	◐
50%	C40_2	VDD_2P5	◐	◐	◐
50%	C22_1	GND	◐	◐	◐
50%	U1_161	GND	◐	●	○
50%	U1_162	GND	◐	●	○
50%	C22_2	VCC_1V8_S3	◐	◐	◐
50%	R21_1	P06_VDD1P0	◐	●	○
50%	C19_1	Net-(U5-FB1)	◐	◐	◐
50%	U1_22	GND	◐	●	○
50%	U1_167	GND	◐	●	○
50%	U1_168	GND	◐	●	○
50%	U1_23	GND	◐	●	○
50%	R25_1	VCC_1V8_S3	◐	●	○
50%	C49_1	GND	◐	◐	◐
50%	C49_2	P06_VDD1P0	◐	◐	◐
50%	U1_173	GND	◐	●	○
50%	U1_174	GND	◐	●	○
50%	C32_1	VCC5V0_SYS	◐	◐	◐
50%	C32_2	GND	◐	◐	◐
50%	R7_1	P06_VDD1P0	◐	●	○
50%	C44_1	GND	◐	◐	◐
50%	U1_179	GND	◐	●	○
50%	U1_180	GND	◐	●	○
50%	C44_2	VDD_2P5	◐	◐	◐
50%	U1_32	GND	◐	●	○
50%	U1_33	GND	◐	●	○
50%	R58_2	VCC_1V8_S3	◐	●	○
50%	U1_185	GND	◐	●	○
50%	U1_186	GND	◐	●	○
50%	C53_1	GND	◐	◐	◐
50%	C53_2	P06_VDD1P0	◐	◐	◐
50%	R52_2	GND	◐	●	○
50%	C21_1	GND	◐	◐	◐
50%	U1_191	GND	◐	●	○
50%	U1_192	GND	◐	●	○
50%	C21_2	VDD_2P5	◐	◐	◐
50%	C38_1	GND	◐	◐	◐
50%	C38_2	VCC5V0_SYS	◐	◐	◐
50%	U1_42	GND	◐	●	○
50%	U1_197	GND	◐	●	○
50%	U1_198	GND	◐	●	○
50%	U1_43	GND	◐	●	○
50%	L2_2	VCC3V3_REG	◐	●	○
50%	R8_1	SDMMC_D1	◐	●	○
50%	C46_1	GND	◐	◐	◐
50%	C46_2	P06_VDD1P0	◐	◐	◐
50%	U1_52	GND	◐	●	○
50%	R2_2	VCC3V3_REG	◐	●	○
50%	U1_57	SDMMC_CLK	◐	●	○
50%	U1_205	GND	◐	●	○
50%	U1_206	GND	◐	●	○
50%	U1_59	GND	◐	●	○
50%	U1_60	GND	◐	●	○
50%	U1_61	SDMMC_D3	◐	●	○
50%	U1_62	SDMMC_CMD	◐	●	○
50%	U1_211	GND	◐	●	○
50%	U1_212	GND	◐	●	○
50%	U1_63	SDMMC_D0	◐	●	○
50%	U1_65	GND	◐	●	○
50%	U1_66	GND	◐	●	○
50%	U1_67	SDMMC_D1	◐	●	○
50%	U1_217	GND	◐	●	○
50%	U1_218	GND	◐	●	○
50%	U1_69	SDMMC_D2	◐	●	○
50%	U1_71	GND	◐	●	○
50%	U1_74	GND	◐	●	○
50%	U1_80	I2C6_SCL_M3	◐	●	○
50%	U1_223	GND	◐	●	○
50%	U1_82	I2C6_SDA_M3	◐	●	○
50%	U1_84	VCC_3V3_S3	◐	●	○
50%	U1_226	UART_TXD	◐	●	○
50%	U1_86	VCC_3V3_S3	◐	●	○
50%	U1_88	VCC_1V8_S3	◐	●	○
50%	U1_229	GND	◐	●	○
50%	U1_230	UART_RXD	◐	●	○
50%	U1_90	VCC_1V8_S3	◐	●	○
50%	U1_232	GND	◐	●	○
50%	U1_98	GND	◐	●	○
50%	R16_1	GND	◐	●	○
50%	U1_235	GND	◐	●	○
50%	C9_1	Net-(C10-Pad2)	◐	◐	◐
50%	C9_2	Net-(C9-Pad2)	◐	◐	◐
50%	R31_2	VCC_3V3_S3	◐	●	○
50%	C14_1	SSTX2N	◐	◐	◐
50%	C14_2	TYPECO_SSTX2N	◐	◐	◐
50%	U1_241	GND	◐	●	○
50%	C4_2	Net-(C4-Pad2)	◐	◐	◐
50%	C1_1	TYPECO_SSTX1N	◐	◐	◐
50%	C1_2	SSTX1N	◐	◐	◐
50%	U1_245	GND	◐	●	○
50%	C30_1	VCC3V3_REG	◐	◐	◐
50%	C30_2	GND	◐	◐	◐
50%	U1_248	GND	◐	●	○
50%	R10_1	SDMMC_D3	◐	●	○
50%	R10_2	Net-(J4-CD/DAT3)	◐	●	○
50%	J10_22	UART_RXD	◐	●	○
50%	J10_32	UART_TXD	◐	●	○
50%	R46_1	VCC3V3_REG	◐	●	○
50%	U1_254	GND	◐	●	○
50%	U1_255	GND	◐	●	○
17%	U1_77	VCC5V0_SYS	◐	○	○
17%	J4_4	VCC_3V3_S3	◐	○	○
17%	J4_6	GND	◐	○	○
17%	J2_A4	VCC5V0_SYS	◐	○	○
17%	J2_B12	GND	◐	○	○
17%	J2_S1	GND	◐	○	○
17%	J2_S2	GND	◐	○	○
17%	J2_S3	GND	◐	○	○
17%	J2_A9	VCC5V0_SYS	◐	○	○
17%	R50_2	GND	◐	○	○
17%	J2_S4	GND	◐	○	○
17%	J10_57	GND	◐	○	○
17%	J2_A12	GND	◐	○	○
17%	J2_B1	GND	◐	○	○
17%	J9_1	GND	◐	○	○
17%	J10_51	GND	◐	○	○
17%	J10_63	GND	◐	○	○
17%	J9_4	GND	◐	○	○
17%	J2_B4	VCC5V0_SYS	◐	○	○
17%	J10_45	GND	◐	○	○
17%	J9_7	GND	◐	○	○
17%	J10_72	VCC3V3_REG	◐	○	○
17%	J10_69	GND	◐	○	○
17%	J9_10	GND	◐	○	○
17%	J10_75	GND	◐	○	○
17%	J2_B9	VCC5V0_SYS	◐	○	○
17%	J9_15	VCC3V3_REG	◐	○	○
17%	J2_A1	GND	◐	○	○
17%	J10_74	VCC3V3_REG	◐	○	○
17%	U5_7	VCC5V0_SYS	◐	○	○
17%	U5_8	VCC5V0_SYS	◐	○	○
17%	U5_10	VCC5V0_SYS	◐	○	○
17%	U5_11	VCC5V0_SYS	◐	○	○
17%	S3_2	GND	◐	○	○
17%	S1_2	GND	◐	○	○
17%	U1_79	VCC5V0_SYS	◐	○	○
17%	U3_7	VCC5V0_SYS	◐	○	○
17%	U3_8	VCC5V0_SYS	◐	○	○
17%	U1_81	VCC5V0_SYS	◐	○	○
17%	J8_1	VCC3V3_REG	◐	○	○
17%	U3_12	VCC5V0_SYS	◐	○	○
17%	J8_4	GND	◐	○	○
17%	J8_7	GND	◐	○	○
17%	J8_10	GND	◐	○	○
17%	J8_13	GND	◐	○	○
17%	J8_16	GND	◐	○	○
17%	J8_19	GND	◐	○	○
17%	C39_1	GND	◐	○	○
17%	C39_2	P06_VDD1P0	◐	○	○
17%	C11_1	GND	◐	○	○
17%	C11_2	VCC5V0_SYS	◐	○	○
17%	J8_22	GND	◐	○	○
17%	U1_83	VCC5V0_SYS	◐	○	○
17%	U1_85	VCC5V0_SYS	◐	○	○
17%	C12_1	GND	◐	○	○
17%	C12_2	VCC3V3_REG	◐	○	○
17%	J5_1	GND	◐	○	○
17%	S2_2	GND	◐	○	○
17%	R51_1	GND	◐	○	○
17%	J10_1	GND	◐	○	○
17%	J10_2	VCC3V3_REG	◐	○	○
17%	J10_4	VCC3V3_REG	◐	○	○
17%	J10_7	GND	◐	○	○
17%	U2_3	VDD_2P5	◐	○	○
17%	U2_6	P06_VDD1P0	◐	○	○
17%	U2_9	VDD_2P5	◐	○	○
17%	U2_24	P06_VDD1P0	◐	○	○
17%	U2_31	P06_VDD1P0	◐	○	○
17%	U2_42	P06_VDD1P0	◐	○	○
17%	J10_18	GND	◐	○	○
17%	U1_87	VCC5V0_SYS	◐	○	○
17%	J10_33	GND	◐	○	○
17%	J1_14	GND	◐	○	○
17%	J1_16	GND	◐	○	○
17%	J10_39	GND	◐	○	○
0%	U1_117	MIPI_CSI0_RX_D0P	○	○	○
0%	U1_118	PCIE20_2_RXN/SATA30_2_RXN	○	○	○
0%	U1_121	MIPI_CSI0_RX_D1N	○	○	○
0%	U1_122	PCIE20_2_TXP/SATA30_2_TXP	○	○	○
0%	U1_123	MIPI_CSI0_RX_D1P	○	○	○
0%	U1_124	PCIE20_2_TXN/SATA30_2_TXN	○	○	○
0%	U1_127	MIPI_CSI0_CLK0N	○	○	○
0%	U1_128	MIPI_DPHY0_RX_D0N	○	○	○
0%	U1_129	MIPI_CSI0_CLK0P	○	○	○
0%	U1_130	MIPI_DPHY0_RX_D0P	○	○	○
0%	U1_133	MIPI_CSI0_RX_D2N	○	○	○
0%	U1_134	MIPI_DPHY0_RX_D1N	○	○	○
0%	U1_135	MIPI_CSI0_RX_D2P	○	○	○
0%	U1_136	MIPI_DPHY0_RX_D1P	○	○	○
0%	U1_139	MIPI_CSI0_RX_D3N	○	○	○
0%	U1_140	MIPI_DPHY0_RX_CLKN	○	○	○
0%	U1_141	MIPI_CSI0_RX_D3P	○	○	○
0%	U1_142	MIPI_DPHY0_RX_CLKP	○	○	○
0%	U1_143		○	○	○
0%	U1_145		○	○	○
0%	U1_146		○	○	○
0%	U1_147		○	○	○
0%	U1_148		○	○	○
0%	U1_149	HDMI0_TX_ON_H	○	○	○
0%	U1_151	HDMI_TX0_CEC_M0	○	○	○
0%	U1_152		○	○	○
0%	U1_153	HDMI0_SBDN-HPD	○	○	○
0%	U1_154		○	○	○
0%	U1_157	MIPI_DPHY0_TX_D0N	○	○	○
0%	U1_158	HDMI0_SBDP	○	○	○
0%	U1_159	MIPI_DPHY0_TX_D0P	○	○	○
0%	U1_160		○	○	○
0%	U1_163	MIPI_DPHY0_TX_D1N	○	○	○
0%	U1_164		○	○	○
0%	U1_165	MIPI_DPHY0_TX_D1P	○	○	○
0%	U1_166		○	○	○
0%	U1_169	MIPI_DPHY0_TX_CLKN	○	○	○
0%	U1_170	HDMI0_TX2P	○	○	○
0%	U1_171	MIPI_DPHY0_TX_CLKP	○	○	○
0%	U1_172	HDMI0_TX2N	○	○	○
0%	U1_175	MIPI_DPHY1_TX_D0N	○	○	○
0%	U1_176	HDMI0_TX1P	○	○	○
0%	U1_177	MIPI_DPHY1_TX_D0P	○	○	○
0%	U1_178	HDMI0_TX1N	○	○	○
0%	U1_181	MIPI_DPHY1_TX_D1N	○	○	○
0%	U1_182	HDMI0_TX0P	○	○	○
0%	U1_183	MIPI_DPHY1_TX_D1P	○	○	○
0%	U1_184	HDMI0_TX0N	○	○	○
0%	U1_187	MIPI_DPHY1_TX_CLKN	○	○	○
0%	U1_188	HDMI0_TX3P	○	○	○
0%	U1_189	MIPI_DPHY1_TX_CLKP	○	○	○
0%	U1_190	HDMI0_TX3N	○	○	○
0%	U1_193	MIPI_DPHY1_TX_D2N	○	○	○
0%	U1_194	MIPI_DPHY1_TX_D3N	○	○	○
0%	U1_195	MIPI_DPHY1_TX_D2P	○	○	○
0%	U1_196	MIPI_DPHY1_TX_D3P	○	○	○
0%	U1_199	HDMI_TX0_SDA_M0	○	○	○
0%	U1_200	HDMI_TX0_SCL_M0	○	○	○
0%	U1_109	PCIE20_PERSTn_3V3_L	○	○	○
0%	U1_201	USB_D+	○	○	○
0%	U1_202	TYPECO_SSTX2P	○	○	○
0%	U1_203	USB_D-	○	○	○
0%	U1_204	TYPECO_SSTX2N	○	○	○
0%	U1_207	TYPEC0_SBU1	○	○	○
0%	U1_208	TYPECO_SSRX2P	○	○	○
0%	U1_209	TYPEC0_SBU2	○	○	○
0%	U1_210	TYPECO_SSRX2N	○	○	○
0%	U1_213		○	○	○
0%	U1_214	TYPECO_SSTX1N	○	○	○
0%	U1_215		○	○	○
0%	U1_216	TYPECO_SSTX1P	○	○	○
0%	U1_219	TYPECO_SSRX1N	○	○	○
0%	U1_220		○	○	○
0%	U1_221	TYPECO_SSRX1P	○	○	○
0%	U1_222	PCIE20_CLKREQ	○	○	○
0%	U1_224	PCIE20_PERSTn	○	○	○
0%	U1_225		○	○	○
0%	U1_227		○	○	○
0%	U1_228	UART_RTS	○	○	○
0%	U1_231		○	○	○
0%	U1_233		○	○	○
0%	U1_234		○	○	○
0%	U1_236		○	○	○
0%	U1_237		○	○	○
0%	U1_238		○	○	○
0%	U1_239		○	○	○
0%	U1_240	UART_CTS	○	○	○
0%	U1_242	GMAC_TXD3	○	○	○
0%	U1_243	PCIE20_WAKEn	○	○	○
0%	U1_244		○	○	○
0%	U1_246	GMAC_TXD0	○	○	○
0%	U1_247	GMAC_TXD2	○	○	○
0%	U1_249	GMAC_TXD1	○	○	○
0%	U1_250		○	○	○
0%	U1_251	GMAC_TXEN	○	○	○
0%	U1_252		○	○	○
0%	U1_253	GMAC_MDIO	○	○	○
0%	U1_256	GMAC_RXD1	○	○	○
0%	U1_257	GMAC_MCLK	○	○	○
0%	U1_258	GMAC_RXCLK	○	○	○
0%	U1_259	GMAC_RXDV	○	○	○
0%	U1_260	GMAC_RXD0	○	○	○
0%	U1_261	GMAC_RXD2	○	○	○
0%	U1_262	GMAC_TXCLK	○	○	○
0%	U1_263	GMAC_RXD3	○	○	○
0%	U1_266		○	○	○
0%	U1_267		○	○	○
0%	U1_268		○	○	○
0%	U1_269	I2S_LRCLK	○	○	○
0%	U1_270	I2S_SDO	○	○	○
0%	U1_271	I2S_SCLK	○	○	○
0%	U1_272		○	○	○
0%	U1_273	I2S_SDI	○	○	○
0%	U1_276	PCIE20_REFCLKP	○	○	○
0%	U1_277		○	○	○
0%	U1_278	PCIE20_REFCLKN	○	○	○
0%	U1_279		○	○	○
0%	U1_281		○	○	○
0%	U1_282	PCIE20_TXP	○	○	○
0%	U1_283		○	○	○
0%	U1_284	PCIE20_TXN	○	○	○
0%	U1_285		○	○	○
0%	U1_288	PCIE20_RXN	○	○	○
0%	U1_290	PCIE20_RXP	○	○	○
0%	U1_291	GMAC_MDC	○	○	○
0%	U1_293		○	○	○
0%	U1_294		○	○	○
0%	U1_296		○	○	○
0%	U1_297		○	○	○
0%	U1_298		○	○	○
0%	R4_1	BOOT_SW	○	○	○
0%	R4_2	Net-(C4-Pad2)	○	○	○
0%	J10_43	PCIE20_RXN	○	○	○
0%	J10_44		○	○	○
0%	J10_46		○	○	○
0%	J10_47	PCIE20_REFCLKP	○	○	○
0%	J10_48		○	○	○
0%	J10_49	PCIE20_REFCLKN	○	○	○
0%	J10_50		○	○	○
0%	J10_52	PCIE20_PERSTn	○	○	○
0%	J10_53	PCIE20_CLKREQ	○	○	○
0%	J10_54		○	○	○
0%	J10_55	PCIE20_WAKEn	○	○	○
0%	J10_56		○	○	○
0%	J10_58		○	○	○
0%	J10_59		○	○	○
0%	J10_60		○	○	○
0%	J10_61		○	○	○
0%	J10_62		○	○	○
0%	J10_64		○	○	○
0%	J10_65		○	○	○
0%	J10_66		○	○	○
0%	J10_67		○	○	○
0%	J10_68		○	○	○
0%	J10_70		○	○	○
0%	J10_71		○	○	○
0%	J10_73		○	○	○
0%	U1_3		○	○	○
0%	U1_4		○	○	○
0%	U1_5		○	○	○
0%	U1_6		○	○	○
0%	U1_9		○	○	○
0%	U1_10		○	○	○
0%	U1_11		○	○	○
0%	U1_12		○	○	○
0%	U1_15		○	○	○
0%	U1_16		○	○	○
0%	U1_17		○	○	○
0%	U1_18		○	○	○
0%	U1_19		○	○	○
0%	U1_20		○	○	○
0%	U1_21	GPIO_A4	○	○	○
0%	U1_24	GPIO1-C0	○	○	○
0%	U1_25	GPIO1_B0	○	○	○
0%	U1_26	GPIO1-C1	○	○	○
0%	U1_27	GPIO1_B1	○	○	○
0%	U1_289		○	○	○
0%	U1_29	GPIO1_B2	○	○	○
0%	U1_30	GPIO1_A3	○	○	○
0%	U1_31	GPIO1_B3	○	○	○
0%	U1_34	GPIO1_A4	○	○	○
0%	U1_35	GPIO1_D6	○	○	○
0%	U1_36	GPIO1_D7	○	○	○
0%	U1_37	GPIO1_B4	○	○	○
0%	U1_38	GPIO1_A5	○	○	○
0%	U1_39	GPIO1_B5	○	○	○
0%	U1_40	GPIO1_A6	○	○	○
0%	U1_41	GPIO1_B6	○	○	○
0%	U1_44	GPIO1_A7	○	○	○
0%	U1_45	GPIO1_B7	○	○	○
0%	U1_46	GPIO1-C4	○	○	○
0%	U1_89		○	○	○
0%	R40_1	0_LED1	○	○	○
0%	R40_2	Net-(J1-LEDG2_A)	○	○	○
0%	Y1_1	CKXTAL1	○	○	○
0%	Y1_2		○	○	○
0%	Y1_3	CKXTAL2	○	○	○
0%	Y1_4		○	○	○
0%	R19_1	Net-(U5-FB1)	○	○	○
0%	U1_64		○	○	○
0%	U1_91		○	○	○
0%	L4_2	Net-(U5-SW2)	○	○	○
0%	R20_1	Net-(U5-FB2)	○	○	○
0%	U1_92	PMIC_RESET_L	○	○	○
0%	U1_93	BOOT_SW	○	○	○
0%	U1_49	GPIO1-D5	○	○	○
0%	U1_94	SARADC_VIN3	○	○	○
0%	R22_2	Net-(U5-FB2)	○	○	○
0%	U1_95	GPIO4_B6	○	○	○
0%	U1_96	SARADC_VIN2	○	○	○
0%	U1_97	GPIO4_A7	○	○	○
0%	U1_72		○	○	○
0%	C28_1	CKXTAL2	○	○	○
0%	U1_99	PWRON_L	○	○	○
0%	U5_1	Net-(U5-FB2)	○	○	○
0%	U1_100	GPIO4_A5	○	○	○
0%	U5_3	Net-(U5-FB1)	○	○	○
0%	U5_4	Net-(U5-PG1)	○	○	○
0%	U1_73		○	○	○
0%	U5_6	Net-(U5-SW1)	○	○	○
0%	R47_2	GPIO1_A3	○	○	○
0%	J4_9		○	○	○
0%	R16_2	Net-(C10-Pad2)	○	○	○
0%	J4_10		○	○	○
0%	R14_2	Net-(C7-Pad2)	○	○	○
0%	U5_12	Net-(U5-SW2)	○	○	○
0%	U5_13	Net-(U5-PG2)	○	○	○
0%	U5_14	Net-(U5-COMP/FSET)	○	○	○
0%	R56_1	Net-(U2-JTAG_CLK)	○	○	○
0%	U1_56	GPIO1-D2	○	○	○
0%	U1_75	SDMMC_PWREN	○	○	○
0%	R31_1	GPIO_VREF	○	○	○
0%	U1_76	SDMMC_DET_L	○	○	○
0%	S3_1	Net-(C5-Pad2)	○	○	○
0%	R3_1	PWRON_L	○	○	○
0%	C13_2	Net-(U3-NR/SS)	○	○	○
0%	S1_1	Net-(C3-Pad2)	○	○	○
0%	R3_2	Net-(C3-Pad2)	○	○	○
0%	U1_28	I2C4_SDA_M3	○	○	○
0%	R12_2	Net-(U3-FB)	○	○	○
0%	U1_78	GPIO_VREF	○	○	○
0%	U1_51	UART_RX	○	○	○
0%	R50_1	R50CC2	○	○	○
0%	U3_2	Net-(U3-NR/SS)	○	○	○
0%	U3_3	Net-(U3-FB)	○	○	○
0%	U1_54	GPIO1-D1	○	○	○
0%	U3_5	Net-(U3-PG)	○	○	○
0%	U3_6	Net-(U3-S-CONF)	○	○	○
0%	R15_1	GPIO1-C1	○	○	○
0%	R15_2	Net-(C10-Pad2)	○	○	○
0%	R13_1	GPIO1-D5	○	○	○
0%	U3_10	Net-(C26-Pad1)	○	○	○
0%	R13_2	Net-(C7-Pad2)	○	○	○
0%	J9_2	MIPI_DPHY0_RX_D0N	○	○	○
0%	U3_13	Net-(C26-Pad1)	○	○	○
0%	U3_14	Net-(U3-BOOT)	○	○	○
0%	R53_1	GMAC_TXCLK	○	○	○
0%	R53_2	Net-(U2-GTX_CLK)	○	○	○
0%	R23_1	Net-(U5-COMP/FSET)	○	○	○
0%	J8_2	I2C4_SDA_M3	○	○	○
0%	J8_3	GPIO1_A3	○	○	○
0%	J9_3	MIPI_DPHY0_RX_D0P	○	○	○
0%	J8_5	GPIO1_B7	○	○	○
0%	J8_6	GPIO1_B6	○	○	○
0%	R54_1	GMAC_RXCLK	○	○	○
0%	R54_2	RES_RXCLK	○	○	○
0%	J9_5	MIPI_DPHY0_RX_D1N	○	○	○
0%	R61_2	GMAC_RXDV	○	○	○
0%	J8_8	MIPI_CSI0_RX_D3P	○	○	○
0%	R45_2	Net-(U2-RBIAS)	○	○	○
0%	J8_9	MIPI_CSI0_RX_D3N	○	○	○
0%	R24_2	GMAC_RXD0	○	○	○
0%	J9_6	MIPI_DPHY0_RX_D1P	○	○	○
0%	R60_2	GMAC_RXD0	○	○	○
0%	J8_11	MIPI_CSI0_RX_D2P	○	○	○
0%	J8_12	MIPI_CSI0_RX_D2N	○	○	○
0%	J9_8	MIPI_DPHY0_RX_CLKN	○	○	○
0%	R18_2	Net-(U5-PG2)	○	○	○
0%	J8_14	MIPI_CSI0_CLK0P	○	○	○
0%	J8_15	MIPI_CSI0_CLK0N	○	○	○
0%	J9_9	MIPI_DPHY0_RX_CLKP	○	○	○
0%	C29_2	CKXTAL1	○	○	○
0%	J8_17	MIPI_CSI0_RX_D1P	○	○	○
0%	J8_18	MIPI_CSI0_RX_D1N	○	○	○
0%	J9_11	GPIO1-D3	○	○	○
0%	R1_2	Net-(U3-S-CONF)	○	○	○
0%	J9_12	GPIO1_D7	○	○	○
0%	J2_A2	SSTX1P	○	○	○
0%	J8_20	MIPI_CSI0_RX_D0P	○	○	○
0%	J8_21	MIPI_CSI0_RX_D0N	○	○	○
0%	J2_A3	SSTX1N	○	○	○
0%	J2_A5	R49CC1	○	○	○
0%	J2_A6	TYPEC0_USB20_OTG_DP	○	○	○
0%	L3_2	Net-(U5-SW1)	○	○	○
0%	R57_1	Net-(U2-JTAG_TMS)	○	○	○
0%	U1_58	GPIO1-D3	○	○	○
0%	J2_A7	TYPEC0_USB20_OTG_DN	○	○	○
0%	U1_48	GPIO1-C6	○	○	○
0%	R5_1	PMIC_RESET_L	○	○	○
0%	R5_2	Net-(C5-Pad2)	○	○	○
0%	U1_68	SW_RECOVERY	○	○	○
0%	J2_A8	TYPEC0_SBU1	○	○	○
0%	J2_A10	TYPECO_SSRX2N	○	○	○
0%	J2_A11	TYPECO_SSRX2P	○	○	○
0%	J2_B2	SSTX2P	○	○	○
0%	J5_2	Net-(C9-Pad2)	○	○	○
0%	J5_3	Net-(C8-Pad2)	○	○	○
0%	J5_4		○	○	○
0%	R59_1	GMAC_MDIO	○	○	○
0%	J5_5		○	○	○
0%	J5_6		○	○	○
0%	S2_1	Net-(C4-Pad2)	○	○	○
0%	J2_B3	SSTX2N	○	○	○
0%	J2_B5	R50CC2	○	○	○
0%	R51_2	R49CC1	○	○	○
0%	J2_B6	TYPEC0_USB20_OTG_DP	○	○	○
0%	R55_1	Net-(U2-JTAG_TDI)	○	○	○
0%	J2_B7	TYPEC0_USB20_OTG_DN	○	○	○
0%	J10_3	USB_D+	○	○	○
0%	J2_B8	TYPEC0_SBU2	○	○	○
0%	J10_5	USB_D-	○	○	○
0%	J10_6		○	○	○
0%	J2_B10	TYPECO_SSRX1N	○	○	○
0%	J10_8	I2S_SCLK	○	○	○
0%	U2_1	MDI0+	○	○	○
0%	U2_2	MDI0-	○	○	○
0%	J2_B11	TYPECO_SSRX1P	○	○	○
0%	U2_4	MDI1+	○	○	○
0%	U2_5	MDI1-	○	○	○
0%	U1_101	TYPEC0_USB20_OTG_ID	○	○	○
0%	U2_7	MDI2+	○	○	○
0%	U2_8	MDI2-	○	○	○
0%	U1_102	PCIE_CLKREQN	○	○	○
0%	U1_295		○	○	○
0%	U2_11	MDI3-	○	○	○
0%	U2_12	Net-(U2-RBIAS)	○	○	○
0%	U2_13		○	○	○
0%	U2_14	CKXTAL2	○	○	○
0%	U2_15	CKXTAL1	○	○	○
0%	U2_16	GMAC_MDC	○	○	○
0%	U2_17	GMAC_MDIO	○	○	○
0%	U2_18	clkout_res	○	○	○
0%	J10_9	I2S_LRCLK	○	○	○
0%	U2_20	Net-(U2-JTAG_CLK)	○	○	○
0%	U2_21		○	○	○
0%	U2_22	Net-(U2-JTAG_TMS)	○	○	○
0%	U2_23	Net-(U2-JTAG_TDI)	○	○	○
0%	U1_103	TYPEC0_USB20_OTG_DN	○	○	○
0%	U2_25	GMAC_TXD3	○	○	○
0%	U2_26	GMAC_TXD2	○	○	○
0%	U2_27	GMAC_TXD1	○	○	○
0%	U2_28	GMAC_TXD0	○	○	○
0%	U2_29	Net-(U2-GTX_CLK)	○	○	○
0%	J10_10		○	○	○
0%	U1_104	PCIE_WAKEN	○	○	○
0%	U2_32	RES_RXCLK	○	○	○
0%	U2_33	GMAC_RXD0	○	○	○
0%	U2_34	GMAC_RXD1	○	○	○
0%	U2_35	GMAC_RXD2	○	○	○
0%	U2_36	GMAC_RXD3	○	○	○
0%	U2_37	GMAC_TXEN	○	○	○
0%	U2_38	GMAC_RXDV	○	○	○
0%	U2_39		○	○	○
0%	U2_40		○	○	○
0%	J10_11		○	○	○
0%	U1_105	TYPEC0_USB20_OTG_DP	○	○	○
0%	U2_43	GPIO1-C1	○	○	○
0%	U2_44	Net-(U2-INT/PWDN)	○	○	○
0%	U2_45		○	○	○
0%	U2_46	0_LED1	○	○	○
0%	U2_47	0_LED2	○	○	○
0%	U2_48		○	○	○
0%	J10_12	I2S_SDI	○	○	○
0%	J10_13		○	○	○
0%	J10_14	I2S_SDO	○	○	○
0%	R41_1	0_LED2	○	○	○
0%	R41_2	Net-(J1-LEDG1_A)	○	○	○
0%	J10_15		○	○	○
0%	J10_16		○	○	○
0%	J10_17		○	○	○
0%	R21_2	Net-(U5-FB1)	○	○	○
0%	U1_106	GPIO4_A6	○	○	○
0%	U1_47	GPIO0-C2	○	○	○
0%	J10_19		○	○	○
0%	R25_2	GMAC_RXDV	○	○	○
0%	J10_20		○	○	○
0%	J10_21		○	○	○
0%	U1_55	UART_TX	○	○	○
0%	J10_23		○	○	○
0%	U1_110	PCIE20_2_REFCLKP	○	○	○
0%	R7_2	Net-(U5-PG1)	○	○	○
0%	U1_111		○	○	○
0%	J10_34	UART_CTS	○	○	○
0%	R58_1	Net-(U2-INT/PWDN)	○	○	○
0%	J10_35	PCIE20_TXP	○	○	○
0%	R49_1	clkout_res	○	○	○
0%	R49_2	GMAC_MCLK	○	○	○
0%	J1_1	Net-(J1-TRCT1)	○	○	○
0%	J1_2	MDI2-	○	○	○
0%	J1_3	MDI2+	○	○	○
0%	J1_4	MDI1-	○	○	○
0%	J1_5	MDI1+	○	○	○
0%	J1_6	Net-(J1-TRCT1)	○	○	○
0%	J1_7	Net-(J1-TRCT1)	○	○	○
0%	J1_8	MDI3-	○	○	○
0%	J1_9	MDI3+	○	○	○
0%	J1_10	MDI0-	○	○	○
0%	J1_11	MDI0+	○	○	○
0%	J1_12	Net-(J1-TRCT1)	○	○	○
0%	J1_13	Net-(J1-LEDG1_A)	○	○	○
0%	U1_112	PCIE20_2_REFCLKN	○	○	○
0%	J1_15	Net-(J1-LEDG2_A)	○	○	○
0%	U1_115	MIPI_CSI0_RX_D0N	○	○	○
0%	J10_36	UART_RTS	○	○	○
0%	J10_37	PCIE20_TXN	○	○	○
0%	R52_1	GMAC_MCLK	○	○	○
0%	J10_38		○	○	○
0%	U1_116	PCIE20_2_RXP/SATA30_2_RXP	○	○	○
0%	J10_40		○	○	○
0%	J10_41	PCIE20_RXP	○	○	○
0%	J10_42		○	○	○
0%	L2_1	Net-(C26-Pad1)	○	○	○
0%	U1_70		○	○	○
0%	R46_2	I2C4_SDA_M3	○	○	○
0%	U1_50	GPIO1-D0	○	○	○
0%	R2_1	Net-(U3-PG)	○	○	○
0%	U2_10	MDI3+	○	○	○

14.10.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Component Properties

Schematic library symbol quality analysis.

15.1 Datasheet Link Integrity

The datasheet link stored in the schematic was followed, and the document it returned was compared against the part number. The rows below are links that resolved to a document covering a different part - most often a sibling variant of the same family, where the specifications read as plausible but describe the wrong device.

	Observation	Status
RefDesC36 Part NumberCL05A105KO5NNNC	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC8 Part NumberCL31A476MQHNNNE Linked document coversC0402C	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1002_X7R_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC27 Part NumberCL31B475KOHNFNE	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1002_X7R_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC41 Part NumberGCM155R71H103KA55D	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC25 Part NumberGRM155R60J106ME15D	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC37 Part NumberGRM155R71H104KE14D	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1003_C0G_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC30 Part NumberMA0805XF106K160 Linked document coversC0402C	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1002_X7R_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesC39 Part NumberMSASL219LB5226MTNA01	The linked datasheet does not cover this part number. the link returns a catalog, not this part's datasheet https://content.kemet.com/datasheets/KEM_C1002_X7R_SMD.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesU1 Part NumberOrange Pi CM5 Linked document coversOPi CM5	The linked datasheet does not cover this part number. the link returns a brochure, not this part's datasheet https://www.orangepi.net/wp-content/uploads/2025/01/OrangePi_CM5_Base_RK3588S_user-manual_v1.3.pdf Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High
RefDesU5 Part NumberXPS62442QWRQRRQ1 Linked document coversTPS62441QWRQRRQ1, TPS62442QWRQRRQ1	The linked datasheet does not cover this part number. Document covers TPS62442QWRQRRQ1, a different concrete part number from XPS62442QWRQRRQ1. https://www.ti.com/lit/gpn/tps62442-q1 Correct the datasheet link in the schematic, or supply the manufacturer PDF for this part.	High

15.2 Library Symbol Grades

Grading schematic library symbol quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Symbol Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U1	B	300	90	64	69	67	0	0	0	10	Hirose DF40C-100DS-0.4V
U3	B	14	3	5	6	0	0	0	0	0	TPS62914QRPYRQ1
U5	B	14	4	8	2	0	0	0	0	0	XPS62442QWRQRRQ1
U2	A	49	12	11	8	15	0	0	0	3	DP83867IRRGZR

15.2.1 Library Quality Summary

Total ICs evaluated	4
Grade A (excellent)	1 (25.0%)
Grade B (good)	3 (75.0%)
Grade C (fair)	0 (0.0%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	0 (0.0%)
OVERALL LIBRARY QUALITY	A (3.92/4.00)

15.3 Component Library Validation

The shared part-number check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Checking for generic/incomplete library symbols using statistical patterns.

Library Symbol Issues (3 symbols)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
Hirose DF40C-100DS-0.4V	DF40C-100DS-0.4V	-	U1	300	P:10 Pwr:90 Bi:67 I:38 O:69 ?:26	Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GNDGMAC1_RXD2/SDIO_D2_M1=Bidirectional]
TPS62914QRPYRQ1	TPS62914QRPYRQ1	-	U3	14	Pwr:3 I:5 O:6	Power-named pins not typed as Power - library pin types incomplete [VO=Input, VIN=Input, SW=Output, VIN=Input, SW=Output]
XPS62442QWRQRRQ1	XPS62442QWRQRRQ1	-	U5	14	Pwr:4 I:8 O:2	Power-named pins not typed as Power - library pin types incomplete [SW1=Input, SW2=Input]

15.3.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library symbol

Power-named pins not typed as Power: Library pin types incomplete

15.4 Symbol vs Datasheet Pin Table

Each symbol's pin numbers are compared with the pin table of its cached datasheet model. A datasheet pin the symbol lacks is a warning only when the datasheet calls it electrical; a pin the datasheet marks NC or mechanical, or a symbol pin the table does not list, is shown for information. An exposed pad is never counted as a mismatch, whether the symbol names it or numbers it one past the last pin. Where it was numbered, the row suggests giving it a name, because a bare number does not tell a reader what the pin is.

5 parts compared with a datasheet model: 5 agree, 0 differ. 3 parts have no cached datasheet model yet; 0 have a cached file that is not this symbol's model and were not compared.

Every symbol with a cached datasheet model matches its pin table.

15.5 Shielded Connector Symbol Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.6 I/O Bank Power

Power-port association not available for U1 (DF40C-100DS-0.4V), U2 (DP83867IRRGZR): the unpowered-pin check was not performed for these parts.

15.7 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
J1	L834-1G1T-S7	16	Footprint	Custom_Parts:CONN16_L834-1G1T-S7_BEL
J2	A2	28	Footprint	Custom_Parts:GCT_USB4056-03-A_REVA2
J4	1040310811	10	Footprint	Custom_Parts:104031-0811_MOL
J5	SJ3-35063BG	6	Footprint	Custom_Parts:SAMESKY_SJ3-35063BG
J8	FH12-22S-0.5SH55	22	Footprint	Custom_Parts:CONN_FH12-22S-0.5SH55_HIR
J9	FH12-15S-0.5SH55	15	Footprint	Custom_Parts:CONN_FH12-15S-0.5SH55_HIR
J10	SM3ZS067U410AER1000	67	Footprint	Custom_Parts:CONN_SM3ZS067U410AER1000_JAE
U1	DF40C-100DS-0.4V	300	Footprint	OPi_CM5
U2	DP83867IRRGZR	49	Footprint	Custom_Parts:RGZ0048B
U3	TPS62914QRPYRQ1	14	Footprint	Custom_Parts:VQFN-HR14_RPY_TEX
U5	XPS62442QWRQRRQ1	14	Footprint	Custom_Parts:VQFN14_RQR_TEX
Y1	H130B-25.000-20-F-3030-TR	4	Footprint	Custom_Parts:H130B2500020F3030TR

15.8 IC Pin Electrical Properties

Unique IC symbols	4
Total IC instances	4

IC Library Symbols
Industry Name	Library Name	RefDes	Notes
DP83867IRRGZR	DP83867IRRGZR	U2
DF40C-100DS-0.4V	Hirose DF40C-100DS-0.4V	U1
TPS62914QRPYRQ1	TPS62914QRPYRQ1	U3
XPS62442QWRQRRQ1	XPS62442QWRQRRQ1	U5

15.8.1 DP83867IRRGZR (DP83867IRRGZR)

Pin	Pin Name	Electrical
1	TD_P_A	Bidirectional
2	TD_M_A	Bidirectional
3	VDDA2P5	Power In
4	TD_P_B	Bidirectional
5	TD_M_B	Bidirectional
6	VDD1P0	Power In
7	TD_P_C	Bidirectional
8	TD_M_C	Bidirectional
9	VDDA2P5	Power In
10	TD_P_D	Bidirectional
11	TD_M_D	Bidirectional
12	RBIAS	Passive
13	VDDA1P8	Power In
14	XO	Passive
15	XI	Passive
16	MDC	Input
17	MDIO	Bidirectional
18	CLK_OUT	Output
19	VDDIO	Power In
20	JTAG_CLK	Input
21	JTAG_TDO	Output
22	JTAG_TMS	Input
23	JTAG_TDI	Input
24	VDD1P0	Power In
25	TX_D3	Input
26	TX_D2	Input
27	TX_D1/SGMII_SIP	Input
28	TX_D0/SGMII_SIN	Input
29	GTX_CLK	Input
30	VDDIO	Power In
31	VDD1P0	Power In
32	RX_CLK	Output
33	RX_D0/SGMII_COP	Output
34	RX_D1/SGMII_CON	Output
35	RX_D2/SGMII_SOP	Output
36	RX_D3/SGMII_SON	Output
37	TX_EN/TX_CTRL	Bidirectional
38	RX_DV/RX_CTRL	Bidirectional
39	RX_ER/GPIO_0	Bidirectional
40	COL/GPIO_1	Output
41	VDDIO	Power In
42	VDD1P0	Power In
43	RESET	Input
44	INT/PWDN	Input
45	LED_2	Bidirectional
46	LED_1	Bidirectional
47	LED_0	Bidirectional
48	VDDA1P8	Power In
49	PAD	Power In

15.8.2 Hirose DF40C-100DS-0.4V (DF40C-100DS-0.4V)

Pin	Pin Name	Electrical
1	GND	Power In
2	GND	Power In
3	Ethernet_Pair3_P	Unknown
4	Ethernet_Pair1_P	Unknown
5	Ethernet_Pair3_N	Unknown
6	Ethernet_Pair1_N	Unknown
7	GND	Power In
8	GND	Power In
9	Ethernet_Pair2_N	Unknown
10	Ethernet_Pair0_N	Unknown
11	Ethernet_Pair2_P	Unknown
12	Ethernet_Pair0_P	Unknown
13	GND	Power In
14	GND	Power In
15	Ethernet_nLED3(3.3v)	Unknown
16	Ethernet_SYNC_IN(1.8v)	Unknown
17	Ethernet_nLED2(3.3v)	Unknown
18	Ethernet_SYNC_OUT(1.8v)	Unknown
19	Ethernet_nLED1(3.3v)	Unknown
20	EEPROM_nWP	Unknown
21	PI_nLED_Activity	Input
22	GND	Power In
23	GND	Power In
24	GPIO26	Bidirectional
25	GPIO21	Bidirectional
26	GPIO19	Bidirectional
27	GPIO20	Bidirectional
28	GPIO13	Bidirectional
29	GPIO16	Bidirectional
30	GPIO6	Bidirectional
31	GPIO12	Bidirectional
32	GND	Power In
33	GND	Power In
34	GPIO5	Bidirectional
35	ID_SC	Bidirectional
36	ID_SD	Bidirectional
37	GPIO7	Bidirectional
38	GPIO11	Bidirectional
39	GPIO8	Bidirectional
40	GPIO9	Bidirectional
41	GPIO25	Bidirectional
42	GND	Power In
43	GND	Power In
44	GPIO10	Bidirectional
45	GPIO24	Bidirectional
46	GPIO22	Bidirectional
47	GPIO23	Bidirectional
48	GPIO27	Bidirectional
49	GPIO18	Bidirectional
50	GPIO17	Bidirectional
51	GPIO15	Output
52	GND	Power In
53	GND	Power In
54	GPIO4	Bidirectional
55	GPIO14	Input
56	GPIO3	Bidirectional
57	SD_CLK	Input
58	GPIO2	Output
59	GND	Power In
60	GND	Power In
61	SD_DAT3	Bidirectional
62	SD_CMD	Bidirectional
63	SD_DAT0	Bidirectional
64	SD_DAT5	Passive
65	GND	Power In
66	GND	Power In
67	SD_DAT1	Bidirectional
68	SD_DAT4	Passive
69	SD_DAT2	Bidirectional
70	SD_DAT7	Passive
71	GND	Power In
72	SD_DAT6	Passive
73	SD_VDD_Override	Unknown
74	GND	Power In
75	SD_PWR_ON	Input
76	Reserved	Passive
77	+5v_(Input)	Power In
78	GPIO_VREF(1.8v/3.3v_Input)	Power In
79	+5v_(Input)	Power In
80	SCL0	Output
81	+5v_(Input)	Power In
82	SDA0	Bidirectional
83	+5v_(Input)	Power In
84	+3.3v_(Output)	Power Out
85	+5v_(Input)	Power In
86	+3.3v_(Output)	Power Out
87	+5v_(Input)	Power In
88	+1.8v_(Output)	Power Out
89	WiFi_nDisable	Power In
90	+1.8v_(Output)	Power Out
91	BT_nDisable	Power In
92	RUN_PG	Input
93	nRPIBOOT	Input
94	AnalogI_In1	Input
95	nPI_LED_PWR	Output
96	Analog_In0	Input
97	Camera_GPIO	Input
98	GND	Power In
99	PWRON_L	Input
100	nEXTRST	Input
101	TYPEC_USB2_OTG_ID	Input
102	PCIe_CLK_nREQ	Output
103	TYPEC_USB2_OTG_N	Bidirectional
104	PCIE_WAKEN	Output
105	TYPEC_USB2_OTG_P	Bidirectional
106	GPIO4A6	Output
107	GND	Power In
108	GND	Power In
109	PCIe_nRST_3V3_L	Output
110	PCIe_CLK_P	Output
111	RESERVED	Unknown
112	PCIe_CLK_N	Output
113	GND	Power In
114	GND	Power In
115	CAM1_RX_D0N	Input
116	PCIe_RX_P	Input
117	CAM1_RX_D0P	Input
118	PCIe_RX_N	Input
119	GND	Power In
120	GND	Power In
121	CAM1_RX_D1N	Input
122	PCIe_TX_P	Output
123	CAM1_RX_D1P	Input
124	PCIe_TX_N	Output
125	GND	Power In
126	GND	Power In
127	CAM1_RX_CLK0N	Input
128	CAM0_RX_D0N	Output
129	CAM1_RX_CLK0P	Input
130	CAM0_RX_DOP	Output
131	GND	Power In
132	GND	Power In
133	CAM1_RX_D2N	Input
134	CAM0_RX_D1N	Output
135	CAM1_RX_D2P	Input
136	CAM0_RX_D1P	Output
137	GND	Power In
138	GND	Power In
139	CAM1_RX_D3N	Input
140	CAM0_RX_CLK_N	Output
141	CAM1_RX_D3P	Input
142	CAM0_RX_CLK_P	Output
143	HDMI1_HPG	Unknown
144	GND	Power In
145	HDMI1_SDA	Unknown
146	HDM1_TX2_P	Unknown
147	HDMI1_SCL	Unknown
148	HDMI_TX2_N	Unknown
149	HDMI0_TX_ON_H	Output
150	GND	Power In
151	HDMI_TX0_CEC_M0	Output
152	HDMI_TX1_P	Unknown
153	HDMI_TX0_SBDN	Input
154	HDMI_TX1_N	Unknown
155	GND	Power In
156	GND	Power In
157	MIPI_DPHY0_TX_D0N	Output
158	HDMI1_TX0_SBDP	Output
159	MIPI_DPHY0_TX_D0P	Output
160	HDMI1_TX0_SBDN	Unknown
161	GND	Power In
162	GND	Power In
163	MIPI_DPHY0_TX_D1N	Output
164	HDMI1_CLK_P	Unknown
165	MIPI_DPHY0_TX_D1P	Output
166	HDMI1_CLK_N	Unknown
167	GND	Power In
168	GND	Power In
169	MIPI_DPHY0_TX_CLKN	Output
170	HDMI0_TX2_P	Output
171	MIPI_DPHY0_TX_CLKP	Output
172	HDMI0_TX2_N	Output
173	GND	Power In
174	GND	Power In
175	MIPI_DPHY1_TX_D0N	Output
176	HDMI0_TX1_P	Output
177	MIPI_DPHY1_TX_D0P	Output
178	HDMI0_TX1_N	Output
179	GND	Power In
180	GND	Power In
181	MIPI_DPHY1_TX_D1N	Output
182	HDMI0_TX0_P	Output
183	MIPI_DPHY1_TX_D1P	Output
184	HDMI0_TX0_N	Output
185	GND	Power In
186	GND	Power In
187	MIPI_DPHY1_TX_CLKN	Output
188	HDMI0_CLK_P	Output
189	MIPI_DPHY1_TX_CLKP	Output
190	HDMI0_CLK_N	Output
191	GND	Power In
192	GND	Power In
193	MIPI_DPHY1_TX_D2N	Output
194	MIPI_DPHY1_TX_D3N	Output
195	MIPI_DPHY1_TX_D2N	Output
196	MIPI_DPHY1_TX_D3N	Output
197	GND	Power In
198	GND	Power In
199	HDMI_TX0_SDA_M0	Bidirectional
200	HDMI0_SCL	Output
201	USB20_HOST1_DP	Bidirectional
202	TYPEC0_SSTX2P	Output
203	USB20_HOST1_DP	Bidirectional
204	TYPEC0_SSTX2N_	Output
205	GND	Power In
206	GND	Power In
207	TYPEC0_SBU1	Output
208	TYPEC0_SSRX2P	Input
209	TYPEC0_SBU2	Output
210	TYPEC0_SSRX2N	Input
211	GND	Power In
212	GND	Power In
213	USB20_HOST0_DP	Bidirectional
214	TYPEC0_SSTX1N	Output
215	USB20_HOST0_DM	Bidirectional
216	TYPEC0_SSTX1P	Output
217	GND	Power In
218	GND	Power In
219	TYPEC0_SSRX1N	Input
220	GPIO3_C6	Bidirectional
221	TYPEC0_SSRX1P	Input
222	PCIE20X1_2_CLKREQn_M0	Input
223	GND	Power In
224	PCIE20X1_2_PERSTn_M0	Passive
225	MIPI_DPHY1_RX_CLKP	Output
226	UART9_TX_M2_BT	Passive
227	MIPI_DPHY1_RX_CLKN	Output
228	UART9_RTSN_M2_BT	Output
229	GND	Power In
230	UART9_RX_M2_BT	Input
231	MIPI_DPHY1_RX_D1P	Output
232	GND	Power In
233	MIPI_DPHY1_RX_D1N	Output
234	GPIO3_B7	Bidirectional
235	GND	Power In
236	GPIO3_C5	Bidirectional
237	MIPI_DPHY1_RX_D0P	Output
238	GPIO3_C4	Passive
239	MIPI_DPHY1_RX_D0N	Output
240	UART9_CTSN_M2_BT	Input
241	GND	Power In
242	GMAC_TXD3	Bidirectional
243	GND	Power In
244	GPIO_1V8_6	Passive
245	GND	Power In
246	GPIO_1V8_7	Passive
247	GMAC1_TXD2/SDIO_D0_M1	Bidirectional
248	GND	Power In
249	GMAC1_TXD1/I2S2_MCLK_M1	Bidirectional
250	GPIO3_C1	Bidirectional
251	GMAC1_TXEN/I2S_SCLK_M1	Bidirectional
252	MIPI_CLK1	Bidirectional
253	GMAC1_MDIO/MIPI_TE1	Bidirectional
254	GND	Power In
255	GND	Power In
256	GMAC_RXD1/MIPI_CLK3	Bidirectional
257	GMAC1_MCLKINOUT/I2S2_LRCK_M1	Bidirectional
258	GMAC_RXCLK	Bidirectional
259	GMAC1_RXDV_CRS/MIPI_CAMERA4_CLK_M1	Bidirectional
260	GMAC_RXCLK	Bidirectional
261	GNDGMAC1_RXD2/SDIO_D2_M1	Bidirectional
262	GMAC_TXCLK	Bidirectional
263	GMAC1_RXD3/SDIO_D3_M1	Bidirectional
264	GND	Power In
265	GND	Power In
266	GPIO0_B0	Output
267	REFCLK_OUT	Output
268	I2S0_MCLK	Output
269	I2S0_SRLK	Output
270	I2S0_SDO0	Input
271	I2S0_SCLK	Output
272	GPIO3_C0	Bidirectional
273	I2S0_SDI0	Input
274	GND	Power In
275	GND	Power In
276	PCIE20_0_REFCLKP	Output
277	GPIO0_D5	Bidirectional
278	PCIE20_0_REFCLKN	Output
279	GPIO0_C7	Bidirectional
280	GND	Power In
281	GPIO0_D4	Bidirectional
282	PCIE20_0_TXP	Output
283	GPIO0_C4	Bidirectional
284	PCIE20_0_TXN	Output
285	GPIO0_D3	Bidirectional
286	GND	Power In
287	GND	Power In
288	PCIE20_0_RXN	Input
289	GPIO0_D0	Bidirectional
290	PCIE20_0_RXP	Input
291	GPIO3_C2	Bidirectional
292	GND	Power In
293	GPIO4_A3	Bidirectional
294	GPIO0_C5	Bidirectional
295	GPIO4_B3	Output
296	CLK32K_IN	Input
297	GPIO4_B2	Input
298	GPIO0_C6	Bidirectional
299	GND	Power In
300	GND	Power In

15.8.3 TPS62914QRPYRQ1 (TPS62914QRPYRQ1)

Pin	Pin Name	Electrical
1	PSNS	Power Out
2	NR/SS	Output
3	FB	Output
4	VO	Input
5	PG	Output
6	S-CONF	Output
7	EN/SYNC	Input
8	VIN	Input
9	PGND	Power Out
10	SW	Output
11	PGND	Power Out
12	VIN	Input
13	SW	Output
14	BOOT	Input

15.8.4 XPS62442QWRQRRQ1 (XPS62442QWRQRRQ1)

Pin	Pin Name	Electrical
1	FB2	Input
2	GND	Power Out
3	FB1	Input
4	PG1	Output
5	MODE/SYNC	Input
6	SW1	Input
7	VIN1	Power In
8	EN1	Input
9	GND	Power Out
10	EN2	Input
11	VIN2	Power In
12	SW2	Input
13	PG2	Output
14	COMP/FSET	Input