Power Supply and Serializer Design Analysis

1 Design Summary

1.1 Design Review: Functional Overview

This Altium 365 design implements the TI TIDA-050036 reference design — a compact automotive camera base board that pairs a TPS650330 power management IC (U1) with a DS90UB953-Q1 FPD-Link III serializer (U2). The board accepts raw power and MIPI CSI-2 video from a camera image sensor module through a 60-pin Samtec board-to-board connector (J1), locally regulates all required supply rails, serializes the camera data into a single FPD-Link III coaxial output through an SMA connector (J2), and provides I2C control back-channel access to both the PMIC and serializer from the host deserializer.

The design is a flat two-sheet schematic comprising 92 components (26 unique part types), 272 pins, and 64 nets. Five MIPI CSI-2 differential pairs (clock plus four data lanes) are annotated as impedance-controlled diff-pairs. The 60-pin connector carries power, ground, CSI-2 high-speed signals, GPIO, I2C, and image sync signals in a structured pinout with ground interleaving between the differential pairs. The SMA output connector is a Rosenberger 50-ohm unit with four ground pins surrounding the signal contact — appropriate for the FPD-Link III coaxial interface. There are 15 test points allocated across the design, with all six identified power rails covered, and several regulator feedback and GPIO signals instrumented. A single project variant (001) is defined that marks all test points, fiducials, and one resistor (R17) as DNP — suggesting a production variant that omits debug instrumentation.

1.2 Design Review: Power Supply Architecture

The power architecture is centered on the TPS650330 (U1), a multi-output automotive camera PMIC in a VQFN-24 package. This device integrates three synchronous buck converters and one LDO in a single IC, specifically designed for camera module applications where board space is at a premium. Input power arrives on the VDD_VIN rail, which is well-bypassed with a total of approximately 52 µF of bulk and decoupling capacitance (1×22 µF in 1206, 2×10 µF in 1206, and 1×0.1 µF in 0402).

The three buck converters use dedicated TFM201610ALMA series inductors: L1 (1.5 µH) for Buck 1 generating VDD_3V5 (3.5 V), and L2, L3 (1.0 µH each) for Buck 2 and Buck 3. The VDD_3V5 rail supplies the serializer analog domain and is bypassed with 2×10 µF (0805) plus 1×1 µF (0603). The VDD_1V8 rail (1.8 V) supplies the serializer digital core and VIO domain, carrying 11 pin connections and a 1×10 µF bypass capacitor. Each buck output feeds back through a 0-ohm series resistor (R1–R3) that provides a convenient Kelvin-sense insertion point and isolates the feedback node, with test points TP1, TP3, and TP9 placed at the FB pins for regulator output verification.

The PMIC's integrated LDO (VLDO, pin 24) provides an additional regulated output, bypassed by C11 and C12 (1 µF each) plus R4 (0 ohm series). The VREG internal regulator output (pin 13) is externally bypassed with C13 (1 µF) and has a 4.7 kΩ pull-up through R7 to the SEQ (sequencing) pin, which controls the power-up sequence. Boot-strap capacitor C1 (0.1 µF) connects between the BOOT pin and the LX_B1 switch node — standard for the PMIC's high-side gate driver.

The serializer (U2) requires multiple supply domains, each locally filtered with ferrite beads (0402 1 kΩ impedance @ 100 MHz — L4, L9–L13) and multi-stage decoupling. The VDDPLL domain (pins 10–11) uses 0.1 µF + 0.01 µF + 0.022 µF in a three-capacitor filter through L9. VDDD (pins 25–26), VDDDRV (pins 15–16), and VDDPLL_CAP each follow a similar pattern of ferrite bead followed by 10 µF bulk plus 0.1 µF and 0.01 µF local decoupling. This multi-stage filtering is consistent with TI's reference design recommendations for minimizing PLL jitter and serializer output noise.

1.3 Design Review: Findings and Observations

Unconnected Pins (17 flagged): The report identifies 17 unconnected pins. Fifteen of these are on J1 (the 60-pin board-to-board connector) and correspond to pins that are intentionally unused or reserved as NC in the connector pinout — the even-numbered pins between the differential pairs (30, 34, 36, 38, 40, 44, 46, 48, 50) plus pins 15, 20, 24, 26, and 28. These are benign and consistent with the design's ground-interleaved diff-pair allocation strategy across the connector. However, it would be good practice to add NO_ERC markers on these pins in the schematic to suppress the warnings and explicitly document intent. Two serializer pins — U2 pin 20 (CLKIN) and U2 pin 22 (RES1) — are also flagged as unconnected. CLKIN being unconnected is expected when the DS90UB953 is operating in CSI-2 forwarded-clock mode rather than external reference clock mode. RES1 should be verified against the DS90UB953 datasheet; TI typically specifies this as a reserved pin that must be left unconnected, so this is likely correct but warrants explicit confirmation.

I2C Bus — Missing Test Points: The LSSI analysis correctly identifies that neither I2C_SCL nor I2C_SDA has a dedicated test point. The I2C bus connects U1 (PMIC) and U2 (serializer) and is accessible through J1 pins 49 and 51, with 4.7 kΩ pull-ups (R11, R12) properly present. While J1 provides functional access to the bus from the host side, dedicated test points on the local I2C traces would allow in-circuit test (ICT) probing, bus quality verification (rise-time, signal integrity), and independent device addressing during board-level debug — particularly useful if the board-to-board connector is not mated during initial power-on characterization.

FPD-Link III Output Path: The serializer's DOUT+/DOUT- outputs (U2 pins 14, 13) pass through an AC-coupling and common-mode filter network before reaching the SMA connector. DOUT+ is AC-coupled through C14 (0.033 µF), then passes through a three-stage ferrite bead chain (L6→L7→L8, all 0603 1500 ohm) before reaching a 10 µH inductor (L5) that provides the DC bias injection path. The series resistors R9 (4.02 kΩ) and R10 (49.9 Ω) establish the correct back-termination and bias network. DOUT- is AC-coupled through C17 (0.015 µF) and terminated through R10. This network topology is consistent with TI's FPD-Link III application notes for coaxial cable transmission in automotive camera applications.

Library Model Quality: The U2 (DS90UB953-Q1) library model receives only a Grade C rating due to 17 of 33 pins being typed as Passive. Pins such as CSI_D0P/N, CSI_CLKP/N, MODE, PDB, RES0, RES1, LPF1, LPF2, and CLKIN would benefit from more specific electrical type assignments (Input for CSI data/clock receivers, Input for mode-select pins, etc.). This does not affect the physical design but limits the effectiveness of automated ERC checks. Similarly, U1's SCL pin is typed as Passive rather than Open-Drain/Bidirectional which is technically what an I2C clock pin should be. These library refinements would improve the model grade and enable more rigorous automated design rule checking.

EMC and Grounding: The EMC check for connector shell grounding passes — the SMA connector J2 has four ground pins (2–5) connected to DGND, providing proper RF return path for the FPD-Link III output. The 60-pin connector J1 has generous ground pin allocation (pins 5, 6, 11, 12, 18, 21, 22, 27, 32, 37, 42, 47, 52) interleaving the high-speed differential pairs, which is appropriate for controlled-impedance connector transitions.

Variant Configuration and Testability: A single Altium 365 variant (001) designates all 15 test points plus fiducials and R17 as DNP. R17 sits in the 953_GPIO3/IMG_VSYNC path, so removing it in production disconnects the image sensor VSYNC from the serializer's GPIO3. This suggests the variant is a stripped production build where debug instrumentation and certain optional signal connections are removed for cost reduction. For a production board where ICT is planned, the DNP of all test points in the variant should be carefully reconsidered — the power rail test points at minimum (TP1–3, TP5, TP9–15) provide essential coverage for power supply verification during manufacturing test.

1.4 Processed Sheets

1.5 Table of Variants

2 Component Value Properties

Component values should be in VALUE property (or typed fields like Capacitance/Resistance/Inductance). Values in the comment field affect BOM generation and parameter queries.

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

3.2 Implied/Hidden Net Connections

No components with implied/hidden net connections found.

3.3 Summary

4 Power Overview

5 Connector Pinouts

5.1 J1 Receptacle_30x2_LeftRight (I2C)

5.2 J2 SMA_Contact1_GND2345

6 Indicator Documentation

7 Switch Documentation

8 Designer Annotated Nets

Designer-added point markers indicating special routing or handling requirements. Differential pairs are shown combined.

9 Low-Speed Serial Interfaces (LSSI)

Detected: 1 I2C

9.1 I2C

9.2 LSSI DFT Analysis

10 High-Speed Serial Interfaces (HSSI)

8 differential pair(s)

10.1 Differential Pairs

Differential pairs with designer-specified class annotations.

11 Memory Interface Analysis

12 EMC Design Checks

13 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

13.1 Power Rail Test Point Check

13.2 Kelvin Test Points Check

No current sense resistors found in range (0 < R < 1.0 ohm).

13.3 Test Point Report

13.3.1 Test Points by Sheet

13.3.2 All Test Points

13.4 Boundary Scan Testability

14 Model Quality

Schematic symbol and library model quality analysis.

14.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

14.1.1 Library Quality Summary

14.2 Component Library Validation

14.3 Shielded Connector Model Quality

14.4 Footprints and Other Models

14.5 IC Pin Electrical Properties

14.5.1 CMP-0080054-3

14.5.2 DS90UB953-Q1