psu-ext Design Analysis

1 Design Summary

out of 100

Depth of review, as a baseline: 123 verified datasheet parameters applied and 238 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

Design Type	Hierarchical (6 sheets)
Total Components	138
Total Pins	414
Total Nets	79
Total Test Points	0
Not Fitted (DNP)	10

Improve your score:

Improve fault coverage (opens/shorts) +4
Add test points on indicator signals +1
Add test points on switch signals +1
Improve JTAG/I2C/SPI bus accessibility +1
Move component values to VALUE property +1
Add ordering part numbers to resistors, inductors and capacitors +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1
Add test points on OE/enable pins +1
Add Kelvin 4-wire test points on sense resistors +1

Points deducted for open High/Medium AI findings:

0 High, 4 Medium -2

AI findings to review:

Power findings — 1 Low, 19 Review
HSSI findings — 7 Review
Memory findings — 2 Low, 6 Review
Functional findings — 3 Medium, 18 Review
EMC/ESD findings — 1 Medium, 4 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 21 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

The inserted test point count is unusually high because Optical (AOI) and X-ray (AXI) inspection contributes no coverage — none of the footprint names are recognized as IPC-7351B or IPC-7251 compliant. Repair the library footprint names to follow IPC naming and resubmit; the inserted test point count will drop to typical levels.

1.1 Design Overview

AI-Assisted — The board is built around an ESP32-S3-WROOM-1 module (U5), a 240 MHz Wi-Fi/Bluetooth SoC rated from -40 to 85 °C (Espressif datasheet, source: Tomachie). A W25Q16JVSS 16 Mbit SPI flash (U6) provides external non-volatile storage. A 32.768 kHz crystal (Y1) supplies the low-frequency clock.

Measurement Front End

An ADS1115IDGS 16-bit, 860 SPS ADC (U8) sits at I2C address 0x48. It has a selectable full-scale range from ±0.256 V to ±6.144 V (Texas Instruments datasheet, http://www.ti.com/lit/ds/symlink/ads1113.pdf).

An INA240A2D current-sense amplifier (U10) has a gain of 50 V/V and a -4 V to 80 V common-mode range (Texas Instruments datasheet, http://www.ti.com/lit/ds/symlink/ina240.pdf). TSZ122 and LM321 op-amps condition the voltage channel. An LM2664 charge pump generates the -3V3 rail.

Isolation

An ISO1540 I2C isolator (U7) extends a second I2C bus to J2. It is rated 2500 VRMS per UL 1577 (Texas Instruments datasheet, http://www.ti.com/lit/ds/symlink/iso1541.pdf). The isolated side is powered by an RFM-0505S 1 W isolated converter (PS1), which provides a 1 kVDC withstand (RECOM datasheet, https://www.mouser.com/datasheet/2/468/RFM-1307831.pdf).

Power Tree

Input power enters through the USB Type-C receptacle J1, which has USBLC6-2SC6 ESD protection. The AP22818 current-limited switch U2 sources the VUSB rail. Two LD1117S33 regulators produce the supply rails:

- U3 sources V3.3.
- U4 sources V3.3-F.

The board also carries the +5V, V5-F and -3V3 rails, with the GND, GNDS and PGND ground domains.

User Interface and I/O

User I/O comprises two push buttons, five LEDs and an HF49FD 5 V relay (K1) driven through an MMBT2222A transistor (Q1). SMBJ36A TVS diodes guard the external inputs.

1.2 Processed Sheets

#	Sheet Name
1	psu-ext.kicad_sch
2	usb.kicad_sch
3	power.kicad_sch
4	esp32.kicad_sch
5	front-end-adc-c.kicad_sch
6	front-end-voltage.kicad_sch

1.3 Structured DNP (Not Fitted)

Parts marked do-not-populate at the part level, outside of assembly variants. They remain present in the netlist but are not assembled.

Status	RefDes	Part Type	Value	Footprint
DNP	C17	100nF	100nF	Capacitor_SMD:C_0805_2012Metric
DNP	C19	100nF	100nF	Capacitor_SMD:C_0805_2012Metric
DNP	C25	1nF	1nF	Capacitor_SMD:C_0805_2012Metric
DNP	D9	ESD5Zxx	ESD5Zxx	Diode_SMD:D_SOD-523
DNP	D10	B5817W	B5817W	Diode_SMD:Nexperia_CFP3_SOD-123W
DNP	D11	SMBJ36A	SMBJ36A	Diode_SMD:D_SMB
DNP	D12	SMBJ36A	SMBJ36A	Diode_SMD:D_SMB
DNP	R19	10k	10k	Resistor_SMD:R_0805_2012Metric
DNP	R20	10k	10k	Resistor_SMD:R_0805_2012Metric
DNP	U6	W25Q16JVSS	W25Q16JVSS	Package_SO:SOIC-8_5.3x5.3mm_P1.27mm

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
18 SMT footprints do not follow IPC-7351B naming
3 footprints (connectors, specialty) — compliance unknown
3 footprints could not be classified for inspection

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	33	C31, C30, C36, C35, C34, C37, C32, C38 (+25 more)	✓
Capacitors	VALUE holds both the capacitance and a voltage rating (e.g. "0.1uF 50V", "10uF 6.3V"). Tomachie has already separated the two and uses the capacitance as the value, so the analysis and the AI read a clean magnitude and are not misled by the embedded rating — the misinterpretation risk is low. This is a cleanliness note, not a parsing failure: to keep the schematic self-describing and safe for downstream BOM/ICT/AOI tools that read VALUE literally, move the voltage into a dedicated Voltage property. (C8 currently has VALUE="330p 1kV")	2	C8, C7
Resistors	Values in VALUE or Resistance	43	R37, R45, R38, R36, R39, R40, R41, R42 (+35 more)	✓
Crystals	Values in VALUE or Frequency	1	Y1	✓

2.1 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the MANUFACTURER part number. This check decodes the manufacturer part number and compares the two. A distributor catalogue number is a different thing and cannot be used here - an LCSC C-number or a Digi-Key -ND number identifies a stock item, it encodes no capacitance, voltage or tolerance, so there is nothing in it to check against. Where the two readings disagree both are shown and neither is assumed correct: if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose numbering scheme is not recognized are reported as not checked rather than passed.

78 of 78 fitted resistor/inductor/capacitor part(s) carry no ordering part number: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C18, C20, C21, C22 (+58 more). Without a part number the BOM cannot state what to buy, and none of the part-number cross-checks in this section can run for these parts. Add a manufacturer part number to each part in the library.

2.2 Capacitor Derating Check

Derating profile	industrial_default
Maximum ambient	85 °C
Checks performed	0

A capacitor is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Every other derating check - for capacitors and for every other part class - is applied by the AI analysis within its report sections.

21 part(s) sit across a resolved power rail with no stated voltage rating and could not be checked: C1, C10, C11, C12, C13, C2, C20, C22, C23, C24, C26, C28, .... Record each rating in a Voltage property.

Derating Settings Used in This Analysis
Parameter	Value	Source	Applied
capacitor_voltage_pct	20% (80)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_voltage_pct	30% (70)	SD-18	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_mno2_voltage_pct	60% (40)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	40% (60)	ECSS	Applied by the AI analysis where the rating is in evidence
capacitor_temperature_margin_c	20 °C	ECSS, EEE-INST-002, SD-18	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_temperature_margin_c	25 °C	SD-18	Applied by the AI analysis where the rating is in evidence
resistor_power_pct	45% (55)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	25% (75)	ECSS, EEE-INST-002	Applied by the AI analysis where the rating is in evidence
resistor_temperature_margin_c	25 °C	ECSS, EEE-INST-002, SD-18	Applied by the AI analysis where the rating is in evidence
diode_reverse_voltage_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_average_forward_current_pct	35% (65)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_power_dissipation_pct	50% (50)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_margin_c	40 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_cap_c	110 °C	ECSS, EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_vds_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_vgs_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_continuous_current_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_junction_temperature_margin_c	40 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_junction_temperature_cap_c	110 °C	ECSS, EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_vce_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_continuous_current_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_junction_temperature_margin_c	40 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_junction_temperature_cap_c	110 °C	ECSS, EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_input_voltage_pct	15% (85)	ECSS, EEE-INST-002	Applied by the AI analysis where the rating is in evidence
regulator_output_current_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_power_dissipation_pct	50% (50)	EEE-INST-002, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_margin_c	40 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_cap_c	100 °C	ECSS, EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_output_current_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_power_dissipation_pct	50% (50)	EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_margin_c	40 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_cap_c	100 °C	ECSS, EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
connector_current_per_contact_pct	40% (60)	ECSS, EEE-INST-002, MIL-STD-1547B	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
connector_temperature_margin_c	20 °C	ECSS, EEE-INST-002, MIL-STD-1547B	Applied by the AI analysis where the rating is in evidence
relay_contact_current_resistive_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
relay_temperature_margin_c	25 °C	SD-18	Applied by the AI analysis where the rating is in evidence
tvs_junction_temperature_margin_c	40 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
tvs_junction_temperature_cap_c	110 °C	ECSS, EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
switch_contact_current_resistive_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B	Applied by the AI analysis where the rating is in evidence

2.3 Part Lifecycle and Silicon Errata

Status as found on the manufacturer's website by the AI enrichment run, on the date shown; the page read is linked. Silicon errata: whether the manufacturer publishes an errata sheet for the part - its presence only. No errata document is read or analysed, and no action is implied by its existence.

Item	Lifecycle	Silicon errata	Status
K1 (HF49FD_005-1H12T)	Datasheet could not be obtained, so the lifecycle status (NRND / obsolete) could not be determined	—	Review
U8 (ADS1115IDGS)	The lifecycle status (NRND / obsolete) for this part is indeterminate from the datasheet - please review	Not determined	Review
D5, D6, D7, D8, D9 (ESD5Zxx)	Lifecycle status (NRND / obsolete) could not be determined	—	Review
D10 (B5817W)	No NRND / obsolete marking on the datasheet obtained 2026-09-18	—
D11, D12, D13 (SMBJ36A)	No NRND / obsolete marking on the datasheet obtained 2026-09-19	—
D15 (LL4148)	No NRND / obsolete marking on the datasheet obtained 2026-09-18	—
PS1 (RFM-0505S)	No NRND / obsolete marking on the datasheet obtained 2026-09-18	—
Q1 (MMBT2222A)	Active, as of 2026-09-18	—
U1 (USBLC6-2SC6)	Active, as of 2026-09-22	None found on the manufacturer's website, as of 2026-09-22
U2 (AP22818AKEWT)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U3, U4 (LD1117S33)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U5 (ESP32-S3-WROOM-1)	No NRND / obsolete marking on the datasheet obtained 2026-08-30	Errata sheet published: ESP32-S3 Series SoC Errata
U6 (W25Q16JVSS)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U7 (ISO1540)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U9 (LM321)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U10 (INA240A2D)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U11 (TSZ122IYDT)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
U12 (LM2664M6)	Active, as of 2026-09-18	None found on the manufacturer's website, as of 2026-09-18
Y1 (FC-135_32.7680KA-A0)	No NRND / obsolete marking on the datasheet obtained 2026-09-18	—

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

7 unconnected pin(s) found:

7 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
U5_12	IO8	Bidirectional	ESP32-S3-WROOM-1	-	No net
U5_17	IO9	Bidirectional	ESP32-S3-WROOM-1	-	No net
U5_18	IO10	Bidirectional	ESP32-S3-WROOM-1	-	No net
U5_32	IO39	Bidirectional	ESP32-S3-WROOM-1	MTCK
U5_33	IO40	Bidirectional	ESP32-S3-WROOM-1	MTDO
U5_34	IO41	Bidirectional	ESP32-S3-WROOM-1	MTDI
U5_35	IO42	Bidirectional	ESP32-S3-WROOM-1	MTMS

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden pins of any electrical type stacked behind visible pins in the symbol.

Implied Net Connections
Component	Type	Pin	Net	Status
U5	ESP32-S3-WROOM-1	40 (GND)	GND	Fail — hidden pin not visible on schematic
U5	ESP32-S3-WROOM-1	41 (GND)	GND	Fail — hidden pin not visible on schematic
U10	INA240A2D	4 (GND)	GNDS	Fail — hidden pin not visible on schematic
J1	TYPE-C-31-M-12	B1_A12 (GND)	GND	Fail — hidden pin not visible on schematic
J1	TYPE-C-31-M-12	B4_A9 (VBUS)	+5V	Fail — hidden pin not visible on schematic
J1	TYPE-C-31-M-12	S3 (SHIELD)	GND	Fail — hidden pin not visible on schematic
J1	TYPE-C-31-M-12	S2 (SHIELD)	GND	Fail — hidden pin not visible on schematic
J1	TYPE-C-31-M-12	S4 (SHIELD)	GND	Fail — hidden pin not visible on schematic

3.3 Open-Collector Pull-up Audit

Examined 1 candidate pin(s) on 1 net(s). 1 to verify with destination IC.

Finding	Recommended Action	Severity
Open-collector / open-drain outputs need an external pull-up resistor to a power rail to function. This audit lists pins where a pull-up appears to be missing or where the pin type may not match the schematic library.
U2_3 (FLG) on Net-(U2-FLG) U2 (AP22818AKEWT) Current limited 2.0A power switch, single channel, SOT-23-5 test point TP2 · library: Open Collector	Information: this net may be missing a pull-up. The destination IC (MCU/FPGA/other) may enable a configurable internal pull-up — verify its datasheet/BSDL. If none, add an external pull-up to a power rail.	Review

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires that pin 1, the cathode, is on the left with the footprint at zero rotation. Tomachie will call out schematic-symbol problems that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, or a novice may wrongly indict a correct part — keeping consistent is the least-expensive path for everyone who handles the PCB.
D15 LL4148 unidirectional · pin_names · Flyback Protection	Pin 1 (K): VUSB Pin 2 (A): Net-(D14-K)	Consistent
D12 SMBJ36A unidirectional · pin_names	Pin 1 (K): SENSE_N Pin 2 (A): GNDS	Consistent
D13 SMBJ36A unidirectional · pin_names	Pin 1 (K): PSU_P Pin 2 (A): PGND	Consistent
D10 B5817W unidirectional · pin_names · Schottky Rectifier	Pin 1 (K): GNDS Pin 2 (A): Net-(D10-A)	Consistent
D11 SMBJ36A unidirectional · pin_names	Pin 1 (K): SENSE_P Pin 2 (A): Net-(D10-A)	Consistent
D6 ESD5Zxx unidirectional · pin_names	Pin 1 (K): Net-(D6-K) Pin 2 (A): GND	Consistent
D8 ESD5Zxx unidirectional · pin_names	Pin 1 (K): Net-(D8-K) Pin 2 (A): GND	Consistent
D5 ESD5Zxx unidirectional · pin_names	Pin 1 (K): Net-(D5-K) Pin 2 (A): GND	Consistent
D7 ESD5Zxx unidirectional · pin_names	Pin 1 (K): Net-(D7-K) Pin 2 (A): GND	Consistent
D9 ESD5Zxx unidirectional · pin_names	Pin 1 (K): V3.3 Pin 2 (A): GND	Consistent

3.5 Polarized Capacitor Orientation

Capacitor	Connections	Polarity	Severity
Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
C3	Pin 1 (+): VUSB Pin 2: GND
C9	Pin 1 (+): V5-F Pin 2: GNDS

3.6 Checks Not Performed

Items this report did not check, with the reason. None of these is a finding against the design - an item that was not checked says nothing about it either way.

Checks the AI review could not perform are listed at Review severity in each AI section's Findings table, each naming the input that was missing.

Item	Not checked	Notes
Part Number vs Stated Values	The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.
Capacitors and resistors (datasheets and parameter curves)	Datasheets for capacitors and resistors, and the parameter curves they carry (ripple current, derating against temperature, DC bias, a jumper's temperature rise), are obtained on the premium tier only. This standard-tier run reads a datasheet already on file and otherwise states no rating for these parts.
Part lifecycle (NRND / obsolete)	The lifecycle status (NRND / obsolete) for this part is indeterminate from the datasheet - please review

3.7 Summary

Total NO_ERC markers in design	12
Pins needing attention (warnings)	7
Pins for information only	0

4 Power Overview

Power rails	9
Power management sources identified	4

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
Rail	Voltage	Source	Consumers
+5V	5.00V	J1 External	U1 (USBLC6-2SC6), U2 (AP22818AKEWT)
GND	-	J1 External	-
GNDS	-	-	-
PGND	-	-	-
V3.3	-	U3 LD1117S33	U5 (ESP32-S3-WROOM-1), U6 (W25Q16JVSS), U7 (ISO1540)
V3.3-F	-	U4 LD1117S33	U10 (INA240A2D), U11 (TSZ122IYDT), U12 (LM2664M6), U7 (ISO1540), U8 (ADS1115IDGS), U9 (LM321)
V5-F	-	-	U4 (LD1117S33)
VUSB	-	U2 AP22818AKEWT	U3 (LD1117S33)
-3V3	-3.30V	-	U12 (LM2664M6)

4.2 Regulator Enable Pull Resistors

1 regulator enable pin(s) examined for what drives them and which way they are pulled. 0 pulled toward the enabling level while a power output drives the net.

Regulator	Enable pin	Net	Driven by	Pull-up	Pull-down	Finding	Severity
U2 [AP22818AKEWT]	U2_4 (EN) (enabled high)	Net-(U2-EN)	-	R5 10k -> +5V	-	No driver on the net; the pull resistor sets the level.	Information

4.3 Galvanic Isolation Barriers

1 isolated return(s) share parts with the reference ground GND. The potential each isolated side can reach relative to GND is not stated by the schematic and is asked together with the rail voltages; every part spanning a barrier is judged against that answer once its datasheet has been read.

Isolated ground	Recognised by	Two-pin parts between the grounds	Parts with a pin on each ground	Connectors	Far-side potential
GNDS	its ground symbol name	C8: C8_2 \| C8_1	PS1 [RFM-0505S]: PS1_3 (-VOUT) \| PS1_1 (-VIN); U7 [ISO1540]: U7_5 (GND2) \| U7_4 (GND1)	-	not stated (asked with the rail voltages)

4.4 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.4.1 Power Tree Overview

AI-Assisted — All power enters on the USB Type-C receptacle J1. VBUS arrives on +5V, which carries 1µF (C1), the USBLC6-2SC6 (U1) VBUS pin, and the D1 indicator LED with its 1k (R3) resistor. CC1 and CC2 each return to GND through 5.1k (R1, R2), so the board presents as a Type-C sink. It does not read the source's current advertisement.

The AP22818A current-limited switch U2 passes +5V to VUSB. VUSB feeds three things:
- the LD1117S33 U3, which makes V3.3 (3.3 V fixed) for the ESP32-S3-WROOM-1 (U5), the side-1 supply of the ISO1540 (U7), and the flash U6, which is do-not-install;
- the RECOM RFM-0505S isolated converter PS1;
- the K1 relay coil and its Q1/D15/D14 driver.

PS1 produces V5-F, an unregulated nominal 5 V referenced to GNDS. The second LD1117S33, U4, regulates V5-F down to V3.3-F (3.3 V fixed) for the isolated analog front end: U10, U11, U8, U9, U7 side 2, and U12. The LM2664 U12 inverts V3.3-F into -3V3.

No rail carries a designer voltage annotation except +5V. Every other level follows from its source: VUSB is +5V less U2's channel drop, V3.3 and V3.3-F come from fixed 3.3 V regulators, V5-F is PS1's nominal 5 V output, and -3V3 is the inverted V3.3-F.

No enable or power-good signal is used for sequencing. U2's EN is pulled to +5V, so every rail rises together once VBUS is present:
- U2 soft-starts VUSB (0.6 ms typical rise, Diodes Incorporated datasheet https://www.diodes.com/assets/Datasheets/AP22816_17_18.pdf);
- U3 and PS1 follow VUSB;
- U4 follows V5-F;
- U12 follows V3.3-F.

The U2 input and output pins, U3, U4, U12 and PS1 all have their supply and ground pins on sourced rails and ground nets. None depends on a capacitor-only net.

4.4.2 USB Input and AP22818A Load Switch (U2)

AI-Assisted — U2 is always enabled. R5 (10k) ties Net-(U2-EN) to +5V, which holds EN at VIN. That is above the 1.5 V VIH and within the VIN+0.3 V absolute maximum (Diodes Incorporated datasheet).

Capacitor provision matches the datasheet guidance:
- The datasheet asks for 1uF low-ESR on IN; C1 is 1µF on +5V.
- The datasheet asks for 0.1uF plus at least 10uF on OUT in USB applications. U2's own output capacitance on the usb sheet is C2 100nF plus C3 47µF.

Inrush is within the current limit. The whole VUSB group totals 57.2µF. At the fastest stated 0.6 ms rise it draws I = C·dV/dt = 57.2µF × 5 V / 0.6 ms = 0.48 A. That is below the 2.2 A minimum overload current limit.

~FLG is open-drain. It pulls toward +5V through R4 (1k) and the D2 LED, so D2 lights on an overcurrent or overtemperature fault. The fault sink current is bounded by 5 V / 1k = 5 mA; the LED forward voltage is not subtracted, so the real current is lower. At the 60 Ω maximum on-resistance this gives at most 0.3 V at FLG. TP2 reads the flag directly.

The current through U2 was built from datasheet figures:
- U3 input: 517 mA. This is the 0.5 A supply capability the Espressif datasheet (source: Tomachie) requires for U5, plus U7 VCC1 at 7.1 mA maximum, plus the LD1117 10 mA maximum quiescent current.
- PS1: 250 mA maximum input current.
- D14 path: at most 5.25 mA.

This totals 0.77 A before the K1 coil, whose current is not in the data. Against the 2.0 A rating derated 30% to 1.4 A (regulators and converters, output current, at most 70%), 0.63 A remains for the coil.

Conduction loss is 0.77² × 95 mΩ = 56 mW. With the stated 123 C/W junction-to-ambient figure, that is a 7 C rise, or 92 C at the 85 C design ambient. This is under the 100 C junction limit, although the 95 mΩ figure is stated at 25 C and excludes the coil current.

4.4.3 LD1117S33 3.3 V Regulator (U3, V3.3)

AI-Assisted — U3 takes VI from VUSB and GND from GND, and VO drives V3.3. The regulator's own output capacitance on the power sheet is C5, a 10µF 1206 ceramic. It is a nominal value; DC-bias loss is not applied. The LD1117S33 datasheet (https://www.sm0vpo.com/_pdf/LM/LM1117.PDF) states no minimum output capacitance or ESR window, so loop stability cannot be judged against a requirement. C12 10µF and C13 100nF on the esp32 sheet, and C20 100nF on the front-end-adc-c sheet, decouple their loads.

Output current meets the derated rating:
- Design load: 507 mA, being the Espressif 0.5 A supply requirement for U5 plus 7.1 mA for U7 VCC1.
- Rating: 800 mA minimum output current, derated 30% (regulators and converters, output current, at most 70%) to 560 mA.

Input headroom is adequate at the worst end of the dropout band:
- Maximum dropout at 500 mA is 1.2 V.
- The datasheet guarantees 3.24–3.36 V at 4.5 V input for 0–500 mA.
- VUSB sits 0.07 V below VBUS, which is 0.77 A through 95 mΩ in U2.
- The input requirement is therefore met for VBUS down to about 4.6 V, under the 4.75 V USB 2.0 minimum.

The V3.3 window of 3.24–3.36 V sits inside the 3.0–3.6 V supply range of U5 and the 3–5.5 V range of U7.

Dissipation at the 5.25 V top of the USB band is (5.25 − 3.3) × 0.507 A + 5.25 V × 10 mA = 1.04 W. The datasheet gives only θJC of 15 C/W, with no junction-to-ambient figure or package power rating. The junction temperature is therefore not computed, and it depends entirely on the copper under the SOT-223 tab.

4.4.4 Isolated Supply: RFM-0505S (PS1) and LD1117S33 (U4, V3.3-F)

AI-Assisted — PS1 connections:
- +VIN is on VUSB and -VIN on GND.
- +VOUT drives V5-F and -VOUT drives GNDS.
- VUSB lies within the 5 VDC ±10% nominal input (RECOM datasheet https://www.mouser.com/datasheet/2/468/RFM-1307831.pdf).

PS1 capacitor provision:
- The V5-F capacitance is 47.1µF: C9 47µF electrolytic and C10 100nF. This is well under the 470 µF maximum capacitive load.
- C7 and C8, both 330pF 1kV, match the 330pF/1kV output capacitors the datasheet suggests for EN55032 Class B. C7 is connected between VUSB and V5-F, and C8 between GND and GNDS.
- On the input, C6 10µF and C3 47µF cover the suggested 10µF, but the 22µH series inductor shown for Class B is not fitted.

V5-F is unregulated. The load regulation band is ±10% typical and ±15% maximum, over 10% to 100% load.

V3.3-F known load is 13.3 mA:
- U10 2.6 mA and U7 VCC2 6.7 mA.
- U8 0.3 mA and U9 1.2 mA. The U9 figure is the 5 V row, used as a bound.
- U11 0.08 mA and U12 quiescent 0.5 mA.
- The R30/R31 divider 0.14 mA and the worst-case pull-ups 1.73 mA.

U12's output load is unknown. Even at its 50 mA continuous maximum, U4 supplies about 63 mA, far below the 560 mA derated rating.

PS1 therefore runs at about 23 mA, roughly 12% of its 200 mA (1 W at 5 V) rating. That is close to the 10% floor of its regulation specification.

U4 input headroom:
- U4 needs 4.4 V: 3.3 V plus the 1.1 V maximum dropout at 100 mA.
- The −15% end of PS1's band is 4.25 V.
- At this light load the output sits toward the upper end of the band, but no load curve is given.

U4 dissipation is at most (5.75 − 3.3) × 0.063 A + 5.75 V × 10 mA = 0.21 W, with no θJA available.

U4 connections and capacitors:
- VI is on V5-F, GND on GNDS, and VO on V3.3-F.
- Its own output capacitor is C11, 10µF ceramic, returned to GNDS; this is a nominal value.
- Six 100nF capacitors plus C35 22µF sit beside the front-end loads.

V3.3-F at 3.24–3.36 V clears every load's stated minimum supply. The tightest are 3 V for U9 (LM321) and 3 V for U7 VCC2.

4.4.5 LM2664 Negative Rail (U12, -3V3)

AI-Assisted — U12 takes V+ from V3.3-F, which is within its 1.8–5.5 V input range (TI datasheet https://www.ti.com/lit/ds/symlink/lm2664.pdf). GND is on GNDS. SD is tied to V3.3-F, which is the datasheet's stated connection for normal operation ("tie to V+").

The output capacitance on -3V3 is 44µF, from C37 and C38 at 22µF each (0805 ceramic, nominal, no DC-bias loss applied). The datasheet test circuit uses a 3.3 µF, 0.3 Ω output capacitor. That is an application figure, not a minimum. The larger ceramic value lowers output ripple and lengthens start-up, and needs no change.

The flying capacitor between CAP+ and CAP- could not be assessed, so its value is not compared with the 3.3 µF test value.

The -3V3 load is R42 and R43 (20k each) into the U11 inverting inputs. Its current depends on the U11 operating point, which is not known. The 50 mA continuous output limit was used as the bounding figure in the U4 budget.

4.4.6 Isolation Barrier Between GND and GNDS

AI-Assisted — GNDS is the isolated return of the analog front end. Three parts connect across it:
- C8 (330pF 1kV) is connected between the two grounds.
- PS1 has a pin on each ground. The RECOM datasheet states 1 kVDC input-to-output, tested for 1 second.
- U7 has a pin on each ground. The TI datasheet (http://www.ti.com/lit/ds/symlink/iso1541.pdf) states 2500 V RMS, UL 1577, and 4242 V peak, DIN EN IEC 60747-17 (VDE 0884-17). The library's 2.5 kVrms agrees.

C7 (330pF 1kV) is additionally connected between VUSB and the isolated V5-F rail.

C7 and C8 have no datasheet and carry only a designer-stated 1kV voltage property, with no safety class. They are therefore unrated as barrier members.

The barrier protects up to at most 1 kVDC, set by PS1. Converted to the RMS regime, that is 707 V RMS (1000 / 1.414), against U7's 2500 V RMS. The figure is bounded above: C7 and C8 state no isolation class, so the true ceiling can only be lower.

No far-side potential and no withstand design goal is stated. The question is open: how much protection must this barrier give, as a continuous far-side voltage and as a transient withstand?

Mechanical fixings also touch both grounds:
- H1 and H2 are on GND.
- H3 and H4 are on GNDS.
- H10 and H11 are on PGND, which the 0R link R29 joins to GNDS.

If these plated holes share conductive standoffs or a metal enclosure, GND and GNDS are joined through the hardware and the barrier is shorted.

4.4.7 Relay Driver and Switched Load Path

AI-Assisted — K1 is a HF49FD_005-1H12T. The part number decodes to a 5 VDC coil, which matches VUSB. Q1 (MMBT2222A) switches the coil low side. D15 (LL4148) is the flyback clamp, with cathode on VUSB and anode on Net-(D14-K); this orientation is consistent. The D14 LED with R32 (1k) indicates coil drive and is bounded at 5.25 mA.

Q1 collector-emitter voltage:
- Off-state VCE is at most about 6.3 V: VUSB at 5.25 V plus the D15 1 V maximum forward voltage at 50 mA (Vishay datasheet http://www.vishay.com/docs/85557/ll4148.pdf).
- The 40 V VCEO (Nexperia datasheet https://assets.nexperia.com/documents/data-sheet/MMBT2222A.pdf) derated 30% (bipolar transistors, VCEO, at most 70%) permits 28 V.

D15 reverse voltage: its 100 V VRRM derated 30% permits 70 V against 5.25 V.

The coil current is not stated, so Q1 collector current and D15 forward current are not closed.

The switched path from PSU_P to LOAD_P powers nothing on the board. It is rated 12 V DC nominal, 0–25 V operating, 30 V survive, and 2.5 A. The K1 contact rating comes from its part description, 5A/30VDC:
- Contact current: 5 A derated 40% (relays, contact current, at most 60%) permits 3 A against 2.5 A.
- Contact voltage: the 30 VDC rating, taken without derating, meets the 25 V operating top and the 30 V survive level.

D13 (SMBJ36A, Kyocera AVX datasheet https://datasheets.kyocera-avx.com/tvsdiodes.pdf) clamps PSU_P to PGND. Its 36 V standoff, taken from the part number, stays non-conducting at the 30 V survive level. Its cathode is on PSU_P and its anode on PGND, which looks consistent for a positive rail. The datasheet pin numbering is unconfirmed, so this orientation needs checking. The datasheet entry gives no clamping voltage for the 36 V part.

4.5 Observations

AI-Assisted — The supply topology is sound and every regulator is inside its derated current rating.

The most consequential system issue is the USB power budget. The design budget through U2 is 0.77 A, before the relay coil. Even using the ESP32's typical 355 mA transmit peak instead of the 0.5 A capability figure, demand is about 0.63 A. Both exceed the 500 mA a USB 2.0 port supplies by default. The fixed 5.1k Rd terminations cannot detect whether the source advertises 1.5 A or 3 A.

The second issue is the isolation barrier. Its ceiling is set by PS1's 1 kVDC one-second test. C7 and C8 carry no safety class, and plated mounting holes sit on both grounds. The barrier's required level needs to be stated before these members can be judged.

Thermal closure for U3 is open. The part dissipates 1.04 W at the USB band top, with no junction-to-ambient figure available.

The relay flyback clamp is a switching diode. The B5817W Schottky already in the library would serve as the Q1 turn-off clamp: its 20 V VRRM derated 30% permits 14 V against 5.25 V, and it is rated 1 A average forward current (SMC Diode Solutions datasheet https://www.sangdest.com.cn/propdf/B5817W-B5819W%20N1752%20REV.A.pdf).

The R30/R31 divider (22k over 2k) sets 3.3 V × 2k / 24k = 0.275 V at U9's non-inverting input. That is inside the LM321 input range.

Capacitor voltage and temperature ratings are not stated on any rail other than C7 and C8.

4.6 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.6.1	J1 (TYPE-C-31-M-12)	+5V	The 5.1k Rd terminations on CC1/CC2 make the board a sink that cannot read the source's current advertisement. Computed demand is 0.77 A design budget, or about 0.63 A with the ESP32 355 mA typical transmit peak, plus the relay coil. This exceeds the 500 mA USB 2.0 default. The board depends on a source that supplies more than the default.	Low
4.6.2	U2 (AP22818A)	VUSB	K1 coil current is not available, so the U2 output-current derating is not closed. The known 0.77 A (U3 517 mA, PS1 250 mA, D14 5.25 mA) against 2.0 A derated 30% to 1.4 A leaves 0.63 A for the coil (Diodes Incorporated datasheet).	Review
4.6.3	U2 (AP22818A)	VUSB	K1 coil current is not available, so the U2 junction-temperature check is not closed. On known loads, 0.77² × 95 mΩ (25 C figure) = 56 mW × 123 C/W gives 92 C at 85 C ambient, against the 100 C limit (Diodes Incorporated datasheet).	Review
4.6.4	J1 (TYPE-C-31-M-12)	+5V	The VBUS contact current rating is not available, so the connector contact derating against the 0.77 A budget is not done.	Review
4.6.5	U3 (LD1117S33)	V3.3	The regulator's junction-to-ambient resistance and package power rating are not available, so the junction-temperature and package-dissipation derating checks are not done. Dissipation is (5.25 − 3.3) × 0.507 A + 5.25 V × 10 mA = 1.04 W (LD1117S33 datasheet, θJC 15 C/W only).	Review
4.6.6	U3 (LD1117S33)	V3.3	The regulator's minimum output capacitance and ESR requirement are not available, so the stability check on C5 10µF ceramic (nominal, no DC-bias loss applied) is not done (LD1117S33 datasheet).	Review
4.6.7	U4 (LD1117S33)	V5-F	The PS1 output-voltage-versus-load curve is not available, so U4 headroom is not closed. U4 needs 4.4 V (3.3 V + 1.1 V maximum dropout at 100 mA), while PS1's −15% band end is 4.25 V. PS1 runs at about 12% load, near its 10% specification floor (RECOM and LD1117S33 datasheets).	Review
4.6.8	U4 (LD1117S33)	V3.3-F	U4 junction-to-ambient resistance is not available, so the junction-temperature check is not done. Dissipation is at most (5.75 − 3.3) × 0.063 A + 5.75 V × 10 mA = 0.21 W (LD1117S33 datasheet).	Review
4.6.9	U4 (LD1117S33)	V3.3-F	The minimum output capacitance and ESR requirement are not available, so the stability check on C11 10µF ceramic to GNDS (nominal) is not done (LD1117S33 datasheet).	Review
4.6.10	PS1 (RFM-0505S)	VUSB	The datasheet's EN55032 Class B input filter (10 µF plus a 22 µH series inductor, an application figure) is partly present: C6 10µF and C3 47µF are fitted but there is no inductor. C7 and C8 330pF 1kV match the suggested Class B capacitors (RECOM datasheet).	Review
4.6.11	U12 (LM2664)	-3V3	The CAP+/CAP- flying capacitor value is not available, so the flying-capacitor check against the 3.3 µF datasheet test value is not done (TI datasheet).	Review
4.6.12	Barrier GND/GNDS (C8, C7, PS1, U7)	GNDS	No far-side potential or withstand goal is stated. Continuous and transient: the barrier protects up to at most 1 kVDC (707 V RMS by ÷1.414), set by PS1 (1 kVDC, 1 s test). U7 is 2500 V RMS UL 1577. C7 and C8 have no safety class and are unrated. Please state the required protection level (RECOM and TI datasheets).	Review
4.6.13	H1-H4, H10, H11, R29	GND / GNDS / PGND	The plated mounting holes are split: H1/H2 on GND, H3/H4 on GNDS, and H10/H11 on PGND, which R29 0R links to GNDS. Conductive standoffs or a metal enclosure common to both groups would join GND to GNDS across the barrier. Please state the intended mounting.	Review
4.6.14	C3, C9 (47µF electrolytic)	VUSB / V5-F	The voltage rating and category temperature are not stated in the schematic data. The VUSB top is 5.25 V (USB band). V5-F is up to 5.75 V at PS1's +15% band end. Ratings are needed for the 30% voltage and 25 C temperature derating checks.	Review
4.6.15	C1, C2, C4, C6 (ceramic)	+5V / VUSB	The voltage rating is not stated in the schematic data. These parts are judged at 5.5 V, the Type-C sink withstand level, against a 20% derating (ceramic capacitors, at most 80%).	Review
4.6.16	C5, C11, C12, C13, C20, C22-C28, C32, C35, C37, C38, C10 (ceramic)	V3.3 / V3.3-F / -3V3 / V5-F	The voltage rating is not stated in the schematic data. The rails are 3.3 V, −3.3 V and V5-F up to 5.75 V; ratings are needed for the 20% ceramic derating check.	Review
4.6.17	Q1 (MMBT2222A), D15 (LL4148)	VUSB	K1 coil current is not available, so the Q1 collector-current derating (600 mA, at most 60%) and the D15 forward-current derating (150 mA, at most 65%) are not done (Nexperia and Vishay datasheets).	Review
4.6.18	D15 (LL4148)	VUSB	The B5817W Schottky already in the library would serve as the Q1 turn-off clamp. Its 20 V VRRM derated 30% permits 14 V against 5.25 V, at a 1 A average forward current rating (SMC Diode Solutions datasheet).	Review
4.6.19	D13 (SMBJ36A)	PSU_P	The clamping voltage of the 36 V part is not available, so the clamp comparison against the 90 V INA240 common-mode absolute maximum and the other path parts is not done (Kyocera AVX and TI INA240 datasheets).	Review
4.6.20	R29 (0R, 0805)	PGND / GNDS	The current carried by the PGND-to-GNDS link is not available, so the jumper current check against the conventional 2 A 0805 rating is not done.	Review
4.6.21	U2 (AP22818A)	+5V / VUSB	IN is on +5V from J1 VBUS, GND is on GND, and OUT drives VUSB. All pins have DC paths to sourced nets.	✓
4.6.22	U2 (AP22818A)	+5V	C1 1µF on IN meets the datasheet's 1uF low-ESR input requirement (Diodes Incorporated datasheet).	✓
4.6.23	U2 (AP22818A)	VUSB	C2 100nF plus C3 47µF on OUT meet the datasheet's '0.1uF bypass and high-value capacitor, at least 10uF in USB applications' (Diodes Incorporated datasheet).	✓
4.6.24	U2 (AP22818A)	VUSB	Inrush: 57.2µF × 5 V / 0.6 ms (fastest stated rise) = 0.48 A, below the 2.2 A minimum overload current limit (Diodes Incorporated datasheet).	✓
4.6.25	U2 (AP22818A)	+5V	R5 10k from Net-(U2-EN) to +5V holds EN at VIN. This is above the 1.5 V VIH and within the VIN+0.3 V absolute maximum, so the switch is on whenever VBUS is present (Diodes Incorporated datasheet).	✓
4.6.26	U2 (AP22818A)	+5V	~FLG open-drain is pulled to +5V through R4 1k and D2. Fault sink current is at most 5 mA, and VOL is at most 0.3 V at the 60 Ω maximum on-resistance. D2 indicates a fault and TP2 gives probe access (Diodes Incorporated datasheet).	✓
4.6.27	U3 (LD1117S33)	VUSB / V3.3	VI is on VUSB, GND is on GND, and VO drives V3.3, with pin DC paths correct. V3.3 at 3.24–3.36 V is within U5's 3.0–3.6 V and U7's 3–5.5 V supply ranges (LD1117S33, Espressif source: Tomachie, and TI datasheets).	✓
4.6.28	U3 (LD1117S33)	V3.3	The 507 mA design load (Espressif 0.5 A requirement plus U7 7.1 mA) is within the 800 mA minimum output current derated 30% to 560 mA (regulators and converters output current, at most 70%) (LD1117S33 datasheet).	✓
4.6.29	U3 (LD1117S33)	VUSB	Headroom uses the 1.2 V maximum dropout at 500 mA; the datasheet guarantees 3.24–3.36 V at 4.5 V input, 0–500 mA. VUSB is VBUS − 0.07 V, so regulation holds for VBUS ≥ about 4.6 V, below the 4.75 V USB 2.0 minimum (LD1117S33 datasheet).	✓
4.6.30	U4 (LD1117S33)	V5-F / V3.3-F	VI is on V5-F (PS1 +VOUT), GND is on GNDS (PS1 -VOUT), and VO drives V3.3-F, with pin DC paths correct. V3.3-F at 3.24–3.36 V clears every load's minimum, the tightest being U9 at 3 V and U7 VCC2 at 3 V (LD1117S33 and TI datasheets).	✓
4.6.31	U4 (LD1117S33)	V3.3-F	The known load is 13.3 mA, rising to 63 mA with U12 at its 50 mA maximum. This is well within 800 mA derated 30% to 560 mA (LD1117S33, TI INA240/ISO1540/ADS1115/LM321/LM2664 and ST TSZ122 datasheets).	✓
4.6.32	PS1 (RFM-0505S)	VUSB / V5-F	VUSB is within the 5 VDC ±10% nominal input. The 47.1µF on V5-F is below the 470 µF maximum capacitive load (RECOM datasheet).	✓
4.6.33	U12 (LM2664)	V3.3-F	V+ at 3.3 V is within 1.8–5.5 V, and SD is tied to V+ as the datasheet states for normal operation (TI datasheet).	✓
4.6.34	U12 (LM2664)	-3V3	The output capacitance of 44µF (C37, C38 22µF ceramic, nominal) exceeds the 3.3 µF datasheet test value, which is an application figure rather than a minimum (TI datasheet).	✓
4.6.35	C3, C9 (47µF electrolytic)	VUSB / V5-F	Polarity is correct: pin 1 is on VUSB and V5-F respectively, and pin 2 is on GND and GNDS.	✓
4.6.36	Q1 (MMBT2222A)	VUSB	Off-state VCE is at most about 6.3 V (5.25 V plus the 1 V maximum forward voltage of D15). The 40 V VCEO derated 30% permits 28 V (Nexperia datasheet).	✓
4.6.37	D15 (LL4148)	VUSB	Orientation is consistent: cathode on VUSB, anode on the coil low side. The 100 V VRRM derated 30% permits 70 V against 5.25 V (Vishay datasheet).	✓
4.6.38	K1 (HF49FD_005-1H12T)	PSU_P / LOAD_P	The part number decodes to a 5 VDC coil, matching VUSB. The 5A/30VDC contact from the part description, derated 40% to 3 A, covers the 2.5 A load. The 30 VDC contact voltage rating meets the 25 V operating top and the 30 V survive level.	✓
4.6.39	D13 (SMBJ36A)	PSU_P	The 36 V standoff (from the part number) stays non-conducting at the 30 V survive level. Orientation looks consistent (cathode on PSU_P, anode on PGND), but the datasheet pinout is unconfirmed (Kyocera AVX datasheet).	✓
4.6.40	R30, R31 (22k/2k)	V3.3-F	The divider gives 3.3 V × 2k / 24k = 0.275 V at U9 + (Net-(U9-+)), within the LM321 input range (TI datasheet).	✓

4.7 Citations

AI-Assisted —

References
ADS1115 (Texas Instruments) — datasheet, cited pages 1,15 www.ti.com/lit/ds/symlink/ads1113.pdf
AP22818A (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/AP22816_17_18.pdf
B5817W (SMC Diode Solutions) — datasheet www.sangdest.com.cn/propdf/B5817W-B5819W%20N1752%20REV.A.pdf
INA240A2 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/ina240.pdf
ISO1540 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/iso1541.pdf
LD1117S33 (SGS-THOMSON Microelectronics) — datasheet www.sm0vpo.com/_pdf/LM/LM1117.PDF
LL4148 (Vishay Semiconductors) — datasheet www.vishay.com/docs/85557/ll4148.pdf
LM2664 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/lm2664.pdf
LM321 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/lm321.pdf
MMBT2222A (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/MMBT2222A.pdf
RFM-0505S (RECOM) — datasheet www.mouser.com/datasheet/2/468/RFM-1307831.pdf
SMBJ (Kyocera AVX) — datasheet, cited pages 1,2,3 datasheets.kyocera-avx.com/tvsdiodes.pdf
TSZ122 (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/tsz121.pdf
USBLC6-2SC6 (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7c...

5 Connector Pinouts

Total connectors

5.1 J1 TYPE-C-31-M-12

J1 - TYPE-C-31-M-12
Pin	Pin Name	Net	Notes
A1_B12	GND	GND
A4_B9	VBUS	+5V
A5	CC1	Net-(J1-CC1)
A6	DP1	D+
A7	DN1	D-
A8	SBU1	NC
B1_A12	GND	GND
B4_A9	VBUS	+5V
B5	CC2	Net-(J1-CC2)
B6	DP2	D+
B7	DN2	D-
B8	SBU2	NC
S1	SHIELD	GND
S2	SHIELD	GND
S3	SHIELD	GND
S4	SHIELD	GND

5.2 J2 Conn_02x03_Odd_Even

J2 - Conn_02x03_Odd_Even
Pin	Pin Name	Net	Notes
1	Pin_1	Net-(D6-K)
2	Pin_2	Net-(D5-K)
3	Pin_3	GND
4	Pin_4	V3.3
5	Pin_5	Net-(D7-K)
6	Pin_6	Net-(D8-K)

5.3 J3 Conn_01x03

J3 - Conn_01x03
Pin	Pin Name	Net	Notes
1	Pin_1	Net-(J3-Pin_1)
2	Pin_2	Net-(J3-Pin_2)
3	Pin_3	GND

6 Indicator Documentation

5 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D2	LED	-	Net-(D2-K)	usb.kicad_sch	LOW = On; R4 (1k); A:+5V K:Net-(D2-K)
D1	LED	-		usb.kicad_sch	R3 (1k); Always-on (VCC to GND, no control signal); A:+5V K:Net-(D1-K)
D14	LED	-	Net-(D14-K)	front-end-adc-c.kicad_sch	Q1 switches this LED; apply a voltage at the base of Q1 to light it; R32 (1k); A:Net-(D14-A) K:Net-(D14-K)
D3	LED	-	Net-(D3-A)	esp32.kicad_sch	HIGH = On; R8 (1k); A:Net-(D3-A) K:GND
D4	LED	-	Net-(D4-A)	esp32.kicad_sch	HIGH = On; R9 (1k); A:Net-(D4-A) K:GND

6.2 Indicator Testability

0 of 4 indicators have test coverage. 1 indicator(s) illuminate on their own (power-on / rail-fed / module-driven) and need no test point. 1 are transistor-driven.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D2	Direct	Net-(D2-K)	Design Warning: Test point needed on Net-(D2-K). Drive LOW to turn on LED D2.
D1	Direct		Power indicator (connector)	✓
D14	Q1	Net-(Q1-B)	Design Warning: Test point needed on Net-(Q1-B) - apply a voltage at the base of Q1 to light LED D14, which tests the transistor at the same time.
D3	Direct	Net-(D3-A)	Design Warning: Test point needed on Net-(D3-A). Drive HIGH to turn on LED D3.
D4	Direct	Net-(D4-A)	Design Warning: Test point needed on Net-(D4-A). Drive HIGH to turn on LED D4.

7 Switch Documentation

2 switch(es) found in design.

7.1 Switch Configurations

SW1 Contact Pairs (SW_Push)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	EN	2	GND	SIGNAL	LOW

SW1 All Pins
Pin #	Pin Name	Net	Paired With	Type
1	1	EN	2	CONTACT
2	2	GND	1	CONTACT

SW2 Contact Pairs (SW_Push)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	IO0	2	GND	SIGNAL	LOW

SW2 All Pins
Pin #	Pin Name	Net	Paired With	Type
1	1	IO0	2	CONTACT
2	2	GND	1	CONTACT

7.2 Switch DFT Analysis

Switches for mode selection are useful for development and manual debug, but production test environments require electrical override capability. A latching switch (DIP, slide, toggle) holds the signal at the rail it closes onto until somebody moves it, so ATE cannot drive past the contact: it needs a test point and a series isolation resistor between the switch and that rail. A momentary switch (push button) does not hold the signal — the bias resistor sets the level again as soon as the button is released — so it needs only a test point for ATE stimulus access.

Design Rationale: Switches for mode selection are valuable for engineering development and bench debug. However, production test and field returns require electrical override capability without manual intervention. Adding test points and isolation resistors creates a lifecycle-robust design that works across development, production test, and field returns without requiring procedure documentation or specialized knowledge of switch positions. The goal is a self-documenting, procedure-proof test interface. BOM impact: One 0201/0402 resistor per controlled signal.

Switch	Signal	Function	Pullup	Rail	Issue	Test Point?
SW1	EN	Momentary control	R18 (10.00K)	V3.3 (3.3V)	No test point — Momentary — ATE needs probe access
SW2	IO0	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access

8 Low-Speed Serial Interfaces (LSSI)

Detected: 2 I2C, 1 SPI

8.1 I2C

I2C: U5 -> U8
Topology: U5 » Targets (U8)
Signal	Net Name	Connector	Test Point	Target Pin
SCL	SCL	(none)	(none)	U5_38 (IO2), U8_10 (SCL)
SDA	SDA	(none)	(none)	U5_39 (IO1), U8_9 (SDA)
Address	Target	Industry Type	Description
0x48 (port I2C (SCL on SCLS), strap-set address, ADDR=GNDS (low))	U8	ADS1115IDGS	Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator, VSSOP-10
Controller	Industry Type	Description
U5	ESP32-S3-WROOM-1	RF Module, ESP32-S3 SoC, Wi-Fi 802.11b/g/n, Bluetooth, BLE, 32-bit, 3.3V, onboard antenna, SMD

I2C: U5
Topology: U5 » Targets (J2)
Sig	Nets	Conn/TP	Target Pin
SCL	SCL1 » R16 » Net-(D7-K)	J2_5	U5_7 (IO7)
SDA	SDA1 » R17 » Net-(D8-K)	J2_6	U5_6 (IO6)
Controller	Industry Type	Description
U5	ESP32-S3-WROOM-1	RF Module, ESP32-S3 SoC, Wi-Fi 802.11b/g/n, Bluetooth, BLE, 32-bit, 3.3V, onboard antenna, SMD

I2C Pull-up Check
Net	Component	Status
SDA	R6	Pull-up resistor 4.7K (R6) found on SDA	✓
SDAS	R26	Pull-up resistor 4.7K (R26) found on SDA	✓
SCL	R7	Pull-up resistor 4.7K (R7) found on SCL	✓
SCLS	R27	Pull-up resistor 4.7K (R27) found on SCL	✓
Net-(D8-K)	R12	Pull-up resistor 4.7K (R12) found on SDA	✓
Net-(D7-K)	R13	Pull-up resistor 4.7K (R13) found on SCL	✓

8.2 SPI

SPI: U5 -> U6
Topology: U5 » Targets (U6)
Signal	Net Name	Connector	Test Point	Target Pin
MOSI	DI_MOSI / DI_MOSI	(none)	(none)	U6_5 (DI/IO₀₎
MISO	DO_MISO / DO_MISO	(none)	(none)	U6_2 (DO/IO₁₎
SCK	CLK / CLK	(none)	(none)	-
CS	CS / CS	(none)	(none)	U6_1 (CS)
Target	CS Net	Industry Type	Description
U6	CS (1 CS)	W25Q16JVSS	16Mbit / 2MiB Serial Flash Memory, Standard/Dual/Quad SPI, 2.7-3.6V, SOIC-8 (208 mil)
Controller	Industry Type	Description
U5	ESP32-S3-WROOM-1	RF Module, ESP32-S3 SoC, Wi-Fi 802.11b/g/n, Bluetooth, BLE, 32-bit, 3.3V, onboard antenna, SMD

8.3 LSSI DFT Analysis

8 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
SCL	SCL	(none)	I2C: U5 -> U8
SDA	SDA	(none)	I2C: U5 -> U8
SCL	Net-(D7-K)	J2_5	I2C: U5
SDA	Net-(D8-K)	J2_6	I2C: U5
CS	CS	(none)	SPI: U5 -> U6
MISO	DO_MISO	(none)	SPI: U5 -> U6
MOSI	DI_MOSI	(none)	SPI: U5 -> U6
SCK	CLK	(none)	SPI: U5 -> U6

9 High-Speed Serial Interfaces (HSSI)

8 differential pair(s)

Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

2 of 6 differential pairs do not specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM.

Differential Pairs
Net Name	Class	Impedance	Notes
SENSE_P/N	DIFF_PAIR
XTAL_32K_P/N	DIFF_PAIR
D+	USB_90R	90 Ohm
D-	USB_90R	90 Ohm
DG+	USB_90R	90 Ohm
DG-	USB_90R	90 Ohm

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Device Port (J1 to U5 via U1)

AI-Assisted — The only serial data link on the board runs from Type-C receptacle J1 to the ESP32-S3 module U5 (pin 14 USB_D+ = IO20, pin 13 USB_D- = IO19). The protocol is USB 2.0, governed by the USB 2.0 Specification. The Espressif ESP32-S3-WROOM-1 datasheet entry (source: Tomachie) does not state the PHY speed class.

J1 A6/B6 (DP1/DP2) are joined on D+ and A7/B7 (DN1/DN2) on D-. This is the correct flip-independent USB 2.0 wiring on a Type-C receptacle. SBU1/SBU2 are not used.

U1 (USBLC6-2SC6) sits in flow-through between the connector and the module. Pins 3/4 (I/O2) carry D+ to DG+, and pins 1/6 (I/O1) carry D- to DG-. U1 VBUS (pin 5) is on +5V, where C1 (1µF) decouples it, and U1 GND (pin 2) is on GND.

The ST datasheet (https://datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7ccf534db0.pdf) gives the following figures. I/O-to-GND capacitance is 2.5 pF typical and 3.5 pF maximum. I/O-to-GND matching is 0.015 pF, which ST states is compliant with USB 2.0 D+/D- balance. The device is rated for data up to 480 Mbit/s, so it covers every USB 2.0 speed.

USB 2.0 is DC-coupled, and no series capacitor appears in either path, as the specification requires. There are no series resistors or external terminations, so the link relies on the transceiver integrated in U5.

All four segments (D+, D-, DG+, DG-) carry a 90 Ω differential net class. This matches the USB 2.0 90 Ω ±15% differential requirement.

Whether U1's clamp level sits below what U5's USB pins tolerate is left to the EMC/ESD review. This section records U1's clamp figures only: 12 V at 1 A and 17 V at 5 A, 8/20 µs.

9.3 Observations

AI-Assisted — The USB 2.0 path is correctly wired and classed. No defect was found on the high-speed signals.

Three checks remain open for lack of input:
- U5 USB transceiver speed and termination: the ESP32-S3 USB PHY figures are not available.
- Y1 load capacitance: the ESP32-S3 oscillator stray or load-capacitor figure is not available.
- Y1 negative resistance: the ESP32-S3 oscillator negative-resistance figure is not available.

None of the D+, D-, DG+ or DG- nets carries a test point. A pad pair on DG+/DG- would allow bench eye or protocol probing downstream of U1.

Flash U6, fitted do-not-install on the FSPI pins (CLK, DI_MOSI, DO_MISO, CS), has no datasheet entry. Its bus timing and series damping are therefore not assessed.

9.4 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.4.1	USB U5 transceiver	USB 2.0	The ESP32-S3 USB PHY speed class and termination figures are not available, so the transceiver speed identification and on-die termination check are not done (Espressif ESP32-S3-WROOM-1 datasheet, source: Tomachie).	Review
9.4.2	USB U1 clamp vs U5 pins	USB 2.0	The ESP32-S3 USB pin absolute-maximum rating is not available, so the check of U1's 17 V (5 A, 8/20 µs) clamp against U5 is not done. Protection ordering is left to the EMC/ESD review (ST USBLC6-2SC6 datasheet, https://datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7ccf534db0.pdf).	Review
9.4.3	USB D+/D-/DG+/DG-	USB 2.0	None of the four USB nets carries a test point. A pad pair on DG+/DG- would allow protocol probing downstream of U1.	Review
9.4.4	RTC crystal Y1	32.768 kHz clock	C14/C18 12pF give 6.00 pF series, implying 6.5 pF stray against the 12.5 pF CL. The ESP32-S3 oscillator stray or load-capacitor figure is not available, so the load-capacitor check is not done (Seiko Epson FC-135 datasheet, source: Tomachie).	Review
9.4.5	RTC crystal Y1	32.768 kHz clock	The ESP32-S3 32 kHz oscillator negative resistance is not available, so the check against Epson's 5 x R1 = 350 kΩ requirement is not done (Seiko Epson FC-135 datasheet, source: Tomachie).	Review
9.4.6	Shunt sense R23/R24	Analog differential	No tolerance is stated on R23/R24, and TI warns that filter resistor mismatch impacts accuracy. Specify matched tolerance (for example Tol:1%) in the resistors' Tolerance property (TI INA240 datasheet, page 18, https://www.ti.com/lit/ds/symlink/ina240.pdf).	Review
9.4.7	FSPI flash U6 (DNI)	SPI	U6 W25Q16JVSS is marked do-not-install and has no datasheet entry, so the SPI bus timing and series-damping checks are not done.	Review
9.4.8	USB J1 to U5 (D+/D-, DG+/DG-)	USB 2.0	J1 A6/B6 are joined on D+ and A7/B7 on D-, reaching U5 USB_D+ (pin 14) and USB_D- (pin 13) through U1 in flow-through. This is correct Type-C USB 2.0 wiring (USB 2.0 Specification; Espressif ESP32-S3-WROOM-1 datasheet, source: Tomachie).	✓
9.4.9	USB J1 to U5	USB 2.0	All four segments carry a 90 Ω differential net class, which matches the USB 2.0 90 Ω ±15% differential requirement (USB 2.0 Specification).	✓
9.4.10	USB J1 to U5	USB 2.0	No series capacitors are present, correct for a DC-coupled USB 2.0 link (USB 2.0 Specification).	✓
9.4.11	USB U1 USBLC6-2SC6	USB 2.0	Capacitance is 2.5 pF typical and 3.5 pF maximum, with 0.015 pF I/O-to-GND matching and a 480 Mbit/s rating. These cover USB 2.0 signalling (ST USBLC6-2SC6 datasheet, https://datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7ccf534db0.pdf).	✓
9.4.12	USB U1 USBLC6-2SC6	USB 2.0	VBUS pin 5 is on +5V with C1 1µF, and GND pin 2 is on GND. This meets ST's recommended 100 nF VBUS decoupling (ST USBLC6-2SC6 datasheet, page 9, https://datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7ccf534db0.pdf).	✓
9.4.13	RTC crystal Y1	32.768 kHz clock	Y1 is on U5 IO15/IO16, the XTAL_32K_P/N pins per the Espressif ESP32-S3-WROOM-1 datasheet (source: Tomachie).	✓
9.4.14	Shunt sense SENSE_P/SENSE_N	Analog differential	R23/R24 4.7R meet TI's 10 Ω or less input filter limit. The filter corner is about 16.9 MHz with C21 1nF, and separate taps on each shunt end give Kelvin sensing (TI INA240 datasheet, pages 18 and 23, https://www.ti.com/lit/ds/symlink/ina240.pdf).	✓

9.5 Citations

AI-Assisted —

References
INA240A2 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/ina240.pdf
SMBJ (Kyocera AVX) — datasheet, cited pages 1,2,3 datasheets.kyocera-avx.com/tvsdiodes.pdf
USBLC6-2SC6 (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7c...

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 U6 MICROWIRE

U6 (W25Q16JVSS) - MICROWIRE
Signal	Pin Name	Pin #	Net Name	Test Point
CLOCK	CLK	6	CLK	-
DATA_IN	DI/IO₀	5	DI_MOSI	-
DATA_OUT	DO/IO₁	2	DO_MISO	-
SELECT	CS	1	CS	-
DESIGN_WARNING: Test points would be needed on CLK, DI_MOSI, DO_MISO and CS if direct on-board programming is desired over indirect programming via the FPGA/CPU (U5)

10.2 AI-Assisted Analysis

10.2.1 External SPI Flash U6 (W25Q16JVSS, do-not-install option)

AI-Assisted — U6 is a Winbond W25Q16JV 16 Mbit (2 MB) serial NOR flash on the esp32 sheet, controlled by the ESP32-S3-WROOM-1 module U5. U6 and its two strap resistors R19 and R20 are marked do-not-install in the part values, so the default assembly carries no external flash. The fitted-option review below assumes all three parts are populated.

Four signals connect U6 to U5: CLK to IO12, DI_MOSI to IO11, DO_MISO to IO13 and CS to IO14. The IO2 (/WP) and IO3 (/HOLD//RESET) pins go only to R20 and R19, 10k each to V3.3. With only DI and DO reaching the controller, the bus supports Standard SPI and Dual SPI. Quad SPI is not available as wired.

The VCC pin is on V3.3, which U3 (LD1117S33) sets at 3.3 V. That is inside the datasheet's 3.0-3.6 V band, so the fast-read instructions are rated to 133 MHz. Read Data (03h) is limited to 50 MHz (Winbond W25Q16JV datasheet, source: Tomachie). The GND pin is on GND.

The datasheet requires /CS to track VCC at power-up and power-down, and lists a pull-up from /CS to VCC as the means. The CS net carries only U5 IO14 and U6 /CS, with no pull-up. Fitting a 10k to V3.3, depopulated together with U6 in the same way as R19/R20, holds U6 deselected through the ramp. This covers the tVSL 20 µs VCC-to-/CS-low interval and prevents a spurious command.

R20 holds /WP high permanently, and no controller pin can pull it low. The hardware status-register lock is therefore unavailable; only the software block-protect bits remain. Routing /WP to a spare U5 output would let firmware hold it LOW to protect the status register, raising it only to rewrite protection settings.

None of the four flash-bus nets carries a series resistor or a test point.

10.3 Observations

AI-Assisted — The flash is expressed as a do-not-install option through its part values rather than a design variant. The test netlist therefore still shows U6, R19 and R20 as connected. Defining the U6 option through the eCAD variant feature would make fitted and unfitted builds unambiguous for assembly and connectivity test. The pull-up proposed for CS belongs in the same variant.

No capacitor on V3.3 is identifiable as U6's local bypass. The rail carries C5 and C12 (10µF) and C13, C19 and C20 (100nF). The Winbond datasheet states no decoupling figure. A 100nF placed at U6 VCC and fitted with U6 keeps the 25 mA program/erase current (ICC5/ICC6 maximum) local to the device.

The ESP32-S3 GPIO output levels are not available, so the input-threshold check against the U6 VIH of 0.7 × VCC (2.31 V at 3.3 V) is not done. Bus timing and series damping were already left open in the signal-integrity review and are not repeated here.

Firmware should observe the datasheet's tPUW minimum of 5 ms after power-up before issuing any write or erase instruction.

10.4 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.4.1	U6 (W25Q16JVSS)	SPI flash	The datasheet requires /CS to track VCC at power-up/down via a pull-up to VCC. The CS net carries only U5 IO14 and U6 /CS, with no pull-up. Add 10k from CS to V3.3, fitted with U6 (Winbond W25Q16JV datasheet, source: Tomachie).	Low
10.4.2	U6 (W25Q16JVSS)	SPI flash	R20 10k between the /WP net and V3.3 holds /WP high permanently, with no controller pin able to lower it, so the hardware status-register lock is unavailable. Drive /WP from a spare U5 output so firmware can hold it LOW to protect the status register (Winbond W25Q16JV datasheet, source: Tomachie).	Low
10.4.3	U6 (W25Q16JVSS)	SPI flash	U6, R19 and R20 are marked do-not-install in their part values, not through a design variant. Define the external-flash option as an eCAD variant so the test netlist matches the build.	Review
10.4.4	U6 (W25Q16JVSS)	SPI flash	Operating mode is Standard/Dual SPI. CLK, DI, DO and /CS go to U5 IO12/IO11/IO13/IO14, while /WP and /HOLD go only to pull-ups, so Quad SPI is not available as wired (Winbond W25Q16JV datasheet, source: Tomachie).	Review
10.4.5	U6 (W25Q16JVSS)	SPI flash	No V3.3 capacitor is identifiable as U6's local bypass, and the datasheet states no decoupling figure. A 100nF at U6 VCC, fitted with U6, keeps the 25 mA maximum program/erase current local (Winbond W25Q16JV datasheet, source: Tomachie).	Review
10.4.6	U6 (W25Q16JVSS)	SPI flash	The ESP32-S3 GPIO output high and low levels are not available, so the logic-level check against the U6 VIH of 0.7 × VCC (2.31 V) and the VIL of 0.3 × VCC (0.99 V) is not done.	Review
10.4.7	U6 (W25Q16JVSS)	SPI flash	None of the four flash-bus nets (CLK, DI_MOSI, DO_MISO, CS) carries a test point. Pads on these nets would allow bus probing when U6 is fitted.	Review
10.4.8	U6 (W25Q16JVSS)	SPI flash	The datasheet gives a tPUW minimum of 5 ms from power-up before any write or erase instruction. This must be honoured in firmware, as nothing in the hardware enforces it (Winbond W25Q16JV datasheet, source: Tomachie).	Review
10.4.9	U6 (W25Q16JVSS)	SPI flash	The VCC pin is on V3.3 at 3.3 V (U3 LD1117S33), inside the 3.0-3.6 V band, giving 133 MHz fast-read and 50 MHz Read Data (03h) capability. The GND pin is on GND (Winbond W25Q16JV datasheet, source: Tomachie).	✓
10.4.10	U6 (W25Q16JVSS)	SPI flash	R19 10k between the /HOLD//RESET net and V3.3 holds the pin inactive, so hold or reset cannot be asserted unintentionally in Standard/Dual SPI use (Winbond W25Q16JV datasheet, source: Tomachie).	✓

11 Functional Analysis

11 device(s) to review across 5 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
Y1	CRYSTAL	FC-135_32.7680KA-A0	32.768 kHz ±20ppm Crystal 12.5pF 70 kOhms 2-SMD, No Lead	-	-
PS1	DEVICE	RFM-0505S	DC-DC Converter, SIP4, 1kV unreg, Single Output, 1W, 5V Out, RFM Series \| RECOM Power Inc. RFM-0505S	-	-
U1	DEVICE	USBLC6-2SC6	Very low capacitance ESD protection diode, 2 data-line, SOT-23-6	-	-
U10	DEVICE	INA240A2D	High- and Low-Side, Bidirectional, Zero-Drift, Current-Sense Amplifier With Enhanced PWM Rejection, 50V/V, SOIC-8	-	-
U11	DEVICE	TSZ122IYDT	Dual operational amplifier	-	-
U12	DEVICE	LM2664M6	Switched Capacitor Voltage Converter, inverts a positive voltage in the range of 1.8 V to 5.5 to the corresponding negative voltage of −1.8 V −5.5 V 40 mA, SOT-23-6	-	-
U8	DEVICE	ADS1115IDGS	Ultra-Small, Low-Power, I2C-Compatible, 860-SPS, 16-Bit ADCs With Internal Reference, Oscillator, and Programmable Comparator, VSSOP-10	I2C	-
U9	DEVICE	LM321	Low Power Single Operational Amplifier, SOT-23-5	-	-
D14	DIODE	LED	Light emitting diode	-	-
K1	RELAY	HF49FD_005-1H12T	Relay: electromagnetic; SPST-NO; Ucoil: 5VDC; 5A/250VAC; 5A/30VDC	-	-
U5	WIRELESS	ESP32-S3-WROOM-1	RF Module, ESP32-S3 SoC, Wi-Fi 802.11b/g/n, Bluetooth, BLE, 32-bit, 3.3V, onboard antenna, SMD	I2C, SPI	-

11.1 Reset-Time Strap Configuration

Each device below takes part of its start-up configuration from resistors the board fits on pins it samples at reset. Every setting is resolved against that device's own datasheet tables - the combination this board selects, and whether the datasheet marks that combination reserved or invalid.

RefDes	Configuration	This Board Selects	Read From	Status
U5	Chip Boot Mode Control	SPI Boot	GPIO0 = U5_27 open (no strap resistor fitted); GPIO46 = U5_16 open (on no net - unconnected)	✓
U5	VDD_SPI Voltage Control	Decided by EFUSE_VDD_SPI_FORCE, EFUSE_VDD_SPI_TIEH, which the board does not set; GPIO45 = open is accepted by at least one row	GPIO45 = U5_26 open (on no net - unconnected)

RefDes	Pin	Read From	Sets
U5	GPIO0 (U5_27)	open (no strap resistor fitted)	Chip boot mode (with GPIO46) = SPI Boot
U5	GPIO3 (U5_15)	open (on no net - unconnected)	source of JTAG signals during the early boot process - the datasheet tabulates no modes for this pin
U5	GPIO45 (U5_26)	open (on no net - unconnected)	VDD_SPI power source = VDD3P3_RTC via RSPI, Voltage = 3.3 V
U5	GPIO46 (U5_16)	open (on no net - unconnected)	Chip boot mode (with GPIO0) = Joint Download Boot (with GPIO0 = 0), ROM message printing =

11.2 Functional Analysis

11.2.1 Y1 32.768 kHz RTC Crystal

AI-Assisted — Y1 (Epson FC-135, 12.5 pF load option per its description) connects across XTAL_32K_P and XTAL_32K_N. These nets go to U5 IO15 and IO16, which the Espressif datasheet (source: Tomachie) names XTAL_32K_P and XTAL_32K_N, so the wiring is correct. C14 and C18 are 12pF each, one from each crystal terminal to GND. The load-capacitor match and the oscillator negative-resistance margin are already reported in the signal-integrity review and are not repeated here.

The crystal is rated −40 to +85 °C operating (Seiko Epson datasheet, source: Tomachie). That equals the design's 85 C maximum ambient, so the rating meets the position.

The ESP32-S3 32 kHz oscillator's drive level is not stated. Y1's 0.5 µW maximum drive level (1.0 µW not-destroyed limit) therefore cannot be compared against it.

11.2.2 PS1 Isolated 5 V DC-DC Converter

AI-Assisted — PS1 (RECOM RFM-0505S) takes +VIN from VUSB and −VIN from GND. It delivers +VOUT on V5-F and −VOUT on GNDS, feeding U4 and the isolated measurement domain. The RECOM datasheet (https://www.mouser.com/datasheet/2/468/RFM-1307831.pdf) specifies a 5 V ±10% input, which is 4.5 V to 5.5 V. VUSB spans about 4.68 V (4.75 V USB minimum less 73 mV across U2 at 0.77 A and 95 mΩ) to 5.25 V. The input is therefore inside the range, and the 5.5 V Type-C withstand level sits exactly at its top.

Capacitance on the output is 47.1µF on V5-F plus 32.6µF behind U4, about 80µF. That is well inside the 470 µF maximum capacitive load.

Output current against the 200 mA rating derated 30% (regulator_output_current_pct = 70) is 140 mA permitted. The power review's 63 mA U4 load plus U4's 10 mA maximum quiescent current gives 73 mA. The total is not closed, however, because U7's VCC2 current is not stated.

The datasheet gives a 105 C maximum case temperature, and PS1 runs without datasheet derating to 85 C ambient. The policy margin for converters (40 C below the datasheet maximum, capped at 100 C) permits 65 C. The design ambient of 85 C already exceeds that before any self-heating, so the part is not rated for this position under the policy.

The isolation barrier PS1 forms with U7, C7 and C8 is judged in the power review.

11.2.3 U1 USB Data-Line ESD Protection

AI-Assisted — U1 (STMicroelectronics USBLC6-2SC6, https://datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7ccf534db0.pdf) is wired flow-through. Connector-side D- enters I/O1 on pin 1 and leaves to U5 as DG- on pin 6. D+ enters I/O2 on pin 3 and leaves as DG+ on pin 4. Both pins of each channel carry the same line, so every data line passes the clamp. VBUS (pin 5) is on +5V ahead of U2, and GND (pin 2) is on GND.

The VBUS-to-GND breakdown is 6 V minimum, above the 5.5 V Type-C withstand level. Leakage is 150 nA maximum at 5.25 V, which is negligible on this rail. U1 dissipates essentially nothing in normal operation, so its junction sits at the 85 C ambient. The IC junction limit is min(100 C, 125 − 40 C) = 85 C, so the part meets the limit exactly.

The datasheet's PCB layout guidance recommends 100 nF on the VBUS pin. The only capacitor on +5V is C1 1µF, which is U2's IN capacitor as the Diodes datasheet asks. U1 therefore has no local capacitor of its own. The clamp coordination with U5 belongs to the EMC/ESD review.

11.2.4 U10 Current-Sense Amplifier and U9 Reference Buffer

AI-Assisted — U10 (TI INA240A2, http://www.ti.com/lit/ds/symlink/ina240.pdf) measures the current through R25 10mR. R25 sits between PSU_P and SNT_N ahead of the K1 contact. IN+ is taken from the PSU_P end through R23 4.7R and IN− from the SNT_N end through R24 4.7R, so source-to-load current reads positive. C21 1nF is fitted across the inputs. Both series resistors meet the datasheet's limit of 10 Ω or less for input filtering.

The common mode is 25 V at the top of the normal band and 30 V at the survive level. The datasheet gives −4 V to 80 V operating and 90 V absolute maximum. VS is on V3.3-F (2.7-5.5 V) and GND on GNDS; V3.3-F carries six 100nF ceramics for its six IC loads plus C35 22µF.

REF2 is on GNDS. REF1 is driven by U9 (TI LM321, http://www.ti.com/lit/ds/symlink/lm321.pdf), wired as a follower of R30 22k / R31 2k from V3.3-F, which gives 0.275 V. The datasheet states for this arrangement: "output set to half of the external reference for 0-V differential input". Zero current therefore reads 0.1375 V, and at 2.5 A the output is 1.3875 V. The ±2.048 V ADC range covers up to 3.82 A forward and 0.275 A reverse.

U9 has a 9 mV maximum offset over −40 to 85 °C. That shifts REF1, and halved at the output it gives ±4.5 mV, equal to ±9 mA of apparent current. A zero-current reading taken with K1 open removes it. U9's 3.3 V supply is inside its 3-30 V range, including LD1117's 3.24 V minimum output. Its 0.275 V input is inside the V+ − 2 V common-mode limit.

R34 1.5k separates U10's output from C27 100nF, which respects the 1 nF capacitive-load limit and forms a 1.06 kHz anti-alias pole into AIN2. Predicted junction temperatures are about 86 C for both U10 and U9, against the 100 C IC limit.

11.2.5 U11 Dual Op-Amp Voltage Channels

AI-Assisted — U11 (STMicroelectronics TSZ122, https://www.st.com/resource/en/datasheet/tsz121.pdf) runs from V3.3-F with V− on GNDS, inside its 1.8-5.5 V range. Both halves are unity-gain followers. Channel A buffers PSU_P through R37 160k + R39 160k over R41 20k with C31 10nF to PGND, and drives AIN0 through R44 1k. Channel B does the same for LOAD_P through R36, R38 and R40 with C30, and drives AIN1 through R45 1k.

The divider ratio is 0.0588, giving 0.71 V at 12 V, 1.47 V at 25 V and 1.76 V at the 30 V survive level. All three are inside the input common-mode range and the ADC's ±2.048 V range. The input filter corner is 846 Hz.

The datasheet requires input current to be limited to 10 mA by a series resistor. The 320k series leg allows 37 µA at 12 V with U11 unpowered, so the requirement is met by a wide margin. The 1k output resistors isolate C33 and C34 100nF from the chopper outputs.

R42 and R43 20k pull each follower output toward −3V3, which is these resistors' only load. With V− on GNDS, the outputs cannot go below GNDS. The resistors therefore act as a constant sourcing load of 165 µA at 0 V to 253 µA at 1.76 V, which keeps the output stage conducting near zero. Moving V− to −3V3 is not an alternative: that would put 6.6 V across a part rated 5.5 V operating and 6 V absolute maximum. The present arrangement is within ratings.

No tolerance is stated on R36 to R41, and divider ratio accuracy follows directly from it.

11.2.6 U12 Negative Charge Pump

AI-Assisted — U12 (TI LM2664, https://www.ti.com/lit/ds/symlink/lm2664.pdf) inverts V3.3-F to −3V3. V+ is on V3.3-F, inside 1.8-5.5 V, and GND is on GNDS. SD is tied to V3.3-F, which the datasheet's states table gives as "Normal operating mode".

C36 10µF sits between CAP+ and CAP−. C37 and C38 22µF, 44µF in total, sit on OUT. Both exceed the 3.3 µF test values in the datasheet's characterisation circuit.

The load is only R42 and R43: 0.48 mA at 25 V on the monitored rails and 0.51 mA at the 30 V survive level. The 40 mA rating derated 30% (regulator_output_current_pct = 70) permits 28 mA. The 25 Ω maximum output resistance drops about 13 mV. The supply absolute maximum is 5.8 V; derated 15% (regulator_input_voltage_pct = 85) it permits 4.93 V against 3.36 V applied.

The datasheet states a −40 to 85 °C operating junction range. Dissipation is about 1.7 mW (500 µA maximum quiescent current at 3.36 V). At 210 C/W that is a 0.4 C rise, so the junction reaches about 85.4 C at the 85 C design ambient. The part is applied outside its datasheet's recommended operating range. An inverting charge pump specified for junction operation to at least 125 C would serve.

C36 carries the full V3.3-F level, but its voltage rating is not stated in the schematic data.

11.2.7 U8 16-Bit ADC

AI-Assisted — U8 (TI ADS1115, http://www.ti.com/lit/ds/symlink/ads1113.pdf) is on the isolated side. VDD is on V3.3-F, inside 2-5.5 V, and GND is on GNDS. ADDR is tied to GNDS, selecting the ground-strapped address. U8 is the only target on the SDAS/SCLS segment behind U7, so no address conflict exists.

The datasheet requires pull-ups to VDD on SDA, SCL and ALERT/RDY. These are R26 4.7k (SDAS to V3.3-F), R27 4.7k (SCLS to V3.3-F) and R28 10k (ALERT/RDY net to V3.3-F), so the requirement is met. ALERT/RDY reaches only R28 and does not cross the barrier, so firmware must poll conversion status over I2C.

The inputs are AIN0 and AIN1 from the U11 followers and AIN2 from U10; AIN3 is left unconnected by the designer. The worst-case levels are 1.76 V, 1.76 V and 1.39 V at 2.5 A, all inside the ±2.048 V range. The anti-alias corners are 1.59 kHz (1k with 100nF) and 1.06 kHz (1.5k with 100nF). Both sit above the 430 Hz Nyquist limit at the 860 SPS maximum data rate, so aliasing rejection at the fastest rate relies on the corner, not on these filters.

11.2.8 K1 Load Relay, Coil Drive and D14 Indicator

AI-Assisted — K1 is a HF49FD_005-1H12T; the 005 suffix encodes a 5 VDC coil, which matches VUSB. Coil pin 1 is on VUSB and pin 2 is on Net-(D14-K), switched to GND by Q1. Q1's base is driven from U5 IO38 (R_CTR) through R33 330R. The base current is at most (3.3 − 0.6)/330 = 8.2 mA. U5's 40 mA IOH (PAD_DRIVER=3) derated 30% (ic_output_current_pct = 70) permits 28 mA (Espressif datasheet, source: Tomachie).

Net-(Q1-B) carries only R33 and Q1. The relay is held off during reset and boot only if IO38 is not driven high while it is high-impedance, and IO38's reset state is not stated.

D15 (LL4148) runs from the coil low side (anode) to VUSB (cathode). That orientation is correct for a flyback clamp. Its Schottky alternative is already reported in the power review.

The contacts switch SNT_N to LOAD_P. Per the library description they are rated 5 A/30 VDC. The contact current rating derated 40% (relay_contact_current_pct = 60) permits 3 A against the 2.5 A load. The 25 V normal-band top and the 30 V survive level are within the 30 VDC catalogue contact voltage. That rating applies to a resistive load; an inductive load is not covered.

R35 10R with C29 220nF forms a snubber across the contacts, but C29's voltage rating is not stated in the schematic data. The coil pick-up voltage is not stated, so pick-up cannot be checked against VUSB at its 4.68 V low end less Q1's saturation drop.

D14 with R32 1k from VUSB returns to the coil low side, so it lights when Q1 energises K1. Its current is at most 5.25 mA, and it sees only about 1 V reverse while D15 clamps.

11.2.9 U5 ESP32-S3-WROOM-1: Supply, Enable and Strapping Pins

AI-Assisted — U5 (Espressif ESP32-S3-WROOM-1, datasheet, source: Tomachie) takes 3V3 (pin 2) from V3.3, which U3 LD1117S33 generates. GND pins 1, 40 and 41 are on GND.

Supply limits are met on both counts. LD1117's 3.24-3.36 V output band sits inside the 3.0-3.6 V supply range and below the 3.6 V absolute maximum. U3's 800 mA minimum output current covers the 0.5 A the datasheet requires the external supply to deliver. V3.3 carries C5 and C12 10µF plus three 100nF ceramics.

The EN network matches the datasheet's recommended RC delay of R = 10 kΩ and C = 1 µF. R18 10k runs from EN to V3.3, with C15 100nF and C16 1µF from EN to GND (1.1µF total) and SW1 to GND for reset. EN reaches 0.75 × VDD about 15 ms after the rail, far beyond the 50 µs minimum tSTBL, and is never floating.

IO0 carries SW2 to GND (C17 is do-not-install) and relies on its weak internal pull-up for the default bit value of 1.

IO3 (pin 15) is left unconnected by the designer. The datasheet states this JTAG-source strap has no internal pull resistors and that its value "must be actively driven by external circuit". As drawn, the strap level at reset is undefined. A 10k resistor to V3.3 or to GND, at the level the designer wants for the JTAG source, meets the requirement.

IO45 (VDD_SPI voltage strap) and IO46 (boot-mode and ROM-print strap) are also unconnected by the designer. Each rests on a weak internal pull-down with a default bit value of 0, so each strap depends on a 45 kΩ internal resistor alone.

IO8, IO9 and IO10 are unconnected in the schematic, and the datasheet places no connection requirement on them. IO35-IO37 are unconnected by the designer; those pins are dedicated to Octal PSRAM only on R8/R16V variants.

11.2.10 U5 ESP32-S3-WROOM-1: Interfaces and Peripherals

AI-Assisted — Native USB is wired with the correct polarity. USB_D- (pin 13) is on DG- and USB_D+ (pin 14) is on DG+, both reaching J1 through U1. Speed class and termination are already covered in the signal-integrity review.

The UART0 console leaves the board on J3. TXD0 runs through R21 22R to J3 pin 1, RXD0 through R22 22R to J3 pin 2, and J3 pin 3 is GND.

The isolated I2C bus is SDA on IO1 and SCL on IO2. R6 4.7k and R7 4.7k pull these to V3.3, and they reach U7 SDA1/SCL1. U7 carries no datasheet here, so its side-1 bus requirements are not judged.

The J2 expansion header brings out a second I2C pair and two trigger lines. SDA1 (IO6) has R12 4.7k to V3.3, and SCL1 (IO7) has R13 4.7k to V3.3. TRG1 (IO4) and TRG2 (IO5) each have 10k (R10, R11) to V3.3. Each line reaches the header through a 22R series resistor (R17, R16, R15, R14) and has an ESD5Zxx clamp to GND. J2 also carries V3.3 on pin 4 and GND on pin 3. Protection ordering at J2 belongs to the EMC/ESD review.

The status LEDs draw from IO17 (R8 1k, D3) and IO18 (R9 1k, D4), each at most 3.3 mA. That is well inside the 40 mA IOH (PAD_DRIVER=3), which derated 30% (ic_output_current_pct = 70) permits 28 mA. The IO38 relay drive and the 32 kHz crystal are covered under K1 and Y1.

The MTCK, MTDO, MTDI and MTMS nets each carry only their U5 pin, with no header or test point on any of the four. Pin-level JTAG therefore cannot be attached to the assembled board.

The module is specified for −40 to 85 °C, which equals the 85 C design ambient. Its thermal resistance is not stated, so the junction-temperature check is not done.

11.2.11 32.768 kHz RTC Crystal (Y1)

AI-Assisted — Y1 (FC-135, 32.768 kHz) connects to U5 IO15 (XTAL_32K_P) and IO16 (XTAL_32K_N). These are the pin functions the Espressif ESP32-S3-WROOM-1 datasheet assigns to them (source: Tomachie).

C14 and C18 (12pF each, to GND) present 6.00 pF in series to the crystal. The library description of Y1 gives CL = 12.5 pF, which is one of the three CL options in the Seiko Epson FC-135 datasheet (source: Tomachie). The design therefore implies 6.5 pF of stray capacitance from the oscillator pins and traces.

The load capacitor choice cannot be closed because the datasheet provided gives no ESP32-S3 32 kHz oscillator stray or load-capacitor figure. The Epson datasheet also requires the oscillator IC's negative resistance to be at least 5 x R1. With R1 at 70 kΩ, that is 350 kΩ, and U5's figure is not available.

The XTAL_32K_P/N pair carries a differential grouping. At 32.768 kHz no impedance control is needed; guard the traces against coupling instead.

11.2.12 Shunt Sense Differential Input (U10)

AI-Assisted — SENSE_P and SENSE_N feed U10 (INA240A2D) pin 8 (+) and pin 1 (-). The taps run through R23 and R24 (4.7R each), taken from opposite ends of shunt R25 (10mR): PSU_P and SNT_N. This separate-tap arrangement matches the Kelvin connection the TI datasheet requires (https://www.ti.com/lit/ds/symlink/ina240.pdf, page 23).

The datasheet asks for series filter resistors of 10 Ω or less, and 4.7R meets that limit. R23, R24 and C21 (1nF) form a differential filter corner at 1/(2π × 9.4 Ω × 1 nF) ≈ 16.9 MHz. This is far above the 400 kHz amplifier bandwidth, so the filter adds negligible error at signal frequencies.

The TI datasheet also warns that resistor mismatch degrades accuracy. R23 and R24 carry no tolerance property in the schematic.

D11 and D12 on these nets are marked do-not-install.

11.3 Findings

AI-Assisted —

#	Device	Finding	Severity
11.3.1	PS1 (RFM-0505S)	Maximum case temperature is 105 C. With the 40 C converter margin, 65 C is permitted, and the 85 C design ambient exceeds this before self-heating: the part is not rated for this position under the policy. Fit an isolated module rated for a case temperature of at least 125 C (RECOM datasheet).	Medium
11.3.2	U12 (LM2664)	−40 to 85 °C operating junction range. 1.7 mW at 210 C/W gives about 85.4 C at the 85 C design ambient, so the part is applied outside its recommended operating range. Fit an inverting charge pump specified for junction operation to at least 125 C (TI datasheet).	Medium
11.3.3	U5 (ESP32-S3-WROOM-1)	IO3 (pin 15) JTAG-source strap is left unconnected by the designer; the datasheet states it has no internal pull and that its value must be actively driven by an external circuit, so the strap level at reset is undefined. Fit a 10k resistor to V3.3 or to GND at the intended JTAG-source level (Espressif datasheet, source: Tomachie).	Medium
11.3.4	Y1 (FC-135)	ESP32-S3 32 kHz oscillator drive level is not available, so the check against Y1's 0.5 µW maximum drive level is not done (Seiko Epson datasheet, source: Tomachie).	Review
11.3.5	PS1 (RFM-0505S)	U7 VCC2 current is not available, so the output-current derating is not closed. 200 mA derated 30% (regulator_output_current_pct = 70) permits 140 mA; the known 73 mA (63 mA U4 load plus 10 mA U4 quiescent) is below it (RECOM datasheet).	Review
11.3.6	U1 (USBLC6-2SC6)	The datasheet's layout guidance recommends 100 nF on VBUS; the only capacitor on +5V is C1 1µF, which is U2's IN capacitor. Adding a local 100nF at U1 pin 5 would follow the recommendation (STMicroelectronics datasheet).	Review
11.3.7	U10 (INA240A2)	REF2 on GNDS and REF1 on U9's 0.275 V selects the mid-external reference mode ('output set to half of the external reference'). Zero current reads 0.1375 V; the range covers 3.82 A forward and 0.275 A reverse into the ±2.048 V ADC range. The alternative, REF1 and REF2 both on GNDS, gives a unidirectional ground-referenced output (TI datasheet).	Review
11.3.8	U9 (LM321)	A 9 mV maximum offset over −40 to 85 °C shifts U10's zero by ±4.5 mV, equal to ±9 mA. A zero-current calibration with K1 open removes it (TI datasheet).	Review
11.3.9	U11 (TSZ122)	R42/R43 20k from the follower outputs to −3V3 act as a 165-253 µA sourcing load while V− is on GNDS. Placing V− on −3V3 would exceed the 5.5 V operating and 6 V absolute-maximum supply rating, so the present wiring is within ratings (STMicroelectronics datasheet).	Review
11.3.10	U11 (TSZ122)	No tolerance is stated on divider resistors R36-R41; state it in each resistor's Tolerance property (for example Tol:1%), as it sets the channel gain accuracy directly.	Review
11.3.11	U12 (LM2664)	C36 (CAP+ to CAP−, carrying up to 3.36 V): voltage rating not stated in the schematic data.	Review
11.3.12	U8 (ADS1115)	ALERT/RDY reaches only R28 and does not cross the U7 barrier; conversion-ready status must be polled over I2C (TI datasheet).	Review
11.3.13	U8 (ADS1115)	AIN0/AIN1/AIN2 worst-case levels of 1.76 V, 1.76 V and 1.39 V are inside the ±2.048 V range; anti-alias corners of 1.59 kHz and 1.06 kHz sit above the 430 Hz Nyquist limit at 860 SPS (TI datasheet).	Review
11.3.14	K1 (HF49FD_005-1H12T)	Coil pick-up voltage is not available, so the pick-up check at VUSB 4.68 V less Q1's saturation drop is not done.	Review
11.3.15	K1 (HF49FD_005-1H12T)	Net-(Q1-B) has only R33 330R and Q1. IO38's reset state is not stated, so it is unknown whether the relay stays de-energised during reset and boot. A 10k base-to-emitter resistor on Q1 would hold it off independently of firmware.	Review
11.3.16	K1 (HF49FD_005-1H12T)	Contact snubber C29 220nF (up to 30 V across the open contacts): voltage rating not stated in the schematic data.	Review
11.3.17	U5 (ESP32-S3-WROOM-1)	IO0 boot strap relies only on its weak internal pull-up (default bit value 1), with SW2 to GND and C17 do-not-install. An external 10k to V3.3 would hold the strap against noise during the 3 ms strap hold time (Espressif datasheet, source: Tomachie).	Review
11.3.18	U5 (ESP32-S3-WROOM-1)	IO45 (VDD_SPI voltage strap) and IO46 (boot-mode / ROM-print strap) are left unconnected by the designer and rest on weak internal pull-downs (default bit value 0) alone. External pull-downs would define these straps independently of the 45 kΩ internal resistors (Espressif datasheet, source: Tomachie).	Review
11.3.19	U5 (ESP32-S3-WROOM-1)	MTCK, MTDO, MTDI, MTMS nets each carry only their U5 pin, with no header or test point, so pin-level JTAG cannot be attached. Test pads on these four nets would give debug access.	Review
11.3.20	U5 (ESP32-S3-WROOM-1)	Module thermal resistance is not available, so the junction-temperature check against the 100 C IC limit is not done.	Review
11.3.21	U5 (ESP32-S3-WROOM-1)	Antenna keep-out dimensions are not available, so the onboard-antenna keep-out check is not done.	Review
11.3.22	Y1 (FC-135)	Terminals on XTAL_32K_P/XTAL_32K_N to U5 IO15/IO16, the ESP32-S3 32 kHz crystal pins (Espressif datasheet, source: Tomachie).	✓
11.3.23	Y1 (FC-135)	−40 to +85 °C operating rating equals the 85 C design ambient; meets (Seiko Epson datasheet, source: Tomachie).	✓
11.3.24	PS1 (RFM-0505S)	VUSB spans 4.68-5.25 V against the 5 V ±10% (4.5-5.5 V) input range; inside range (RECOM datasheet).	✓
11.3.25	PS1 (RFM-0505S)	About 80µF on the output (47.1µF on V5-F plus 32.6µF behind U4) against the 470 µF maximum capacitive load (RECOM datasheet).	✓
11.3.26	U1 (USBLC6-2SC6)	Flow-through wiring: D-/DG- on I/O1 (pins 1/6), D+/DG+ on I/O2 (pins 3/4), VBUS on +5V, GND on GND (STMicroelectronics datasheet).	✓
11.3.27	U1 (USBLC6-2SC6)	VBUS-GND breakdown of 6 V minimum is above the 5.5 V Type-C withstand level; leakage is 150 nA maximum at 5.25 V. Junction at 85 C meets the 85 C IC limit (min of 100 C and 125 − 40 C) (STMicroelectronics datasheet).	✓
11.3.28	U10 (INA240A2)	VS on V3.3-F (2.7-5.5 V range), GND on GNDS. V3.3-F carries six 100nF ceramics for its six IC loads, meeting the 0.1 µF bypass requirement (TI datasheet).	✓
11.3.29	U10 (INA240A2)	IN+ on the PSU_P side and IN− on the SNT_N side of R25 10mR, so positive current reads positive. R23/R24 4.7R meet the datasheet's limit of 10 Ω or less for filter resistors (TI datasheet).	✓
11.3.30	U10 (INA240A2)	Common mode of 25 V (normal band) and 30 V (survive) against −4 V to 80 V operating and 90 V absolute maximum (TI datasheet).	✓
11.3.31	U10 (INA240A2)	R34 1.5k isolates C27 100nF from the output, respecting the 1 nF capacitive-load limit; 1.06 kHz anti-alias pole. Tj of about 86 C against the 100 C IC limit (TI datasheet).	✓
11.3.32	U9 (LM321)	3.3 V supply (3.24 V minimum) inside the 3-30 V range; 0.275 V input inside the V+ − 2 V common-mode limit; Tj of about 86 C against the 100 C IC limit (TI datasheet).	✓
11.3.33	U11 (TSZ122)	V+ on V3.3-F and V− on GNDS; 3.3 V inside the 1.8-5.5 V range; V3.3-F carries the 0.1 µF chopper decoupling (STMicroelectronics datasheet).	✓
11.3.34	U11 (TSZ122)	Dividers of 320k/20k give ratio 0.0588: 1.47 V at 25 V and 1.76 V at 30 V, inside the rail-to-rail input range and the U8 ±2.048 V range (STMicroelectronics datasheet).	✓
11.3.35	U11 (TSZ122)	The 320k series leg limits input current to 37 µA with U11 unpowered at 12 V, against the datasheet's 10 mA limit, which requires a series resistor (STMicroelectronics datasheet).	✓
11.3.36	U11 (TSZ122)	R44/R45 1k isolate C33/C34 100nF from the outputs (STMicroelectronics datasheet).	✓
11.3.37	U12 (LM2664)	SD tied to V3.3-F, which the datasheet gives as 'Normal operating mode'; V+ inside 1.8-5.5 V; supply absolute maximum of 5.8 V derated 15% (regulator_input_voltage_pct = 85) permits 4.93 V against 3.36 V (TI datasheet).	✓
11.3.38	U12 (LM2664)	C36 10µF flying capacitor and C37/C38 22µF output capacitors exceed the 3.3 µF characterisation-circuit values (TI datasheet).	✓
11.3.39	U12 (LM2664)	Load of 0.51 mA (R42/R43 at 30 V) against 40 mA derated 30% (regulator_output_current_pct = 70), which permits 28 mA (TI datasheet).	✓
11.3.40	U8 (ADS1115)	VDD on V3.3-F (2-5.5 V range), GND on GNDS; 0.1 µF decoupling is present on the rail (TI datasheet).	✓
11.3.41	U8 (ADS1115)	ADDR tied to GNDS selects the ground-strapped address; U8 is the only target on the SDAS/SCLS segment (TI datasheet).	✓
11.3.42	U8 (ADS1115)	Required pull-ups present: R26 4.7k (SDAS to V3.3-F), R27 4.7k (SCLS to V3.3-F), R28 10k (ALERT/RDY to V3.3-F) (TI datasheet).	✓
11.3.43	K1 (HF49FD_005-1H12T)	The 005 suffix encodes a 5 VDC coil, which matches VUSB.	✓
11.3.44	K1 (HF49FD_005-1H12T)	D15 flyback clamp runs from the coil low side (anode) to VUSB (cathode); orientation correct (Vishay LL4148 datasheet, http://www.vishay.com/docs/85557/ll4148.pdf).	✓
11.3.45	K1 (HF49FD_005-1H12T)	Contacts rated 5 A/30 VDC per the library description; derated 40% (relay_contact_current_pct = 60) this permits 3 A against the 2.5 A load. The 25 V normal-band top and 30 V survive level are within the 30 VDC rating. This applies to a resistive load only.	✓
11.3.46	K1 (HF49FD_005-1H12T)	IO38 base drive is at most 8.2 mA through R33 330R, against a 40 mA IOH derated 30% (ic_output_current_pct = 70) to 28 mA (Espressif datasheet, source: Tomachie).	✓
11.3.47	D14 (LED)	Anode from VUSB through R32 1k, cathode on the coil low side: lights when K1 is energised; current at most 5.25 mA; about 1 V reverse during D15 clamping.	✓
11.3.48	U5 (ESP32-S3-WROOM-1)	3V3 on V3.3 (LD1117S33 output 3.24-3.36 V) inside the 3.0-3.6 V supply range and below the 3.6 V absolute maximum; GND pins 1, 40, 41 on GND (Espressif datasheet, source: Tomachie).	✓
11.3.49	U5 (ESP32-S3-WROOM-1)	Supply capability: U3's 800 mA minimum output current covers the 0.5 A minimum external-supply requirement (Espressif datasheet, source: Tomachie).	✓
11.3.50	U5 (ESP32-S3-WROOM-1)	EN: R18 10k to V3.3, C15 100nF + C16 1µF to GND, SW1 to GND. Matches the recommended 10 kΩ / 1 µF RC delay; never floating; about 15 ms rise against the 50 µs tSTBL minimum (Espressif datasheet, source: Tomachie).	✓
11.3.51	U5 (ESP32-S3-WROOM-1)	IO8, IO9, IO10 are unconnected in the schematic; the datasheet places no connection requirement on these GPIOs.	✓
11.3.52	U5 (ESP32-S3-WROOM-1)	USB_D-/USB_D+ (pins 13/14) on DG-/DG+ through U1 to J1 D-/D+; polarity correct (Espressif datasheet, source: Tomachie).	✓
11.3.53	U5 (ESP32-S3-WROOM-1)	UART0: TXD0 through R21 22R and RXD0 through R22 22R to J3 pins 1/2, with GND on J3 pin 3.	✓
11.3.54	U5 (ESP32-S3-WROOM-1)	I2C on IO1/IO2 with R6/R7 4.7k pull-ups to V3.3 to U7 side 1. J2 lines SDA1/SCL1 (R12/R13 4.7k) and TRG1/TRG2 (R10/R11 10k) are pulled to V3.3, with 22R series resistors and ESD5Zxx clamps to GND.	✓
11.3.55	U5 (ESP32-S3-WROOM-1)	LED drive from IO17/IO18 through 1k is at most 3.3 mA against a 40 mA IOH derated 30% (ic_output_current_pct = 70) to 28 mA (Espressif datasheet, source: Tomachie).	✓
11.3.56	U5 (ESP32-S3-WROOM-1)	−40 to 85 °C module rating equals the 85 C design ambient; meets (Espressif datasheet, source: Tomachie).	✓

11.4 Citations

AI-Assisted —

References
ADS1115 (Texas Instruments) — datasheet, cited pages 1,15 www.ti.com/lit/ds/symlink/ads1113.pdf
AP22818A (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/AP22816_17_18.pdf
B5817W (SMC Diode Solutions) — datasheet www.sangdest.com.cn/propdf/B5817W-B5819W%20N1752%20REV.A.pdf
INA240A2 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/ina240.pdf
LD1117S33 (SGS-THOMSON Microelectronics) — datasheet www.sm0vpo.com/_pdf/LM/LM1117.PDF
LL4148 (Vishay Semiconductors) — datasheet www.vishay.com/docs/85557/ll4148.pdf
LM2664 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/lm2664.pdf
LM321 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/lm321.pdf
MMBT2222A (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/MMBT2222A.pdf
RFM-0505S (RECOM) — datasheet www.mouser.com/datasheet/2/468/RFM-1307831.pdf
SMBJ (Kyocera AVX) — datasheet, cited pages 1,2,3 datasheets.kyocera-avx.com/tvsdiodes.pdf
TSZ122 (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/tsz121.pdf
USBLC6-2SC6 (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7c...

12 Designer Annotated Nets

Annotated signals

Designer-placed annotation markers on nets that are not already analyzed as HSSI differential pairs or Memory Bus signals.

Designer Annotations
Net Name	Annotation	Impedance	Notes
+5V	PWR
-3V3	PWR
GND	PWR
GNDS	PWR
V3.3	PWR
V3.3-F	PWR
V5-F	PWR
VUSB	PWR

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J1	TYPE-C-31-M-12	J1 (TYPE-C-31-M-12): Shell pins share the logic GND net, so the shield-bond strategy is not captured as design intent.	USB Type-C R2.5 §3.2.1 requires the receptacle shell to be connected to the PCB ground plane; a shield net bonded to logic GND through R\|\|C satisfies it and does not leave the shell floating. Assign a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD) so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MΩ \|\| 4.7 nF (≥2 kV) from the shield net to logic GND. IEC 61000-4-2.

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed:4 connector-facing signal(s). 0 protected, 4 unprotected, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
D+	J1	No ESD Protection
D-	J1	No ESD Protection
Net-(J1-CC1)	J1	No ESD Protection
Net-(J1-CC2)	J1	No ESD Protection

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture

AI-Assisted — The board has two ground domains: GND (logic) and PGND (chassis). The isolated return GNDS is kept apart from GND. Three parts cross between GNDS and GND: C8 is connected between the two grounds, while PS1 (RFM-0505S) and U7 (ISO1540) each have a pin on each ground. This is a galvanic isolation barrier, not a shield bond. The bare capacitor C8 across it is complete as drawn, and GNDS floating at DC is the designer's intent. The barrier ratings are judged in the power review. One question remains for the designer: is the DC potential of GNDS relative to GND meant to stay undefined? If it should be defined, a bleed must itself meet the barrier's insulation class and working voltage (IEC 62368-1 5.5.6, Annex G.10). It would be a series resistor string or a single safety-rated high-voltage resistor, and its value is set by the installation, not by this review.

J1 is the only shielded connector. Its shell contacts S1-S4 sit directly on GND. The external entry points examined are J1, J2 and J3. Every signal on them has either a clamp or a 22R series resistor between the contact and U5, except CC1/CC2, which terminate in R1/R2 5.1k to GND. Judged at professional level, since the board is instrumentation and not declared hobby or internal.

13.3.2 J1 USB Type-C Receptacle

AI-Assisted — J1 is a consumer-facing, hot-plug cable connector, so its shell is exposed to IEC 61000-4-2 contact discharge at first touch. The GND pins A1_B12 and B1_A12 are correctly on logic GND. The symbol has no mid-plate pin.

The data lines D+ and D- land on U1 (USBLC6-2SC6) I/O2 and I/O1. U1 GND pin 2 is on logic GND, which is the correct reference for the device it protects. U1's 17 V clamp (5 A, 8/20 µs) against the U5 USB pins was left open by the signal-integrity review because the U5 pin rating is missing. That comparison is not repeated here.

CC1 and CC2 connect only to R1/R2 5.1k to GND, with no clamp on those contacts. Because they end in passive Rd terminations with no IC pin behind them, the exposure is limited to the resistors. No clamp is drawn on the VBUS contacts; the rating needed for that comparison is not in the data.

13.3.3 J2 Trigger/I2C Header and J3 UART Header

AI-Assisted — J2 and J3 are vertical 2.54 mm pin headers. That form suggests internal or cabled service use rather than a panel connector.

On J2, every signal pin carries a unidirectional ESD5Zxx clamp: D6 on pin 1 (TRG1), D5 on pin 2 (TRG2), D7 on pin 5 (SCL1) and D8 on pin 6 (SDA1). Each clamp sits on the connector-side net, with its cathode on the signal and its anode on GND, and the orientation is consistent. A 22R resistor (R14-R17) then leads to U5 IO5, IO4, IO7 and IO6. The clamp voltage of the fitted ESD5Zxx variant is not in the data, so it cannot be compared with the U5 3.6 V absolute maximum (Espressif ESP32-S3-WROOM-1 datasheet). J2 pin 4 exports V3.3 with no clamp.

On J3, pins 1 and 2 reach U5 TXD0 and RXD0 through R21/R22 22R, with no clamp.

13.4 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.4.1	J1	Shell contacts S1-S4 share the logic GND net, so the shield-bond strategy is not captured as design intent. Assign a dedicated SHIELD_GND_J1 net so the pour and bond parts are explicit. A copper pour under the connector, stitched directly to logic GND, is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use 1 MOhm \|\| 4.7 nF (>= 2 kV) from SHIELD_GND_J1 to logic GND. USB Type-C R2.5 section 3.2.1; IEC 61000-4-2.	Medium
13.4.2	J1	The CC1/CC2 contacts have no clamp and terminate only in R1/R2 5.1k to GND. Worth investigating against IEC 61000-4-2 for a consumer-facing port.	Review
13.4.3	J2	The ESD5Zxx clamp voltage is not available, so the D5-D8 clamp check against the U5 3.6 V absolute maximum is not done (Espressif datasheet).	Review
13.4.4	J3	TX/RX reach U5 TXD0/RXD0 through 22R with no clamp. Acceptable for an internal header; investigate if the header is cabled externally (IEC 61000-4-2).	Review
13.4.5	GNDS barrier	C8, PS1 and U7 cross the GNDS/GND barrier; this is not a shield bond. It is left open whether GNDS is intended to float at DC; any bleed must meet the barrier insulation class (IEC 62368-1 5.5.6).	Review
13.4.6	J1	D+/D- are clamped by U1 with GND pin 2 on logic GND, which is the correct reference (STMicroelectronics USBLC6-2SC6 datasheet).	✓
13.4.7	J2	D5-D8 are unidirectional with the cathode on the signal and the anode on GND; orientation is consistent.	✓

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on LSSI buses	Yes	Place test points on every LSSI bus signal (JTAG, SWD, I2C, I3C, MDIO, SPI, QSPI, UART) that has none
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	9
Rails with TPs	8
Rails without TPs	1
With designer annotation	8

1 power rail(s) need test points in the submitted design.

21 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+5V	PWR	TP1	✓
-3V3	PWR	-	NEEDS TP
GND	PWR	H1_1, H2_1, J2_3, J3_3 (through-hole)	✓
GNDS	PWR	H3_1, H4_1 (through-hole)	✓
PGND		H10_1, H11_1 (through-hole)	✓
V3.3	PWR	TP4	✓
V3.3-F	PWR	TP6	✓
V5-F	PWR	TP5	✓
VUSB	PWR	TP3	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP13	GND	esp32.kicad_sch
TP18	GNDS	front-end-adc-c.kicad_sch
TP19	PGND	front-end-adc-c.kicad_sch
TP23	-3V3	front-end-voltage.kicad_sch
TP25	GNDS	front-end-adc-c.kicad_sch
TP26	GNDS	front-end-voltage.kicad_sch
TP27	GNDS	power.kicad_sch

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP7	SDA	esp32.kicad_sch
TP8	SCL	esp32.kicad_sch
TP9	CLK	esp32.kicad_sch
TP10	DI_MOSI	esp32.kicad_sch
TP11	DO_MISO	esp32.kicad_sch
TP12	CS	esp32.kicad_sch
TP14	EN	esp32.kicad_sch
TP15	IO0	esp32.kicad_sch
TP16	Net-(D3-A)	esp32.kicad_sch
TP17	Net-(D4-A)	esp32.kicad_sch
TP20	Net-(Q1-B)	front-end-adc-c.kicad_sch
TP21	PSU_P	front-end-adc-c.kicad_sch
TP22	SNT_N	front-end-adc-c.kicad_sch
TP24	Net-(D2-K)	usb.kicad_sch

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U2	AP22818AKEWT	EN	4	EN has pull-up resistor but no test point at R5_1, U2_4
U5	ESP32-S3-WROOM-1	EN	3	EN has pull-up resistor but no test point at C15_1, C16_1, R18_2, SW1_1, U5_3

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	1

1 resistor(s) need test points for Kelvin test

RefDes	Value	TP Pin1	TP Pin2	Need Pin1	Need Pin2	Status
R25	10mR	0	0	+2	+2

14.5 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
TestPoint_Pad_D1.5mm	V_IN	6

14.5.1 By Sheet

Test Point	Net Name	Footprint
power (3 test points)
TP4	V3.3	TestPoint_Pad_D1.5mm
TP5	V5-F	TestPoint_Pad_D1.5mm
TP6	V3.3-F	TestPoint_Pad_D1.5mm
usb (3 test points)
TP1	+5V	TestPoint_Pad_D1.5mm
TP2	Net-(U2-FLG)	TestPoint_Pad_D1.5mm
TP3	VUSB	TestPoint_Pad_D1.5mm

14.5.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP1	+5V	usb	TestPoint_Pad_D1.5mm
TP2	Net-(U2-FLG)	usb	TestPoint_Pad_D1.5mm
TP3	VUSB	usb	TestPoint_Pad_D1.5mm
TP4	V3.3	power	TestPoint_Pad_D1.5mm
TP5	V5-F	power	TestPoint_Pad_D1.5mm
TP6	V3.3-F	power	TestPoint_Pad_D1.5mm

14.6 Powered-off Testing

6 nets with test points: 1 pins with opens coverage, 0 pins with partial opens, 66 pins with shorts coverage.

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
C1_1	+5V	Capacitor	-	●
D1_2	+5V	Passive	-	●
D2_2	+5V	Passive	-	●
J1_A4_B9	+5V	Connector	-	●
J1_B4_A9	+5V	Connector	-	●
R5_2	+5V	Passive	-	●
U1_5	+5V	IC	-	●
U2_5	+5V	IC	-	●
R4_1	Net-(U2-FLG)	Passive	-	●
U2_3	Net-(U2-FLG)	IC	●	●
C5_1	V3.3	Capacitor	-	●
C12_1	V3.3	Capacitor	-	●
C13_1	V3.3	Capacitor	-	●
C19_2	V3.3	Capacitor	-	●
C20_1	V3.3	Capacitor	-	●
D9_1	V3.3	Passive	-	●
J2_4	V3.3	Connector	-	●
R6_2	V3.3	Passive	-	●
R7_2	V3.3	Passive	-	●
R10_2	V3.3	Passive	-	●
R11_2	V3.3	Passive	-	●
R12_2	V3.3	Passive	-	●
R13_2	V3.3	Passive	-	●
R18_1	V3.3	Passive	-	●
R19_1	V3.3	Passive	-	●
R20_1	V3.3	Passive	-	●
U3_2	V3.3	IC	-	●
U5_2	V3.3	IC	-	●
U6_8	V3.3	IC	-	●
U7_1	V3.3	IC	-	●
C11_1	V3.3-F	Capacitor	-	●
C22_1	V3.3-F	Capacitor	-	●
C23_1	V3.3-F	Capacitor	-	●
C24_1	V3.3-F	Capacitor	-	●
C26_1	V3.3-F	Capacitor	-	●
C28_1	V3.3-F	Capacitor	-	●
C32_1	V3.3-F	Capacitor	-	●
C35_1	V3.3-F	Capacitor	-	●
R26_1	V3.3-F	Passive	-	●
R27_1	V3.3-F	Passive	-	●
R28_1	V3.3-F	Passive	-	●
R30_1	V3.3-F	Passive	-	●
U4_2	V3.3-F	IC	-	●
U7_8	V3.3-F	IC	-	●
U8_8	V3.3-F	IC	-	●
U9_5	V3.3-F	IC	-	●
U10_6	V3.3-F	IC	-	●
U11_8	V3.3-F	IC	-	●
U12_4	V3.3-F	IC	-	●
U12_5	V3.3-F	IC	-	●
C7_2	V5-F	Capacitor	-	●
C9_1	V5-F	Capacitor	-	●
C10_1	V5-F	Capacitor	-	●
PS1_4	V5-F	Passive	-	●
U4_3	V5-F	IC	-	●
C2_1	VUSB	Capacitor	-	●
C3_1	VUSB	Capacitor	-	●
C4_1	VUSB	Capacitor	-	●
C6_1	VUSB	Capacitor	-	●
C7_1	VUSB	Capacitor	-	●
D15_1	VUSB	Passive	-	●
K1_1	VUSB	Passive	-	●
PS1_2	VUSB	Passive	-	●
R32_1	VUSB	Passive	-	●
U2_1	VUSB	IC	-	●
U3_3	VUSB	IC	-	●

14.7 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

5 power rail nets with test points: 24 source-path pins (opens + shorts), 45 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
C1_1	+5V	Sink	-	●
D1_2	+5V	Sink	-	●
D2_2	+5V	Sink	-	●
J1_A4_B9	+5V	Sink	-	●
J1_B4_A9	+5V	Sink	-	●
R5_2	+5V	Series (U2 → R5)	●	●
TP1_1	+5V	Sink	-	●
U1_5	+5V	Sink	-	●
U2_5	+5V	Series path	●	●
C5_1	V3.3	Sink	-	●
C12_1	V3.3	Sink	-	●
C13_1	V3.3	Sink	-	●
C19_2	V3.3	Sink	-	●
C20_1	V3.3	Sink	-	●
D9_1	V3.3	Sink	-	●
J2_4	V3.3	Sink	-	●
R6_2	V3.3	Series (U7 → R6)	●	●
R7_2	V3.3	Series (U7 → R7)	●	●
R10_2	V3.3	Series (U5 → R10)	●	●
R11_2	V3.3	Series (U5 → R11)	●	●
R12_2	V3.3	Series (U5 → R12)	●	●
R13_2	V3.3	Series (U5 → R13)	●	●
R18_1	V3.3	Series (U5 → R18)	●	●
R19_1	V3.3	Series (U6 → R19)	●	●
R20_1	V3.3	Series (U6 → R20)	●	●
TP4_1	V3.3	Sink	-	●
U3_2	V3.3	Source (VO)	●	●
U5_2	V3.3	Series path	●	●
U6_8	V3.3	Series path	●	●
U7_1	V3.3	Series path	●	●
C11_1	V3.3-F	Sink	-	●
C22_1	V3.3-F	Sink	-	●
C23_1	V3.3-F	Sink	-	●
C24_1	V3.3-F	Sink	-	●
C26_1	V3.3-F	Sink	-	●
C28_1	V3.3-F	Sink	-	●
C32_1	V3.3-F	Sink	-	●
C35_1	V3.3-F	Sink	-	●
R26_1	V3.3-F	Series (U8 → R26)	●	●
R27_1	V3.3-F	Series (U8 → R27)	●	●
R28_1	V3.3-F	Series (U8 → R28)	●	●
R30_1	V3.3-F	Series (U9 → R30)	●	●
TP6_1	V3.3-F	Sink	-	●
U4_2	V3.3-F	Source (VO)	●	●
U7_8	V3.3-F	Series path	●	●
U8_8	V3.3-F	Series path	●	●
U9_5	V3.3-F	Series path	●	●
U10_6	V3.3-F	Sink	-	●
U11_8	V3.3-F	Sink	-	●
U12_4	V3.3-F	Sink	-	●
U12_5	V3.3-F	Sink	-	●
C7_2	V5-F	Sink	-	●
C9_1	V5-F	Sink	-	●
C10_1	V5-F	Sink	-	●
PS1_4	V5-F	Sink	-	●
TP5_1	V5-F	Sink	-	●
U4_3	V5-F	Sink	-	●
C2_1	VUSB	Sink	-	●
C3_1	VUSB	Sink	-	●
C4_1	VUSB	Sink	-	●
C6_1	VUSB	Sink	-	●
C7_1	VUSB	Sink	-	●
D15_1	VUSB	Sink	-	●
K1_1	VUSB	Sink	-	●
PS1_2	VUSB	Sink	-	●
R32_1	VUSB	Sink	-	●
TP3_1	VUSB	Sink	-	●
U2_1	VUSB	Source (OUT)	●	●
U3_3	VUSB	Sink	-	●

14.8 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.9 Inspection

Total: 111 components, 311 of 323 pins with inspection coverage.

14.9.1 AOI

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Package_TO_SOT_SMD
SOT-223-3_TabPin2			SOT (Small Outline Transistor)	Footprint	2	6	U3, U4
SOT-23			SOT (Small Outline Transistor)	Footprint	1	3	Q1
SOT-23-5			SOT (Small Outline Transistor)	Footprint	2	10	U2, U9
SOT-23-6			SOT (Small Outline Transistor)	Footprint	2	12	U1, U12
Capacitor_SMD
CP_Elec_5x5.9			Chip Passive	Designator	2	4	C3, C9
C_0805_2012Metric			Chip Passive	Designator	29	58	C1, C10, C12, C13, C14, C15, C16, C18 ...+21 more
C_1206_3216Metric			Chip Passive	Designator	2	4	C11, C5
C_1206_3216Metric_Pad1.33x1.80mm_HandSolder			Chip Passive	Designator	2	4	C7, C8
Resistor_SMD
R_0805_2012Metric			Chip Passive	Designator	42	84	R1, R10, R11, R12, R13, R14, R15, R16 ...+34 more
R_2512_6332Metric_Pad1.40x3.35mm_HandSolder			Chip Passive	Designator	1	2	R25
Diode_SMD
D_MiniMELF			SOD (Diode Package)	Designator	1	2	D15
D_SMB			SOD (Diode Package)	Designator	1	2	D13
D_SOD-523			SOD (Diode Package)	Footprint	4	8	D5, D6, D7, D8
LED_SMD
LED_0805_2012Metric			SOD (Diode Package)	Designator	5	10	D1, D14, D2, D3, D4
snapeda-footprints
XTAL_FC-135_32.7680KA-A0			Oscillator / Crystal	Designator	1	2	Y1
Subtotal: 97 components, 211 pins
Opens only (leads visible, shorts unreliable)
Package_SO
SOIC-8_3.9x4.9mm_P1.27mm			SOIC/SOP	Footprint	5	24	U10, U11, U11, U11, U7
TSSOP-10_3x3mm_P0.5mm			SOIC/SOP	Footprint	1	10	U8
RF_Module
ESP32-S3-WROOM-1			SOIC/SOP	Designator	1	41	U5
Subtotal: 7 components, 75 pins
Presence check (manual verification)
Connector_PinHeader_2.54mm
PinHeader_1x03_P2.54mm_Vertical			Connector	Designator	1	3	J3
PinHeader_2x03_P2.54mm_Vertical			Connector	Designator	1	6	J2
snapeda-footprints
HRO_TYPE-C-31-M-12			Connector	Designator	1	16	J1
Subtotal: 3 components, 25 pins

14.9.2 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
Button_Switch_SMD
SW_SPST_TS-1088-xR025	Unclassified	Unknown	2	4	SW1, SW2
snapeda-footprints
CONV_RFM-0505S	Unclassified	Unknown	1	4	PS1
RELAY_HF49FD_005-1H12T	Unclassified	Unknown	1	4	K1
Subtotal: 4 components, 12 pins

14.10 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.10.1 Fault Coverage Summary

Fault Coverage Summary (349 pins)
Test Method	Opens	Shorts
X-ray (AXI)	0 (0.0%)	0 (0.0%)
Optical (AOI)	0 (0.0%)	0 (0.0%)
Electrical
Powered-off Testing	24 (6.9%)	66 (18.9%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	6 (1.7%)	6 (1.7%)
Total	56 (16.0%)	162 (46.4%)
Total Fault Coverage	56 (16.0%)	162 (46.4%)
No coverage	293 (84.0%)	187 (53.6%)

14.10.2 Uncovered Pins (187)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
C31_1	Net-(U11A-+)
C30_1	Net-(U11B-+)
R37_1	PSU_P
R37_2	Net-(R37-Pad2)
R45_1	AIN1
R45_2	Net-(U11B--)
R38_1	Net-(R36-Pad2)
R38_2	Net-(U11B-+)
C36_1	Net-(U12-CAP+)
C36_2	Net-(U12-CAP-)
U11_1	Net-(U11A--)
U11_2	Net-(U11A--)
U11_3	Net-(U11A-+)
R36_1	LOAD_P
R36_2	Net-(R36-Pad2)
R39_1	Net-(R37-Pad2)
R39_2	Net-(U11A-+)
R40_2	Net-(U11B-+)
C34_1	AIN1
U12_3	Net-(U12-CAP-)
U12_6	Net-(U12-CAP+)
R41_2	Net-(U11A-+)
U11_5	Net-(U11B-+)
U11_6	Net-(U11B--)
U11_7	Net-(U11B--)
R42_2	Net-(U11A--)
R44_1	AIN0
R44_2	Net-(U11A--)
R43_2	Net-(U11B--)
C33_1	AIN0
D2_1	Net-(D2-K)
R4_2	Net-(D2-K)
R3_1	Net-(D1-K)
U2_4	Net-(U2-EN)
R2_1	Net-(J1-CC2)
D1_1	Net-(D1-K)
J1_A5	Net-(J1-CC1)
J1_A6	D+
J1_A7	D-
J1_A8
J1_B5	Net-(J1-CC2)
J1_B6	D+
J1_B7	D-
J1_B8
R5_1	Net-(U2-EN)
R1_1	Net-(J1-CC1)
U1_1	D-
U1_3	D+
U1_4	DG+
U1_6	DG-
D15_2	Net-(D14-K)
U8_2	Net-(U8-ALERT/RDY)
U8_4	AIN0
U8_5	AIN1
U8_6	AIN2
U8_7
U8_9	SDAS
U8_10	SCLS
R26_2	SDAS
U9_1	Net-(U9-+)
U9_3	Net-(U10-REF1)
U9_4	Net-(U10-REF1)
R35_1	LOAD_P
R35_2	Net-(C29-Pad1)
D12_1	SENSE_N
D13_1	PSU_P
R27_2	SCLS
D10_2	Net-(D10-A)
R30_2	Net-(U9-+)
R33_1	R_CTR
R33_2	Net-(Q1-B)
C29_1	Net-(C29-Pad1)
C29_2	SNT_N
C21_1	SENSE_P
C21_2	SENSE_N
R23_1	SENSE_P
R23_2	PSU_P
R28_2	Net-(U8-ALERT/RDY)
C27_1	AIN2
U7_2	SDA
U7_3	SCL
U7_6	SCLS
U7_7	SDAS
D11_1	SENSE_P
D11_2	Net-(D10-A)
U10_1	SENSE_N
U10_5	Net-(R34-Pad2)
U10_7	Net-(U10-REF1)
U10_8	SENSE_P
D14_1	Net-(D14-K)
D14_2	Net-(D14-A)
Q1_1	Net-(Q1-B)
Q1_3	Net-(D14-K)
R25_1	SNT_N
R25_2	PSU_P
K1_2	Net-(D14-K)
K1_3	SNT_N
K1_4	LOAD_P
R34_1	AIN2
R34_2	Net-(R34-Pad2)
R31_1	Net-(U9-+)
R32_2	Net-(D14-A)
R24_1	SENSE_N
R24_2	SNT_N
R12_1	SDA1
R15_1	TRG1
R15_2	Net-(D6-K)
D3_2	Net-(D3-A)
D6_1	Net-(D6-K)
U5_3	EN
U5_4	TRG1
U5_5	TRG2
U5_6	SDA1
U5_7	SCL1
U5_8	XTAL_32K_P
U5_9	XTAL_32K_N
U5_10	ST_USB
U5_11	ST_WLAN
U5_12
U5_13	DG-
U5_14	DG+
U5_15
U5_16
U5_17
U5_18
U5_19	DI_MOSI
U5_20	CLK
U5_21	DO_MISO
U5_22	CS
U5_23
U5_24
U5_25
U5_26
U5_27	IO0
U5_28
U5_29
U5_30
U5_31	R_CTR
U5_32	MTCK
U5_33	MTDO
U5_34	MTDI
U5_35	MTMS
U5_36	RX
U5_37	TX
U5_38	SCL
U5_39	SDA
R11_1	TRG2
R17_1	SDA1
R21_1	Net-(J3-Pin_1)
R21_2	TX
C14_1	XTAL_32K_P
Y1_1	XTAL_32K_P
Y1_2	XTAL_32K_N
D5_1	Net-(D5-K)
R10_1	TRG1
R8_1	ST_USB
R8_2	Net-(D3-A)
R14_1	TRG2
R14_2	Net-(D5-K)
C17_1	IO0
C16_1	EN
U6_1	CS
U6_2	DO_MISO
U6_3	Net-(U6-WP/IO₂₎
U6_5	DI_MOSI
U6_6	CLK
U6_7	Net-(U6-HOLD/RESET/IO₃₎
R20_2	Net-(U6-WP/IO₂₎
C18_1	XTAL_32K_N
SW1_1	EN
R18_2	EN
J3_1	Net-(J3-Pin_1)
J3_2	Net-(J3-Pin_2)
C15_1	EN
R22_1	Net-(J3-Pin_2)
R22_2	RX
SW2_1	IO0
J2_1	Net-(D6-K)
J2_2	Net-(D5-K)
R7_1	SCL
R16_1	SCL1
R19_2	Net-(U6-HOLD/RESET/IO₃₎
R13_1	SCL1
R9_1	ST_WLAN
R9_2	Net-(D4-A)
D4_2	Net-(D4-A)
R6_1	SDA

14.10.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
C31_1	Net-(U11A-+)	-	-	-	-	-	-
C31_2	PGND	●	●	-	-	-	-
C30_1	Net-(U11B-+)	-	-	-	-	-	-
C30_2	PGND	●	●	-	-	-	-
R37_1	PSU_P	-	-	-	-	-	-
R37_2	Net-(R37-Pad2)	-	-	-	-	-	-
R45_1	AIN1	-	-	-	-	-	-
R45_2	Net-(U11B--)	-	-	-	-	-	-
R38_1	Net-(R36-Pad2)	-	-	-	-	-	-
R38_2	Net-(U11B-+)	-	-	-	-	-	-
C36_1	Net-(U12-CAP+)	-	-	-	-	-	-
C36_2	Net-(U12-CAP-)	-	-	-	-	-	-
U11_1	Net-(U11A--)	-	-	-	-	-	-
U11_2	Net-(U11A--)	-	-	-	-	-	-
U11_3	Net-(U11A-+)	-	-	-	-	-	-
C35_1	V3.3-F	-	●	-	-	-	-
C35_2	GNDS	-	●	-	-	-	-
R36_1	LOAD_P	-	-	-	-	-	-
R36_2	Net-(R36-Pad2)	-	-	-	-	-	-
R39_1	Net-(R37-Pad2)	-	-	-	-	-	-
R39_2	Net-(U11A-+)	-	-	-	-	-	-
R40_1	PGND	●	●	-	-	-	-
R40_2	Net-(U11B-+)	-	-	-	-	-	-
C34_1	AIN1	-	-	-	-	-	-
C34_2	GNDS	●	●	-	-	-	-
C37_1	-3V3	-	●	-	-	-	-
C37_2	GNDS	-	●	-	-	-	-
U12_1	GNDS	-	●	-	-	-	-
U12_2	-3V3	●	●	-	-	-	-
U12_3	Net-(U12-CAP-)	-	-	-	-	-	-
U12_4	V3.3-F	-	●	-	-	-	-
U12_5	V3.3-F	-	●	-	-	-	-
U12_6	Net-(U12-CAP+)	-	-	-	-	-	-
U11_4	GNDS	●	●	-	-	-	-
U11_8	V3.3-F	-	●	-	-	-	-
R41_1	PGND	●	●	-	-	-	-
R41_2	Net-(U11A-+)	-	-	-	-	-	-
C32_1	V3.3-F	-	●	-	-	-	-
C32_2	GNDS	-	●	-	-	-	-
U11_5	Net-(U11B-+)	-	-	-	-	-	-
U11_6	Net-(U11B--)	-	-	-	-	-	-
U11_7	Net-(U11B--)	-	-	-	-	-	-
R42_1	-3V3	●	●	-	-	-	-
R42_2	Net-(U11A--)	-	-	-	-	-	-
R44_1	AIN0	-	-	-	-	-	-
R44_2	Net-(U11A--)	-	-	-	-	-	-
R43_1	-3V3	●	●	-	-	-	-
R43_2	Net-(U11B--)	-	-	-	-	-	-
C38_1	-3V3	-	●	-	-	-	-
C38_2	GNDS	-	●	-	-	-	-
C33_1	AIN0	-	-	-	-	-	-
C33_2	GNDS	●	●	-	-	-	-
D2_1	Net-(D2-K)	-	-	-	-	-	-
D2_2	+5V	-	●	-	-	-	-
R4_1	Net-(U2-FLG)	-	●	-	-	-	-
R4_2	Net-(D2-K)	-	-	-	-	-	-
R3_1	Net-(D1-K)	-	-	-	-	-	-
R3_2	GND	-	●	-	-	-	-
C3_1	VUSB	-	●	-	-	-	-
C3_2	GND	-	●	-	-	-	-
U2_1	VUSB	●	●	-	-	-	-
U2_2	GND	-	●	-	-	-	-
U2_3	Net-(U2-FLG)	-	●	-	-	-	-
U2_4	Net-(U2-EN)	-	-	-	-	-	-
U2_5	+5V	●	●	-	-	-	-
C2_1	VUSB	-	●	-	-	-	-
C2_2	GND	-	●	-	-	-	-
R2_1	Net-(J1-CC2)	-	-	-	-	-	-
R2_2	GND	-	●	-	-	-	-
D1_1	Net-(D1-K)	-	-	-	-	-	-
D1_2	+5V	-	●	-	-	-	-
J1_A1_B12	GND	-	●	-	-	-	-
J1_A4_B9	+5V	-	●	-	-	-	-
J1_A5	Net-(J1-CC1)	-	-	-	-	-	-
J1_A6	D+	-	-	-	-	-	-
J1_A7	D-	-	-	-	-	-	-
J1_A8		-	-	-	-	-	-
J1_B1_A12	GND	-	●	-	-	-	-
J1_B4_A9	+5V	-	●	-	-	-	-
J1_B5	Net-(J1-CC2)	-	-	-	-	-	-
J1_B6	D+	-	-	-	-	-	-
J1_B7	D-	-	-	-	-	-	-
J1_B8		-	-	-	-	-	-
J1_S1	GND	-	●	-	-	-	-
J1_S2	GND	-	●	-	-	-	-
J1_S3	GND	-	●	-	-	-	-
J1_S4	GND	-	●	-	-	-	-
R5_1	Net-(U2-EN)	-	-	-	-	-	-
R5_2	+5V	●	●	-	-	-	-
R1_1	Net-(J1-CC1)	-	-	-	-	-	-
R1_2	GND	-	●	-	-	-	-
U1_1	D-	-	-	-	-	-	-
U1_2	GND	-	●	-	-	-	-
U1_3	D+	-	-	-	-	-	-
U1_4	DG+	-	-	-	-	-	-
U1_5	+5V	-	●	-	-	-	-
U1_6	DG-	-	-	-	-	-	-
C1_1	+5V	-	●	-	-	-	-
C1_2	GND	-	●	-	-	-	-
D15_1	VUSB	-	●	-	-	-	-
D15_2	Net-(D14-K)	-	-	-	-	-	-
U8_1	GNDS	●	●	-	-	-	-
U8_2	Net-(U8-ALERT/RDY)	-	-	-	-	-	-
U8_3	GNDS	●	●	-	-	-	-
U8_4	AIN0	-	-	-	-	-	-
U8_5	AIN1	-	-	-	-	-	-
U8_6	AIN2	-	-	-	-	-	-
U8_7		-	-	-	-	-	-
U8_8	V3.3-F	●	●	-	-	-	-
U8_9	SDAS	-	-	-	-	-	-
U8_10	SCLS	-	-	-	-	-	-
R26_1	V3.3-F	●	●	-	-	-	-
R26_2	SDAS	-	-	-	-	-	-
C24_1	V3.3-F	-	●	-	-	-	-
C24_2	GNDS	-	●	-	-	-	-
U9_1	Net-(U9-+)	-	-	-	-	-	-
U9_2	GNDS	●	●	-	-	-	-
U9_3	Net-(U10-REF1)	-	-	-	-	-	-
U9_4	Net-(U10-REF1)	-	-	-	-	-	-
U9_5	V3.3-F	●	●	-	-	-	-
R35_1	LOAD_P	-	-	-	-	-	-
R35_2	Net-(C29-Pad1)	-	-	-	-	-	-
D12_1	SENSE_N	-	-	-	-	-	-
D12_2	GNDS	-	●	-	-	-	-
D13_1	PSU_P	-	-	-	-	-	-
D13_2	PGND	-	●	-	-	-	-
R27_1	V3.3-F	●	●	-	-	-	-
R27_2	SCLS	-	-	-	-	-	-
C26_1	V3.3-F	-	●	-	-	-	-
C26_2	GNDS	-	●	-	-	-	-
C20_1	V3.3	-	●	-	-	-	-
C20_2	GND	-	●	-	-	-	-
D10_1	GNDS	-	●	-	-	-	-
D10_2	Net-(D10-A)	-	-	-	-	-	-
R30_1	V3.3-F	●	●	-	-	-	-
R30_2	Net-(U9-+)	-	-	-	-	-	-
R33_1	R_CTR	-	-	-	-	-	-
R33_2	Net-(Q1-B)	-	-	-	-	-	-
C29_1	Net-(C29-Pad1)	-	-	-	-	-	-
C29_2	SNT_N	-	-	-	-	-	-
C21_1	SENSE_P	-	-	-	-	-	-
C21_2	SENSE_N	-	-	-	-	-	-
R23_1	SENSE_P	-	-	-	-	-	-
R23_2	PSU_P	-	-	-	-	-	-
R28_1	V3.3-F	●	●	-	-	-	-
R28_2	Net-(U8-ALERT/RDY)	-	-	-	-	-	-
C27_1	AIN2	-	-	-	-	-	-
C27_2	GNDS	●	●	-	-	-	-
C28_1	V3.3-F	-	●	-	-	-	-
C28_2	GNDS	-	●	-	-	-	-
U7_1	V3.3	●	●	-	-	-	-
U7_2	SDA	-	-	-	-	-	-
U7_3	SCL	-	-	-	-	-	-
U7_4	GND	-	●	-	-	-	-
U7_5	GNDS	-	●	-	-	-	-
U7_6	SCLS	-	-	-	-	-	-
U7_7	SDAS	-	-	-	-	-	-
U7_8	V3.3-F	●	●	-	-	-	-
D11_1	SENSE_P	-	-	-	-	-	-
D11_2	Net-(D10-A)	-	-	-	-	-	-
C22_1	V3.3-F	-	●	-	-	-	-
C22_2	GNDS	-	●	-	-	-	-
C23_1	V3.3-F	-	●	-	-	-	-
C23_2	GNDS	-	●	-	-	-	-
U10_1	SENSE_N	-	-	-	-	-	-
U10_2	GNDS	●	●	-	-	-	-
U10_3	GNDS	●	●	-	-	-	-
U10_4	GNDS	●	●	-	-	-	-
U10_5	Net-(R34-Pad2)	-	-	-	-	-	-
U10_6	V3.3-F	-	●	-	-	-	-
U10_7	Net-(U10-REF1)	-	-	-	-	-	-
U10_8	SENSE_P	-	-	-	-	-	-
R29_1	PGND	-	●	-	-	-	-
R29_2	GNDS	-	●	-	-	-	-
D14_1	Net-(D14-K)	-	-	-	-	-	-
D14_2	Net-(D14-A)	-	-	-	-	-	-
Q1_1	Net-(Q1-B)	-	-	-	-	-	-
Q1_2	GND	-	●	-	-	-	-
Q1_3	Net-(D14-K)	-	-	-	-	-	-
R25_1	SNT_N	-	-	-	-	-	-
R25_2	PSU_P	-	-	-	-	-	-
K1_1	VUSB	-	●	-	-	-	-
K1_2	Net-(D14-K)	-	-	-	-	-	-
K1_3	SNT_N	-	-	-	-	-	-
K1_4	LOAD_P	-	-	-	-	-	-
R34_1	AIN2	-	-	-	-	-	-
R34_2	Net-(R34-Pad2)	-	-	-	-	-	-
R31_1	Net-(U9-+)	-	-	-	-	-	-
R31_2	GNDS	●	●	-	-	-	-
C25_1	PGND	-	●	-	-	-	-
C25_2	GNDS	-	●	-	-	-	-
R32_1	VUSB	-	●	-	-	-	-
R32_2	Net-(D14-A)	-	-	-	-	-	-
R24_1	SENSE_N	-	-	-	-	-	-
R24_2	SNT_N	-	-	-	-	-	-
C11_1	V3.3-F	-	●	-	-	-	-
C11_2	GNDS	-	●	-	-	-	-
C4_1	VUSB	-	●	-	-	-	-
C4_2	GND	-	●	-	-	-	-
C8_1	GND	-	●	-	-	-	-
C8_2	GNDS	-	●	-	-	-	-
C10_1	V5-F	-	●	-	-	-	-
C10_2	GNDS	-	●	-	-	-	-
C7_1	VUSB	-	●	-	-	-	-
C7_2	V5-F	-	●	-	-	-	-
U4_1	GNDS	-	●	-	-	-	-
U4_2	V3.3-F	●	●	-	-	-	-
U4_3	V5-F	-	●	-	-	-	-
PS1_1	GND	-	●	-	-	-	-
PS1_2	VUSB	-	●	-	-	-	-
PS1_3	GNDS	-	●	-	-	-	-
PS1_4	V5-F	-	●	-	-	-	-
C9_1	V5-F	-	●	-	-	-	-
C9_2	GNDS	-	●	-	-	-	-
U3_1	GND	-	●	-	-	-	-
U3_2	V3.3	●	●	-	-	-	-
U3_3	VUSB	-	●	-	-	-	-
C5_1	V3.3	-	●	-	-	-	-
C5_2	GND	-	●	-	-	-	-
C6_1	VUSB	-	●	-	-	-	-
C6_2	GND	-	●	-	-	-	-
R12_1	SDA1	-	-	-	-	-	-
R12_2	V3.3	●	●	-	-	-	-
R15_1	TRG1	-	-	-	-	-	-
R15_2	Net-(D6-K)	-	-	-	-	-	-
D3_1	GND	-	●	-	-	-	-
D3_2	Net-(D3-A)	-	-	-	-	-	-
C12_1	V3.3	-	●	-	-	-	-
C12_2	GND	-	●	-	-	-	-
D6_1	Net-(D6-K)	-	-	-	-	-	-
D6_2	GND	-	●	-	-	-	-
D8_1	Net-(D8-K)	●	◐	-	-	-	-
D8_2	GND	-	●	-	-	-	-
U5_1	GND	●	●	-	-	-	-
U5_2	V3.3	●	●	-	-	-	-
U5_3	EN	-	-	-	-	-	-
U5_4	TRG1	-	-	-	-	-	-
U5_5	TRG2	-	-	-	-	-	-
U5_6	SDA1	-	-	-	-	-	-
U5_7	SCL1	-	-	-	-	-	-
U5_8	XTAL_32K_P	-	-	-	-	-	-
U5_9	XTAL_32K_N	-	-	-	-	-	-
U5_10	ST_USB	-	-	-	-	-	-
U5_11	ST_WLAN	-	-	-	-	-	-
U5_12		-	-	-	-	-	-
U5_13	DG-	-	-	-	-	-	-
U5_14	DG+	-	-	-	-	-	-
U5_15		-	-	-	-	-	-
U5_16		-	-	-	-	-	-
U5_17		-	-	-	-	-	-
U5_18		-	-	-	-	-	-
U5_19	DI_MOSI	-	-	-	-	-	-
U5_20	CLK	-	-	-	-	-	-
U5_21	DO_MISO	-	-	-	-	-	-
U5_22	CS	-	-	-	-	-	-
U5_23		-	-	-	-	-	-
U5_24		-	-	-	-	-	-
U5_25		-	-	-	-	-	-
U5_26		-	-	-	-	-	-
U5_27	IO0	-	-	-	-	-	-
U5_28		-	-	-	-	-	-
U5_29		-	-	-	-	-	-
U5_30		-	-	-	-	-	-
U5_31	R_CTR	-	-	-	-	-	-
U5_32	MTCK	-	-	-	-	-	-
U5_33	MTDO	-	-	-	-	-	-
U5_34	MTDI	-	-	-	-	-	-
U5_35	MTMS	-	-	-	-	-	-
U5_36	RX	-	-	-	-	-	-
U5_37	TX	-	-	-	-	-	-
U5_38	SCL	-	-	-	-	-	-
U5_39	SDA	-	-	-	-	-	-
U5_40	GND	●	●	-	-	-	-
U5_41	GND	●	●	-	-	-	-
R11_1	TRG2	-	-	-	-	-	-
R11_2	V3.3	●	●	-	-	-	-
R17_1	SDA1	-	-	-	-	-	-
R17_2	Net-(D8-K)	●	◐	-	-	-	-
R21_1	Net-(J3-Pin_1)	-	-	-	-	-	-
R21_2	TX	-	-	-	-	-	-
C14_1	XTAL_32K_P	-	-	-	-	-	-
C14_2	GND	●	●	-	-	-	-
Y1_1	XTAL_32K_P	-	-	-	-	-	-
Y1_2	XTAL_32K_N	-	-	-	-	-	-
D5_1	Net-(D5-K)	-	-	-	-	-	-
D5_2	GND	-	●	-	-	-	-
R10_1	TRG1	-	-	-	-	-	-
R10_2	V3.3	●	●	-	-	-	-
R8_1	ST_USB	-	-	-	-	-	-
R8_2	Net-(D3-A)	-	-	-	-	-	-
R14_1	TRG2	-	-	-	-	-	-
R14_2	Net-(D5-K)	-	-	-	-	-	-
C17_1	IO0	-	-	-	-	-	-
C17_2	GND	●	●	-	-	-	-
C16_1	EN	-	-	-	-	-	-
C16_2	GND	●	●	-	-	-	-
U6_1	CS	-	-	-	-	-	-
U6_2	DO_MISO	-	-	-	-	-	-
U6_3	Net-(U6-WP/IO₂₎	-	-	-	-	-	-
U6_4	GND	-	●	-	-	-	-
U6_5	DI_MOSI	-	-	-	-	-	-
U6_6	CLK	-	-	-	-	-	-
U6_7	Net-(U6-HOLD/RESET/IO₃₎	-	-	-	-	-	-
U6_8	V3.3	●	●	-	-	-	-
R20_1	V3.3	●	●	-	-	-	-
R20_2	Net-(U6-WP/IO₂₎	-	-	-	-	-	-
C18_1	XTAL_32K_N	-	-	-	-	-	-
C18_2	GND	●	●	-	-	-	-
SW1_1	EN	-	-	-	-	-	-
SW1_2	GND	-	●	-	-	-	-
R18_1	V3.3	●	●	-	-	-	-
R18_2	EN	-	-	-	-	-	-
J3_1	Net-(J3-Pin_1)	-	-	-	-	-	-
J3_2	Net-(J3-Pin_2)	-	-	-	-	-	-
J3_3	GND	-	●	-	-	-	-
C15_1	EN	-	-	-	-	-	-
C15_2	GND	●	●	-	-	-	-
R22_1	Net-(J3-Pin_2)	-	-	-	-	-	-
R22_2	RX	-	-	-	-	-	-
SW2_1	IO0	-	-	-	-	-	-
SW2_2	GND	-	●	-	-	-	-
C19_1	GND	-	●	-	-	-	-
C19_2	V3.3	-	●	-	-	-	-
D7_1	Net-(D7-K)	●	◐	-	-	-	-
D7_2	GND	-	●	-	-	-	-
C13_1	V3.3	-	●	-	-	-	-
C13_2	GND	-	●	-	-	-	-
J2_1	Net-(D6-K)	-	-	-	-	-	-
J2_2	Net-(D5-K)	-	-	-	-	-	-
J2_3	GND	-	●	-	-	-	-
J2_4	V3.3	-	●	-	-	-	-
J2_5	Net-(D7-K)	●	◐	-	-	-	-
J2_6	Net-(D8-K)	●	◐	-	-	-	-
R7_1	SCL	-	-	-	-	-	-
R7_2	V3.3	●	●	-	-	-	-
R16_1	SCL1	-	-	-	-	-	-
R16_2	Net-(D7-K)	●	◐	-	-	-	-
R19_1	V3.3	●	●	-	-	-	-
R19_2	Net-(U6-HOLD/RESET/IO₃₎	-	-	-	-	-	-
R13_1	SCL1	-	-	-	-	-	-
R13_2	V3.3	●	●	-	-	-	-
R9_1	ST_WLAN	-	-	-	-	-	-
R9_2	Net-(D4-A)	-	-	-	-	-	-
D9_1	V3.3	-	●	-	-	-	-
D9_2	GND	-	●	-	-	-	-
D4_1	GND	-	●	-	-	-	-
D4_2	Net-(D4-A)	-	-	-	-	-	-
R6_1	SDA	-	-	-	-	-	-
R6_2	V3.3	●	●	-	-	-	-

14.11 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.11.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	39.9%	0.9%	0.0%	1.8%	0.0%	23.1%	16.1%	0.0%
Optical Inspection (AOI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
Combined	39.9%	0.9%	0.0%	1.8%	0.0%	23.1%	16.1%	0.0%

14.11.2 PCB Device/Pin Count

Devices (PCOLA): 109
Pins (SOQ): 323

14.11.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	8522 / 100,000	8.5%
SOQ	13055 / 100,000	13.1%
Combined	10788 / 100,000	10.8%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	8522 / 100,000	13055 / 100,000
Optical/X-ray Inspection	0 / 100,000	0 / 100,000
Combined (max)	8522 / 100,000	13055 / 100,000

14.11.4 PCOLA (109 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
40%	C7	330p 1kV / C_1206_3216Metric_Pad1.33x1.80mm_HandSolder *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
20%	U5	ESP32-S3-WROOM-1 / ESP32-S3-WROOM-1 *	IC	◐	○	○	◐	○	LSSI, Powered_Off
10%	C31	10nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C30	10nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C15	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	SW2	SW_Push / SW_SPST_TS-1088-xR025 *	Switch	◐	○	○	○	○	Powered_Off
10%	D7	ESD5Zxx / D_SOD-523 *	Diode	◐	○	○	○	○	Powered_Off
10%	C13	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U11	TSZ122IYDT / SOIC-8_3.9x4.9mm_P1.27mm *	IC	◐	○	○	○	○	Powered_Off
10%	C35	22uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J2	Conn_02x03_Odd_Even / PinHeader_2x03_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	R7	4.7k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R40	20k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C34	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C37	22uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U12	LM2664M6 / SOT-23-6 *	IC	◐	○	○	○	○	Powered_Off
10%	R41	20k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C32	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R42	20k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R16	22R / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R43	20k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C38	22uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C33	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	D2	LED / LED_0805_2012Metric *	Diode	◐	○	○	○	○	Powered_Off
10%	R4	1k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R3	1k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C3	47uF / CP_Elec_5x5.9 *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U2	AP22818AKEWT / SOT-23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	C2	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R2	5.1k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	D1	LED / LED_0805_2012Metric *	Diode	◐	○	○	○	○	Powered_Off
10%	J1	TYPE-C-31-M-12 / HRO_TYPE-C-31-M-12 *	Connector	◐	○	○	—	○	Powered_Off
10%	R5	10k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R1	5.1k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	U1	USBLC6-2SC6 / SOT-23-6 *	IC	◐	○	○	○	○	Powered_Off
10%	C1	1uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	D15	LL4148 / D_MiniMELF *	Diode	◐	○	○	○	○	Powered_Off
10%	U8	ADS1115IDGS / TSSOP-10_3x3mm_P0.5mm *	IC	◐	○	○	○	○	Powered_Off
10%	R26	4.7k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C24	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U9	LM321 / SOT-23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	R13	4.7k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	D13	SMBJ36A / D_SMB *	Diode	◐	○	○	○	○	Powered_Off
10%	R27	4.7k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C26	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C20	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R30	22k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	D4	LED / LED_0805_2012Metric *	Diode	◐	○	○	○	○	Powered_Off
10%	R6	4.7k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R28	10k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C27	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C28	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U7	ISO1540 / SOIC-8_3.9x4.9mm_P1.27mm *	IC	◐	○	○	○	○	Powered_Off
10%	C22	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C23	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U10	INA240A2D / SOIC-8_3.9x4.9mm_P1.27mm *	IC	◐	○	○	○	○	Powered_Off
10%	R29	0R / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	Q1	MMBT2222A / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	K1	HF49FD_005-1H12T / RELAY_HF49FD_005-1H12T *	Other	◐	○	○	○	○	Powered_Off
10%	R31	2k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R32	1k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C11	10uF / C_1206_3216Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C4	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C8	330p 1kV / C_1206_3216Metric_Pad1.33x1.80mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C10	100nF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U4	LD1117S33 / SOT-223-3_TabPin2 *	IC	◐	○	○	○	○	Powered_Off
10%	PS1	RFM-0505S / CONV_RFM-0505S *	Other	◐	○	○	○	○	Powered_Off
10%	C9	47uF / CP_Elec_5x5.9 *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U3	LD1117S33 / SOT-223-3_TabPin2 *	IC	◐	○	○	○	○	Powered_Off
10%	C5	10uF / C_1206_3216Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C6	10uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R12	4.7k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	D3	LED / LED_0805_2012Metric *	Diode	◐	○	○	○	○	Powered_Off
10%	C12	10uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	D6	ESD5Zxx / D_SOD-523 *	Diode	◐	○	○	○	○	Powered_Off
10%	D8	ESD5Zxx / D_SOD-523 *	Diode	◐	○	○	○	○	Powered_Off
10%	R11	10k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R17	22R / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C14	12pF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	D5	ESD5Zxx / D_SOD-523 *	Diode	◐	○	○	○	○	Powered_Off
10%	R10	10k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C16	1uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C18	12pF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	SW1	SW_Push / SW_SPST_TS-1088-xR025 *	Switch	◐	○	○	○	○	Powered_Off
10%	R18	10k / R_0805_2012Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	J3	Conn_01x03 / PinHeader_1x03_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
0%	R37	160k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R45	1k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R38	160k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	C36	10uF / C_0805_2012Metric *	Capacitor	○	○	○	—	○
0%	R36	160k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R39	160k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R44	1k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R35	10R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R33	330R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	C29	220nF / C_0805_2012Metric *	Capacitor	○	○	○	—	○
0%	R21	22R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	D14	LED / LED_0805_2012Metric *	Diode	○	○	○	○	○
0%	R22	22R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	Y1	FC-135_32.7680KA-A0 / XTAL_FC-135_32.7680KA-A0 *	Other	○	○	○	○	○
0%	R24	4.7R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R23	4.7R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R8	1k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R14	22R / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R34	1.5k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	C21	1nF / C_0805_2012Metric *	Capacitor	○	○	○	—	○
0%	R9	1k / R_0805_2012Metric *	Resistor	○	○	○	—	○
0%	R25	10mR / R_2512_6332Metric_Pad1.40x3.35mm_HandSolder *	Resistor	○	○	○	—	○
0%	R15	22R / R_0805_2012Metric *	Resistor	○	○	○	—	○

14.11.5 SOQ (323 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
50%	C27_2	GNDS	◐	●	○
50%	C31_2	PGND	◐	●	○
50%	U2_1	VUSB	◐	●	○
50%	C30_2	PGND	◐	●	○
50%	R26_1	V3.3-F	◐	●	○
50%	U12_2	-3V3	◐	●	○
50%	R30_1	V3.3-F	◐	●	○
50%	R43_1	-3V3	◐	●	○
50%	R27_1	V3.3-F	◐	●	○
50%	R5_2	+5V	◐	●	○
50%	U8_8	V3.3-F	◐	●	○
50%	U8_1	GNDS	◐	●	○
50%	U11_4	GNDS	◐	●	○
50%	U10_2	GNDS	◐	●	○
50%	R41_1	PGND	◐	●	○
50%	U2_5	+5V	◐	●	○
50%	U7_8	V3.3-F	◐	●	○
50%	C33_2	GNDS	◐	●	○
50%	R28_1	V3.3-F	◐	●	○
50%	U8_3	GNDS	◐	●	○
50%	U10_3	GNDS	◐	●	○
50%	R40_1	PGND	◐	●	○
50%	U7_1	V3.3	◐	●	○
50%	R42_1	-3V3	◐	●	○
50%	C34_2	GNDS	◐	●	○
50%	U9_2	GNDS	◐	●	○
50%	U9_5	V3.3-F	◐	●	○
50%	U10_4	GNDS	◐	●	○
50%	R31_2	GNDS	◐	●	○
50%	U4_2	V3.3-F	◐	●	○
50%	U3_2	V3.3	◐	●	○
50%	C16_2	GND	◐	●	○
50%	R12_2	V3.3	◐	●	○
50%	D8_1	Net-(D8-K)	◐	●	○
50%	U5_1	GND	◐	●	○
50%	U5_2	V3.3	◐	●	○
50%	R6_2	V3.3	◐	●	○
50%	U5_40	GND	◐	●	○
50%	U5_41	GND	◐	●	○
50%	R11_2	V3.3	◐	●	○
50%	R17_2	Net-(D8-K)	◐	●	○
50%	C14_2	GND	◐	●	○
50%	R10_2	V3.3	◐	●	○
50%	C18_2	GND	◐	●	○
50%	R18_1	V3.3	◐	●	○
50%	C15_2	GND	◐	●	○
50%	D7_1	Net-(D7-K)	◐	●	○
50%	J2_5	Net-(D7-K)	◐	●	○
50%	J2_6	Net-(D8-K)	◐	●	○
50%	R7_2	V3.3	◐	●	○
50%	R16_2	Net-(D7-K)	◐	●	○
50%	R13_2	V3.3	◐	●	○
17%	PS1_2	VUSB	◐	○	○
17%	C23_1	V3.3-F	◐	○	○
17%	C23_2	GNDS	◐	○	○
17%	U7_4	GND	◐	○	○
17%	C38_1	-3V3	◐	○	○
17%	C38_2	GNDS	◐	○	○
17%	U7_5	GNDS	◐	○	○
17%	D2_2	+5V	◐	○	○
17%	R4_1	Net-(U2-FLG)	◐	○	○
17%	R3_2	GND	◐	○	○
17%	C3_1	VUSB	◐	○	○
17%	C3_2	GND	◐	○	○
17%	U2_2	GND	◐	○	○
17%	U2_3	Net-(U2-FLG)	◐	○	○
17%	C24_1	V3.3-F	◐	○	○
17%	C2_1	VUSB	◐	○	○
17%	C2_2	GND	◐	○	○
17%	C24_2	GNDS	◐	○	○
17%	R2_2	GND	◐	○	○
17%	D1_2	+5V	◐	○	○
17%	J1_A1_B12	GND	◐	○	○
17%	J1_A4_B9	+5V	◐	○	○
17%	U1_5	+5V	◐	○	○
17%	C22_1	V3.3-F	◐	○	○
17%	D13_2	PGND	◐	○	○
17%	J1_B1_A12	GND	◐	○	○
17%	J1_B4_A9	+5V	◐	○	○
17%	C22_2	GNDS	◐	○	○
17%	J1_S1	GND	◐	○	○
17%	U10_6	V3.3-F	◐	○	○
17%	R29_1	PGND	◐	○	○
17%	R29_2	GNDS	◐	○	○
17%	Q1_2	GND	◐	○	○
17%	K1_1	VUSB	◐	○	○
17%	J1_S2	GND	◐	○	○
17%	R32_1	VUSB	◐	○	○
17%	C11_1	V3.3-F	◐	○	○
17%	C11_2	GNDS	◐	○	○
17%	C4_1	VUSB	◐	○	○
17%	C4_2	GND	◐	○	○
17%	C8_1	GND	◐	○	○
17%	C8_2	GNDS	◐	○	○
17%	C10_1	V5-F	◐	○	○
17%	C10_2	GNDS	◐	○	○
17%	C7_1	VUSB	◐	○	○
17%	C7_2	V5-F	◐	○	○
17%	U4_1	GNDS	◐	○	○
17%	J1_S3	GND	◐	○	○
17%	U4_3	V5-F	◐	○	○
17%	PS1_1	GND	◐	○	○
17%	PS1_3	GNDS	◐	○	○
17%	PS1_4	V5-F	◐	○	○
17%	C9_1	V5-F	◐	○	○
17%	C9_2	GNDS	◐	○	○
17%	U3_1	GND	◐	○	○
17%	J1_S4	GND	◐	○	○
17%	U3_3	VUSB	◐	○	○
17%	C5_1	V3.3	◐	○	○
17%	C5_2	GND	◐	○	○
17%	C6_1	VUSB	◐	○	○
17%	C28_1	V3.3-F	◐	○	○
17%	R1_2	GND	◐	○	○
17%	D3_1	GND	◐	○	○
17%	C12_1	V3.3	◐	○	○
17%	C12_2	GND	◐	○	○
17%	D6_2	GND	◐	○	○
17%	C26_1	V3.3-F	◐	○	○
17%	D8_2	GND	◐	○	○
17%	U1_2	GND	◐	○	○
17%	C26_2	GNDS	◐	○	○
17%	C35_1	V3.3-F	◐	○	○
17%	C35_2	GNDS	◐	○	○
17%	C20_1	V3.3	◐	○	○
17%	C20_2	GND	◐	○	○
17%	C1_1	+5V	◐	○	○
17%	C1_2	GND	◐	○	○
17%	D5_2	GND	◐	○	○
17%	D15_1	VUSB	◐	○	○
17%	C6_2	GND	◐	○	○
17%	C37_1	-3V3	◐	○	○
17%	SW1_2	GND	◐	○	○
17%	C37_2	GNDS	◐	○	○
17%	J3_3	GND	◐	○	○
17%	U12_1	GNDS	◐	○	○
17%	SW2_2	GND	◐	○	○
17%	U12_4	V3.3-F	◐	○	○
17%	D7_2	GND	◐	○	○
17%	C13_1	V3.3	◐	○	○
17%	C13_2	GND	◐	○	○
17%	J2_3	GND	◐	○	○
17%	J2_4	V3.3	◐	○	○
17%	U12_5	V3.3-F	◐	○	○
17%	U11_8	V3.3-F	◐	○	○
17%	C28_2	GNDS	◐	○	○
17%	C32_1	V3.3-F	◐	○	○
17%	C32_2	GNDS	◐	○	○
17%	D4_1	GND	◐	○	○
0%	C29_2	SNT_N	○	○	○
0%	C21_1	SENSE_P	○	○	○
0%	C21_2	SENSE_N	○	○	○
0%	R23_1	SENSE_P	○	○	○
0%	R23_2	PSU_P	○	○	○
0%	R28_2	Net-(U8-ALERT/RDY)	○	○	○
0%	C27_1	AIN2	○	○	○
0%	U7_2	SDA	○	○	○
0%	U7_3	SCL	○	○	○
0%	U7_6	SCLS	○	○	○
0%	U7_7	SDAS	○	○	○
0%	U10_1	SENSE_N	○	○	○
0%	U11_6	Net-(U11B--)	○	○	○
0%	U10_5	Net-(R34-Pad2)	○	○	○
0%	C31_1	Net-(U11A-+)	○	○	○
0%	U10_7	Net-(U10-REF1)	○	○	○
0%	U10_8	SENSE_P	○	○	○
0%	C30_1	Net-(U11B-+)	○	○	○
0%	R37_1	PSU_P	○	○	○
0%	D14_1	Net-(D14-K)	○	○	○
0%	D14_2	Net-(D14-A)	○	○	○
0%	Q1_1	Net-(Q1-B)	○	○	○
0%	R37_2	Net-(R37-Pad2)	○	○	○
0%	Q1_3	Net-(D14-K)	○	○	○
0%	R25_1	SNT_N	○	○	○
0%	R25_2	PSU_P	○	○	○
0%	R45_1	AIN1	○	○	○
0%	K1_2	Net-(D14-K)	○	○	○
0%	K1_3	SNT_N	○	○	○
0%	K1_4	LOAD_P	○	○	○
0%	R34_1	AIN2	○	○	○
0%	R34_2	Net-(R34-Pad2)	○	○	○
0%	R31_1	Net-(U9-+)	○	○	○
0%	R45_2	Net-(U11B--)	○	○	○
0%	R38_1	Net-(R36-Pad2)	○	○	○
0%	R32_2	Net-(D14-A)	○	○	○
0%	R24_1	SENSE_N	○	○	○
0%	R24_2	SNT_N	○	○	○
0%	R38_2	Net-(U11B-+)	○	○	○
0%	C36_1	Net-(U12-CAP+)	○	○	○
0%	C36_2	Net-(U12-CAP-)	○	○	○
0%	U11_1	Net-(U11A--)	○	○	○
0%	U11_2	Net-(U11A--)	○	○	○
0%	U11_3	Net-(U11A-+)	○	○	○
0%	R36_1	LOAD_P	○	○	○
0%	R36_2	Net-(R36-Pad2)	○	○	○
0%	R39_1	Net-(R37-Pad2)	○	○	○
0%	R39_2	Net-(U11A-+)	○	○	○
0%	R40_2	Net-(U11B-+)	○	○	○
0%	C34_1	AIN1	○	○	○
0%	U12_3	Net-(U12-CAP-)	○	○	○
0%	U12_6	Net-(U12-CAP+)	○	○	○
0%	R35_2	Net-(C29-Pad1)	○	○	○
0%	R41_2	Net-(U11A-+)	○	○	○
0%	U11_5	Net-(U11B-+)	○	○	○
0%	U11_7	Net-(U11B--)	○	○	○
0%	R42_2	Net-(U11A--)	○	○	○
0%	R44_1	AIN0	○	○	○
0%	R44_2	Net-(U11A--)	○	○	○
0%	R43_2	Net-(U11B--)	○	○	○
0%	C33_1	AIN0	○	○	○
0%	D2_1	Net-(D2-K)	○	○	○
0%	R4_2	Net-(D2-K)	○	○	○
0%	R3_1	Net-(D1-K)	○	○	○
0%	R12_1	SDA1	○	○	○
0%	U2_4	Net-(U2-EN)	○	○	○
0%	R15_1	TRG1	○	○	○
0%	R15_2	Net-(D6-K)	○	○	○
0%	R2_1	Net-(J1-CC2)	○	○	○
0%	D3_2	Net-(D3-A)	○	○	○
0%	D1_1	Net-(D1-K)	○	○	○
0%	J1_A5	Net-(J1-CC1)	○	○	○
0%	D6_1	Net-(D6-K)	○	○	○
0%	J1_A6	D+	○	○	○
0%	J1_A7	D-	○	○	○
0%	J1_A8		○	○	○
0%	J1_B5	Net-(J1-CC2)	○	○	○
0%	J1_B6	D+	○	○	○
0%	U5_3	EN	○	○	○
0%	U5_4	TRG1	○	○	○
0%	U5_5	TRG2	○	○	○
0%	U5_6	SDA1	○	○	○
0%	U5_7	SCL1	○	○	○
0%	U5_8	XTAL_32K_P	○	○	○
0%	U5_9	XTAL_32K_N	○	○	○
0%	U5_10	ST_USB	○	○	○
0%	U5_11	ST_WLAN	○	○	○
0%	U5_12		○	○	○
0%	U5_13	DG-	○	○	○
0%	U5_14	DG+	○	○	○
0%	U5_15		○	○	○
0%	U5_16		○	○	○
0%	U5_17		○	○	○
0%	J1_B7	D-	○	○	○
0%	U5_19	DI_MOSI	○	○	○
0%	U5_20	CLK	○	○	○
0%	U5_21	DO_MISO	○	○	○
0%	U5_22	CS	○	○	○
0%	U5_23		○	○	○
0%	U5_24		○	○	○
0%	U5_25		○	○	○
0%	U5_26		○	○	○
0%	U5_27	IO0	○	○	○
0%	U5_28		○	○	○
0%	U5_29		○	○	○
0%	U5_30		○	○	○
0%	U5_31	R_CTR	○	○	○
0%	U5_32	MTCK	○	○	○
0%	U5_33	MTDO	○	○	○
0%	U5_34	MTDI	○	○	○
0%	U5_35	MTMS	○	○	○
0%	U5_36	RX	○	○	○
0%	U5_37	TX	○	○	○
0%	U5_38	SCL	○	○	○
0%	U5_39	SDA	○	○	○
0%	J1_B8		○	○	○
0%	R5_1	Net-(U2-EN)	○	○	○
0%	R11_1	TRG2	○	○	○
0%	R1_1	Net-(J1-CC1)	○	○	○
0%	R17_1	SDA1	○	○	○
0%	U1_1	D-	○	○	○
0%	R21_1	Net-(J3-Pin_1)	○	○	○
0%	R21_2	TX	○	○	○
0%	C14_1	XTAL_32K_P	○	○	○
0%	U1_3	D+	○	○	○
0%	Y1_1	XTAL_32K_P	○	○	○
0%	Y1_2	XTAL_32K_N	○	○	○
0%	D5_1	Net-(D5-K)	○	○	○
0%	U1_4	DG+	○	○	○
0%	R10_1	TRG1	○	○	○
0%	U1_6	DG-	○	○	○
0%	R8_1	ST_USB	○	○	○
0%	R8_2	Net-(D3-A)	○	○	○
0%	U5_18		○	○	○
0%	R14_2	Net-(D5-K)	○	○	○
0%	C16_1	EN	○	○	○
0%	D15_2	Net-(D14-K)	○	○	○
0%	C18_1	XTAL_32K_N	○	○	○
0%	U8_2	Net-(U8-ALERT/RDY)	○	○	○
0%	SW1_1	EN	○	○	○
0%	U8_4	AIN0	○	○	○
0%	U8_5	AIN1	○	○	○
0%	R18_2	EN	○	○	○
0%	J3_1	Net-(J3-Pin_1)	○	○	○
0%	J3_2	Net-(J3-Pin_2)	○	○	○
0%	U8_6	AIN2	○	○	○
0%	C15_1	EN	○	○	○
0%	U8_7		○	○	○
0%	R22_1	Net-(J3-Pin_2)	○	○	○
0%	R22_2	RX	○	○	○
0%	SW2_1	IO0	○	○	○
0%	U8_9	SDAS	○	○	○
0%	U8_10	SCLS	○	○	○
0%	R26_2	SDAS	○	○	○
0%	U9_1	Net-(U9-+)	○	○	○
0%	U9_3	Net-(U10-REF1)	○	○	○
0%	J2_1	Net-(D6-K)	○	○	○
0%	J2_2	Net-(D5-K)	○	○	○
0%	U9_4	Net-(U10-REF1)	○	○	○
0%	R35_1	LOAD_P	○	○	○
0%	D13_1	PSU_P	○	○	○
0%	R27_2	SCLS	○	○	○
0%	R7_1	SCL	○	○	○
0%	R30_2	Net-(U9-+)	○	○	○
0%	R16_1	SCL1	○	○	○
0%	R33_1	R_CTR	○	○	○
0%	R13_1	SCL1	○	○	○
0%	R33_2	Net-(Q1-B)	○	○	○
0%	R9_1	ST_WLAN	○	○	○
0%	R9_2	Net-(D4-A)	○	○	○
0%	C29_1	Net-(C29-Pad1)	○	○	○
0%	D4_2	Net-(D4-A)	○	○	○
0%	R6_1	SDA	○	○	○
0%	R14_1	TRG2	○	○	○

14.11.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Component Properties

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Model Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U1	F	6	0	0	0	0	0	0	0	6	USBLC6-2SC6
U12	F	6	1	1	0	0	0	0	0	4	LM2664M6
U10	C	8	2	2	1	0	0	0	0	3	INA240A2D
U5	B	41	2	1	0	36	0	0	0	2	ESP32-S3-WROOM-1
U11	A	8	2	4	2	0	0	0	0	0	TSZ122IYDT
U2	A	5	3	1	0	0	1	0	0	0	AP22818AKEWT
U3	A	3	3	0	0	0	0	0	0	0	LD1117S33
U4	A	3	3	0	0	0	0	0	0	0	LD1117S33
U6	A	8	2	2	0	4	0	0	0	0	W25Q16JVSS
U7	A	8	4	0	0	4	0	0	0	0	ISO1540
U8	A	10	2	6	1	1	0	0	0	0	ADS1115IDGS
U9	A	5	2	2	1	0	0	0	0	0	LM321

15.1.1 Library Quality Summary

Total ICs evaluated	12
Grade A (excellent)	8 (66.7%)
Grade B (good)	1 (8.3%)
Grade C (fair)	1 (8.3%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	2 (16.7%)
OVERALL LIBRARY QUALITY	B (3.31/4.00)

15.2 Component Library Validation

The shared part-number check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (4 models)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
ESP32-S3-WROOM-1	ESP32-S3-WROOM-1	-	U5	41	P:2 Pwr:2 Bi:36 I:1	Pin 1 (GND) at same location as pin 40 (GND); Pin 1 (GND) at same location as pin 41 (GND); Pin 40 (GND) at same location as pin 41 (GND); Power-named pins not typed as Power - library pin types incomplete [GND=Passive, GND=Passive]
INA240A2D	INA240A2D	-	U10	8	P:3 Pwr:2 I:2 O:1	Pin 2 (GND) at same location as pin 4 (GND); Power-named pins not typed as Power - library pin types incomplete [GND=Passive]
LM2664M6	LM2664M6	-	U12	6	P:4 Pwr:1 I:1	Power-named pins not typed as Power - library pin types incomplete [OUT=Passive, V+=Passive]
USBLC6-2SC6	USBLC6-2SC6	-	U1	6	P:6	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, VBUS=Passive]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Symbol vs Datasheet Pin Table

Each symbol's pin numbers are compared with the pin table of its cached datasheet model. A datasheet pin the symbol lacks is a warning only when the datasheet calls it electrical; a pin the datasheet marks NC or mechanical, or a symbol pin the table does not list, is shown for information. An exposed pad is never counted as a mismatch, whether the symbol names it or numbers it one past the last pin. Where it was numbered, the row suggests giving it a name, because a bare number does not tell a reader what the pin is.

23 parts compared with a datasheet model: 23 agree, 0 differ. 1 parts have no cached datasheet model yet; 2 have a cached file that is not this symbol's model and were not compared.

Every symbol with a cached datasheet model matches its pin table.

15.4 Shielded Connector Model Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.5 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
J1	TYPE-C-31-M-12	16	Footprint	snapeda-footprints:HRO_TYPE-C-31-M-12
J2	-	6	Footprint	Connector_PinHeader_2.54mm:PinHeader_2x03_P2.54mm_Vertical
J3	-	3	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
K1	HF49FD_005-1H12T	4	Footprint	snapeda-footprints:RELAY_HF49FD_005-1H12T
PS1	RFM-0505S	4	Footprint	snapeda-footprints:CONV_RFM-0505S
Q1	MMBT2222A	3	Footprint	Package_TO_SOT_SMD:SOT-23
TP1	-	1	Footprint	TestPoint:TestPoint_Pad_D1.5mm
TP2	-	1	Footprint	TestPoint:TestPoint_Pad_D1.5mm
TP3	-	1	Footprint	TestPoint:TestPoint_Pad_D1.5mm
TP4	V3.3	1	Footprint	TestPoint:TestPoint_Pad_D1.5mm
TP5	V5F	1	Footprint	TestPoint:TestPoint_Pad_D1.5mm
TP6	V3.3F	1	Footprint	TestPoint:TestPoint_Pad_D1.5mm
U1	USBLC6-2SC6	6	Footprint	Package_TO_SOT_SMD:SOT-23-6
U2	AP22818AKEWT	5	Footprint	Package_TO_SOT_SMD:SOT-23-5
U3	LD1117S33	3	Footprint	Package_TO_SOT_SMD:SOT-223-3_TabPin2
U4	LD1117S33	3	Footprint	Package_TO_SOT_SMD:SOT-223-3_TabPin2
U5	ESP32-S3-WROOM-1	41	Footprint	RF_Module:ESP32-S3-WROOM-1
U6	W25Q16JVSS	8	Footprint	Package_SO:SOIC-8_5.3x5.3mm_P1.27mm
U7	ISO1540	8	Footprint	Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
U8	ADS1115IDGS	10	Footprint	Package_SO:TSSOP-10_3x3mm_P0.5mm
U9	LM321	5	Footprint	Package_TO_SOT_SMD:SOT-23-5
U10	INA240A2D	8	Footprint	Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
U11	TSZ122IYDT	6	Footprint	Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
U12	LM2664M6	6	Footprint	Package_TO_SOT_SMD:SOT-23-6

15.6 IC Pin Electrical Properties

Unique IC models	11
Total IC instances	12

IC Library Models
Industry Name	Library Name	RefDes	Notes
ADS1115IDGS	ADS1115IDGS	U8
AP22818AKEWT	AP22818AKEWT	U2
ESP32-S3-WROOM-1	ESP32-S3-WROOM-1	U5
INA240A2D	INA240A2D	U10
ISO1540	ISO1540	U7
LD1117S33	LD1117S33	U3, U4
LM2664M6	LM2664M6	U12
LM321	LM321	U9
TSZ122IYDT	TSZ122IYDT	U11
USBLC6-2SC6	USBLC6-2SC6	U1
W25Q16JVSS	W25Q16JVSS	U6

15.6.1 ADS1115IDGS (ADS1115IDGS)

Pin	Pin Name	Electrical
1	ADDR	Input
2	ALERT/RDY	Output
3	GND	Power In
4	AIN0	Input
5	AIN1	Input
6	AIN2	Input
7	AIN3	Input
8	VDD	Power In
9	SDA	Bidirectional
10	SCL	Input

15.6.2 AP22818AKEWT (AP22818AKEWT)

Pin	Pin Name	Electrical
1	OUT	Power Out
2	GND	Power In
3	FLG	Open Collector
4	EN	Input
5	IN	Power In

15.6.3 ESP32-S3-WROOM-1 (ESP32-S3-WROOM-1)

Pin	Pin Name	Electrical
1	GND	Power In
2	3V3	Power In
3	EN	Input
4	IO4	Bidirectional
5	IO5	Bidirectional
6	IO6	Bidirectional
7	IO7	Bidirectional
8	IO15	Bidirectional
9	IO16	Bidirectional
10	IO17	Bidirectional
11	IO18	Bidirectional
12	IO8	Bidirectional
13	USB_D-	Bidirectional
14	USB_D+	Bidirectional
15	IO3	Bidirectional
16	IO46	Bidirectional
17	IO9	Bidirectional
18	IO10	Bidirectional
19	IO11	Bidirectional
20	IO12	Bidirectional
21	IO13	Bidirectional
22	IO14	Bidirectional
23	IO21	Bidirectional
24	IO47	Bidirectional
25	IO48	Bidirectional
26	IO45	Bidirectional
27	IO0	Bidirectional
28	IO35	Bidirectional
29	IO36	Bidirectional
30	IO37	Bidirectional
31	IO38	Bidirectional
32	IO39	Bidirectional
33	IO40	Bidirectional
34	IO41	Bidirectional
35	IO42	Bidirectional
36	RXD0	Bidirectional
37	TXD0	Bidirectional
38	IO2	Bidirectional
39	IO1	Bidirectional
40	GND	Passive
41	GND	Passive

15.6.4 INA240A2D (INA240A2D)

Pin	Pin Name	Electrical
1	-	Input
2	GND	Power In
3	REF2	Passive
4	GND	Passive
5		Output
6	V+	Power In
7	REF1	Passive
8	+	Input

15.6.5 ISO1540 (ISO1540)

Pin	Pin Name	Electrical
1	VCC1	Power In
2	SDA1	Bidirectional
3	SCL1	Bidirectional
4	GND1	Power In
5	GND2	Power In
6	SCL2	Bidirectional
7	SDA2	Bidirectional
8	VCC2	Power In

15.6.6 LD1117S33 (LD1117S33)

Pin	Pin Name	Electrical
1	GND	Power In
2	VO	Power Out
3	VI	Power In

15.6.7 LM2664M6 (LM2664M6)

Pin	Pin Name	Electrical
1	GND	Power In
2	OUT	Passive
3	CAP-	Passive
4	SD	Input
5	V+	Passive
6	CAP+	Passive

15.6.8 LM321 (LM321)

Pin	Pin Name	Electrical
1	+	Input
2	V-	Power In
3	-	Input
4		Output
5	V+	Power In

15.6.9 TSZ122IYDT (TSZ122IYDT)

Pin	Pin Name	Electrical
1		Output
2	-	Input
3	+	Input
4	V-	Power In
5	+	Input
6	-	Input
7		Output
8	V+	Power In

15.6.10 USBLC6-2SC6 (USBLC6-2SC6)

Pin	Pin Name	Electrical
1	I/O1	Passive
2	GND	Passive
3	I/O2	Passive
4	I/O2	Passive
5	VBUS	Passive
6	I/O1	Passive

15.6.11 W25Q16JVSS (W25Q16JVSS)

Pin	Pin Name	Electrical
1	CS	Input
2	DO/IO₁	Bidirectional
3	WP/IO₂	Bidirectional
4	GND	Power In
5	DI/IO₀	Bidirectional
6	CLK	Input
7	HOLD/RESET/IO₃	Bidirectional
8	VCC	Power In