cursus Design Analysis

AI-Assisted — This report presents a schematic-phase design review of the Cursus board, a single-sheet design built around an STM32F405RGT6 microcontroller. The board integrates inertial and barometric sensing, flash storage, LoRa telemetry, USB-C connectivity, pyrotechnic firing channels, servo outputs, and regulated power distribution. The design contains 139 components across 100 nets.


SYSTEM ARCHITECTURE

The Cursus board is a compact avionics flight computer intended for rocketry or similar applications. The STM32F405RGT6 (U1) serves as the central processor, communicating with peripheral sensors and radios over two SPI buses and one I2C bus. Six pyrotechnic firing channels and four servo outputs provide actuation capability. A LoRa radio module enables long-range telemetry, and a USB-C port provides a data and power interface. The design is implemented on a single schematic sheet.


POWER ARCHITECTURE

The board employs a two-stage power conversion topology fed from two independent input sources.

Input Power Sources

The USB-C connector J1 provides VBUS power. A separate battery input rail, VBAT+, connects through P-channel MOSFET Q4 (AO3401A) to the pyrotechnic supply rail VBAT+_PYRO and also feeds the main power conversion path. Both VBUS and VBAT+ are OR-ed through Schottky diodes D11 and D12 (SS14, 40 V, 1 A) onto the intermediate node Net-(D11-K), which serves as the combined input rail for the step-down converter. Three 10 µF ceramic capacitors (C15, C16, C17) decouple this node to ground.

The enable pin of U17 is controlled through R11 (10 kΩ) from the Net-(D11-K) node, providing input-voltage-dependent startup behavior.

Step-Down Converter — TPS563200 (U17), 5 V Rail

U17 is a TPS563200 synchronous buck converter generating the +5V rail. The input supply on VIN (pin 3) connects to the diode-OR output node Net-(D11-K). The switch node (pin 2) connects through a 3.3 µH inductor L2 to the +5V output rail. A 0.1 µF ceramic bootstrap capacitor C18 is placed between VBST (pin 6) and SW (pin 2), matching the TPS56x200 datasheet requirement (SLVSCB0 Rev E).

The output voltage is set by a resistor divider from +5V to the VFB pin (pin 4): R12 (54.9 kΩ, top) and R13 (10 kΩ, bottom). Using the internal reference voltage of 0.765 V specified in the TPS56x200 datasheet, the calculated output voltage is VOUT = 0.765 × (1 + 54.9k / 10k) = 4.96 V. This is within acceptable tolerance of the 5 V target.

Output capacitance on the +5V rail consists of three 22 µF ceramic capacitors (C19, C20, C21) and one 10 µF tantalum capacitor (C53), providing substantial bulk capacitance suitable for the D-CAP2 control topology.

The TPS563200 operates over a 4.5 V to 17 V input range. The diode-OR node voltage will be approximately one Schottky diode drop below the lower of VBUS (nominally 5 V) or VBAT+. When powered solely from USB VBUS at 5 V, the input to U17 will be approximately 4.6–4.7 V after the SS14 forward drop, which is near the minimum operating voltage of 4.5 V. Under load transients or with USB cable voltage drop, the input could dip below the UVLO threshold. The battery voltage on VBAT+ must be considered as the primary operating supply for reliable 5 V regulation.

LDO — AMS1117-3.3 (U19), 3.3 V Rail

U19 is an AMS1117-3.3 linear regulator converting the +5V rail to +3.3V. The input (pin 3, VI) connects to +5V, and the output (pin 2, VO) provides the +3.3V rail. The dropout voltage is typically 1.1 V at 0.8 A per the AMS1117 datasheet (ds1117.pdf), so the 5 V to 3.3 V conversion provides approximately 1.7 V of headroom, which is adequate.

The +3.3V rail is the most heavily loaded rail in the design, supplying the STM32F405 MCU, the ICM-42688-P IMU, the BMP388 barometric sensor, the ADXL375 accelerometer, the W25Q128JVSIQ flash memory, the RFM95W LoRa module, the LSF0102 level translator (low side), the 74AHC1G32 OR gate, and the RGB LED D1. The rail is decoupled with a substantial capacitor bank: twelve 0.1 µF ceramics, one 10 nF ceramic, two 10 µF ceramics, one 1 µF ceramic, one 2.2 µF ceramic, and one 22 µF tantalum.

The AMS1117 datasheet requires an output capacitor with ESR not exceeding 0.5 Ω for stability. The 22 µF tantalum C52 on the +3.3V rail satisfies this requirement, as tantalum capacitors in the EIA-3216-18 (Kemet A case) size typically exhibit ESR in the range of 1–3 Ω, which actually exceeds the 0.5 Ω maximum. The large number of parallel ceramic capacitors will reduce the effective ESR well below 0.5 Ω in aggregate, but ceramics alone present very low ESR that can cause instability with the AMS1117. The stability of this LDO with the specific output capacitor mix warrants attention during prototype testing.

Analog Supply — +3.3VA

The +3.3VA rail is derived from +3.3V through ferrite bead FB1 (100 Ω at the rated frequency). This filtered rail supplies the VDDA pin (pin 13) of the STM32F405. It is decoupled with one 0.01 µF ceramic (C7) and one 1 µF ceramic (C8). The STM32F405 hardware development application note AN4488 recommends 1 µF + 10 nF on VDDA, which aligns with the values present (1 µF from C8 and 10 nF approximated by the 0.01 µF of C7, though 10 nF is the standard recommendation rather than 0.01 µF).

Pyrotechnic Supply — VBAT+_PYRO

The VBAT+_PYRO rail is a switched battery rail gated by P-channel MOSFET Q5 (AO3401A). Q5's source connects to VBAT+, and its drain connects to VBAT+_PYRO via J13. The gate of Q5 is controlled through R18 (10 kΩ pull-down to GND), providing a default-off state. This rail powers the collector side of six optocoupler output transistors (U6–U8, U11–U13) and connects to the servo motor power pins (M1–M4) and the pyrotechnic output terminal blocks (J4, J6, J8–J11) through their respective switching circuits.


MICROCONTROLLER — STM32F405RGT6 (U1)

The STM32F405RGT6 is an Arm Cortex-M4 MCU with 1 MB flash and 192 KB SRAM in an LQFP-64 package. It operates from the +3.3V rail on five power pins (VDD pins 64, 19, 32, 48, and VBAT pin 1) and the +3.3VA rail on VDDA (pin 13). Three ground pins (VSS pins 63, 18, and VSSA pin 12) connect to GND.

The two internal voltage regulator capacitors VCAP_1 (pin 31) and VCAP_2 (pin 47) each have a 2.2 µF ceramic capacitor to ground (C51 and C11 respectively), matching the STM32F405 datasheet requirement.

Clock Source

A 16 MHz crystal (ABM8-16Mhz-B2-T1) connects between PH0 (pin 5, HSE_IN) and PH1 (pin 6, HSE_OUT) with 26 pF load capacitors C12 and C13 to ground. The STM32F405 HSE oscillator is designed for 4–26 MHz crystals. The 26 pF load capacitor value is relatively high; typical 16 MHz crystals specify load capacitance in the 8–20 pF range. The actual load capacitance seen by the crystal is approximately (26 pF × 26 pF) / (26 pF + 26 pF) = 13 pF plus PCB stray capacitance. The crystal's specified load capacitance must match this effective value for accurate frequency.

Reset Circuit

The NRST pin (pin 7) has a 10 kΩ pull-up resistor R1 to +3.3V and a 0.1 µF capacitor C10 to ground, forming an RC filter. A tactile switch SW2 connects NRST to ground for manual reset.

Boot Configuration

BOOT0 (pin 60) is connected through R2 (10 kΩ) to a slide switch S1 (JS102011JCQN). The switch common pin (pin 2) connects to R2, pin 1 connects to GND, and pin 3 connects to +3.3V. This allows selection between normal boot (BOOT0 low) and system bootloader mode (BOOT0 high) for firmware programming via USB or UART.

Debug Interface

SWD debug access is provided through connector J2 (1×4 pin header, 2.54 mm pitch). Pin 1 connects to +3.3V, pin 2 carries SWDIO (PA13), pin 3 carries SWCLK (PA14), and pin 4 connects to GND.

Peripheral Pin Assignments

SPI1 bus: PA5 (SCK), PA6 (MISO), PA7 (MOSI) — serves the ICM-42688-P (U10) and ADXL375 (U4). Chip selects are PC5 (ICM_CS) and PC4 (ADXL_CS).

SPI2 bus: PB10 (SCK), PC2 (MISO), PC3 (MOSI) — serves the W25Q128JVSIQ flash (U5) and RFM95W LoRa module (U9). Chip selects are PC15 (FLASH_CS) and PC1 (LORA_CS).

I2C1 bus: PB6 (SCL), PB7 (SDA) — serves the BMP388 barometric sensor (U3). Both lines have 4.7 kΩ pull-ups (R14, R15) to +3.3V.

USB: PA11 (D−), PA12 (D+) — connected to the USB-C connector J1.

UART5: PD2 (RX), PC12 (TX) — routed to connector J12 (JST SH 4-pin).

USART1: PA9 (RX), PA10 (TX) — routed through the LSF0102 level translator U16 to connector J3 (JST SH 4-pin) at 5 V logic levels. Both USART1 lines have 1 kΩ series resistors (R37, R38) with pull-ups to +3.3V on the MCU side.

LoRa control: PA0 (LORA_DIO0), PA1 (LORA_DIO1), PC0 (LORA_RST).

Servo PWM outputs: PC6 (SERVO1/M4), PC7 (SERVO2/M2), PC8 (SERVO3/M3), PC9 (SERVO4/M1).

Pyrotechnic control outputs: PB5 (PYRO1), PB4 (PYRO2), PB3 (PYRO3), PC11 (PYRO4), PC10 (PYRO5), PA15 (PYRO6).

LED outputs: PB15 (LED_RED), PB14 (LED_GRN), PB13 (LED_BLU).

Buzzer: PC13 (BUZZER).

IMU interrupt: PB2 (ICM_INT1).

Intentionally unconnected MCU pins: PB9, PB8, PC14, PA3, PB11, PA2, PA4, PB0, PB12, PB1, PA8. These eleven GPIO pins are marked as designer-intentional no-connects.


INERTIAL MEASUREMENT — ICM-42688-P (U10)

The ICM-42688-P is a 6-axis IMU (accelerometer and gyroscope) from TDK InvenSense, communicating over SPI1. Power pins VDDIO (pin 5) and VDD (pin 8) both connect to +3.3V. The chip select AP_CS (pin 12) is driven by PC5 on the MCU. The SPI data pins AP_SCL/AP_SCLK (pin 13), AP_SDA/AP_SDIO/AP_SDI (pin 14), and AP_SDO/AP_AD0 (pin 1) connect to SPI1_SCK, SPI1_MOSI, and SPI1_MISO respectively.

The INT1/INT output (pin 4) connects to PB2 on the MCU (ICM_INT1). Pins RESV_2 (pin 2), RESV_3 (pin 3), RESV_7 (pin 7), and RESV_10 (pin 10) are reserved pins tied to GND, and INT2/FSYNC/CLKIN (pin 9) and NC (pin 10) are designer no-connects. The ICM-42688-P datasheet (ds-000347 v1.6) specifies that reserved pins should be left unconnected or connected to GND; the connection of RESV_7 and RESV_11 to GND is acceptable.

No dedicated decoupling capacitors are visible on the VDDIO or VDD pins of U10 beyond the shared +3.3V rail capacitors. The ICM-42688-P datasheet recommends 0.1 µF bypass capacitors on both VDD and VDDIO placed close to the device. The shared rail capacitors may be physically distant on the PCB. Dedicated local bypass capacitors for U10 are recommended.


HIGH-G ACCELEROMETER — ADXL375BCCZ (U4)

The ADXL375 is a ±200 g three-axis digital accelerometer from Analog Devices, communicating over SPI1. The VDD_I/O pin (pin 1) connects to +3.3V. The VS (supply) pin (pin 6) is powered through a 33 Ω series resistor R16 from +3.3V, with two 10 µF tantalum capacitors (C27) and 0.1 µF ceramic (C28) decoupling VS to ground. The series resistor and local decoupling form an RC filter on the analog supply, which is good practice for this high-g sensor.

The SPI interface uses SCL/SCLK (pin 14) on SPI1_SCK, SDA/SDI/SDIO (pin 13) on the output of OR gate U2, SDO/ALT_ADDRESS (pin 12) on SPI1_MISO, and chip select *CS (pin 7) on ADXL_CS (PC4).

The OR gate U2 (74AHC1G32) has its output driving the SDA/SDI/SDIO pin of U4. Its two inputs connect to ADXL_CS (PC4) and SPI1_MOSI (PA7). This implements a gating function: when ADXL_CS is high (deselected), the OR gate output is forced high regardless of MOSI state, preventing spurious data from reaching the ADXL375 data input while the SPI bus is communicating with the ICM-42688-P on the same bus. When ADXL_CS is low (selected), the OR gate passes the MOSI signal through to the ADXL375. This is a valid approach for shared-bus SPI designs where the slave device's SDI pin does not have a dedicated chip-select-gated input.

Pins RESERVED (3, 11), NC (10), INT1 (8), and INT2 (9) are designer no-connects. The ADXL375 datasheet (Rev. B) states that INT1 and INT2 are interrupt outputs; leaving both unconnected means the MCU must poll the ADXL375 status registers for data-ready and event detection, which increases bus traffic.


BAROMETRIC SENSOR — BMP388 (U3)

The BMP388 is a high-precision barometric pressure sensor from Bosch Sensortec, communicating over I2C1. VDDIO (pin 1) and VDD (pin 10) connect to +3.3V. Three VSS pins (3, 8, 9) connect to GND. The SDO pin (pin 5) is tied to GND, setting the I2C address to 0x76.

The I2C interface uses SCK (pin 2) for I2C1_SCL and SDI (pin 4) for I2C1_SDA. The CSB pin (pin 6) is tied to +3.3V, selecting I2C mode per the BMP388 datasheet (BST-BMP388-DS001-07).

The INT output (pin 7) is a designer no-connect. Similar to the ADXL375, this means data-ready interrupts are unavailable and the MCU must poll the sensor.

No dedicated decoupling capacitors are placed specifically for U3. The BMP388 shares the +3.3V rail decoupling. The BMP388 datasheet recommends a 100 nF capacitor close to VDD. Layout placement of the shared rail capacitors near U3 is important.


FLASH MEMORY — W25Q128JVSIQ (U5)

The W25Q128JVSIQ is a 128 Mbit (16 MB) SPI NOR flash from Winbond, communicating over SPI2. VCC (pin 8) connects to +3.3V, and GND (pin 4) connects to ground.

The SPI interface uses CLK (pin 6) on SPI2_SCK, DI/IO0 (pin 5) on SPI2_MISO, and DO/IO1 (pin 2) on SPI2_MOSI. The active-low chip select /CS (pin 1) is driven by FLASH_CS (PC15).

The /WP (write protect, pin 3) and /HOLD/RESET (pin 7) pins are each pulled high to +3.3V through 10 kΩ resistors R5 and R6 respectively. This disables write protection and hold functions, allowing normal operation.

Note on SPI signal naming: The net names SPI2_MISO and SPI2_MOSI appear swapped relative to the flash pin functions (DI is the flash data input, DO is the flash data output). The MCU's PC2 (MISO from the MCU's perspective) connects to DI/IO0 (data input to the flash), and PC3 (MOSI from the MCU's perspective) connects to DO/IO1 (data output from the flash). This is electrically incorrect — the MCU's MOSI should connect to the flash's DI, and the MCU's MISO should connect to the flash's DO. The LoRa module U9 is on the same SPI2 bus, and its MOSI (pin 3, data input) connects to SPI2_MOSI (PC3), and its MISO (pin 2, data output) connects to SPI2_MISO (PC2), which is correct for U9. This means the flash U5 has its data input and output lines swapped relative to the LoRa module. This is a wiring error that will prevent communication with the flash memory.


LORA TELEMETRY — RFM95W-868S2 (U9)

The RFM95W-868S2 is an 868 MHz LoRa transceiver module based on the Semtech SX1276, communicating over SPI2. The 3.3V supply pin (pin 13) connects to +3.3V. Three GND pins (1, 8, 10) connect to ground.

The SPI interface uses SCK (pin 4) on SPI2_SCK, MOSI (pin 3) on SPI2_MOSI, MISO (pin 2) on SPI2_MISO, and NSS (pin 5) on LORA_CS (PC1). The RESET pin (pin 6) connects to LORA_RST (PC0). DIO0 (pin 14) and DIO1 (pin 15) connect to LORA_DIO0 (PA0) and LORA_DIO1 (PA1) for interrupt signaling.

The antenna port ANT (pin 9) connects to SMA connector J7 (Samtec SMA-J-P-H-ST-EM1 edge-mount). DIO2 (pin 16), DIO3 (pin 11), DIO4 (pin 12), and DIO5 (pin 7) are designer no-connects.

No dedicated decoupling capacitor is visible for U9 beyond the shared +3.3V rail capacitors. The RFM95W can draw up to 120 mA during transmit; a local bypass capacitor close to pin 13 is recommended.


LEVEL TRANSLATOR — LSF0102DCUR (U16)

The LSF0102 is a dual bidirectional level translator from Texas Instruments. VREF_A (pin 2) connects to +3.3V (low-voltage side), and VREF_B (pin 7) connects to a filtered 5 V reference derived from the +5V rail through R39 (200 kΩ) with a 0.1 µF capacitor C33 to ground. The EN pin (pin 8) is tied to the same VREF_B node, enabling the translator when the 5 V rail is present.

Channel A1 (pin 3) connects to USART1_RX, and channel A2 (pin 4) connects to USART1_TX on the 3.3 V side. Channel B1 (pin 5) and B2 (pin 6) connect to J3 pins 2 and 3 respectively on the 5 V side.

The LSF0102 datasheet specifies that VREF_A must be the lower voltage. With VREF_A at 3.3 V and VREF_B at 5 V, this requirement is satisfied.

The R39 (200 kΩ) resistor feeding VREF_B from +5V through a 0.1 µF capacitor forms a very slow RC filter (τ = 20 ms). The 200 kΩ value is unusually high for a supply reference; the LSF0102 draws minimal supply current (< 1 µA typical), so the voltage drop across R39 is negligible in steady state. However, the high impedance makes VREF_B susceptible to noise coupling. The B-side pull-up resistors for the open-drain outputs on J3 are connected to +5V through R40 and R41 (both 1 kΩ), which do not flow through R39 and therefore do not cause voltage drop on VREF_B.


USB-C CONNECTOR (J1)

J1 is a USB 2.0-only 16-pin Type-C receptacle (GCT USB4110). The CC1 (pin A5) and CC2 (pin B5) pins each have 5.1 kΩ pull-down resistors (R3, R4) to GND, correctly identifying the board as a USB-C sink (UFP) per the USB Type-C specification.

The D+ lines (A6, B6) are connected together on the USB_D+ net to PA12, and the D− lines (A7, B7) are connected together on the USB_D− net to PA11. This is correct for a USB 2.0 device — both orientations of the Type-C plug are supported.

The SBU1 (A8) and SBU2 (B8) pins are designer no-connects, which is appropriate for a USB 2.0-only implementation.

VBUS pins (A4, A9, B4, B9) connect to the VBUS power rail, which feeds through Schottky diode D12 to the power input node.


PYROTECHNIC FIRING CHANNELS

Six pyrotechnic channels (PYRO1 through PYRO6) are implemented using optocouplers for galvanic isolation between the control logic and the pyrotechnic battery supply. Each channel follows an identical topology:

The MCU GPIO drives a series resistor (330 Ω: R19, R22, R25, R28, R31, R34) into the LED anode (pin 1) of a TLP291 optocoupler (U6–U8, U11–U13). The LED cathode (pin 2) connects to GND. On the output side, the phototransistor collector (pin 4) connects to VBAT+_PYRO, and the emitter (pin 3) drives through a current-limiting resistor (100 Ω: R20, R23, R26, R29, R32, R35) to the gate of an N-channel MOSFET (AO3400A: Q2, Q3, Q6–Q9). Each MOSFET gate has a 10 kΩ pull-down resistor to GND (R21, R24, R27, R30, R33, R36) ensuring the default-off state.

The MOSFET drain connects through a 1N4007-equivalent rectifier diode (US1M: D2, D3, D5, D8–D10) to the VBAT+_PYRO rail (diode cathode on VBAT+_PYRO), and also to one pin of a screw terminal (J4, J6, J8–J11). The other screw terminal pin connects to VBAT+_PYRO. The diode provides flyback protection for inductive pyrotechnic loads. The MOSFET source connects to GND.

The TLP291 optocouplers are noted by Toshiba as not recommended for new designs. The TLP291(SE is the current replacement with identical electrical specifications.

With a 330 Ω series resistor and 3.3 V MCU output, the optocoupler LED forward current is approximately (3.3 V − 1.2 V) / 330 Ω ≈ 6.4 mA, which is within the TLP291 operating range. At a minimum CTR of 50%, the phototransistor can conduct approximately 3.2 mA, which through the 100 Ω gate resistor produces approximately 0.32 V at the MOSFET gate — this is below the AO3400A threshold voltage of approximately 1.0–1.5 V. The MOSFET will not turn on reliably.

The issue is that the phototransistor in the TLP291 is a current-output device, and the gate voltage is developed across the 10 kΩ pull-down resistor (R21 etc.), not the 100 Ω series resistor. The phototransistor collector is on VBAT+_PYRO, and the emitter current flows through R20 (100 Ω) to the MOSFET gate node, then through R21 (10 kΩ) to GND. The gate voltage is therefore approximately 3.2 mA × 10 kΩ = 32 V (clamped by the VBAT+_PYRO supply voltage). In practice, the phototransistor will saturate, and the gate voltage will be approximately VBAT+_PYRO minus the phototransistor saturation voltage. This is well above the AO3400A gate threshold, so the circuit will function correctly provided VBAT+_PYRO is above approximately 2 V. However, the AO3400A has a maximum VGS rating of ±20 V. If VBAT+_PYRO exceeds 20 V, the gate-source voltage will exceed the absolute maximum rating and damage the MOSFET. A zener clamp or resistive divider on the gate is needed if the battery voltage can exceed 20 V.


SERVO OUTPUTS

Four servo connectors (M1–M4) use standard 3-pin headers (2.54 mm pitch). The PWM pin (pin 1) connects to MCU timer outputs on PC6–PC9. The power pin (pin 2) connects to VBAT+_PYRO, and the ground pin (pin 3) connects to GND. Standard hobby servos expect 4.8–6.0 V supply; the VBAT+_PYRO rail voltage depends on the battery and may exceed this range. If the battery voltage is higher than 6 V, a separate regulated supply for the servos is needed.


BUZZER CIRCUIT

A magnetic buzzer LS1 (CMI-9705-0580-SMT-TR, 5 Vdc rated) is driven through NPN transistor Q1 (BC817). The buzzer positive terminal connects to +3.3V, and the negative terminal connects to the collector of Q1 through diode D4 (US1M, cathode to +3.3V). Q1's base is driven through R10 (1 kΩ) from the BUZZER net (PC13). The emitter connects to GND.

The buzzer is rated for 5 Vdc but is powered from the 3.3 V rail. This will result in reduced sound output. If full acoustic output is required, the buzzer should be powered from the 5 V rail. The US1M diode D4 provides flyback clamping for the inductive buzzer element.


RGB LED (D1)

An RGB LED D1 (ASMB-KTF0-0A306) has its common anode connected to +3.3V. The red, green, and blue cathodes are driven through individual series resistors: R7 (91 Ω) for red on PB15, R8 (24 Ω) for green on PB14, and R9 (47 Ω) for blue on PB13. The resulting LED currents at 3.3 V (assuming typical forward voltages of approximately 2.0 V red, 3.0 V green, 3.0 V blue) are approximately 14 mA red, 12.5 mA green, and 6.4 mA blue. The green channel resistor of 24 Ω results in relatively high current if the forward voltage is lower than 3.0 V; the STM32F405 GPIO maximum sink current is 25 mA per pin, so this is within limits.


EXTERNAL CONNECTORS AND INTERFACES

Screw Terminal J13: Connects the VBAT+_PYRO switched output through Q5 drain. Pin 1 is GND, pin 2 is the Q5 drain output. This provides an external connection point for the switched pyrotechnic battery rail.

Screw Terminal J5: Connects Q4 drain output. Pin 1 is GND, pin 2 is Q4 drain. Q4 (AO3401A, P-channel) has its source on VBAT+ and gate controlled by R17 (10 kΩ pull-down to GND). With the gate pulled to GND and source at VBAT+, Q4 is normally on (VGS = −VBAT+), connecting VBAT+ to J5 pin 2 and to Q5's source.

SMA Connector J7: Provides the antenna connection for the RFM95W LoRa module. The center pin connects to ANT (U9 pin 9), and the shield connects to GND.

JST SH Connectors J3 and J12: J3 provides the level-translated USART1 interface at 5 V logic levels. J12 provides UART5 at 3.3 V logic levels with +5V power on pin 1 and GND on pin 2.


DESIGN OBSERVATIONS AND RECOMMENDATIONS

SPI2 Flash Wiring Error

The W25Q128JVSIQ flash memory U5 has its DI (data input, pin 5) connected to SPI2_MISO (PC2, MCU data input) and its DO (data output, pin 2) connected to SPI2_MOSI (PC3, MCU data output). This is reversed — the MCU's MOSI should drive the flash's DI, and the flash's DO should drive the MCU's MISO. The LoRa module U9 on the same SPI2 bus is wired correctly. This error will prevent flash memory communication and must be corrected.

Pyrotechnic Channel Gate Voltage

The AO3400A MOSFETs (Q2, Q3, Q6–Q9) have a maximum gate-source voltage rating of ±20 V. The pyrotechnic channel gate drive voltage is approximately equal to VBAT+_PYRO when the optocoupler is active. If the battery voltage exceeds 20 V, gate clamping (e.g., a 12–15 V zener diode from gate to source) is required to protect the MOSFETs.

AMS1117-3.3 Output Capacitor ESR

The AMS1117 requires output capacitor ESR between approximately 0.1 Ω and 0.5 Ω for stable operation. The 22 µF tantalum C52 alone may have ESR above 0.5 Ω depending on the specific part selected, while the parallel ceramic capacitors drive the aggregate ESR very low. A specific tantalum capacitor with characterized ESR in the 0.1–0.5 Ω range should be selected, or a small series resistor can be added to a ceramic-only output to ensure ESR remains within the stable range.

TPS563200 Input Voltage Margin on USB Power

When operating from USB VBUS alone (nominally 5.0 V), the voltage at U17's VIN pin after the SS14 Schottky diode drop is approximately 4.6–4.7 V. The TPS563200 minimum operating input voltage is 4.5 V. This leaves minimal margin for USB cable drops and transient loading. The design appears intended to operate primarily from battery power, with USB providing charging or programming capability rather than full-load operation.

Sensor Decoupling

The ICM-42688-P (U10), BMP388 (U3), and RFM95W (U9) lack visible dedicated bypass capacitors. While the +3.3V rail has extensive bulk decoupling, each of these devices should have a 100 nF ceramic capacitor placed as close as possible to its supply pins during layout. This is a layout-phase action item.

Buzzer Supply Voltage

The CMI-9705-0580-SMT-TR buzzer is rated for 5 Vdc operation but is powered from the 3.3 V rail. Sound pressure level will be reduced. If adequate acoustic output is achieved at 3.3 V during testing, no change is needed; otherwise, the buzzer supply should be reconnected to +5V with appropriate transistor drive modifications.

TLP291 End-of-Life Status

The TLP291 optocoupler used in all six pyrotechnic channels (U6–U8, U11–U13) is marked by Toshiba as not recommended for new designs. The pin-compatible TLP291(SE should be substituted for production longevity.

ADXL375 and BMP388 Interrupt Lines

Both the ADXL375 (U4) and BMP388 (U3) have their interrupt output pins left unconnected by design. This requires the MCU to poll these sensors for data readiness, increasing SPI/I2C bus utilization and potentially increasing latency in time-critical flight applications. Connecting at least one interrupt line from each sensor to available MCU GPIOs would enable event-driven data acquisition.

USB-C Data Line Resistors

The USB 2.0 specification recommends series resistors (typically 22–33 Ω) on the D+ and D− lines for impedance matching and ESD current limiting. No series resistors are present between J1 and the MCU USB pins (PA11, PA12). The STM32F405 has internal series resistance on the USB transceiver, but external resistors are common practice for improved signal integrity and ESD robustness.

P-Channel MOSFET Default States

Q4 (AO3401A) has its gate pulled to GND through R17 (10 kΩ). With the source on VBAT+, this means Q4 is normally on whenever a battery is connected, as VGS = −VBAT+. This connects VBAT+ to J5 and to Q5's source. Q5's gate is similarly pulled to GND through R18 (10 kΩ), making Q5 also normally on. The VBAT+_PYRO rail is therefore energized by default whenever a battery is connected. No MCU GPIO is visible driving R17 or R18 to control these MOSFETs. If the intent is MCU-controlled arming of the pyrotechnic supply, a GPIO connection to the gate drive network is needed. If the intent is always-on battery distribution, the current design is functional but presents a safety consideration for pyrotechnic applications where the firing supply should be armed only when commanded.

AI-Assisted — The Cursus board receives power from two external sources. The first is a USB Type-C receptacle J1, which provides the VBUS rail at a nominal 5 V. The USB-C connector uses 5.1 kΩ pull-down resistors R3 and R4 on the CC1 and CC2 lines respectively, identifying the board as a USB sink device requesting default 5 V power. No USB Power Delivery controller is present, so the maximum available current is limited to the USB default (500 mA from USB 2.0 hosts, or up to 1.5 A / 3 A from USB-C sources advertising higher current via CC resistor detection).

The second external source is the VBAT+ rail, which connects through connector J5 (pin 2 to Q4 source, pin 1 to GND). This appears to be a battery input. A separate VBAT+_PYRO rail is provided externally through multiple screw terminals (J4, J6, J8, J9, J10, J11) and powers the pyrotechnic firing circuits and servo motors.

VBUS and VBAT+ are OR-ed together through Schottky diodes D12 (from VBUS) and D11 (from VBAT+) into the intermediate net Net-(D11-K). This OR-ed node feeds the TPS563200 buck converter U17. The Schottky diodes (SS14, 40 V, 1 A) provide reverse-current blocking and allow either source to supply the system. Three 10 µF ceramic capacitors C15, C16, and C17 decouple this intermediate node to ground.

From Net-(D11-K), the power chain proceeds as follows: U17 (TPS563200) steps down to +5V, which then feeds U19 (AMS1117-3.3) to produce the +3.3V rail. The +3.3VA analog supply is derived from +3.3V through a 100 Ω ferrite bead FB1, providing additional high-frequency noise filtering for the STM32F405 VDDA pin. The VBAT+_PYRO rail is independent and externally supplied, powering the optocoupler collector sides and servo motor positive terminals directly.

AI-Assisted — U17 is a Texas Instruments TPS563200, a 3 A synchronous step-down regulator in a SOT-23-6 package. Per the TPS56x200 datasheet (SLVSCB0 Rev E), the device operates with D-CAP2 mode control and requires no external compensation network. The operating input voltage range is 4.5 V to 17 V.

The VIN pin (pin 3) connects to Net-(D11-K), the OR-ed output of D11 and D12. With a nominal VBUS of 5 V and an SS14 Schottky forward drop of approximately 0.3–0.5 V, the voltage at VIN will be approximately 4.5–4.7 V when powered from USB alone. This is at the very edge of the TPS563200 minimum operating input voltage of 4.5 V. Under load transients or with USB cable voltage drop, VIN could dip below 4.5 V, potentially causing the regulator to drop out of regulation. When powered from a battery at VBAT+ (typical lithium cell at 3.0–4.2 V), the voltage after D11 will be approximately 2.7–3.9 V, which is well below the 4.5 V minimum. The buck converter cannot regulate from a single lithium cell. The design appears to require either USB power or a battery voltage above approximately 5 V for proper operation of U17.

The enable pin (pin 5) is connected through R11 (10 kΩ) from Net-(D11-K). There is no resistor divider to set a UVLO threshold — R11 simply pulls EN high whenever input voltage is present. The TPS563200 datasheet states EN is active-high and can use a resistor divider from VIN to set a programmable UVLO. Without a lower resistor to ground forming a divider, the regulator will attempt to start as soon as any voltage appears on VIN, even if it is below the minimum operating voltage. Adding a resistor divider on EN to set a UVLO threshold at approximately 4.5 V would prevent the regulator from attempting to start at insufficient input voltages.

The output voltage is set by the feedback divider from +5V through R12 (54.9 kΩ) to the VFB pin (pin 4) and R13 (10 kΩ) from VFB to GND. The pre-calculated divider ratio is 0.154. Using the verified VFB reference voltage of 0.765 V from the TPS56x200 datasheet, the calculated output voltage is VOUT = 0.765 V / 0.154 = 4.968 V, which rounds to approximately 5.0 V. This is within the acceptable range for a nominal 5 V output.

The bootstrap capacitor C18 (0.1 µF ceramic) connects between the VBST pin (pin 6) and the SW pin (pin 2). The TPS563200 datasheet specifies a 0.1 µF capacitor for this function, so this value is correct.

The output inductor L2 is 3.3 µH in an 0805 footprint, connecting from the SW node to the +5V rail. The TPS563200 datasheet application section recommends inductor selection based on the ripple current ratio (typically 20–40% of maximum load current). At 650 kHz switching frequency, 5 V input, and 5 V output, the duty cycle approaches 100%, which means the converter is operating near its maximum duty cycle limit. The inductor ripple current depends on (VIN − VOUT) / (L × f) × D, which will be very small when VIN ≈ VOUT. However, the 0805 footprint for a 3.3 µH inductor raises a concern about saturation current rating. At 3 A maximum output current, the inductor must have a saturation current rating of at least 3.6 A (1.2× margin). Many 0805 inductors are rated for only 1–2 A. The specific inductor part number is not specified in the schematic, so the saturation current and DCR ratings cannot be fully assessed, but the footprint size is a risk for a 3 A converter.

Output capacitance on the +5V rail consists of three 22 µF ceramic capacitors (C19, C20, C21) and one 10 µF tantalum capacitor (C53), totaling approximately 76 µF nominal. The TPS563200 uses D-CAP2 control, which requires minimum output capacitance for stability. The datasheet recommends a minimum of 2 × 22 µF ceramic (X5R or X7R, 6.3 V or higher) for a 5 V output. The three 22 µF ceramics exceed this minimum. However, the capacitor voltage ratings are not specified in the schematic. For a 5 V output, capacitors rated at 6.3 V or higher are required; 10 V rated parts are preferred for adequate derating. The tantalum C53 (10 µF) provides additional bulk capacitance.

Input capacitance at Net-(D11-K) consists of three 10 µF ceramic capacitors (C15, C16, C17), totaling 30 µF nominal. The TPS563200 datasheet recommends at least 10 µF of input capacitance, so this is adequate.

AI-Assisted — U19 is an AMS1117-3.3, a fixed 3.3 V output LDO regulator rated for 1 A output current. Per the AMS1117 datasheet (ds1117.pdf, Advanced Monolithic Systems), the device has a typical dropout voltage of 1.1 V at 0.8 A and a maximum of 1.3 V. The input pin VI (pin 3) connects to the +5V rail, giving a nominal headroom of 5.0 V − 3.3 V = 1.7 V, which comfortably exceeds the maximum dropout voltage.

The output pin VO (pin 2) drives the +3.3V rail, which is the primary digital supply for the entire board. This rail powers the STM32F405RGT6 MCU (U1), the ICM-42688-P IMU (U10), the BMP388 barometric sensor (U3), the ADXL375 high-g accelerometer (U4), the W25Q128JVSIQ flash memory (U5), the RFM95W-868S2 LoRa transceiver (U9), the LSF0102DCUR level translator (U16), and the 74AHC1G32 OR gate (U2). The total current draw depends on the operating modes of these devices, but the RFM95W alone can draw up to 120 mA during transmit at +20 dBm, and the STM32F405 can draw up to 100–150 mA at full clock speed with peripherals active. The combined worst-case current could approach or exceed the 1 A rating of the AMS1117-3.3, particularly if multiple peripherals are active simultaneously.

The AMS1117 datasheet specifies that the output capacitor is critical for stability. A minimum of 22 µF tantalum with ESR not exceeding 0.5 Ω is required, or alternatively 50 µF aluminum electrolytic. The +3.3V rail has extensive decoupling: twelve 0.1 µF ceramics, one 10 nF ceramic, two 10 µF ceramics, one 1 µF ceramic, one 2.2 µF ceramic, and one 22 µF tantalum (C52). The 22 µF tantalum C52 satisfies the AMS1117 output stability requirement. However, the large number of low-ESR ceramic capacitors in parallel could reduce the total ESR below the minimum ESR required by the AMS1117 for stability. The AMS1117 datasheet does not specify a minimum ESR explicitly, but the device is designed to be stable with moderate-ESR capacitors (tantalum or aluminum electrolytic). If the tantalum C52 dominates the ESR characteristic at the regulator output, stability should be maintained, but during layout the tantalum should be placed closest to the regulator output pin.

The AMS1117 datasheet recommends a 10 µF input capacitor. The +5V rail already has substantial capacitance (three 22 µF ceramics and one 10 µF tantalum), which is more than adequate for the LDO input.

The +3.3VA rail is derived from +3.3V through ferrite bead FB1 (100 Ω at 100 MHz). This filtered rail supplies only the VDDA pin (pin 13) of the STM32F405. The decoupling on +3.3VA consists of one 0.01 µF ceramic (C7) and one 1 µF ceramic (C8). The STM32F405 datasheet (DS8626) and application note AN4488 recommend 1 µF + 10 nF on VDDA, which matches C8 (1 µF) and C7 (0.01 µF = 10 nF). This is correct.

AI-Assisted — The STM32F405RGT6 (U1) has five VDD pins (pins 1, 19, 32, 48, 64) on the +3.3V rail, one VDDA pin (pin 13) on +3.3VA, and three ground pins (pins 12, 18, 63). Per ST application note AN4488 Rev 7, each VDD pin requires a 100 nF ceramic capacitor placed as close as possible to the pin, plus one 4.7 µF bulk capacitor shared among all VDD pins. The schematic provides twelve 0.1 µF ceramics on the +3.3V rail, which is more than sufficient for the five VDD pins. The two 10 µF ceramics and one 22 µF tantalum provide bulk capacitance.

The VCAP_1 (pin 31) and VCAP_2 (pin 47) pins each require a 2.2 µF ceramic capacitor to ground per the STM32F405 datasheet. VCAP_1 connects to C51 (2.2 µF ceramic) and VCAP_2 connects to C11 (2.2 µF ceramic), both to GND. These values are correct per the datasheet requirement.

The VBAT pin (pin 1) is tied directly to +3.3V. This is acceptable when no backup battery is used — the MCU RTC and backup registers will lose state on power loss, but the connection is electrically valid. A 0.1 µF decoupling capacitor is recommended close to VBAT per AN4488; the shared +3.3V decoupling capacitors serve this purpose.

AI-Assisted — The VBAT+_PYRO rail is supplied externally through screw terminals J4, J6, J8, J9, J10, and J11 (pin 2 of each). This rail powers the collector side of six TLP291 optocouplers (U6, U7, U8, U11, U12, U13) and the positive terminals of four servo motors (M1–M4). The TLP291 optocouplers are rated for 80 V collector-emitter voltage, providing substantial margin for typical pyrotechnic battery voltages. The TLP291 is not recommended for new designs per Toshiba; the TLP291(SE is the current replacement with identical electrical specifications.

The pyrotechnic firing topology uses the MCU GPIO pins (PB3, PB4, PB5, PC10, PC11, PA15) driving through 330 Ω series resistors to the optocoupler LED anodes, with 100 Ω resistors on the phototransistor emitter side. The optocoupler collectors connect to VBAT+_PYRO through flyback diodes (US1M, 1000 V, 1 A general-purpose rectifiers D2, D3, D5, D8, D9, D10), and the emitter outputs drive screw terminal connectors for external pyrotechnic loads. The US1M diodes provide inductive load clamping.

The VBAT+_PYRO rail has no on-board decoupling capacitors. For a rail that may experience high transient currents during pyrotechnic firing, bulk capacitance near the screw terminals would help maintain rail stability and reduce conducted noise coupling to other circuits.

Two P-channel MOSFETs Q4 and Q5 (AO3401A, −30 V, −4 A) appear to serve as high-side switches. Q4 has its source on VBAT+ and drain connected to J5 pin 2. Q5 has its source on VBAT+_PYRO and drain connected to J13 pin 2. Their gates are pulled to GND through R17 and R18 (10 kΩ) respectively, which means both MOSFETs are turned on by default (gate pulled low relative to source turns on a P-FET). The gate drive source for these MOSFETs is not visible in the signal nets — they appear to be permanently enabled by the pull-down resistors.

AI-Assisted — U16 (LSF0102DCUR) is a dual bidirectional level translator from Texas Instruments. Its VREF_A pin (pin 2) connects to +3.3V, and its VREF_B pin (pin 7) connects to Net-(U16-VREF_B). This net is supplied through R39 (200 kΩ) from the +5V rail, with C33 (0.1 µF ceramic) to GND. The EN pin (pin 8) is also tied to this same net.

The LSF0102 datasheet (Rev B) states that VREF_A must be the lower voltage reference. With VREF_A at 3.3 V and VREF_B derived from +5V, this requirement is satisfied. However, the 200 kΩ resistor R39 feeding VREF_B through a 0.1 µF capacitor creates a very high-impedance supply for the B-side reference. The LSF0102 VREF_B pin draws supply current for the B-side level shifting. With a 200 kΩ series resistor, even a few microamperes of supply current will cause significant voltage drop, and the VREF_B voltage will not reach 5 V. The time constant of R39 and C33 is 200 kΩ × 0.1 µF = 20 ms, which also means slow power-up of the B-side reference. This resistor value appears excessively high for a supply pin and may result in the B-side operating at a voltage significantly below 5 V. A lower value resistor or a direct connection to +5V would be more appropriate.

The A-side channels (A1, A2) connect to USART1_RX and USART1_TX respectively, interfacing with the STM32F405 UART. The B-side channels (B1, B2) connect to J3 pins 2 and 3 through resistors R40 and R41 (1 kΩ each to +5V, serving as pull-ups). This provides a level-translated UART interface at the J3 connector.

AI-Assisted — The input OR-ing uses two SS14 Schottky diodes (D11 from VBAT+, D12 from VBUS). The SS14 is rated at 40 V reverse voltage and 1 A average forward current. With the AMS1117-3.3 drawing up to 1 A and the TPS563200 potentially delivering up to 3 A, the total input current through a single diode could exceed the 1 A rating of the SS14 during peak load conditions. The forward voltage drop of the SS14 at 1 A is typically 0.5 V, which combined with USB cable drop could bring the TPS563200 VIN dangerously close to its 4.5 V minimum.

The USB Type-C connector J1 has its SBU1 (pin A8) and SBU2 (pin B8) pins left unconnected, which is correct for a USB 2.0-only implementation. The CC1 and CC2 pins have 5.1 kΩ pull-downs to GND (R3, R4), correctly identifying the board as a USB sink per the USB Type-C specification.

AI-Assisted — Several cross-cutting concerns emerge from the power architecture review.

The power sequencing is implicit: when input voltage appears at Net-(D11-K), U17 enables immediately (R11 pulls EN high with no UVLO divider), produces +5V, which then feeds U19 to produce +3.3V. There is no controlled sequencing or power-good monitoring. The TPS563200 has no PGOOD output pin, and the AMS1117-3.3 has no enable or power-good pin. The system relies on the natural ramp-up sequence, which is acceptable for this class of design but provides no fault indication to the MCU.

The ADXL375 (U4) has its VS supply pin (pin 6) connected through R16 (33 Ω) from +3.3V, with two capacitors C27 (10 µF tantalum) and C28 (0.1 µF ceramic) to GND on the VS side. The ADXL375 datasheet (Rev B, Analog Devices) specifies VS as the power supply pin. The 33 Ω series resistor with the decoupling capacitors forms an RC filter for additional noise rejection on the accelerometer supply, which is good practice for a high-g sensor.

The 0805 inductor footprint for L2 at 3.3 µH in a 3 A converter remains a significant concern. During layout, the inductor selection must prioritize saturation current rating above 3.6 A and low DCR to minimize power loss. An 0805 inductor meeting these requirements may not be readily available; a larger footprint (1210 or 1008) is more typical for this current level.

The design has no test points on any power rail. For a board with pyrotechnic circuits and multiple power domains, test points on +5V, +3.3V, +3.3VA, VBAT+_PYRO, and Net-(D11-K) would significantly aid bring-up and production testing.

AI-Assisted —

Device	Rail	Observation	Severity
U17 (TPS563200)	+5V	When powered from a single lithium cell (3.0–4.2 V) through D11, VIN will be approximately 2.7–3.9 V, well below the 4.5 V minimum. The buck converter cannot regulate from a single lithium cell.	High
L2 (3.3 µH)	+5V	Inductor in 0805 footprint for a 3 A buck converter. Most 0805 inductors at 3.3 µH are rated for 1–2 A saturation current. A saturation current of at least 3.6 A is needed. Footprint may be undersized.	High
U16 (LSF0102DCUR)	Net-(U16-VREF_B)	VREF_B supplied through R39 (200 kΩ) from +5V. This extremely high impedance will cause significant voltage drop from VREF_B supply current, and the B-side reference voltage will be well below 5 V. The RC time constant with C33 (0.1 µF) is 20 ms, causing slow start-up. A much lower resistance or direct connection is recommended.	High
U17 (TPS563200)	+5V	EN pin (pin 5) connected through R11 (10 kΩ) directly from VIN with no lower divider resistor to GND. No UVLO threshold is set. Regulator will attempt to start at any input voltage, including below the 4.5 V minimum operating voltage (TPS56x200 datasheet SLVSCB0 Rev E, Section 7.3).	Medium
U17 (TPS563200)	+5V	When powered from USB (5 V nominal) through SS14 Schottky D12 (approximately 0.3–0.5 V drop), VIN at U17 is approximately 4.5–4.7 V. This is at the minimum operating input voltage of 4.5 V per datasheet. USB cable resistance and connector drop could push VIN below minimum.	Medium
U19 (AMS1117-3.3)	+3.3V	Total load on +3.3V rail includes STM32F405, ICM-42688-P, BMP388, ADXL375, W25Q128JVSIQ, RFM95W (up to 120 mA TX), LSF0102, 74AHC1G32, RGB LED, buzzer driver, and multiple pull-up resistors. Combined worst-case current may approach or exceed the 1 A rating of the AMS1117.	Medium
D11/D12 (SS14)	Net-(D11-K)	SS14 Schottky diodes rated at 1 A average forward current. If total system draw approaches 1–2 A, the active diode may be stressed beyond its rating. Consider upgrading to a higher-current Schottky (e.g., 2–3 A rated).	Medium
U16 (LSF0102DCUR)	Net-(U16-VREF_B)	EN pin (pin 8) tied to VREF_B net. EN threshold per LSF0102 datasheet is referenced to VREF_B. Since VREF_B voltage is uncertain due to the 200 kΩ feed resistor, reliable enable behavior is not guaranteed.	Medium
VBAT+_PYRO	VBAT+_PYRO	No decoupling capacitors on the VBAT+_PYRO rail. Pyrotechnic firing events cause high transient currents that could couple noise into other circuits through shared ground paths.	Medium
U19 (AMS1117-3.3)	+3.3V	Large number of parallel ceramic capacitors on +3.3V rail may reduce total ESR below the range where the AMS1117 is characterized for stability. Tantalum C52 should be placed closest to VO pin during layout to dominate the ESR seen by the regulator.	Low
U6–U8, U11–U13 (TLP291)	VBAT+_PYRO	The TLP291 is not recommended for new designs per Toshiba. The TLP291(SE is the current replacement with identical specifications.	Low
—	All rails	No test points are present on any power rail (+5V, +3.3V, +3.3VA, VBAT+_PYRO, Net-(D11-K)). Test points would aid board bring-up and production testing.	Low
Q4/Q5 (AO3401A)	VBAT+ / VBAT+_PYRO	P-channel MOSFET gates pulled to GND by 10 kΩ resistors (R17, R18). With source on the positive battery rail, VGS is negative and the FETs are permanently on. No MCU control of these switches is visible in the schematic.	Low
U17 (TPS563200)	+5V	Output voltage set by R12 (54.9 kΩ) / R13 (10 kΩ) divider. Using verified VREF of 0.765 V (TPS56x200 datasheet SLVSCB0 Rev E), VOUT = 0.765 / 0.154 = 4.97 V. Within acceptable tolerance for a 5 V rail.	✓
U17 (TPS563200)	+5V	Bootstrap capacitor C18 is 0.1 µF ceramic between VBST and SW. Matches TPS563200 datasheet requirement of 0.1 µF.	✓
U17 (TPS563200)	+5V	Input capacitance at Net-(D11-K): three 10 µF ceramics (C15, C16, C17) totaling 30 µF. Exceeds datasheet minimum of 10 µF.	✓
U17 (TPS563200)	+5V	Output capacitance: three 22 µF ceramics (C19, C20, C21) plus one 10 µF tantalum (C53). Exceeds D-CAP2 minimum requirement of 2 × 22 µF ceramic per datasheet.	✓
U19 (AMS1117-3.3)	+3.3V	Input from +5V rail provides 1.7 V headroom, exceeding maximum dropout of 1.3 V at 0.8 A (AMS1117 datasheet ds1117.pdf).	✓
U19 (AMS1117-3.3)	+3.3V	Output capacitor C52 (22 µF tantalum) satisfies AMS1117 stability requirement of minimum 22 µF tantalum with ESR ≤ 0.5 Ω.	✓
FB1 (100 Ω)	+3.3VA	Ferrite bead filtering +3.3V to +3.3VA for STM32F405 VDDA. Decoupling on +3.3VA is 0.01 µF (C7) and 1 µF (C8), matching AN4488 Rev 7 recommendation of 1 µF + 10 nF for VDDA.	✓
U1 (STM32F405)	VCAP	VCAP_1 has C51 (2.2 µF ceramic) and VCAP_2 has C11 (2.2 µF ceramic) to GND. Matches STM32F405 datasheet DS8626 requirement of 2.2 µF on each VCAP pin.	✓
R3/R4 (5.1 kΩ)	VBUS	CC1 and CC2 pull-downs to GND are 5.1 kΩ each, correctly identifying the board as a USB Type-C sink per USB Type-C Specification Rev 2.0, Table 4-25.	✓

AI-Assisted —

References
AMS1117-3.3 (Advanced Monolithic Systems) — AMS1117 datasheet, Advanced Monolithic Systems, ds1117.pdf www.advanced-monolithic.com/pdf/ds1117.pdf
TPS563200 (Texas Instruments) — TPS56x200 datasheet, SLVSCB0, Rev E, TI.com www.ti.com/lit/ds/symlink/tps562200.pdf

AI-Assisted — U5 is a Winbond W25Q128JVSIQ, a 128 Mbit NOR flash supporting standard, dual, and quad SPI modes at clock frequencies up to 133 MHz. The device operates from the +3.3V rail, which falls within its specified 2.7 V to 3.6 V supply range. A single 100 nF ceramic bypass capacitor is present on VCC (pin 8). The Winbond datasheet recommends a 100 nF decoupling capacitor close to the VCC pin, so this is adequate for the device itself.

The flash chip select (/CS, pin 1) is directly driven by U1 (STM32F405RG) on PC15 via the net FLASH_CS. No external pull-up is present on /CS. The W25Q128JV datasheet states that /CS must be driven high to deselect the device; since the STM32 GPIO can hold the pin high, an external pull-up is not strictly required but would provide a defined state during MCU reset. This is a low-severity observation.

The /WP (IO2, pin 3) line is pulled high to +3.3V through R5 (10 kohm), and the /HOLD/RESET (IO3, pin 7) line is pulled high to +3.3V through R6 (10 kohm). Per the Winbond W25Q128JV datasheet, when the Quad Enable (QE) bit is cleared (factory default for the IQ ordering option), /WP enables write protection and /HOLD enables the hold function. Pulling both high disables write protection and hold, which is correct for normal operation. When QE is set to enable quad mode, these pins become IO2 and IO3 respectively. The 10 kohm pull-ups will need to be overdriven by the STM32 SPI outputs during quad-mode transfers. At 3.3 V with 10 kohm, the pull-up current is 330 uA, which is well within the STM32 GPIO sink capability and will not cause contention issues during quad operation.

The W25Q128JVSIQ SOIC-8 package does not include a dedicated hardware /RESET pin. Reset must be performed via the software reset command sequence (66h followed by 99h). The /HOLD/RESET pin (IO3) can serve as a reset input only when QE=0; once quad mode is enabled, this pin functions as IO3 and the reset function is unavailable through hardware. This is acceptable for most embedded applications but means the flash cannot be hardware-reset independently of the SPI bus once quad mode is active.

AI-Assisted — U5 (W25Q128JVSIQ) and U9 (RFM95W-868S2 LoRa transceiver) share the SPI2 bus driven by U1 (STM32F405RG). The clock line SPI2_SCK connects U1 pin PB10 to U5 pin 6 (CLK) and U9 pin 4 (SCK), which is correct. However, the two data lines are cross-wired between the two slave devices.

On the net SPI2_MOSI, U1 pin PC3 drives U5 pin 2 (DO/IO1, which is the flash data output in standard SPI mode) and U9 pin 3 (MOSI, which is the LoRa module data input). The Winbond W25Q128JV datasheet defines pin 2 as DO — the serial data output in standard SPI mode. The RFM95W datasheet defines pin 3 as MOSI — the serial data input. The STM32 MOSI output is therefore correctly connected to U9 but incorrectly connected to the flash output pin.

On the net SPI2_MISO, U1 pin PC2 connects to U5 pin 5 (DI/IO0, which is the flash data input in standard SPI mode) and U9 pin 2 (MISO, which is the LoRa module data output). The STM32 MISO input is correctly connected to U9 but incorrectly connected to the flash input pin.

In summary, the MOSI and MISO connections to U5 are swapped. The STM32 MOSI line drives the flash DO pin instead of DI, and the STM32 MISO line reads from the flash DI pin instead of DO. This means the controller will attempt to write data into the flash output pin and read data from the flash input pin. The bus cannot function correctly in this configuration — neither standard SPI reads nor writes to the flash will succeed, and in quad mode the IO0/IO1 assignments will likewise be reversed.

This is a wiring error that requires a schematic correction. U5 pin 2 (DO/IO1) must be connected to SPI2_MISO, and U5 pin 5 (DI/IO0) must be connected to SPI2_MOSI. Alternatively, if the board has already been fabricated, two trace cuts and two jumper wires between U5 pins 2 and 5 and the respective SPI2 data nets would be needed. This finding is high severity because the flash memory is completely non-functional as wired.

AI-Assisted — The SPI2 bus has no series termination resistors on any of the data or clock lines between U1, U5, and U9. The STM32F405 SPI2 peripheral can operate at a maximum of fPCLK/2. With a typical 84 MHz APB1 clock, the maximum SPI2 clock is 42 MHz. The W25Q128JV supports up to 133 MHz, and the RFM95W SPI interface operates up to 10 MHz. In practice the bus will likely be clocked at or below 10 MHz to accommodate the LoRa module, at which frequency the absence of series resistors is acceptable for short PCB traces. If the flash is to be operated at higher speeds independently (with U9 deselected), series resistors of 22 to 33 ohm on the clock and data lines close to U1 would improve signal quality, but this is a layout-dependent consideration and is low severity at the schematic phase.

U5 and U9 have independent chip selects: FLASH_CS (U1 PC15 to U5 /CS) and LORA_CS (U1 PC1 to U9 NSS). When one device is selected, the other must be deselected so that its data outputs are high-impedance. This is correctly implemented with separate GPIO-driven chip selects. However, the MOSI/MISO swap on U5 described above must be corrected before this bus-sharing arrangement can function.

The W25Q128JVSIQ quad-mode data lines IO2 and IO3 (pins 3 and 7) are on dedicated nets with pull-up resistors and are not shared with U9. This means quad-mode operation of the flash, once the wiring error is corrected, will not interfere with the LoRa transceiver, and vice versa. The two additional data lines are exclusively connected to U5.

AI-Assisted — U5 VCC (pin 8) is connected to the +3.3V rail. The +3.3V rail is sourced by U19 (AMS1117-3.3) and is decoupled with a substantial capacitor bank including twelve 100 nF ceramics, two 10 uF ceramics, one 10 nF ceramic, one 1 uF ceramic, one 2.2 uF ceramic, and one 22 uF tantalum. U5 has one 100 nF ceramic capacitor on its VCC pin, which is consistent with the Winbond datasheet recommendation. The GND pin (pin 4) is connected to the ground plane.

The +3.3V supply voltage is within the W25Q128JV operating range of 2.7 V to 3.6 V. No further power supply concerns are identified for this device.

AI-Assisted — The only memory device in this design is U5 (W25Q128JVSIQ). There are no DDR, SRAM, or NVRAM interfaces present.

The critical finding is the SPI2 MOSI/MISO wiring reversal between U5 and U9. This error renders the flash memory completely inoperative and must be corrected before board bring-up. All other aspects of the flash interface — chip select routing, pull-ups on /WP and /HOLD, power supply voltage, and decoupling — are correctly implemented.

The ADXL375 accelerometer (U4) and ICM-42688-P IMU (U10) share a separate SPI1 bus and are not memory devices; they are not covered in this memory interface review. The SPI1 bus does not exhibit any direction conflicts.

AI-Assisted —

Memory	Interface	Finding	Severity
W25Q128JVSIQ (U5)	SPI2 Shared Bus	SPI2_MOSI net connects STM32 PC3 (MOSI output) to U5 pin 2 (DO/IO1, flash data output) and U9 pin 3 (MOSI input). Flash MOSI/MISO pins are swapped — bus cannot function. Requires schematic correction.	High
W25Q128JVSIQ (U5)	SPI2 Shared Bus	SPI2_MISO net connects STM32 PC2 (MISO input) to U5 pin 5 (DI/IO0, flash data input) and U9 pin 2 (MISO output). Flash MOSI/MISO pins are swapped — bus cannot function. Requires schematic correction.	High
W25Q128JVSIQ (U5)	SPI2 Signal Integrity	No series termination resistors on SPI2 clock or data lines. Acceptable at low clock rates (10 MHz for LoRa compatibility); consider 22–33 ohm series resistors near U1 if higher-speed flash-only transfers are planned.	Low
W25Q128JVSIQ (U5)	QSPI NOR Flash	No external pull-up on /CS. STM32 GPIO holds /CS high when deselected, but pin is undefined during MCU reset until GPIO initialization completes.	Low
W25Q128JVSIQ (U5)	QSPI NOR Flash	Supply voltage 3.3 V is within the Winbond-specified 2.7 V to 3.6 V operating range (W25Q128JV datasheet).	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	VCC bypass capacitor: one 100 nF ceramic present on pin 8, consistent with Winbond datasheet recommendation.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	/CS (pin 1) driven by dedicated STM32 GPIO (PC15) on net FLASH_CS. Separate from LoRa chip select.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	/WP (IO2, pin 3) pulled high to +3.3V via R5 (10 kohm). Correct for disabling write protection and compatible with quad-mode overdriving.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	/HOLD/RESET (IO3, pin 7) pulled high to +3.3V via R6 (10 kohm). Correct for disabling hold function and compatible with quad-mode overdriving.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	GND (pin 4) connected to ground plane.	✓
RFM95W-868S2 (U9)	SPI2 Shared Bus	LoRa transceiver chip select (NSS, pin 5) driven by dedicated STM32 GPIO (PC1) on net LORA_CS, independent of flash /CS.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	Quad-mode data lines IO2 (pin 3) and IO3 (pin 7) are on dedicated nets not shared with U9. Quad operation will not conflict with LoRa transceiver once MOSI/MISO wiring is corrected.	✓

AI-Assisted — U1 is an STM32F405RGT6 in LQFP-64, powered from the +3.3V rail on VDD pins 64, 19, 32, and 48, and on VBAT pin 1. The supply voltage of 3.3V is within the 1.8 to 3.6V operating range per datasheet DS8626. VDDA (pin 13) is supplied from the +3.3VA rail, which is derived from +3.3V through ferrite bead FB1 (100 ohm). The +3.3VA rail is bypassed with a 0.01 uF ceramic (C7) and a 1 uF ceramic (C8). ST application note AN4488 Rev 7 recommends 1 uF plus 0.01 uF on VDDA, which matches the design. VSSA (pin 12) is connected to GND. The +3.3V rail carries a total of eighteen bypass capacitors including twelve 0.1 uF ceramics, one 10 nF ceramic, two 10 uF ceramics, one 1 uF ceramic, one 2.2 uF ceramic, and one 22 uF tantalum. This is generous decoupling for five VDD pins and is acceptable.

VCAP_1 (pin 31) and VCAP_2 (pin 47) each have a 2.2 uF ceramic capacitor to GND (C51 and C11 respectively). The STM32F405 datasheet specifies 2.2 uF on each VCAP pin, so this is correct.

The 16 MHz crystal ABM8-16Mhz-B2-T1 is connected between PH0 (pin 5, HSE_IN) and PH1 (pin 6, HSE_OUT). The crystal load capacitance is 18 pF. The load capacitors C12 and C13 are each 26 pF. Using the standard formula CL = (C1 x C2)/(C1 + C2) + Cstray, with C1 = C2 = 26 pF and assuming approximately 5 pF stray capacitance, the effective load is 13 + 5 = 18 pF, which matches the crystal specification.

BOOT0 (pin 60) is connected through R2 (10k) to the slide switch S1. S1 pin 1 is tied to GND and pin 3 is tied to +3.3V, so the switch selects between GND (boot from flash) and +3.3V (boot from system memory). This is a correct boot mode selection circuit.

NRST (pin 7) has a 10k pull-up to +3.3V (R1) and a 0.1 uF capacitor to GND (C10), with push button SW2 to GND. This matches ST recommendations for an external reset circuit.

SWDIO (PA13, pin 46) connects to J2 pin 2, and SWCLK (PA14, pin 49) connects to J2 pin 3. J2 pin 1 provides +3.3V and pin 4 is GND. This is a standard SWD debug header.

USB D+ (PA12, pin 45) and D- (PA11, pin 44) connect directly to the USB Type-C connector J1. Both A-side and B-side D+/D- pins on J1 are tied together, which is correct for a USB 2.0 device on a Type-C receptacle. The CC1 and CC2 pins on J1 each have a 5.1k pull-down resistor to GND (R3 and R4), correctly identifying this as a USB device (UFP) per USB Type-C specification.

SPI1 bus connects to U10 (ICM-42688-P) and U4 (ADXL375) with SPI1_SCK on PA5, SPI1_MOSI on PA7, and SPI1_MISO on PA6. Separate chip selects ICM_CS (PC5) and ADXL_CS (PC4) are provided. The ADXL375 SDA/SDI/SDIO pin (U4 pin 13) is not directly on SPI1_MOSI but instead receives data through OR gate U2, which is discussed in the U2 subsection.

SPI2 bus connects to U5 (W25Q128JVSIQ) and U9 (RFM95W) with SPI2_SCK on PB10, SPI2_MOSI on PC3, and SPI2_MISO on PC2. Separate chip selects FLASH_CS (PC15) and LORA_CS (PC1) are provided. However, the SPI2 data line wiring has a critical error described in the W25Q128JVSIQ subsection.

I2C1 bus (PB6/SCL, PB7/SDA) connects to U3 (BMP388) with 4.7k pull-ups to +3.3V (R14, R15). This is appropriate for I2C at standard or fast mode.

USART1 TX (PA10, pin 43) and RX (PA9, pin 42) connect through level translator U16 to connector J3. Each line has a 1k series resistor (R37, R38) with pull-ups to +3.3V.

UART5 TX (PC12, pin 53) and RX (PD2, pin 54) connect directly to connector J12.

Servo outputs SERVO1 through SERVO4 are driven from PC6, PC7, PC8, and PC9 to servo connectors M4, M2, M3, and M1 respectively. The servo power pins connect to VBAT+_PYRO, and the ground pins connect to GND.

Pyrotechnic channel outputs PYRO1 through PYRO6 are driven from PB5, PB4, PB3, PC11, PC10, and PA15 through 330 ohm series resistors to optocoupler LED inputs.

Eleven GPIO pins are intentionally unconnected in the schematic (PB9, PB8, PC14, PA3, PB11, PA2, PA4, PB0, PB12, PB1, PA8), which is acceptable for unused I/O on this MCU.

AI-Assisted — The SPI2 bus shared between U5 (W25Q128JVSIQ flash) and U9 (RFM95W LoRa module) has a wiring error on both data lines. On the SPI2_MOSI net (PC3 on U1), the W25Q128JVSIQ pin 2 (DO/IO1) is a data output, while the RFM95W pin 3 (MOSI) is a data input. These two pins have opposite directions and cannot coexist on the same wire. Similarly, on the SPI2_MISO net (PC2 on U1), the W25Q128JVSIQ pin 5 (DI/IO0) is a data input, while the RFM95W pin 2 (MISO) is a data output. The W25Q128JVSIQ uses Winbond naming where DI is the data-in pin (equivalent to MOSI from the controller) and DO is the data-out pin (equivalent to MISO). The current wiring connects the flash DO (output) to the LoRa MOSI (input) on the same net as the MCU MOSI output, creating a bus conflict where two outputs drive the same line. Likewise, the flash DI (input) shares a net with the LoRa MISO (output) and the MCU MISO input, meaning the MCU output and the LoRa output would fight. The MOSI and MISO connections to U5 are swapped. U5 pin 5 (DI/IO0) should be on SPI2_MOSI, and U5 pin 2 (DO/IO1) should be on SPI2_MISO. This must be corrected before fabrication.

AI-Assisted — U10 is an ICM-42688-P 6-axis IMU powered from +3.3V on both VDD (pin 8) and VDDIO (pin 5). The 3.3V supply is within the 1.71 to 3.6V range for both rails. The GND pin (pin 6) is connected to ground. No dedicated bypass capacitors are visible specifically for U10 in the schematic; however, U10 shares the +3.3V rail which has extensive decoupling. The ICM-42688-P datasheet recommends a 100 nF capacitor close to each supply pin (VDD and VDDIO). The designer should ensure that at least two of the twelve 0.1 uF ceramics on the +3.3V rail are placed physically adjacent to U10 during layout.

The SPI interface uses SPI1_SCK (PA5) on AP_SCL/AP_SCLK (pin 13), SPI1_MOSI (PA7) on AP_SDA/AP_SDIO/AP_SDI (pin 14), and SPI1_MISO (PA6) on AP_SDO/AP_AD0 (pin 1). The chip select ICM_CS (PC5) drives AP_CS (pin 12). This wiring is correct for SPI mode.

INT1/INT (pin 4) connects to U1 PB2 on net ICM_INT1, providing interrupt capability to the MCU. INT2/FSYNC/CLKIN (pin 9) is intentionally unconnected in the schematic, which is acceptable when only one interrupt output is needed.

RESV_3 (pin 3), RESV_2 (pin 2), and RESV_10 (pin 10) are intentionally unconnected. RESV_7 (pin 7) and RESV_11 (pin 11) are tied to GND. The ICM-42688-P datasheet states that reserved pins should be left unconnected. Tying RESV_7 and RESV_11 to GND rather than leaving them floating is unlikely to cause a problem but deviates from the datasheet instruction to leave reserved pins unconnected.

AI-Assisted — U3 is a BMP388 pressure sensor with VDDIO (pin 1) and VDD (pin 10) both connected to +3.3V. The 3.3V supply is within the 1.65 to 3.6V range for VDD and the 1.2 to 3.6V range for VDDIO. Three VSS pins (3, 8, 9) are all connected to GND. The BMP388 datasheet recommends 100 nF bypass capacitors on VDD and VDDIO. The +3.3V rail has ample 0.1 uF ceramics; placement near U3 during layout is important.

The I2C interface uses SCK (pin 2) on I2C1_SCL and SDI (pin 4) on I2C1_SDA, with 4.7k pull-ups to +3.3V. SDO (pin 5) is tied to GND, which sets the I2C address to 0x76 (per BMP388 datasheet, SDO low = address 0x76). CSB (pin 6) is tied to +3.3V, which selects I2C mode per the datasheet. This configuration is correct.

INT (pin 7) is intentionally unconnected in the schematic. The interrupt output is optional and not required for polled operation, so this is acceptable.

AI-Assisted — U4 is an ADXL375BCCZ high-g accelerometer. VDD_I/O (pin 1) is connected to +3.3V. VS (pin 6) is supplied through R16 (33 ohm) from +3.3V, with two bypass capacitors to GND: C27 (10 uF tantalum) and C28 (0.1 uF ceramic). The 33 ohm series resistor with the bypass capacitors forms an RC filter on the VS supply, which is a common technique for noise-sensitive analog sensors. The ADXL375 VS operating range is 2.0 to 3.6V. With 33 ohm in series and typical quiescent current of approximately 145 uA, the voltage drop across R16 is negligible (about 5 mV), so VS remains within specification. Three GND pins (2, 4, 5) are all connected to ground.

The SPI interface uses SPI1_SCK on SCL/SCLK (pin 14) and SPI1_MISO on SDO/ALT_ADDRESS (pin 12). The SDA/SDI/SDIO pin (pin 13) receives data from OR gate U2 output (pin 4) rather than directly from SPI1_MOSI. The chip select CS (pin 7, active low) is driven by the ADXL_CS net (PC4 on U1), which also connects to U2 input pin 1.

INT1 (pin 8) and INT2 (pin 9) are both intentionally unconnected. The ADXL375 can operate without interrupts using polled SPI reads, but for a high-g event detection application, connecting at least INT1 to an MCU GPIO would allow hardware-triggered data capture. This is a design choice rather than an error.

RESERVED pins 3 and 11 are intentionally unconnected, and NC pin 10 is intentionally unconnected. The ADXL375 datasheet states these pins should not be connected, so this is correct.

AI-Assisted — U2 is a 74AHC1G32 single 2-input OR gate powered from +3.3V (VCC pin 5) with GND on pin 3. The supply is within the 2.0 to 5.5V operating range. Input pin 1 connects to ADXL_CS (PC4), and input pin 2 connects to SPI1_MOSI (PA7). The output (pin 4) drives U4 SDA/SDI/SDIO (pin 13).

This OR gate arrangement means that when ADXL_CS is high (deselected), the ADXL375 SDA/SDI/SDIO pin is held high regardless of SPI1_MOSI activity, preventing unintended data clocking into the ADXL375 while the ICM-42688-P is being addressed on the same SPI1 bus. When ADXL_CS is low (selected), the OR gate output follows SPI1_MOSI. This is a valid bus isolation technique for shared SPI buses where the slave MOSI pin might latch data even when CS is inactive. The logic is correct: OR(CS, MOSI) = MOSI when CS=0, and OR(CS, MOSI) = 1 when CS=1.

AI-Assisted — U5 is a W25Q128JVSIQ 128 Mbit SPI NOR flash. VCC (pin 8) is on +3.3V and GND (pin 4) is connected to ground. The 3.3V supply is within the 2.7 to 3.6V operating range. The /WP (pin 3) and /HOLD/RESET (pin 7) pins are each pulled high to +3.3V through 10k resistors (R5 and R6), which disables write protection and prevents inadvertent hold or reset states. The chip select /CS (pin 1) is driven by FLASH_CS (PC15 on U1).

As detailed in the SPI2 bus wiring error subsection, the MOSI and MISO connections to U5 are swapped. U5 pin 2 (DO/IO1, the data output) is on the SPI2_MOSI net, and U5 pin 5 (DI/IO0, the data input) is on the SPI2_MISO net. This is reversed from correct operation and must be fixed.

AI-Assisted — U9 is an RFM95W-868S2 LoRa module powered from +3.3V on pin 13 (3.3V). Three GND pins (1, 8, 10) are connected to ground. The 3.3V supply is within the 1.8 to 3.7V operating range. The module integrates a 32 MHz crystal internally, so no external crystal is needed.

The SPI interface uses SPI2_SCK on SCK (pin 4), SPI2_MOSI on MOSI (pin 3), and SPI2_MISO on MISO (pin 2). The chip select LORA_CS (PC1) drives NSS (pin 5). RESET (pin 6) is driven by LORA_RST (PC0). DIO0 (pin 14) connects to PA0 (LORA_DIO0) and DIO1 (pin 15) connects to PA1 (LORA_DIO1) on the MCU. These two interrupt lines are sufficient for LoRa TX/RX done and timeout signaling.

DIO5 (pin 7), DIO3 (pin 11), DIO2 (pin 16), and DIO4 (pin 12) are all intentionally unconnected. These are optional diagnostic outputs and are not required for basic LoRa operation.

The ANT pin (pin 9) connects directly to SMA connector J7 via net Net-(J7-In). No matching network components are visible between the module and the SMA connector. The RFM95W module datasheet specifies a 50 ohm antenna impedance. The SMA connector is a Samtec edge-mount type. If the SMA connector and antenna present a 50 ohm load, no external matching is needed since the module has an internal matching network for 868 MHz. The PCB trace from U9 pin 9 to J7 must be a controlled-impedance 50 ohm transmission line, and a ground plane keep-out under the antenna connector area should be considered during layout.

The SPI2 data lines to U9 are correctly oriented (MOSI to MOSI input, MISO from MISO output), but the shared bus with U5 has the swapped connections described in the SPI2 wiring error subsection. Once U5 connections are corrected, U9 SPI wiring will function properly.

AI-Assisted — U16 is an LSF0102DCUR dual bidirectional level translator. VREF_A (pin 2) is connected to +3.3V, and VREF_B (pin 7) is connected to a net derived from +5V through R39 (200k) with C33 (0.1 uF) to GND. The EN pin (pin 8) is tied to the same VREF_B net, so the device is enabled when the +5V rail is present. GND (pin 1) is connected to ground.

The LSF0102 datasheet requires VREF_A to be the lower voltage side. Here VREF_A = 3.3V and VREF_B is derived from +5V. The 200k resistor from +5V with 0.1 uF to GND forms an RC filter with a very long time constant (20 ms), which will cause slow startup of the B-side reference. During normal operation, the VREF_B voltage will be close to 5V since the only DC load is the high-impedance VREF_B and EN inputs. This satisfies the requirement that VREF_A < VREF_B.

The A-side channels A1 (pin 3) and A2 (pin 4) connect to USART1_RX and USART1_TX respectively, with 1k series resistors (R38, R37) pulled up to +3.3V. The B-side channels B1 (pin 6) and B2 (pin 5) connect to J3 pins 2 and 3, with pull-ups to +5V through R40 and R41 (both 1k). The LSF0102 is an open-drain switch-based translator that requires external pull-up resistors on both sides. The 1k pull-ups are present on both sides, which is correct. However, the B-side net Net-(J3-Pin_2) has two 1k resistors (R40 and R41) both pulling up to +5V on the B1 channel, resulting in an effective 500 ohm pull-up. This asymmetry between B1 (500 ohm effective) and B2 (1k) is unusual but not necessarily an error; it may be intentional for a specific load on that line.

AI-Assisted — Six TLP291 optocouplers are used for pyrotechnic channel isolation. The TLP291 is not recommended for new designs per Toshiba. Each optocoupler LED anode (pin 1) connects through a 330 ohm series resistor to an MCU GPIO (PYRO1 through PYRO6), and the LED cathode (pin 2) connects to GND. With a 3.3V GPIO high output and typical LED forward voltage of 1.1V, the LED current is approximately (3.3 - 1.1) / 330 = 6.7 mA, which is within the TLP291 maximum forward current of 50 mA and provides adequate drive for the 50-100% CTR range.

The phototransistor collector (pin 4) of each optocoupler connects to the VBAT+_PYRO rail, and the emitter (pin 3) connects through a 100 ohm resistor to the gate of an N-channel MOSFET (Q2, Q3, Q6, Q7, Q8, Q9). The 100 ohm resistor limits gate current and provides some filtering. Each MOSFET gate also has a 10k pull-down resistor to GND to ensure the gate is held low when the optocoupler is off.

The mapping is: U6 drives Q2 (PYRO1, J4), U7 drives Q3 (PYRO2, J6), U8 drives Q6 (PYRO3, J8), U11 drives Q7 (PYRO4, J9), U12 drives Q8 (PYRO5, J10), U13 drives Q9 (PYRO6, J11).

AI-Assisted — Six AO3400A N-channel MOSFETs serve as low-side switches for pyrotechnic channels. Each MOSFET source (pin 2) is connected to GND, and the drain (pin 3) connects through a US1M diode (cathode on VBAT+_PYRO, anode on the drain net) to a screw terminal connector. The screw terminal pin 1 connects to the MOSFET drain net, and pin 2 connects to VBAT+_PYRO, forming a current path: VBAT+_PYRO through the pyrotechnic load (connected across the screw terminal) through the MOSFET to GND.

The US1M diodes (D2, D3, D5, D8, D9, D10) are oriented with cathode on VBAT+_PYRO and anode on the MOSFET drain side. This provides a freewheeling path for inductive loads. The US1M is a 1000V, 1A ultra-fast recovery rectifier. For pyrotechnic igniter loads, which are primarily resistive, the freewheeling diode is a precautionary measure. The 1000V rating provides substantial margin for any voltage transients on the VBAT+_PYRO rail.

The AO3400A has a Vds rating of 30V. The VBAT+_PYRO rail voltage is not explicitly defined in the schematic but is supplied externally through screw terminals and servo connectors. If VBAT+_PYRO exceeds 30V, the MOSFETs would be overstressed. The gate drive voltage from the optocoupler phototransistor is limited by the VBAT+_PYRO rail voltage. With a 10k pull-down and 100 ohm series resistor, the gate voltage will be close to VBAT+_PYRO when the optocoupler is on (assuming sufficient CTR). For Vgs, the AO3400A maximum is ±12V. If VBAT+_PYRO exceeds 12V, a gate voltage clamp (such as a Zener diode) would be needed to protect the gate. No such clamp is present in the design. A Schottky diode clamp from gate to source would be a better solution for protecting the gate oxide when the MOSFET is intentionally off and transients could couple to the gate.

AI-Assisted — Q4 is an AO3401A P-channel MOSFET with source (pin 2) on VBAT+ and drain (pin 3) connected to J5 pin 2. The gate (pin 1) is pulled down to GND through R17 (10k), which means Q4 is normally on (Vgs = -VBAT+). This provides a normally-on high-side switch from the VBAT+ rail to connector J5. There is no MCU control of Q4 gate visible in the schematic; R17 simply holds the gate at GND. The AO3401A Vgs maximum is ±12V. If VBAT+ exceeds 12V, the gate-source voltage will exceed the absolute maximum rating, which would damage the device. A gate voltage clamp or resistive divider is needed if VBAT+ can exceed 12V.

Q5 is identically configured with source on VBAT+_PYRO (not VBAT+), drain to J13 pin 2, and gate pulled to GND through R18 (10k). The same Vgs concern applies: if VBAT+_PYRO exceeds 12V, Q5 gate oxide is at risk. A Schottky diode clamp from gate to source would be a better solution for protecting the gate when the transistor is intentionally held on with a large Vgs.

AI-Assisted — Q1 is a BC817 NPN transistor used to drive buzzer LS1. The base (pin 1) is driven through R10 (1k) from U1 PC13 (BUZZER net). The emitter (pin 2) is on GND, and the collector (pin 3) connects to the cathode side of D4 (US1M) and the negative terminal of LS1. The positive terminal of LS1 connects to +3.3V. D4 is oriented with cathode on +3.3V and anode on the collector net, providing a freewheeling path.

The CMI-9705-0580-SMT-TR buzzer is rated for 5 VDC with an operating range of 3 to 8 VDC. It is being driven from +3.3V, which is within the operating range but at the low end. The rated current is 30 mA. With a 3.3V GPIO high output and 1k base resistor, the base current is approximately (3.3 - 0.7) / 1000 = 2.6 mA. With minimum hFE of 160, the transistor can sink up to 416 mA, which is more than sufficient for the 30 mA buzzer load. The sound pressure level at 3.3V will be lower than the 80 dB specification at 5V, but the buzzer will function.

AI-Assisted — D11 and D12 are SS14 Schottky diodes forming an OR-ing circuit for the input to the TPS563200 buck regulator (U17). D11 cathode connects to the Net-(D11-K) node (U17 VIN), and its anode connects to VBAT+. D12 cathode connects to the same Net-(D11-K) node, and its anode connects to VBUS (USB). This allows the board to be powered from either the battery (VBAT+) or USB (VBUS), with the higher voltage source dominating. Three 10 uF ceramic capacitors (C15, C16, C17) bypass the combined input node to GND.

The SS14 has a 40V reverse voltage rating. If VBAT+ or VBUS can approach or exceed 40V, the diodes would be overstressed. For typical battery voltages (e.g., 2S to 4S LiPo, 7.4 to 16.8V) and USB (5V), the 40V rating provides adequate margin. The forward voltage drop is 500 mV maximum at 1A, which is acceptable for this application. R11 (10k) connects from Net-(D11-K) to the EN pin of U17, providing an enable signal proportional to the input voltage.

AI-Assisted — D4 is a US1M diode with cathode on +3.3V and anode on the buzzer driver collector net (Net-(D4-A)). This serves as a freewheeling diode for the buzzer LS1, which is an internally driven magnetic buzzer. The US1M 1000V rating is far in excess of what is needed for a 3.3V application, and the 1A current rating exceeds the 30 mA buzzer current. The forward voltage drop of up to 1.7V is acceptable for a freewheeling application where the diode only conducts briefly during switching transients. A Schottky diode would provide faster clamping with lower forward voltage, but the US1M is functionally adequate.

AI-Assisted — D1 is an ARGB LED (ASMB-KTF0-0A306) with common anode on +3.3V. The red cathode (RK, pin 2) is driven through R7 (91 ohm) from PB15 (LED_RED). The green cathode (GK, pin 3) is driven through R8 (24 ohm) from PB14 (LED_GRN). The blue cathode (BK, pin 4) is driven through R9 (47 ohm) from PB13 (LED_BLU). The MCU drives each cathode low to turn on the corresponding color. The different resistor values compensate for the different forward voltages and luminous intensities of the red, green, and blue dies to achieve color balance. The resistor values are reasonable for a 3.3V supply with typical LED forward voltages of 2.0V (red), 3.0V (green), and 3.0V (blue).

AI-Assisted — Four servo motor connectors M1 through M4 use standard 3-pin headers. The PWM pin (pin 1) of each servo connects to an MCU timer-capable GPIO: M4 to PC6 (SERVO1), M2 to PC7 (SERVO2), M3 to PC8 (SERVO3), M1 to PC9 (SERVO4). The power pin (pin 2) connects to VBAT+_PYRO, and the ground pin (pin 3) connects to GND. Standard hobby servos expect 4.8 to 6.0V power. If VBAT+_PYRO is a higher voltage battery rail, the servos may be overvoltaged. The PWM signal level is 3.3V from the MCU, which is typically sufficient for servo signal input thresholds (usually >2.5V for logic high). PC6 through PC9 are on TIM3 and TIM8, which support PWM output generation.

AI-Assisted — The crystal ABM8-16Mhz-B2-T1 is an Abracon ABM8-16.000MHZ-B2-T in a 3225 4-pad package. It operates at 16 MHz fundamental mode with 18 pF load capacitance and ±20 ppm frequency tolerance at 25 degrees C. The crystal connects between PH0 (HSE_IN) and PH1 (HSE_OUT) on U1, with ground pins 2 and 4 connected to GND. Load capacitors C12 and C13 are each 26 pF. As calculated in the U1 subsection, the effective load capacitance matches the 18 pF crystal specification when accounting for approximately 5 pF of stray capacitance. The 16 MHz frequency is within the STM32F405 HSE range of 4 to 26 MHz and is the standard crystal frequency for this MCU family, enabling USB-compatible 48 MHz PLL output.

AI-Assisted —

Device	Category	Finding	Severity
U5 (W25Q128JVSIQ) / U9 (RFM95W-868S2)	SPI Wiring	SPI2 data lines are swapped on U5: pin 2 (DO, output) is on SPI2_MOSI and pin 5 (DI, input) is on SPI2_MISO. This creates a bus conflict with U9 whose MOSI and MISO are correctly oriented. The flash MOSI/MISO connections must be swapped.	High
U5 (W25Q128JVSIQ)	Flash Memory	Power supply, /WP and /HOLD pull-ups, and chip select are correct. SPI data lines are swapped (see SPI2 wiring error finding).	High
Q2/Q3/Q6/Q7/Q8/Q9 (AO3400A)	Transistor	Gate drive from optocoupler phototransistor on VBAT+_PYRO rail has no Vgs clamp. If VBAT+_PYRO exceeds 12V, the ±12V Vgs absolute maximum rating will be violated. A Schottky diode clamp from gate to source is recommended.	High
Q4 (AO3401A)	Transistor	Gate pulled to GND through R17 (10k), making Vgs = -VBAT+. If VBAT+ exceeds 12V, the ±12V Vgs maximum rating is violated. A Schottky diode clamp or resistive divider is needed.	High
Q5 (AO3401A)	Transistor	Gate pulled to GND through R18 (10k), making Vgs = -VBAT+_PYRO. Same Vgs overvoltage risk as Q4 if VBAT+_PYRO exceeds 12V.	High
U6/U7/U8/U11/U12/U13 (TLP291)	Optocoupler	LED drive current approximately 6.7 mA through 330 ohm resistors is within specification. Phototransistor outputs correctly drive MOSFET gates through 100 ohm series resistors with 10k pull-downs. The TLP291 is not recommended for new designs per Toshiba.	Medium
Q2/Q3/Q6/Q7/Q8/Q9 (AO3400A)	Transistor	Vds rating is 30V. If VBAT+_PYRO exceeds 30V, drain-source breakdown will occur. The external supply voltage must be limited accordingly.	Medium
U10 (ICM-42688-P)	Sensor	Power supply, SPI interface, chip select, and INT1 interrupt connection are correct. RESV_7 and RESV_11 are tied to GND; datasheet recommends leaving reserved pins unconnected.	Low
U4 (ADXL375BCCZ)	Sensor	INT1 and INT2 are both unconnected. For high-g event detection, connecting at least INT1 to an MCU GPIO would enable hardware-triggered data capture.	Low
LS1 (CMI-9705-0580-SMT-TR)	Buzzer	Rated for 5 VDC (range 3-8V), driven from 3.3V. Will function but at reduced sound pressure level compared to 5V rating.	Low
U1 (STM32F405RGT6)	MCU	VDD and VDDA supply voltages, VCAP capacitors (2.2 uF each), HSE crystal, BOOT0 selection, NRST circuit, and SWD debug interface are all correctly configured per datasheet DS8626 and AN4488.	✓
U1 (STM32F405RGT6)	MCU	USB Type-C CC1/CC2 pull-downs (5.1k to GND) correctly identify device as UFP per USB Type-C specification.	✓
U3 (BMP388)	Sensor	Power supply, I2C interface with 4.7k pull-ups, SDO tied low for address 0x76, and CSB tied high for I2C mode are all correct per BMP388 datasheet BST-BMP388-DS001-07.	✓
U4 (ADXL375BCCZ)	Sensor	Power supply with filtered VS rail (33 ohm + 10 uF tantalum + 0.1 uF ceramic), SPI interface through OR gate U2, chip select, and reserved/NC pin handling are correct per ADXL375 datasheet Rev. B.	✓
U2 (74AHC1G32)	Logic	OR gate correctly isolates ADXL375 MOSI input on shared SPI1 bus. Supply voltage and logic function are correct.	✓
U9 (RFM95W-868S2)	Wireless	Power supply, SPI interface, chip select, reset, DIO0/DIO1 interrupt lines, and antenna connection to SMA connector are correct. No external matching network is needed as the module includes internal matching. PCB trace to J7 must be 50 ohm controlled impedance.	✓
U16 (LSF0102DCUR)	Level Translator	VREF_A (3.3V) is correctly the lower voltage side. VREF_B derived from +5V through 200k resistor. EN tied to VREF_B for automatic enable. Pull-up resistors present on both sides per TI LSF0102 datasheet Rev. B.	✓
Q1 (BC817)	Transistor	Base drive through 1k resistor provides approximately 2.6 mA base current, sufficient to saturate for 30 mA buzzer load. Emitter grounded, collector to buzzer with freewheeling diode D4. Correct configuration.	✓
D2/D3/D5/D8/D9/D10 (US1M)	Rectifier	Freewheeling diodes on pyrotechnic channels with cathode on VBAT+_PYRO and anode on MOSFET drain. 1000V/1A rating provides ample margin. Orientation is correct.	✓
D11/D12 (SS14)	Rectifier	Schottky OR-ing diodes from VBAT+ and VBUS to buck regulator input. 40V rating provides adequate margin for typical battery and USB voltages. Correct orientation.	✓
D4 (US1M)	Rectifier	Freewheeling diode for buzzer with cathode on +3.3V and anode on collector. 1000V rating is excessive but functional. Correct orientation.	✓
D1 (LED_ARGB)	LED	Common anode on +3.3V with individual cathode resistors (91, 24, 47 ohm for R/G/B). Current limiting and color balance resistor values are reasonable for 3.3V operation.	✓
M1/M2/M3/M4 (Motor_Servo)	Servo	PWM signals from timer-capable GPIOs (PC6-PC9). Power from VBAT+_PYRO rail. Standard servo pinout. External supply voltage must be appropriate for the servos used (typically 4.8-6.0V).	✓
ABM8-16Mhz-B2-T1	Crystal	16 MHz fundamental mode crystal with 18 pF load capacitance. Load capacitors C12/C13 (26 pF each) match the 18 pF specification with approximately 5 pF stray capacitance. Ground pins 2 and 4 connected to GND. Correct per Abracon ABM8 datasheet.	✓

AI-Assisted —

References
74AHC1G32 (Nexperia / Diodes Inc / TI (multiple sources)) — Nexperia 74AHC1G32 datasheet Rev. 12, 19 Sep 2024 assets.nexperia.com/documents/data-sheet/74AHC_AHCT1G32.pdf
ABM8-16.000MHZ-B2-T (Abracon) — Abracon ABM8 series datasheet, product page abracon.com abracon.com/Resonators/abm8.pdf
ADXL375BCCZ (Analog Devices) — ADXL375 datasheet Rev. B, Analog Devices, 32 pages www.analog.com/media/en/technical-documentation/data-shee...
AMS1117-3.3 (Advanced Monolithic Systems) — AMS1117 datasheet, Advanced Monolithic Systems, ds1117.pdf www.advanced-monolithic.com/pdf/ds1117.pdf
AO3400A (Alpha & Omega Semiconductor) — Alpha & Omega Semiconductor AO3400A datasheet, aosmd.com www.aosmd.com/res/datasheets/AO3400A.pdf
AO3401A (Alpha & Omega Semiconductor) — Alpha & Omega Semiconductor AO3401A datasheet Rev 3.1 December 2023, aosmd.com www.aosmd.com/res/datasheets/AO3401A.pdf
BMP388 (Bosch Sensortec) — BMP388 datasheet BST-BMP388-DS001-07, Revision 1.7, November 2020, 59 pages www.bosch-sensortec.com/media/boschsensortec/downloads/da...
CMI-9705-0580-SMT-TR (Same Sky (formerly CUI Devices)) — Same Sky product page and distributor specs (DigiKey, Mouser) www.sameskydevices.com/product/resource/cmi-9705-0580-smt...
ICM-42688-P (TDK InvenSense) — ICM-42688-P datasheet ds-000347 v1.6, 06/20/2021, TDK InvenSense, 110 pages product.tdk.com/system/files/dam/doc/product/sensor/morti...
LSF0102DCUR (Texas Instruments) — TI LSF0102 datasheet, Rev. B; also Nexperia LSF0102 datasheet Rev. 3, Sep 2020 www.ti.com/lit/ds/symlink/lsf0102.pdf
RFM95W-868S2 (HopeRF (Shenzhen Hope Microelectronics) / RF Solutions (distributor brand)) — RFM95/96/97/98(W) Datasheet Version 2.0, hoperf.com (via cdn.sparkfun.com); GlobalSpec/DigiKey hosted datasheet cdn.sparkfun.com/assets/a/9/6/1/0/RFM95W-V2.0.pdf
SS14 (onsemi) — onsemi SS14 datasheet, August 2023 Rev. 3 www.onsemi.com/products/discrete-power-modules/schottky-d...
STM32F405RGT6 (STMicroelectronics) — STM32F405xx/STM32F407xx Datasheet DS8626, st.com; AN4488 Rev 7 (Hardware Development App Note) www.st.com/resource/en/datasheet/stm32f405rg.pdf
TLP291 (Toshiba) — TLP291(SE datasheet, Rev.2.0, 2019-07-08; TLP291 datasheet 2014-09-22, RS-Online hosted PDF toshiba.semicon-storage.com/info/TLP291_datasheet_en_2014...
TPS563200 (Texas Instruments) — TPS56x200 datasheet, SLVSCB0, Rev E, TI.com www.ti.com/lit/ds/symlink/tps562200.pdf
US1M (Diodes Incorporated) — Diodes Incorporated DS16008 Rev. 11-2 www.diodes.com/datasheet/download/US1M.pdf

AI-Assisted — The design uses a single flat ground domain. All ground connections throughout the board, including the USB Type-C connector shell, all IC ground pins, all connector ground pins, and all passive return paths, share a single net named GND. There is no separate chassis ground, no analog ground split (the +3.3VA rail is filtered through a 100 ohm ferrite bead FB1 from +3.3V, but the return path for U1 VSSA still merges into the common GND), and no dedicated shield ground nets for any shielded connector. This single-ground topology is common in small embedded systems and is acceptable provided the layout implements a solid, unbroken ground plane. However, the schematic does not capture any design intent for ground plane partitioning, pour isolation, or connector shield bonding strategy, which means the layout engineer has no net-level guidance for these critical EMC features.

The power architecture feeds VBUS from the USB Type-C connector J1 through Schottky diode D12 (SS14, 40 V 1 A) and battery voltage VBAT+ through Schottky diode D11 (SS14) into a common node that supplies the TPS563200 buck regulator U17. Three 10 uF ceramic capacitors (C15, C16, C17) provide input filtering on this node. The TPS563200 switches at a nominal frequency around 500 kHz to 1.4 MHz depending on load, and the switching node Net-(U17-SW) connects through a 3.3 uH inductor L2 to the +5V output rail. The +5V rail feeds the AMS1117-3.3 LDO U19 to produce +3.3V. The switching regulator is a significant source of conducted and radiated emissions. The schematic shows a 0.1 uF bootstrap capacitor C18 on the VBST pin, which is standard. Output capacitance on +5V consists of three 22 uF ceramic capacitors (C19, C20, C21) and one 10 uF tantalum (C53). Input capacitance on the combined VBUS/VBAT+ node consists of three 10 uF ceramics. No common-mode choke or pi-filter is present on the USB VBUS line between J1 and the power input, which means conducted emissions from the switching regulator can propagate back through the USB cable. Per CISPR 32 and EN 55032 Class B requirements for information technology equipment, conducted emissions on the USB cable between 150 kHz and 30 MHz are regulated, and the TPS563200 fundamental switching frequency falls within this band.

The LoRa radio module U9 (RFM95W-868S2) operates at 868 MHz and connects to an SMA edge-mount connector J7 via a direct trace from pin 9 (ANT) to J7 pin 1 (In). The SMA connector outer conductor (J7 pin 2, Ext) is tied to GND. No band-pass or low-pass harmonic filter is present between U9 and J7. The RFM95W module contains an internal matching network, but harmonics of the 868 MHz carrier (particularly the second and third harmonics at 1.736 GHz and 2.604 GHz) may exceed ETSI EN 300 220 spurious emission limits without external filtering. The absence of a pi-network or SAW filter between U9 and J7 is a radiated emissions risk.

The six pyrotechnic firing channels use screw terminal connectors (J4, J6, J8, J9, J10, J11) that connect to external wiring carrying battery-level voltages through MOSFET switches (Q2, Q3, Q6, Q7, Q8, Q9) and flyback diodes (D2, D3, D5, D8, D9, D10). These screw terminals will have long external cable runs in a rocketry or similar application, making them effective antennas for both radiated emissions pickup and ESD coupling. No filtering or transient suppression is present on any screw terminal signal line.

AI-Assisted — J1 is a GCT USB4110 16-position USB 2.0 Type-C receptacle. This is an external, consumer-facing connector that will be mated and unmated by end users, making it the primary ESD entry point on the board. The connector shell pin (SH) is connected directly to the logic GND net. The four GND pins (A1, A12, B1, B12) are also on the same GND net. There is no dedicated SHIELD_GND net for J1, which means the schematic does not capture the shield bonding strategy as explicit design intent.

The USB Type-C specification R2.5, Section 3.2.1 requires the receptacle shell to be connected to the PCB ground plane. The schematic satisfies this requirement by placing SH on GND. However, the bonding method between the shell pad and the ground plane is a layout decision that the schematic does not constrain. Two enclosure scenarios apply.

In a plastic enclosure with no earth ground, the shell pad should bond directly to the ground plane through dense via stitching underneath the connector footprint. During an IEC 61000-4-2 ESD strike to the connector shell, the entire ground plane rises in common mode with the shell, keeping differential voltage across the D+/D- and CC pins near zero. This is the preferred approach for battery-powered consumer devices.

In a metal chassis with earth ground, the designer should evaluate whether an R-parallel-C isolation network (typically 1 Mohm in parallel with 4.7 nF rated at 2 kV or higher) is needed between the shell copper pour and the logic GND plane. The shell pour would bond mechanically to the chassis at the connector cutout, while the RC network provides a controlled high-frequency path to logic ground. The capacitor shunts ESD transient energy while the resistor bleeds static charge. If the chassis and logic ground can be bonded without creating ground loops, direct bonding may be acceptable.

The schematic currently places SH on the same net as logic GND, so the layout tool cannot distinguish between shell copper and logic ground copper. A dedicated net (for example SHIELD_GND_USB) on the SH pin would allow the layout engineer to create an isolated copper pour under J1 and explicitly place bond components or direct vias as the enclosure design requires.

On the signal lines, USB_D+ and USB_D- connect directly from J1 (pins A6/B6 and A7/B7 respectively) to U1 (STM32F405RGTx) pins PA12 and PA11 with no series filtering and no ESD protection device. The CC1 and CC2 pins connect through 5.1k pull-down resistors R3 and R4 to GND, which is correct for a USB Type-C sink device per the USB Type-C specification. The SBU1 (A8) and SBU2 (B8) pins are intentionally unconnected in the schematic, which is acceptable for a USB 2.0 only implementation. VBUS pins (A4, A9, B4, B9) connect to the VBUS power rail, which feeds through Schottky diode D12 to the power input. No common-mode choke is present on the D+/D- pair, and no TVS or ESD protection array is present on any USB signal line. ST application note AN4879 (Rev 3) states that the system "should comply with both the JESD22-A114D (also known as HBM) and with the IEC 61000-4-2 standards" and recommends placing an ESD protection device as close as possible to the USB connector. The STM32F405 internal ESD structures provide HBM-level (2 kV) protection per JESD22-A114D, but this is insufficient for system-level IEC 61000-4-2 contact discharge testing at Level 4 (8 kV). The absence of an external ESD protection device (such as a USBLC6-2SC6 or equivalent low-capacitance TVS array) on USB_D+, USB_D-, CC1, CC2, and VBUS is a significant gap for IEC 61000-4-2 compliance.

AI-Assisted — J7 is a Samtec SMA-J-P-H-ST-EM1 edge-mount SMA coaxial connector used for the LoRa antenna connection to U9 (RFM95W-868S2). The center pin (J7 pin 1) connects directly to U9 pin 9 (ANT), and the outer conductor (J7 pin 2) connects to GND. This is an external connector — the antenna may be removed and reattached by the user, and the exposed center pin is accessible when no antenna is connected.

No ESD protection is present on the RF signal path between J7 and U9. When the antenna is disconnected, the exposed SMA center pin is a direct ESD entry point to the RFM95W module's RF front end. The SX1276 transceiver IC inside the RFM95W module has limited internal ESD tolerance. An ESD strike to the unprotected center pin can damage the LNA or PA output stage. Per IEC 61000-4-2, any user-accessible connector must withstand at least Level 2 contact discharge (4 kV) for consumer products. Semtech and other RF IC vendors offer low-capacitance TVS devices specifically designed for antenna port protection that add minimal insertion loss at sub-GHz frequencies. A device such as the Semtech SM712 or a low-capacitance unidirectional TVS rated for the 868 MHz band placed between J7 pin 1 and GND would provide system-level ESD protection without significantly degrading RF performance.

From an EMC perspective, the direct connection from U9 to J7 with no external harmonic filter means that any spurious emissions from the RFM95W transmitter will radiate directly from the antenna. The RFM95W module includes an internal low-pass filter, but its attenuation at the second and third harmonics may not be sufficient to meet ETSI EN 300 220-1 spurious emission limits, particularly at maximum transmit power (+20 dBm). A discrete low-pass filter or pi-network between U9 pin 9 and J7 would provide additional harmonic suppression.

AI-Assisted — Eight screw terminal connectors (J4, J5, J6, J8, J9, J10, J11, J13) provide connections for pyrotechnic firing circuits and battery power. These are Phoenix 1771091 two-position screw terminals designed for wire-to-board connections. In the intended application, these connectors will have external cable runs to pyrotechnic charges, battery packs, and deployment mechanisms. The cable lengths may be substantial (tens of centimeters to meters), making these wires effective antennas for both radiated emission pickup and ESD coupling.

J4 through J6 and J8 through J11 each connect one pin to the VBAT+_PYRO rail and the other pin to a pyrotechnic firing circuit output through a MOSFET drain and flyback diode. For example, J4 pin 1 connects to Net-(D2-A), which is the drain of Q2 (AO3400A N-channel MOSFET) through flyback diode D2 (US1M). J4 pin 2 connects to VBAT+_PYRO. The MOSFET gate drive circuits include 330 ohm series resistors (R19, R22, R25, R28, R31, R34) from the optocoupler outputs and 100 ohm gate-to-source resistors (R20, R23, R26, R29, R32, R35) as pull-downs. The optocouplers (U6, U7, U8, U11, U12, U13 — all TLP291) provide galvanic isolation between the MCU control signals and the pyrotechnic firing circuits.

J5 connects to Q4 (AO3401A P-channel MOSFET) drain, and J13 connects to Q5 (AO3401A) drain. These appear to be power switching outputs rather than pyrotechnic channels.

No TVS diodes, varistors, or transient suppression devices are present on any screw terminal connection. The VBAT+_PYRO rail has no overvoltage protection. The US1M flyback diodes (1000 V, 1 A) across the pyrotechnic loads provide inductive kickback clamping but do not protect against externally coupled ESD or surge events. Long cable runs to pyrotechnic charges in a field environment are subject to electrostatic charging (triboelectric effects from cable movement) and potentially to nearby lightning-induced transients. Per IEC 61000-4-2 and IEC 61000-4-5 (surge immunity), external wiring interfaces in industrial or field-deployed equipment require transient protection.

The optocoupler isolation (TLP291 devices with 80 V collector-emitter rating) provides a degree of protection for the MCU side, since the STM32F405 GPIO pins drive the optocoupler LED side through 1k series resistors (R37, R38 for UART, and the pyro drive resistors), and the phototransistor side is on the VBAT+_PYRO domain. However, the VBAT+_PYRO rail itself connects directly to the battery input and to the servo motor power pins (M1-M4 pin 2), with no filtering or protection between the screw terminals and the rail. A transient on any screw terminal propagates to all devices on VBAT+_PYRO.

AI-Assisted — J3 is a JST SH SM04B 4-position horizontal connector carrying a level-translated UART interface. Pin 1 connects to +5V, pin 2 connects to Net-(J3-Pin_2) which is the B1 output of level translator U16 (LSF0102DCUR) with two 1k pull-up resistors R40 and R41 to +5V, pin 3 connects to Net-(J3-Pin_3) which is the B2 output of U16 with one 1k pull-up R40 to +5V, and pin 4 connects to GND. This connector provides a 5 V logic-level UART interface for external peripherals.

J12 is a JST SH SM04B 4-position connector carrying UART5. Pin 1 connects to +5V, pin 2 connects to GND, pin 3 connects to UART5_RX (U1 pin PD2), and pin 4 connects to UART5_TX (U1 pin PC12). The UART5 signals connect directly to the STM32F405 GPIO pins with no series resistors and no ESD protection.

Both J3 and J12 are small-pitch JST connectors typically used for board-to-board or short-range internal wiring. If these connectors remain internal to an enclosure with short cable runs, the ESD risk is low and the absence of external protection is acceptable. However, if either connector is accessible to the end user or connects to cables that exit the enclosure, ESD protection would be needed. The UART5 lines on J12 are particularly exposed because they connect directly to STM32F405 GPIO pins with no series resistance to limit ESD current. J3 benefits from the LSF0102DCUR level translator U16, which provides some degree of isolation, and the 1k pull-up resistors R40/R41 add series impedance that helps limit ESD current.

AI-Assisted — J2 is a 1x04 2.54 mm vertical SMD pin header carrying the SWD debug interface. Pin 1 connects to +3.3V, pin 2 carries SWDIO (U1 pin PA13), pin 3 carries SWCLK (U1 pin PA14), and pin 4 connects to GND. This is an internal debug connector that is typically only used during development and production programming. No ESD protection is present, which is standard practice for internal debug headers. If this connector is accessible through the enclosure (for example, through a debug port opening), a low-capacitance TVS array would be appropriate, but for a sealed production unit this is acceptable.

AI-Assisted — Four servo motor connectors (M1, M2, M3, M4) use 1x03 2.54 mm pin headers with PWM signal, positive power, and ground connections. The PWM pins connect directly to STM32F405 GPIO pins: M1 pin 1 (PWM) to PC9 (SERVO4), M2 pin 1 to PC7 (SERVO2), M3 pin 1 to PC8 (SERVO3), M4 pin 1 to PC6 (SERVO1). The positive power pins (pin 2) connect to VBAT+_PYRO, and the ground pins (pin 3) connect to GND.

Servo motors contain DC motors with brushes that generate significant electrical noise during operation. The PWM signal lines from the STM32 connect directly to the servo connectors with no series filtering (no series resistors, no ferrite beads, no RC snubbers). Motor brush noise can couple back through the PWM line into the MCU GPIO, potentially causing EMI issues and corrupting adjacent analog or digital signals. The VBAT+_PYRO power connection to the servos also lacks any local decoupling or filtering at the connector, so motor current transients propagate directly onto the shared battery rail.

From an ESD perspective, servo connectors are external and will be handled by users during assembly. The direct GPIO connection to the STM32 with no series impedance means an ESD event on a servo PWM pin couples directly to the MCU. A series resistor (100 to 330 ohm) on each PWM line near the MCU would limit ESD current and also help filter high-frequency motor noise. The servo power and ground pins carry high transient currents during motor stall conditions, and the lack of any bulk capacitance or TVS protection at the connector means these transients propagate to the entire VBAT+_PYRO rail.

AI-Assisted — The SMA connector J7 outer conductor (pin 2, Ext) connects to GND. For proper RF performance and EMC, the ground connection from the SMA connector shell to the ground plane must be low-inductance. The schematic captures this connection correctly, but the implementation depends entirely on layout. Multiple ground vias directly adjacent to the SMA connector shell pads are essential to minimize the ground return inductance at 868 MHz. Any inductance in the ground path degrades the antenna match and increases common-mode radiation from the coaxial-to-microstrip transition. The edge-mount SMA footprint (Samtec SMA-J-P-H-ST-EM1) has ground tabs that must connect to a solid ground plane with minimal trace length.

AI-Assisted — The TPS563200 (U17) is a synchronous buck converter operating from the combined VBUS/VBAT+ input (through Schottky diodes D11 and D12) to produce the +5V rail. The switching node Net-(U17-SW) carries high dV/dt transitions that are the primary source of conducted and radiated emissions on this board. The input filter consists of three 10 uF ceramic capacitors (C15, C16, C17) on the Net-(D11-K) node. The output filter consists of inductor L2 (3.3 uH) and four output capacitors (three 22 uF ceramics C19, C20, C21 and one 10 uF tantalum C53) on the +5V rail.

The TPS563200 datasheet (SLVSCB0E, Rev E) recommends placing input capacitors as close as possible to the VIN and GND pins to minimize the hot loop area. The schematic shows adequate capacitance values, but the critical EMC performance depends on layout. The switching loop (VIN pin 3, SW pin 2, through L2, through output capacitors, back through input capacitors to GND pin 1) must be minimized in area.

No input common-mode choke or EMI filter is present between the USB VBUS input and the switching regulator. The USB cable acts as a transmission line for conducted emissions from the switching regulator. For EN 55032 Class B compliance, a common-mode choke on the VBUS line or a pi-filter (capacitor-ferrite-capacitor) between J1 VBUS pins and D12 would reduce conducted emissions propagating back through the USB cable. The current path from J1 VBUS through D12 to U17 VIN has only the Schottky diode as a series element, which provides no high-frequency filtering.

AI-Assisted — Several systemic EMC and ESD concerns span multiple connectors and subsystems.

First, no ESD protection devices exist anywhere in this design. There are no TVS diodes, no ESD protection arrays, and no varistors on any connector interface. Every external connector (J1, J4-J11, J13, J7, M1-M4) connects to active silicon (STM32F405, RFM95W, or MOSFET gates) with at most a series resistor as the only current-limiting element. For a product intended to meet IEC 61000-4-2 at any level, external ESD protection is needed on all user-accessible connector pins.

Second, the single-ground architecture means that an ESD event on any connector injects current into the same ground plane that serves all sensitive analog and digital circuits, including the VDDA supply for the STM32 ADC, the BMP388 pressure sensor (U3), the ICM-42688-P IMU (U10), and the ADXL375 accelerometer (U4). The ferrite bead FB1 (100 ohm) between +3.3V and +3.3VA provides some power supply isolation for the analog domain, but the ground return is shared. An ESD strike on J1 or any screw terminal will cause ground bounce across the entire board, potentially corrupting sensor readings or causing MCU latch-up.

Third, the 16 MHz crystal oscillator (ABM8-16Mhz-B2-T1) connects to U1 pins PH0 and PH1 with 26 pF load capacitors C12 and C13 to GND. The crystal traces are sensitive to EMI coupling. If the crystal is placed near the switching regulator or near any connector with long external cables, radiated emissions from the switching node or ESD-induced transients can couple into the oscillator circuit and cause clock jitter or frequency pulling.

Fourth, the ADXL375 accelerometer U4 has its VS (sensor supply) pin powered through a 33 ohm series resistor R16 from +3.3V, with two 10 uF tantalum capacitors C27 and C53 providing local decoupling. The SPI1 bus connecting U4, U10, and U1 has no series termination resistors, which is acceptable for short trace lengths but means that any EMI coupling onto the SPI1 traces (SCK, MOSI, MISO) can propagate to all three devices. The SPI1_MOSI net also connects to U2 (74AHC1G32 OR gate) pin 2, which feeds U4 SDA/SDI/SDIO through U2 pin 4. This OR gate insertion adds a propagation delay and a potential EMI emission point if the trace from U2 to U4 is long.

Fifth, the USB Type-C CC1 and CC2 pins have 5.1k pull-down resistors R3 and R4 to GND, which correctly identify this device as a USB Type-C sink per the USB Type-C specification. However, these pins are directly exposed to the connector with no ESD clamping. The CC pins are adjacent to VBUS pins in the Type-C connector, and a VBUS-to-CC short circuit event (caused by debris or connector damage) would apply up to 20 V (in USB PD scenarios, though this design does not implement PD) or 5 V (standard USB) directly to the CC pin, which connects through R3/R4 to GND. The 5.1k resistor limits current to approximately 1 mA at 5 V, which is safe for steady-state, but an ESD transient bypasses the resistor's current-limiting effect due to parasitic inductance at high frequencies.

AI-Assisted —

Connector	Finding	Risk
J1 (USB-C)	No ESD protection device on USB_D+ (PA12), USB_D- (PA11), CC1, or CC2 lines. ST AN4879 Rev 3 recommends an ESD protection device placed as close as possible to the USB connector. IEC 61000-4-2 Level 4 contact discharge (8 kV) exceeds STM32F405 internal HBM rating (2 kV per JESD22-A114D). In-field failure mode: USB transceiver damage or MCU latch-up during cable insertion.	High
J7 (SMA)	No ESD protection on the antenna center pin. When the antenna is disconnected, the exposed SMA center pin provides a direct ESD path to the RFM95W RF front end (U9 pin 9). In-field failure mode: LNA or PA damage from contact discharge per IEC 61000-4-2. A low-capacitance TVS rated for sub-GHz operation is appropriate.	High
J4, J6, J8-J11 (Screw Terminals)	No TVS or transient suppression on pyrotechnic firing circuit screw terminals. Long external cable runs act as antennas for ESD and surge coupling. Flyback diodes D2, D3, D5, D8, D9, D10 (US1M, 1000 V) clamp inductive kickback but do not protect against externally coupled transients. In-field failure mode: MOSFET gate oxide damage or VBAT+_PYRO rail corruption from ESD or surge per IEC 61000-4-2 and IEC 61000-4-5.	High
M1-M4 (Servo)	PWM signal lines (SERVO1-SERVO4) connect directly from STM32F405 GPIO (PC6, PC7, PC8, PC9) to servo connectors with no series resistors, no ferrite beads, and no ESD protection. Servo motors generate brush noise that couples back into the MCU. In-field failure mode: conducted emissions on servo cables, ESD damage to GPIO during connector handling, and EMI-induced sensor measurement errors from motor noise coupling into the shared ground plane.	High
All Connectors	No ESD protection devices (TVS diodes, ESD arrays, varistors) exist anywhere in the design. Every external connector interface relies solely on IC internal ESD structures, which are rated for component-level HBM (JESD22-A114D) but not for system-level IEC 61000-4-2 contact or air discharge. This is a systemic gap affecting all external interfaces.	High
J1 (USB-C)	Shell pin SH is on the logic GND net with no dedicated SHIELD_GND net. The schematic does not capture shield bonding strategy as design intent for the layout engineer. A dedicated net per the USB Type-C specification Section 3.2.1 and IEC 61000-4-2 best practices is needed to enable proper enclosure-dependent grounding (direct bond for plastic enclosure, R-parallel-C isolation for metal chassis).	Medium
J1 (USB-C)	No common-mode choke or EMI filter on VBUS between J1 and the TPS563200 buck regulator input. Conducted emissions from the switching regulator propagate back through the USB cable. Likely failure mode: EN 55032 Class B conducted emissions exceedance in the 500 kHz to 5 MHz range.	Medium
J1 (USB-C)	VBUS pins (A4, A9, B4, B9) are connected together on the VBUS rail and feed through Schottky diode D12 (SS14) to the power input. No TVS or overvoltage clamp on VBUS. A cable-side fault or hot-plug transient could exceed the SS14 reverse voltage rating (40 V) or damage downstream components. IEC 61000-4-5 surge immunity applies to power input ports.	Medium
J7 (SMA)	No external harmonic filter between U9 (RFM95W) and J7. Spurious emissions at second and third harmonics of 868 MHz may exceed ETSI EN 300 220-1 limits. In-field failure mode: radiated emissions test failure during type approval.	Medium
J5, J13 (Screw Terminals)	Power switching outputs through P-channel MOSFETs Q4 and Q5 (AO3401A). No transient protection on the output terminals. Same ESD and surge exposure as pyrotechnic channels.	Medium
M1-M4 (Servo)	Servo power pins connect to VBAT+_PYRO with no local decoupling capacitor at the connector. Motor stall current transients propagate to the shared battery rail affecting all pyrotechnic circuits and the main power input. In-field failure mode: ground bounce and supply droop causing spurious pyrotechnic firing or MCU brownout.	Medium
All Connectors	Single GND domain for all connectors, ICs, and analog circuits. No ground plane partitioning captured in the schematic. ESD current from any connector shares the return path with sensitive analog circuits (U1 VDDA, U3 BMP388, U10 ICM-42688-P, U4 ADXL375). In-field failure mode: sensor data corruption and MCU latch-up during ESD events per IEC 61000-4-2.	Medium
J3 (JST SH)	Level-translated UART interface through U16 (LSF0102DCUR) with 1k pull-up resistors R40/R41 to +5V. The level translator and series resistance provide some ESD current limiting. Acceptable for an internal connector with short cable runs. If externally accessible, TVS protection is needed per IEC 61000-4-2.	Low
J12 (JST SH)	UART5_RX (PD2) and UART5_TX (PC12) connect directly to STM32F405 GPIO with no series resistors and no ESD protection. Acceptable for an internal connector. If externally accessible, this is an ESD risk per IEC 61000-4-2.	Low
J1 (USB-C)	CC1 and CC2 pull-down resistors R3 (5.1k) and R4 (5.1k) to GND are correct per USB Type-C specification for a sink device. Verified against USB Type-C Cable and Connector Specification.	✓
J1 (USB-C)	SBU1 (A8) and SBU2 (B8) are intentionally unconnected, which is correct for USB 2.0 only operation per USB Type-C specification.	✓
J7 (SMA)	SMA outer conductor (J7 pin 2) is connected to GND, providing the RF ground return. Correct for a single-ended 50 ohm antenna interface.	✓
J4, J6, J8-J11 (Screw Terminals)	Optocoupler isolation (TLP291, U6-U8, U11-U13) between MCU GPIO and pyrotechnic MOSFET gates provides galvanic separation of the control domain from the firing domain. This is good practice for both safety and EMC.	✓
J2 (Pin Header)	SWD debug interface (SWDIO on PA13, SWCLK on PA14) with no ESD protection. Standard practice for internal debug headers. Acceptable if not accessible in the final product enclosure.	✓