cursus Design Analysis

AI-Assisted — The Cursus board is a single-sheet flight computer built around an STM32F405RGT6 microcontroller in LQFP-64. It integrates inertial sensing (ICM-42688-P six-axis IMU and ADXL375 high-g accelerometer), barometric pressure sensing (BMP388), 128 Mbit NOR flash (W25Q128JVSIQ), a LoRa radio module (RFM95W-868S2 at 868 MHz), six pyrotechnic firing channels, four servo outputs, USB-C for data/charging, a UART port level-shifted to 5 V, and a secondary UART on a JST connector. Power is derived from an external battery through a TPS563200 synchronous buck converter producing 5 V, followed by an AMS1117-3.3 linear regulator producing 3.3 V. A ferrite-filtered 3.3 VA rail supplies the MCU analog domain. The design contains 139 components across 100 nets.

Power Architecture

Input Power Path

External power enters through two paths that are OR-ed together at the node Net-(D11-K). A battery voltage (VBAT+) passes through a Schottky diode D11 (SS14, 40 V / 1 A), and USB VBUS passes through a second Schottky diode D12 (SS14). Three 10 µF ceramic capacitors (C15, C16, C17) decouple this combined input node. A 10 kΩ resistor R11 connects from this node to the enable pin of the TPS563200 (U17), providing a direct enable without a UVLO divider. This means the converter will attempt to start at any input voltage above its internal UVLO threshold, which may be undesirable if the battery voltage sags below the TPS563200 minimum operating input of 4.5 V. Adding a resistor divider from the input node to EN would allow a defined UVLO turn-on threshold to be set, preventing operation at marginal input voltages.

The VBAT+ rail also feeds two P-channel MOSFETs Q4 and Q5 (AO3401A) that switch the VBAT+_PYRO rail for pyrotechnic and servo power. Q4 gate is pulled to ground through R17 (10 kΩ), and Q5 gate is similarly pulled to ground through R18 (10 kΩ). With the gates pulled low and the source at VBAT+, both P-FETs are normally on. The MCU does not appear to have direct gate drive control of Q4 or Q5 from the schematic data; the gates connect only to their respective pull-down resistors. This means the pyrotechnic power rail is always energized whenever the battery is connected, which is a safety concern for a flight computer handling energetic devices. A series gate-drive resistor from an MCU GPIO would allow software-controlled arming.

5 V Buck Converter (U17, TPS563200)

The TPS563200 receives input from Net-(D11-K) on its VIN pin. The switch node connects through a 3.3 µH inductor L2 to the +5 V output rail. A 0.1 µF bootstrap capacitor connects between VBST and SW, matching the TI datasheet requirement exactly. Output capacitance on the +5 V rail consists of three 22 µF ceramic capacitors (C19, C20, C21) plus one 10 µF tantalum (C53), totaling approximately 76 µF. The TPS563200 datasheet (SLVSCB0 Rev E) recommends a minimum of 47 µF output capacitance for the D-CAP2 control loop; the design exceeds this comfortably.

The feedback divider uses R12 (54.9 kΩ, top) from +5 V and R13 (10 kΩ, bottom) to ground, with the midpoint connected to VFB. The calculated output voltage is 0.765 V × (1 + 54.9 k / 10 k) = 0.765 × 6.49 = 4.965 V. This is within approximately 0.7% of the 5.0 V target, which is acceptable given standard resistor tolerances. Using 1% tolerance resistors for R12 and R13 is important here, as the datasheet specifies.

The input decoupling on VIN (three 10 µF ceramics) is adequate. The TI datasheet recommends at least 10 µF ceramic input capacitance; 30 µF total provides margin for DC bias derating.

3.3 V LDO (U19, AMS1117-3.3)

The AMS1117-3.3 receives 5 V on its input and produces a fixed 3.3 V output. The dropout voltage is typically 1.1 V at 0.8 A, so the 1.7 V headroom from a 5 V input is sufficient. The output capacitor is a single 22 µF tantalum (C52). The AMS1117 datasheet requires an output capacitor of at least 22 µF with ESR not exceeding 0.5 Ω for stability; a single tantalum capacitor of this value satisfies the requirement, though the ESR of the specific tantalum part should be within the 0.5 Ω limit. The input side has the 10 µF tantalum C27 (which is actually on the ADXL375 VS rail based on net tracing) — looking more carefully, the AMS1117 input is the +5 V rail, which has the three 22 µF ceramics and one 10 µF tantalum already mentioned. The AMS1117 datasheet recommends a 10 µF input capacitor; the shared +5 V rail capacitance satisfies this.

The +3.3 V rail supplies the MCU (five VDD pins plus VBAT), the BMP388, the ICM-42688-P, the ADXL375 VDD_I/O, the W25Q128JVSIQ, the RFM95W, the LSF0102 low-side reference, the 74AHC1G32 logic gate, and the RGB LED anode. Total decoupling on the +3.3 V rail is twelve 0.1 µF, one 10 nF, two 10 µF ceramic, one 1 µF, one 2.2 µF, and one 22 µF tantalum — a generous distribution.

3.3 VA Analog Supply

The +3.3VA rail is derived from +3.3V through ferrite bead FB1 (100 Ω at the rated frequency). It is decoupled with one 0.01 µF and one 1 µF capacitor (C7, C8). This rail feeds only U1 pin 13 (VDDA). The STM32F405 datasheet (DS8626) and application note AN4488 recommend 1 µF + 10 nF (or 100 nF) on VDDA. The 1 µF from C8 is present; C7 at 0.01 µF (10 nF) satisfies the second requirement. The VSSA pin (pin 12) connects to ground. This filtering arrangement is consistent with ST's recommendations.

VCAP Pins

U1 pins 31 (VCAP_1) and 47 (VCAP_2) each have a 2.2 µF capacitor to ground (C51 and C11 respectively). The STM32F405 datasheet requires 2.2 µF on each VCAP pin for the internal 1.2 V core regulator. This is correctly implemented.

Microcontroller Configuration (U1, STM32F405RGT6)

Clock Source

A 16 MHz crystal (ABM8-16Mhz-B2-T1) connects between PH0 (HSE_IN, pin 5) and PH1 (HSE_OUT, pin 6) with 26 pF load capacitors C12 and C13 to ground. The STM32F405 datasheet specifies load capacitance values depending on the crystal; 26 pF is a plausible value for many 16 MHz crystals with a specified load capacitance of around 12–13 pF (accounting for stray capacitance). The specific crystal datasheet should be consulted to confirm the load capacitance match.

Boot Configuration

The BOOT0 pin (pin 60) connects through R2 (10 kΩ) to a slide switch S1 (JS102011JCQN). One terminal of S1 connects to ground, and the common terminal connects through R2 to BOOT0. The third terminal of S1 connects to +3.3V via the switch's routing. This allows selecting between system flash boot (BOOT0 low) and system memory boot (BOOT0 high) for DFU programming over USB. No pull-up or pull-down is present on BOOT0 itself beyond the switch path, so the switch position fully determines the boot mode.

Reset Circuit

NRST (pin 7) has a 10 kΩ pull-up R1 to +3.3V, a 0.1 µF capacitor C10 to ground for noise filtering, and a pushbutton SW2 to ground. This is a standard reset circuit consistent with ST recommendations.

Debug Interface

PA13 (SWDIO) and PA14 (SWCLK) connect to connector J2 pins 2 and 3 respectively. J2 is a 4-pin 2.54 mm vertical header. Pin 1 connects to +3.3V (target voltage reference) and pin 4 connects to ground. This provides a minimal SWD debug interface. No SWO trace pin is routed to the debug header.

USB Interface

PA11 (USB_D−) and PA12 (USB_D+) connect directly to the USB-C connector J1 on both the A-side and B-side differential pairs (A6/B6 for D+, A7/B7 for D−). The CC1 and CC2 pins each have a 5.1 kΩ pull-down resistor to ground (R3 on CC1, R4 on CC2), correctly identifying the device as a USB sink/device per the USB Type-C specification. The SBU1 and SBU2 pins are marked as designer no-connect, which is appropriate for a USB 2.0-only device. No ESD protection is visible on the USB data lines; adding a TVS diode array rated for USB 2.0 would improve robustness, particularly given the flight environment.

No series resistors are present on the USB D+ and D− lines. The STM32F405 has an integrated USB transceiver, and while many designs omit series resistors, a 22 Ω series resistor on each line is sometimes recommended for impedance matching. The STM32F405 datasheet does not strictly require them, but they can help with signal integrity.

SPI Bus Allocation

Two SPI buses are used. SPI1 (PA5/SCK, PA6/MISO, PA7/MOSI) serves the ICM-42688-P and the ADXL375, with separate chip selects ICM_CS (PC5) and ADXL_CS (PC4). SPI2 (PB10/SCK, PC2/MISO, PC3/MOSI) serves the W25Q128JVSIQ flash and the RFM95W LoRa module, with chip selects FLASH_CS (PC15) and LORA_CS (PC1).

I2C Bus

I2C1 (PB6/SCL, PB7/SDA) connects to the BMP388 pressure sensor. Pull-up resistors R14 and R15 (4.7 kΩ each) to +3.3V are present. For a 3.3 V bus at standard 100 kHz or fast 400 kHz mode, 4.7 kΩ is a standard and appropriate value.

Sensor Subsystem

ICM-42688-P (U10)

The six-axis IMU communicates over SPI1. Its VDDIO (pin 5) and VDD (pin 8) both connect to +3.3V. The INT1 output (pin 4) connects to MCU pin PB2 (ICM_INT1). Pins RESV_2, RESV_3, RESV_7, RESV_10, and RESV_11 are handled as follows: RESV_2 and RESV_3 are designer no-connect; RESV_7 and RESV_11 connect to ground; RESV_10 is designer no-connect. The ICM-42688-P datasheet (DS-000347 v1.6) states that RESV pins should be left unconnected. Connecting RESV_7 and RESV_11 to ground contradicts this requirement. These pins should be left floating (unconnected) per the manufacturer's instructions. INT2/FSYNC/CLKIN (pin 9) is marked as designer no-connect, which is acceptable if the secondary interrupt and FSYNC functions are not needed.

The ICM-42688-P datasheet recommends a 100 nF decoupling capacitor on VDD and a 100 nF capacitor on VDDIO, placed as close as possible to the respective pins. The +3.3V rail has ample 100 nF capacitors, but none are explicitly dedicated to U10 in the decoupling summary. The layout must place 100 nF capacitors immediately adjacent to U10 pins 5 and 8.

ADXL375 (U4)

The high-g accelerometer communicates over SPI1. Its VDD_I/O (pin 1) connects to +3.3V, and VS (pin 6) connects through a 33 Ω resistor R16 from +3.3V to a filtered node with two capacitors (C27, 10 µF tantalum, and C28, 0.1 µF) to ground. This RC filter on the analog supply is good practice for the ADXL375. The ADXL375 datasheet recommends a 0.1 µF capacitor on VS and a 10 µF tantalum on VS for optimal noise performance; both are present.

The SDA/SDI/SDIO pin (pin 13) does not connect directly to the SPI1_MOSI net. Instead, it connects through U2, a 74AHC1G32 single OR gate. The OR gate inputs are ADXL_CS (pin 1) and SPI1_MOSI (pin 2), with the output (pin 4) driving U4 pin 13. This is a known technique to implement SPI communication with the ADXL375 in 4-wire SPI mode: the OR gate ensures that the SDI line is held high when CS is deasserted, preventing the part from interpreting bus traffic intended for other devices on the shared MOSI line. This is correctly implemented.

The SDO/ALT_ADDRESS pin (pin 12) connects to SPI1_MISO, serving as the data output in SPI mode. The CS pin (pin 7) connects to ADXL_CS. INT1 (pin 8) and INT2 (pin 9) are both marked as designer no-connect. If interrupt-driven data acquisition is desired, at least INT1 should be routed to an MCU GPIO. For polled operation, leaving them unconnected is acceptable.

Pins 3, 10, and 11 (RESERVED and NC) are marked as designer no-connect, which is correct per the ADXL375 datasheet.

BMP388 (U3)

The barometric pressure sensor communicates over I2C1. VDDIO (pin 1) and VDD (pin 10) both connect to +3.3V. SDO (pin 5) connects to ground, setting the I2C address to 0x76. CSB (pin 6) connects to +3.3V, selecting I2C mode. INT (pin 7) is marked as designer no-connect; if interrupt-driven pressure readings are needed, this pin would need routing to an MCU GPIO. Three VSS pins (3, 8, 9) all connect to ground. The BMP388 datasheet recommends a 100 nF decoupling capacitor on both VDD and VDDIO; these are served by the +3.3V rail bulk decoupling, but dedicated capacitors placed close to U3 during layout are essential.

Flash Memory (U5, W25Q128JVSIQ)

The 128 Mbit NOR flash connects to SPI2. The /CS pin connects to FLASH_CS (PC15). The /WP (write protect, pin 3) and /HOLD/RESET (pin 7) pins are each pulled high to +3.3V through 10 kΩ resistors R5 and R6 respectively, keeping write protection disabled and the hold/reset function inactive during normal operation. VCC (pin 8) connects to +3.3V with decoupling from the rail. This is a straightforward and correct implementation.

LoRa Radio (U9, RFM95W-868S2)

The RFM95W-868S2 module connects to SPI2 with chip select LORA_CS (PC1). The RESET pin connects to MCU PC0 (LORA_RST). DIO0 connects to PA0 (LORA_DIO0) and DIO1 connects to PA1 (LORA_DIO1), providing interrupt capability for receive-done and timeout events. DIO2, DIO3, DIO4, and DIO5 are marked as designer no-connect; DIO0 and DIO1 are sufficient for basic LoRa operation.

The ANT pin (pin 9) connects to an SMA edge-mount connector J7 (Samtec SMA-J-P-H-ST-EM1). The antenna feed ground (J7 pin 2) connects to the ground plane. A 50 Ω matched trace from U9 pin 9 to J7 is required during layout. No matching network or filtering is shown between the module and the SMA connector; the RFM95W module includes an internal matching network, so direct connection to a 50 Ω antenna or feedline is appropriate.

The 3.3V supply pin (pin 13) connects to +3.3V. The RFM95W can draw up to approximately 120 mA during transmit at +20 dBm; the AMS1117-3.3 has sufficient current capacity, but the total 3.3 V rail load budget should be assessed to ensure the LDO does not exceed its thermal limits.

Pyrotechnic Firing Channels

Six pyrotechnic channels (PYRO1 through PYRO6) are implemented with an identical topology. Each channel consists of an MCU GPIO driving a current-limiting resistor into the LED side of a TLP291 optocoupler, with the phototransistor side switching an N-channel MOSFET (AO3400A) gate. The MOSFET drain connects through a US1M rectifier diode (for back-EMF clamping) to a screw terminal, and the source connects to ground. The screw terminal's other pin connects to VBAT+_PYRO, providing the firing current path through the pyrotechnic device.

The TLP291 optocoupler is noted by Toshiba as not recommended for new designs. The TLP291(SE is the current replacement with identical electrical specifications and should be substituted.

Taking PYRO1 as representative: MCU PB5 drives R19 (330 Ω) into U6 pin 1 (LED anode). U6 pin 2 (LED cathode) connects to ground. At 3.3 V with a typical 1.2 V LED forward drop, the LED current is approximately (3.3 − 1.2) / 330 = 6.4 mA, which is within the TLP291 rated forward current range. U6 pin 3 (collector) connects through R20 (100 Ω) to the gate of Q2 (AO3400A). U6 pin 4 (emitter) connects to VBAT+_PYRO. The gate of Q2 also has a 10 kΩ pull-down R21 to ground, ensuring the MOSFET remains off when the optocoupler is not conducting.

When the optocoupler conducts, the phototransistor pulls the gate toward VBAT+_PYRO through R20. The AO3400A has a gate threshold of typically 1.4 V and is fully enhanced at 4.5 V VGS. As long as VBAT+_PYRO exceeds approximately 2 V, the MOSFET will turn on. The 100 Ω series gate resistor limits gate charge current and provides some dV/dt immunity.

The US1M diodes (D2–D5, D8–D10) are rated at 1000 V / 1 A and serve as flyback clamps across the pyrotechnic load. Their cathodes connect to VBAT+_PYRO and their anodes connect to the respective MOSFET drain nodes. This clamps any inductive kickback from the pyrotechnic initiator wiring to one diode drop above VBAT+_PYRO.

The six channels map as follows: PYRO1 on PB5 through U6/Q2 to J4, PYRO2 on PB4 through U7/Q3 to J6, PYRO3 on PB3 through U8/Q6 to J8, PYRO4 on PC11 through U11/Q7 to J9, PYRO5 on PC10 through U12/Q8 to J10, PYRO6 on PA15 through U13/Q9 to J11.

As noted in the power architecture section, the VBAT+_PYRO rail is always energized when the battery is connected because Q4 and Q5 gates are simply pulled to ground. This is a significant safety concern: an unintended optocoupler activation or MOSFET gate noise could fire a pyrotechnic channel. A software-controlled arming switch (MCU GPIO driving Q4/Q5 gates through a resistor, with the pull-down providing the safe default) would add a critical safety layer.

Servo Outputs

Four servo channels connect MCU timer-capable pins (PC6, PC7, PC8, PC9) to 3-pin headers (M1–M4) for standard hobby servo connectors. The servo power pins connect to VBAT+_PYRO, and the ground pins connect to system ground. The PWM signal level is 3.3 V from the MCU. Most hobby servos accept 3.3 V logic levels, but some may require 5 V signaling. If 5 V servos are used, a level shifter on the PWM lines may be needed.

Level Translator (U16, LSF0102DCUR)

The LSF0102 bidirectional level translator bridges the USART1 TX and RX signals between the 3.3 V MCU domain and a 5 V domain. VREF_A (pin 2) connects to +3.3V (low side), and VREF_B (pin 7) connects to a filtered 5 V node through R39 (200 kΩ) from +5V with C33 (0.1 µF) to ground. The EN pin (pin 8) is tied to the same VREF_B node, enabling the translator when 5 V is present.

The A-side signals (A1, A2) connect to USART1_RX and USART1_TX respectively, each with a 1 kΩ series resistor (R38, R37) pulled up to +3.3V. The B-side signals (B1, B2) connect to JST connector J3 pins 2 and 3, with R40 and R41 (1 kΩ each) pulling up to +5V.

The LSF0102 datasheet states that VREF_A must be the lower voltage. With VREF_A at 3.3 V and VREF_B at 5 V, this requirement is met. The LSF0102 is a switch-based (not buffer-based) translator and requires pull-up resistors on both sides, which are present. The 1 kΩ pull-up values are appropriate for UART signaling at typical baud rates.

The 200 kΩ resistor R39 from +5V to VREF_B creates a very slow RC time constant with C33 (200 kΩ × 100 nF = 20 ms), which provides soft-start sequencing but also means VREF_B will be significantly below 5 V under any load. The LSF0102 VREF_B input current is negligible (leakage only), so the DC voltage should settle to approximately 5 V. However, the EN pin is also connected to this node, and the LSF0102 EN threshold is typically 0.7 × VREF_B. This should function correctly in steady state, but the slow ramp may cause the translator to be in an undefined state during power-up for approximately 60 ms (three time constants). During this period, the UART lines may glitch.

Buzzer Circuit

A piezoelectric buzzer LS1 (CMI-9705-0580-SMT-TR, 5 V rated) is driven through an NPN transistor Q1 (BC817). The MCU pin PC13 drives R10 (1 kΩ) into the base of Q1. The collector connects through diode D4 (US1M, cathode to +3.3V) to the buzzer negative terminal, and the buzzer positive terminal connects to +3.3V. When Q1 turns on, current flows from +3.3V through the buzzer, through Q1 to ground. D4 provides flyback protection.

The CMI-9705-0580-SMT-TR is rated for 5 V operation. Driving it from 3.3 V will produce reduced sound output. The datasheet specifies 80 dB SPL at 5 V; at 3.3 V the output will be noticeably lower. If adequate volume is required, the buzzer could be powered from the 5 V rail instead, with appropriate transistor and diode voltage ratings.

RGB LED (D1)

An ARGB LED D1 has its common anode connected to +3.3V. The red, green, and blue cathodes connect through series resistors R7 (91 Ω), R8 (24 Ω), and R9 (47 Ω) to MCU pins PB15 (LED_RED), PB14 (LED_GRN), and PB13 (LED_BLU) respectively. The MCU sinks current through the LED when the GPIO is driven low. The different resistor values compensate for the different forward voltage drops of the red, green, and blue dies to achieve approximate color balance. At 3.3 V with typical forward voltages of 2.0 V (red), 3.0 V (green), and 3.0 V (blue), the approximate currents are: red (3.3 − 2.0) / 91 = 14 mA, green (3.3 − 3.0) / 24 = 12.5 mA, blue (3.3 − 3.0) / 47 = 6.4 mA. These are within the STM32F405 GPIO sink capability of 25 mA per pin.

UART5

A secondary UART (UART5_TX on PC12, UART5_RX on PD2) connects to JST connector J12 (pins 4 and 3 respectively). J12 pin 1 provides +5V and pin 2 provides ground. This port operates at 3.3 V logic levels directly from the MCU, despite the connector carrying 5 V power. If the connected device transmits at 5 V logic levels, the MCU inputs could be damaged. The STM32F405 PD2 pin is 5 V tolerant (most Port D pins are), but this should be confirmed for the specific pin assignment. PC12 is also 5 V tolerant per the datasheet. The 5 V power on pin 1 is for powering the external device, not for signal levels.

Connector and Interface Summary

J1 is a USB-C 2.0 receptacle providing data connectivity and VBUS power input. J2 is a 4-pin SWD debug header. J3 is a JST SH 4-pin connector carrying the level-shifted UART1 at 5 V logic levels plus 5 V power and ground. J4 through J6 and J8 through J11 are screw terminals for pyrotechnic outputs. J7 is an SMA edge-mount connector for the LoRa antenna. J12 is a JST SH 4-pin connector for UART5 at 3.3 V logic with 5 V power. J13 is a screw terminal connected to Q5 drain, providing switched battery power output.

Unconnected Pins Review

The designer has intentionally left several MCU pins unconnected: PB9, PB8, PC14, PA3, PB11, PA2, PA4, PB0, PB12, PB1, and PA8. These are general-purpose I/O pins with no assigned function in this design. The STM32F405 datasheet recommends configuring unused GPIO pins as analog inputs (to minimize power consumption) or as outputs driven low. This is a firmware configuration matter and does not require schematic changes.

On the ICM-42688-P, RESV_2, RESV_3, and RESV_10 are correctly left unconnected. However, as noted above, RESV_7 (pin 7) and RESV_11 (pin 11) are connected to ground rather than left floating, which contradicts the datasheet instruction to leave RESV pins unconnected.

On the ADXL375, INT1 (pin 8) and INT2 (pin 9) are left unconnected. The ADXL375 datasheet states that unused interrupt pins may be left unconnected, so this is acceptable for polled operation.

On the RFM95W, DIO5 (pin 7), DIO3 (pin 11), DIO2 (pin 16), and DIO4 (pin 12) are left unconnected. These are optional diagnostic/status outputs and are not required for basic LoRa operation.

Key Observations and Recommendations

Pyrotechnic Safety: The VBAT+_PYRO rail has no software-controlled arming mechanism. Q4 and Q5 are always on when the battery is connected. Adding MCU-controlled gate drive to at least one of these P-FETs would provide an arming/disarming capability essential for safe handling of pyrotechnic devices.

ICM-42688-P Reserved Pins: Pins 7 (RESV_7) and 11 (RESV_11) are connected to ground. The ICM-42688-P datasheet (DS-000347 v1.6) specifies that all RESV pins must be left unconnected. These ground connections should be removed.

TLP291 End-of-Life Status: All six optocouplers (U6–U8, U11–U13) use the TLP291, which Toshiba has marked as not recommended for new designs. The TLP291(SE is the recommended replacement with identical specifications and footprint.

Buzzer Voltage: The CMI-9705-0580-SMT-TR buzzer is rated for 5 V but is powered from the 3.3 V rail, resulting in reduced acoustic output. Powering from 5 V would restore full rated performance.

Input UVLO: The TPS563200 EN pin is connected through a simple 10 kΩ resistor from the input voltage without a divider to ground. This provides no defined under-voltage lockout threshold. A resistor divider from the input to EN with the lower resistor to ground would establish a clean turn-on/turn-off threshold, preventing the converter from operating at input voltages below its minimum specification.

ESD Protection: No ESD protection devices are visible on the USB data lines, the SMA antenna port, or the external-facing screw terminals. For a flight computer subject to handling and environmental exposure, TVS protection on these interfaces would improve reliability.

Decoupling Placement: While the total decoupling capacitance on the +3.3V rail is generous, the BMP388 and ICM-42688-P do not have explicitly dedicated bypass capacitors visible in the decoupling summary. During layout, 100 nF capacitors must be placed immediately adjacent to the VDD and VDDIO pins of each sensor IC.

Level Translator Startup: The 200 kΩ / 100 nF RC on the LSF0102 VREF_B and EN creates a 20 ms time constant, potentially causing UART line glitches during power-up. If the connected device is sensitive to spurious characters during startup, reducing R39 to a lower value (e.g., 10 kΩ) would shorten the transition period while still providing sequencing.

Power Budget: The AMS1117-3.3 is rated for 1 A maximum output. The combined load of the STM32F405 (approximately 100 mA at full speed), RFM95W (up to 120 mA transmitting), ICM-42688-P (approximately 3 mA), ADXL375 (approximately 0.15 mA), BMP388 (approximately 0.7 mA), W25Q128JVSIQ (approximately 25 mA during erase), and miscellaneous pull-ups and LED current totals approximately 300–400 mA in worst case. This is within the LDO's capability, but the thermal dissipation at (5.0 − 3.3) × 0.4 = 0.68 W in a SOT-223 package requires adequate copper area for heat spreading. The SOT-223 tab is connected to VOUT, so the output copper plane serves as the heatsink.

AI-Assisted — The design is powered from two external sources. The first is a USB Type-C receptacle (J1) providing 5 V on the VBUS rail. The second is an external battery connected through screw terminals and P-channel MOSFET switches, supplying the VBAT+ and VBAT+_PYRO rails at a nominal 3.7 V.

VBUS from J1 and VBAT+ are OR-ed together through two Schottky diodes, D12 (SS14, from VBUS) and D11 (SS14, from VBAT+), onto the intermediate net Net-(D11-K). This OR-ed node feeds the input of U17, a TPS563200 synchronous buck converter, which steps the voltage down to produce the +5V rail. The +5V rail in turn feeds U19, an AMS1117-3.3 linear regulator, which produces the +3.3V rail. A ferrite bead FB1 (100 ohm) filters the +3.3V rail to create the +3.3VA analog supply for the STM32F405 VDDA pin.

The VBAT+_PYRO rail is a separate, unregulated battery rail that directly powers the collector sides of six TLP291 optocouplers (U6 through U8, U11 through U13), the servo motor power pins (M1 through M4), and the pyrotechnic firing circuits through screw terminals (J4, J6, J8 through J11). This rail is switched through P-channel MOSFETs Q4 and Q5 from VBAT+.

The power sequencing is straightforward: when either USB or battery voltage is present, the Schottky OR circuit passes the higher source (minus one diode drop) to U17. U17 starts when its EN pin is pulled high through R11 from the OR-ed input node. Once the +5V rail is established, U19 regulates it down to +3.3V, and the MCU and all digital peripherals power up. The VBAT+_PYRO rail is independently controlled by the MCU through the P-channel MOSFET gate drivers and is not sequenced with the digital supply.

AI-Assisted — U17 is a Texas Instruments TPS563200, a 3 A synchronous step-down converter in a SOT-23-6 package, operating in D-CAP2 mode with internal compensation. Per the TPS56x200 datasheet (SLVSCB0 Rev E), the operating input range is 4.5 V to 17 V, and the internal feedback reference voltage is 0.765 V.

The input to U17 pin VIN comes from the Schottky-OR node Net-(D11-K). When powered from USB (5 V nominal), the voltage at this node is approximately 5 V minus the SS14 forward drop (roughly 0.3 V to 0.45 V at light load), yielding approximately 4.55 V to 4.7 V. This is very close to the TPS563200 minimum operating input voltage of 4.5 V. Under load, the Schottky drop increases, and the input voltage could dip below the UVLO threshold. When powered from a single-cell LiPo battery (VBAT+), the nominal 3.7 V minus the diode drop yields approximately 3.25 V to 3.4 V, which is well below the 4.5 V minimum. The buck converter cannot regulate from a single LiPo cell through a Schottky diode. This is a significant concern if standalone battery operation is intended.

The input decoupling on Net-(D11-K) consists of three 10 uF ceramic capacitors (C15, C16, C17). The TPS563200 datasheet recommends a minimum of 10 uF ceramic input capacitance, so 30 uF total is adequate.

The output voltage is set by a resistor divider from the +5V rail to the VFB pin (pin 4). R12 (54.9 kohm) connects from +5V to VFB, and R13 (10 kohm) connects from VFB to GND. Using the pre-calculated ratio of 0.154 and the verified VREF of 0.765 V, the output voltage is 4.968 V. This is within acceptable tolerance of the 5 V target.

The bootstrap capacitor C18 (0.1 uF ceramic) is connected between the VBST pin (pin 6) and the SW pin (pin 2), matching the datasheet requirement of 0.1 uF.

The output inductor L2 is 3.3 uH in an 0805 package. The TPS563200 datasheet typical application for 5 V output at 3 A recommends a 3.3 uH inductor, so this value is correct. However, the 0805 footprint is very small for a power inductor carrying up to 3 A. Typical 0805 inductors are rated for saturation currents of 1.5 A to 2.5 A. The inductor must be rated for at least the peak current, which is the DC load current plus half the ripple current. At 3 A output with 3.3 uH and 650 kHz switching, the ripple current is modest, but the DC component alone may exceed the saturation rating of a standard 0805 inductor. The specific inductor part number and its saturation current rating should be selected carefully.

The output capacitance on the +5V rail consists of three 22 uF ceramic capacitors (C19, C20, C21) and one 10 uF tantalum capacitor (C53), totaling 76 uF nominal. The TPS563200 D-CAP2 topology requires output capacitors with sufficient ESR for stable operation. The datasheet recommends a minimum of 47 uF ceramic output capacitance for a 5 V output, so 66 uF ceramic plus 10 uF tantalum is adequate. The tantalum capacitor C53 adds beneficial ESR that aids D-CAP2 ripple injection.

The enable pin (EN, pin 5) is connected through R11 (10 kohm) to the input OR node Net-(D11-K). There is no resistor divider on EN to set a UVLO threshold — R11 simply pulls EN high whenever input voltage is present. The TPS563200 EN pin has an internal pull-down, so the device will enable as soon as the input voltage rises above the internal UVLO. If a defined start-up threshold is desired (for example, to prevent operation below 4.5 V from a depleted battery), a resistor divider on EN would be appropriate.

The TPS563200 does not have a power-good output pin, so there is no sequencing signal available to downstream regulators or the MCU from this stage.

AI-Assisted — U19 is an AMS1117-3.3, a fixed 3.3 V output LDO regulator rated for 1 A output current. Per the AMS1117 datasheet (ds1117.pdf, Advanced Monolithic Systems), the typical dropout voltage is 1.1 V at 0.8 A, with a maximum of 1.3 V. The absolute maximum input voltage is 15 V.

The input pin VI (pin 3) is connected to the +5V rail. With a nominal 4.97 V input and 3.3 V output, the headroom is approximately 1.67 V, which comfortably exceeds the 1.3 V maximum dropout. This ensures regulation across the full load range.

The AMS1117 datasheet specifies that the output capacitor is critical for stability and requires a minimum of 22 uF tantalum with ESR not exceeding 0.5 ohm. On the +3.3V rail, the total capacitance is substantial: twelve 0.1 uF ceramics, one 10 nF ceramic, two 10 uF ceramics, one 1 uF ceramic, one 2.2 uF ceramic, and one 22 uF tantalum (C52). The 22 uF tantalum C52 satisfies the stability requirement, as tantalum capacitors in the EIA-3216 (Kemet A) size typically have ESR in the range of 0.5 to 3 ohm, which is within the AMS1117 stable ESR window. The large number of low-ESR ceramic capacitors in parallel could reduce the effective ESR below the minimum needed for stability. The AMS1117 is known to oscillate when the output ESR is too low. The tantalum capacitor C52 should be placed closest to the output pin to dominate the ESR seen by the regulator. During layout, care must be taken to ensure the tantalum is the primary capacitor at the regulator output, with the distributed ceramics further away near their respective loads.

The AMS1117 datasheet also recommends a 10 uF input capacitor. On the +5V rail, there is ample input capacitance (three 22 uF ceramics and one 10 uF tantalum), so this requirement is met.

The +3.3V rail powers a significant number of devices: the STM32F405 MCU (U1), ICM-42688-P IMU (U10), BMP388 barometric sensor (U3), ADXL375 high-g accelerometer (U4), W25Q128JVSIQ flash memory (U5), RFM95W LoRa transceiver (U9), LSF0102 level translator (U16), 74AHC1G32 OR gate (U2), an RGB LED (D1), a buzzer driver, and various pull-up resistors. The total current draw depends on the operating mode, but the RFM95W alone can draw up to 120 mA during transmit, the STM32F405 draws up to 100 mA at full speed, and the remaining sensors and peripherals add perhaps 20 to 50 mA. The total is likely in the range of 250 to 400 mA under worst-case conditions, well within the 1 A rating of the AMS1117.

The AMS1117 has a minimum load current requirement of 5 mA (typical) to 10 mA (maximum). Given the number of always-on peripherals on the +3.3V rail, this minimum is easily met.

The AMS1117-3.3 is a fixed-output device with no external feedback pin. The output voltage is internally trimmed to 3.3 V with a tolerance of plus or minus 2% (3.234 V to 3.366 V per the datasheet).

AI-Assisted — The +3.3VA rail is derived from the +3.3V rail through ferrite bead FB1 (100 ohm at 100 MHz). This filtered rail supplies only the VDDA pin (pin 13) of the STM32F405 MCU. The decoupling on the +3.3VA side consists of one 0.01 uF ceramic (C7) and one 1 uF ceramic (C8).

The STM32F405 datasheet (DS8626) and hardware development application note AN4488 Rev 7 specify that VDDA requires a 1 uF capacitor and a 10 nF (0.01 uF) capacitor, plus a ferrite bead to isolate the analog supply from digital noise. The schematic provides exactly this: C8 (1 uF) and C7 (0.01 uF) on the +3.3VA side of FB1. This meets the ST recommendation.

The VSSA pin (pin 12) is connected to GND, which is correct. The STM32F405 datasheet requires VSSA to be connected to the same ground as VSS.

AI-Assisted — The STM32F405RGT6 in the LQFP-64 package has five VDD pins (pins 1, 19, 32, 48, 64), one VDDA pin (pin 13), three ground pins (pins 12, 18, 63), and two VCAP pins (pins 31 and 47).

The total decoupling on the +3.3V rail shared with U1 includes twelve 0.1 uF ceramics, one 10 nF ceramic, two 10 uF ceramics, one 1 uF ceramic, one 2.2 uF ceramic, and one 22 uF tantalum. This is shared across all devices on the rail, but the quantity is generous. The STM32F405 datasheet and AN4488 recommend one 100 nF ceramic per VDD pin (five total) plus one 4.7 uF bulk capacitor. With twelve 0.1 uF ceramics on the rail and two 10 uF ceramics, this requirement is well exceeded, provided the layout places at least one 0.1 uF capacitor adjacent to each VDD pin.

The VCAP_1 pin (pin 31) has a 2.2 uF ceramic capacitor (C51) to GND, and VCAP_2 pin (pin 47) has a 2.2 uF ceramic capacitor (C11) to GND. The STM32F405 datasheet specifies 2.2 uF capacitors on each VCAP pin for the internal 1.2 V core voltage regulator. This is correctly implemented.

The VBAT pin (pin 1) is connected directly to +3.3V. This is acceptable when no battery backup is needed for the RTC or backup SRAM — the VBAT pin is simply powered from the main supply. The datasheet recommends a 100 nF decoupling capacitor close to VBAT, which is available from the shared rail capacitors but should be confirmed during layout.

AI-Assisted — The USB VBUS and battery VBAT+ rails are OR-ed through two SS14 Schottky diodes (D11 from VBAT+, D12 from VBUS) onto the common input node Net-(D11-K). The SS14 is rated for 40 V reverse voltage and 1 A average forward current. At the expected load currents (up to 1 A for the entire board including servos on a separate rail), the SS14 is adequate for the digital supply path.

The USB Type-C connector J1 has CC1 and CC2 pins connected through 5.1 kohm resistors (R3, R4) to GND. This correctly identifies the board as a USB Type-C sink device requesting default USB power (5 V, up to 900 mA for USB 3.x or 500 mA for USB 2.0). There is no USB PD controller, so the board operates at the default 5 V VBUS level only.

The SBU1 (pin A8) and SBU2 (pin B8) pins on J1 are unconnected in the schematic, which is correct for a USB 2.0-only application — these pins are used only for USB Alternate Modes.

The VBAT+_PYRO rail is switched from VBAT+ through P-channel MOSFETs Q4 and Q5 (AO3401A, rated -4.0 A, -30 V). Q4 switches power to screw terminal J5, and Q5 switches power to screw terminal J13. The gates of Q4 and Q5 are pulled to GND through R17 and R18 (10 kohm each), keeping the MOSFETs on by default when VBAT+ is present (since the source is at VBAT+ and the gate is at GND, VGS is negative, turning on the P-FET). This means the pyrotechnic and servo power is always on when the battery is connected. The MCU does not appear to have direct gate control of Q4 and Q5 — the gate nets Net-(Q4-G) and Net-(Q5-G) connect only to the MOSFET gate and the pull-down resistor. If the intent is for the MCU to control these switches, a drive signal is missing. If the intent is always-on battery distribution, the current design is functional but offers no software-controlled power gating.

The pyrotechnic firing channels use N-channel MOSFETs (Q2, Q3, Q6 through Q9, AO3400A) driven by the MCU through optocouplers (U6 through U8, U11 through U13, TLP291). Each optocoupler LED side is driven from an MCU GPIO through a 330 ohm series resistor (R19, R22, R25, R28, R31, R34) and a 100 ohm resistor (R20, R23, R26, R29, R32, R35). The phototransistor output side switches the N-FET gate. Each N-FET gate has a 10 kohm pull-down to GND (R21, R24, R27, R30, R33, R36) to ensure the FET is off when the optocoupler is not driven. The TLP291 optocouplers are noted by Toshiba as not recommended for new designs; a replacement such as the TLP291(SE or an equivalent from another manufacturer should be considered for production longevity.

AI-Assisted — U16 (LSF0102DCUR) is a dual bidirectional level translator from Texas Instruments. Its VREF_A pin (pin 2) is connected to +3.3V, and its VREF_B pin (pin 7) is connected to the net Net-(U16-VREF_B), which is supplied through R39 (200 kohm) from the +5V rail with a 0.1 uF decoupling capacitor C33 to GND. The EN pin (pin 8) is tied to the same net as VREF_B.

Per the LSF0102 datasheet (TI, Rev B), VREF_A must be the lower voltage reference. With VREF_A at 3.3 V and VREF_B at 5 V, this condition is satisfied. The A-side channels (A1, A2) connect to the MCU USART1_RX and USART1_TX signals through 1 kohm series resistors (R38, R37), and the B-side channels (B1, B2) connect to the external JST connector J3.

The VREF_B supply through R39 (200 kohm) from +5V is unusual. With the EN pin also connected to this node, the LSF0102 EN threshold is typically 0.7 times VREF_B. The 200 kohm resistor combined with the 0.1 uF capacitor creates a slow RC time constant of 20 ms, which means the level translator will enable slowly after the +5V rail comes up. The steady-state voltage at VREF_B depends on the current drawn by the VREF_B pin and EN pin. The LSF0102 VREF_B input current is very low (leakage level), so the voltage should be close to 5 V in steady state. However, the high impedance makes this node susceptible to noise coupling. A lower-value resistor or a direct connection to +5V would provide a more robust supply.

AI-Assisted — The power architecture is a simple two-stage design suitable for a rocketry flight computer or similar embedded application. The primary concern is the input voltage margin for the TPS563200 when operating from a single-cell LiPo battery through the Schottky diode. A fully charged LiPo cell at 4.2 V minus the SS14 diode drop of approximately 0.35 V yields about 3.85 V at the buck converter input, which is below the 4.5 V minimum operating voltage. The converter will not regulate under battery-only operation unless the battery voltage is at least approximately 4.85 V (requiring a 2S configuration or a boost stage). If single-cell LiPo operation is intended, the power architecture needs revision — either replacing the buck with a buck-boost converter or eliminating the Schottky diode in favor of an ideal diode controller.

The thermal dissipation in U19 (AMS1117-3.3) is modest. With a 5 V input and 3.3 V output at an estimated 300 mA load, the power dissipation is (5.0 - 3.3) x 0.3 = 0.51 W. The SOT-223 package can handle this, but adequate copper area on the output tab pad is needed for heat spreading.

The design has no dedicated power-good or voltage monitoring signals. Neither U17 nor U19 provides a power-good output. The MCU has no way to detect if the supply rails are within regulation. For a flight-critical application, adding voltage monitoring (even a simple ADC channel with a resistor divider) on the +5V or battery rail would improve system robustness.

The ADXL375 VS pin (U4 pin 6) is supplied through R16 (33 ohm) from +3.3V, with two decoupling capacitors C27 (10 uF tantalum) and C28 (0.1 uF ceramic) to GND. The ADXL375 datasheet (Rev B, Analog Devices) specifies VS as the analog supply voltage pin requiring decoupling. The 33 ohm series resistor provides additional filtering, forming an RC low-pass with the 10 uF capacitor (time constant approximately 330 us, cutoff around 480 Hz). This is a reasonable analog supply filter for a vibration sensor.

The servo motors (M1 through M4) are powered directly from VBAT+_PYRO with no local decoupling capacitors visible on that rail near the servo connectors. Servo motors can draw significant transient currents (up to 1 A per servo during stall), and the lack of bulk capacitance on the VBAT+_PYRO rail near the servo headers could cause voltage dips that affect the pyrotechnic firing circuits sharing the same rail. Adding bulk capacitance near the servo connectors is recommended.

AI-Assisted —

Device	Rail	Observation	Severity
U17 (TPS563200)	Net-(D11-K)	Input voltage from single-cell LiPo (3.7 V nominal) through SS14 Schottky diode yields approximately 3.25 V to 3.85 V at VIN, below the 4.5 V minimum operating voltage specified in the TPS56x200 datasheet. The converter cannot regulate under battery-only operation from a single LiPo cell.	High
L2	+5V	Output inductor is 3.3 uH in 0805 footprint. Value matches datasheet recommendation, but 0805 package inductors typically saturate at 1.5 to 2.5 A, below the 3 A maximum output current rating of the TPS563200.	Medium
U19 (AMS1117-3.3)	+3.3V	Output capacitor C52 (22 uF tantalum, Kemet A case) satisfies the datasheet requirement of 22 uF tantalum with ESR not exceeding 0.5 ohm. However, twelve parallel 0.1 uF ceramics on the same rail reduce effective ESR significantly. The tantalum must be placed closest to the regulator output pin during layout to ensure the AMS1117 sees adequate ESR for stability.	Medium
Q4, Q5 (AO3401A)	VBAT+_PYRO	P-channel MOSFET gates are pulled to GND through 10 kohm resistors (R17, R18) with no MCU drive signal connected. MOSFETs are always on when VBAT+ is present. If software-controlled power gating of the pyrotechnic rail is intended, a drive path from the MCU is missing.	Medium
M1-M4 (Servos)	VBAT+_PYRO	Servo motors share the VBAT+_PYRO rail with pyrotechnic firing circuits. No bulk decoupling capacitors are visible on this rail. Servo transient currents could cause voltage dips affecting pyrotechnic channel reliability.	Medium
U17 (TPS563200)	EN	Enable pin connected through R11 (10 kohm) to input node with no resistor divider for UVLO threshold setting. Device enables at any input voltage above internal UVLO. No controlled start-up threshold.	Low
U6-U8, U11-U13 (TLP291)	VBAT+_PYRO	The TLP291 is marked by Toshiba as not recommended for new designs. The TLP291(SE or an alternative optocoupler should be selected for long-term availability.	Low
U16 (LSF0102DCUR)	VREF_B	VREF_B supplied through R39 (200 kohm) from +5V with 0.1 uF capacitor C33. The 200 kohm source impedance creates a 20 ms RC time constant and high noise susceptibility. A lower-value resistor would improve robustness. Per TI LSF0102 datasheet Rev B, VREF_A (3.3 V) is correctly the lower reference.	Low
General	All rails	No power-good or voltage monitoring signals exist in the design. Neither U17 nor U19 has a power-good output, and no ADC-based rail monitoring is implemented. For a flight-critical application, this limits fault detection capability.	Low
U17 (TPS563200)	+5V	Output voltage set to 4.97 V by R12 (54.9 kohm) / R13 (10 kohm) divider with 0.765 V reference (TPS56x200 datasheet SLVSCB0 Rev E). Within acceptable tolerance of 5 V target.	✓
U17 (TPS563200)	Net-(D11-K)	Input decoupling consists of three 10 uF ceramic capacitors (C15, C16, C17) totaling 30 uF. Datasheet recommends minimum 10 uF ceramic. Adequate.	✓
U17 (TPS563200)	+5V	Output capacitance is three 22 uF ceramics (C19, C20, C21) plus one 10 uF tantalum (C53), totaling 76 uF. Datasheet recommends minimum 47 uF ceramic for 5 V output. Adequate.	✓
U17 (TPS563200)	VBST	Bootstrap capacitor C18 is 0.1 uF ceramic between VBST and SW. Matches datasheet requirement.	✓
U19 (AMS1117-3.3)	+3.3V	Fixed 3.3 V output with 5 V input provides 1.67 V headroom, exceeding the 1.3 V maximum dropout at 0.8 A (AMS1117 datasheet ds1117.pdf). Adequate margin.	✓
U19 (AMS1117-3.3)	+5V input	Input capacitance on +5V rail (three 22 uF ceramics plus one 10 uF tantalum) exceeds the 10 uF minimum input capacitor recommendation. Adequate.	✓
FB1	+3.3VA	100 ohm ferrite bead with 1 uF (C8) and 0.01 uF (C7) decoupling on the analog side matches STM32F405 AN4488 Rev 7 recommendation for VDDA filtering.	✓
U1 (STM32F405)	VCAP_1 / VCAP_2	Each VCAP pin has a 2.2 uF ceramic capacitor (C51, C11) to GND, matching the STM32F405 datasheet DS8626 requirement.	✓
U1 (STM32F405)	VBAT	VBAT pin (pin 1) connected directly to +3.3V. Acceptable when RTC battery backup is not required. Per AN4488, a 100 nF capacitor should be placed close to this pin during layout.	✓
D11, D12 (SS14)	Net-(D11-K)	Schottky OR-ing diodes rated 40 V, 1 A. Adequate for the digital supply path current. Forward voltage drop reduces available headroom for U17 from low-voltage sources.	✓
R3, R4 (5.1 kohm)	CC1, CC2	USB Type-C CC pull-down resistors are 5.1 kohm to GND, correctly identifying the board as a default-power sink per USB Type-C specification Rev 2.0.	✓

AI-Assisted —

References
AMS1117-3.3 (Advanced Monolithic Systems) — AMS1117 datasheet, Advanced Monolithic Systems, ds1117.pdf www.advanced-monolithic.com/pdf/ds1117.pdf
TPS563200 (Texas Instruments) — TPS56x200 datasheet, SLVSCB0, Rev E, TI.com www.ti.com/lit/ds/symlink/tps562200.pdf

AI-Assisted — The design implements a USB 2.0 Full-Speed interface between the STM32F405RGTx (U1) and a 16-pin USB Type-C receptacle (J1). U1 pins PA11 and PA12 carry the USB_D- and USB_D+ signals respectively, connecting directly to J1 pins A7/B7 (D-) and A6/B6 (D+). Both D- pins on the connector are tied together on net USB_D-, and both D+ pins are tied together on net USB_D+, which is the correct wiring for a USB 2.0-only Type-C receptacle where the connector orientation is handled by the CC logic.

The STM32F405 OTG_FS peripheral includes an internal Full-Speed PHY with integrated impedance matching on the driver outputs. Per ST application note AN4879, the FS impedance driver is managed internally, so no external series termination resistors are required on the D+/D- lines. The direct connection from U1 to J1 without series resistors is therefore correct for this interface. The USB 2.0 Full-Speed specification requires 90 ohm differential impedance on the PCB traces. No impedance class assignment is visible in the schematic; during layout, the USB_D+ and USB_D- traces must be routed as a 90 ohm differential pair with length matching.

The CC1 pin (J1 A5) is connected through R3 (5.1 kohm) to GND, and CC2 pin (J1 B5) is connected through R4 (5.1 kohm) to GND. These 5.1 kohm pull-downs correctly identify the port as a USB Type-C Upstream Facing Port (UFP/device), per the USB Type-C specification. No active CC controller is present, which is acceptable for a device-only USB 2.0 implementation.

The SBU1 (J1 pin A8) and SBU2 (J1 pin B8) pins are intentionally unconnected in the schematic, which is correct for a USB 2.0-only design that does not implement Alternate Mode or USB Power Delivery communication.

AI-Assisted — The RFM95W-868S2 LoRa transceiver module (U9) connects its ANT pin (pin 9) directly to the SMA edge-mount connector J7 (Samtec SMA-J-P-H-ST-EM1) pin 1 via net Net-(J7-In). The SMA connector ground (J7 pin 2) is tied to GND. This is a single-ended 50 ohm RF path operating at 868 MHz (per the module part number suffix). The SMA connector is an appropriate choice for sub-GHz RF connections, providing a well-characterized 50 ohm impedance-controlled interface.

The trace from U9 pin 9 to J7 must be routed as a 50 ohm single-ended controlled-impedance microstrip or coplanar waveguide. At 868 MHz, even short trace length mismatches or impedance discontinuities can cause meaningful return loss. No matching network components are present between U9 and J7; the RFM95W module includes an internal matching network, so the PCB trace should present a clean 50 ohm path to the SMA connector. The three GND pins on U9 (pins 1, 8, 10) are all connected to GND, providing adequate ground return for the RF section.

The RFM95W 3.3V power pin (pin 13) is connected to the +3.3V rail. The module shares the same decoupling capacitors as the rest of the +3.3V rail. For optimal RF performance, the 3.3V supply to U9 should have local decoupling placed as close as possible to pin 13 during layout.

AI-Assisted — This design contains only two interfaces that warrant high-speed or RF signal integrity consideration: the USB 2.0 Full-Speed link and the 868 MHz LoRa RF path. There are no multi-gigabit SerDes lanes, no differential high-speed clocks, and no MIPI or PCIe interfaces.

The USB interface is Full-Speed only (12 Mbit/s), which is relatively forgiving of trace impedance variations compared to High-Speed USB. Nevertheless, the 90 ohm differential impedance target should be maintained during layout to pass USB compliance testing. The absence of ESD protection on the USB data lines is the most significant signal integrity risk for the USB interface.

The LoRa RF path is straightforward with a direct module-to-SMA connection. The primary layout concern is maintaining 50 ohm impedance on the ANT trace and minimizing its length. No AC coupling is required on this path as the RFM95W module handles DC biasing internally.

AI-Assisted —

Interface	Protocol	Finding	Severity
USB 2.0 FS (J1 to U1)	USB 2.0 Full-Speed	No ESD protection device on USB D+/D- lines. AN4879 recommends a TVS array (e.g. USBLC6) placed close to the receptacle for compliance and reliability.	Medium
USB 2.0 FS (J1 to U1)	USB 2.0 Full-Speed	PA9 (native VBUS sensing pin per DS8626) is used for USART1_RX. No VBUS sense path exists to U1. If the board operates independently of USB power, firmware cannot detect host attach/detach. Either reassign a GPIO for VBUS sensing via a resistor divider, or disable VBUS sensing in the USB HAL if the device is always bus-powered.	Medium
USB 2.0 FS (J1 to U1)	USB 2.0 Full-Speed	Layout must route USB_D+ and USB_D- as a 90 ohm differential pair. No impedance class assignment is visible at the schematic level — this is a layout-phase requirement.	Low
USB 2.0 FS (J1 to U1)	USB 2.0 Full-Speed	D+/D- direct connection from U1 PA11/PA12 to J1 without external series resistors is correct per AN4879 — the STM32F405 internal FS PHY manages driver impedance.	✓
USB 2.0 FS (J1 to U1)	USB 2.0 Full-Speed	CC1 (R3, 5.1 kohm to GND) and CC2 (R4, 5.1 kohm to GND) correctly identify the port as a Type-C UFP device per USB Type-C specification.	✓
USB 2.0 FS (J1 to U1)	USB 2.0 Full-Speed	SBU1 and SBU2 intentionally unconnected — correct for USB 2.0-only without Alternate Mode.	✓
USB Type-C (J1)	USB Type-C	16-pin USB 2.0-only Type-C receptacle is appropriate for the Full-Speed interface. D+ and D- pins from both connector orientations (A-side and B-side) are correctly tied together.	✓
LoRa 868 MHz (U9 to J7)	LoRa / SX1276	ANT pin (U9 pin 9) connects directly to SMA connector J7 with no intervening components. RFM95W internal matching network handles impedance transformation; PCB trace must be 50 ohm controlled impedance.	✓
LoRa 868 MHz (U9 to J7)	LoRa / SX1276	SMA edge-mount connector (Samtec SMA-J-P-H-ST-EM1) is an appropriate connector for sub-GHz RF, providing a well-defined 50 ohm interface.	✓
LoRa 868 MHz (U9 to J7)	LoRa / SX1276	U9 GND pins (1, 8, 10) all connected to GND — adequate ground return for RF section.	✓

AI-Assisted — The design contains a single memory device: U5, a Winbond W25Q128JVSIQ 128 Mbit (16M x 8) NOR flash in an 8-pin SOIC package, powered from the +3.3V rail. The W25Q128JVSIQ operates on a 2.7 V to 3.6 V supply, so the 3.3 V rail is within specification. VCC (pin 8) connects to +3.3V and GND (pin 4) connects to ground. A single 0.1 uF ceramic capacitor is expected near VCC; the +3.3V rail carries twelve 0.1 uF ceramics, one 10 nF ceramic, two 10 uF ceramics, one 1 uF ceramic, one 2.2 uF ceramic, and one 22 uF tantalum shared across all 3.3 V consumers. No dedicated per-device bypass capacitor is explicitly identifiable for U5 alone from the schematic, but the rail is well-decoupled overall. During layout, a 0.1 uF ceramic should be placed as close as possible to U5 pin 8.

The flash is wired for Quad SPI (4-bit) operation. All four data lines are connected: IO0 (DI, pin 5) is on net SPI2_MISO, IO1 (DO, pin 2) is on net SPI2_MOSI, IO2 (/WP, pin 3) is on net Net-(U5-{slash}WP(IO2)), and IO3 (/HOLD/RESET, pin 7) is on net Net-(U5-{slash}HOLD{slash}RESET(IO3)). The clock line CLK (pin 6) is on net SPI2_SCK, and chip select /CS (pin 1) is on net FLASH_CS driven by U1 pin PC15. The SPI2 bus is shared with the LoRa transceiver U9 (RFM95W-868S2), which also connects to SPI2_SCK, SPI2_MOSI, and SPI2_MISO. Each device has an independent chip select (FLASH_CS for U5, LORA_CS for U9), so bus contention is avoided when firmware correctly manages the select lines.

The /WP (IO2) pin is pulled high to +3.3V through R5 (10 kohm), and the /HOLD/RESET (IO3) pin is pulled high to +3.3V through R6 (10 kohm). Per the Winbond W25Q128JV datasheet, when the Quad Enable (QE) bit in Status Register-2 is set, /WP becomes IO2 and /HOLD becomes IO3, disabling their special functions. The pull-ups on these lines ensure that in standard SPI mode (before QE is set), write protection is inactive (/WP high) and the device is not held (/HOLD high). This is correct practice. The W25Q128JVSIQ part number suffix "IQ" indicates the QE bit is factory-set to 1, meaning Quad mode is available immediately after power-up without firmware needing to write the status register.

The /CS pin does not have a dedicated external pull-up resistor. The Winbond datasheet states that /CS must track VCC on power-up and recommends a pull-up resistor on /CS if desired. Since /CS is directly driven by the STM32F405 GPIO (PC15), the pin will be in a high-impedance state during MCU reset until firmware configures it. During this interval, /CS floats, which could cause the flash to accept spurious commands. Adding a 10 kohm pull-up resistor from FLASH_CS to +3.3V is recommended to keep the flash deselected during power-up and MCU reset.

No series resistors are present on any of the SPI2 data or clock lines. The W25Q128JVSIQ supports SPI clock frequencies up to 133 MHz. The STM32F405 SPI2 peripheral is clocked from APB1 (up to 42 MHz), so the maximum achievable SPI clock is 42 MHz with a prescaler of 1. At these frequencies on short PCB traces, series resistors are not strictly required, but 33 ohm series resistors on CLK and data lines can improve signal integrity and reduce EMI if trace lengths exceed approximately 2 to 3 cm. This is a layout-dependent consideration.

The SPI2 bus is operated in standard full-duplex SPI mode from the STM32 side (MOSI on PC3, MISO on PC2, SCK on PB10). For Quad SPI operation, the STM32F405 does not have a dedicated QSPI peripheral; Quad mode would need to be bit-banged or managed through software-controlled GPIO toggling of the IO2 and IO3 lines after issuing Quad-mode commands via SPI2. This limits practical Quad throughput. If only standard or Dual SPI is used, IO2 and IO3 remain in their default /WP and /HOLD roles, and the pull-ups on R5 and R6 keep them properly deasserted.

AI-Assisted — The design has no DDR, SDRAM, SRAM, or NVRAM interfaces. The only memory device is the W25Q128JVSIQ QSPI NOR flash (U5). The memory architecture is minimal and appropriate for the STM32F405RGT6 microcontroller, which has 1 MB of internal flash and 192 KB of internal SRAM. The external flash serves as supplemental non-volatile storage for data logging, configuration, or firmware images.

The SPI2 bus sharing between U5 (flash) and U9 (LoRa radio) means that flash access and radio communication cannot occur simultaneously. Firmware must serialize access and manage chip selects carefully. If high-throughput flash access is needed during radio operation, this bus-sharing topology becomes a bottleneck. For the typical use case of a flight computer or data logger (suggested by the pyrotechnic channels, IMU, barometer, and servo outputs), sequential access is generally acceptable.

The ADXL375 (U4) high-g accelerometer and ICM-42688-P (U10) IMU are on a separate SPI1 bus (PA5/PA6/PA7), which avoids contention with the flash and radio. The BMP388 barometer (U3) is on the I2C1 bus (PB6/PB7). This bus partitioning is well-organized for the sensor and storage workload.

AI-Assisted —

Memory	Interface	Finding	Severity
W25Q128JVSIQ (U5)	QSPI NOR Flash	/CS (pin 1, net FLASH_CS) has no external pull-up resistor. During MCU reset, /CS floats and the flash may accept spurious commands. Winbond datasheet recommends a pull-up on /CS to track VCC during power-up. Add a 10 kohm pull-up to +3.3V.	Medium
W25Q128JVSIQ (U5)	QSPI NOR Flash	No series resistors on SPI2 clock or data lines. Acceptable at STM32F405 SPI2 speeds (up to 42 MHz) with short traces, but 33 ohm series resistors are recommended if trace lengths exceed 2 to 3 cm for EMI reduction.	Low
W25Q128JVSIQ (U5)	QSPI NOR Flash	STM32F405RGT6 does not have a dedicated QSPI peripheral. True Quad SPI throughput requires software-managed GPIO for IO2/IO3 after issuing Quad commands via SPI2. Practical throughput is limited to Dual SPI or standard SPI unless bit-banging is implemented.	Low
W25Q128JVSIQ (U5)	QSPI NOR Flash	+3.3V rail decoupling includes multiple ceramic and tantalum capacitors shared across all 3.3 V devices. During layout, place a 0.1 uF ceramic capacitor immediately adjacent to U5 pin 8.	Low
W25Q128JVSIQ (U5)	QSPI NOR Flash	VCC (pin 8) connected to +3.3V rail, within the 2.7 V to 3.6 V operating range specified in the Winbond W25Q128JV datasheet.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	All four data lines (IO0 through IO3), CLK, and /CS are connected. Quad SPI wiring is complete per the Winbond W25Q128JV datasheet pin assignments.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	/WP (IO2) pulled high to +3.3V via R5 (10 kohm) and /HOLD/RESET (IO3) pulled high to +3.3V via R6 (10 kohm). Correct per Winbond datasheet recommendations for default deasserted state in standard SPI mode.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	SPI2 bus is shared between U5 (flash) and U9 (LoRa radio RFM95W-868S2). Independent chip selects (FLASH_CS and LORA_CS) prevent bus contention. Firmware must serialize access.	✓
W25Q128JVSIQ (U5)	QSPI NOR Flash	Part number suffix IQ indicates factory-default QE=1 (Quad Enable set). No firmware initialization of QE bit is required per Winbond W25Q128JV datasheet Status Register-2 description.	✓

AI-Assisted — U1 is an STM32F405RGT6 Arm Cortex-M4 MCU in LQFP-64, operating from the +3.3V rail. Five VDD pins (pins 64, 19, 32, 48, and 1/VBAT) are connected to +3.3V, and three ground pins (63, 18, 12/VSSA) are connected to GND. The +3.3V rail carries eighteen decoupling capacitors in total: twelve 100 nF ceramics, one 10 nF ceramic, two 10 uF ceramics, one 1 uF ceramic, one 2.2 uF ceramic, and one 22 uF tantalum. This exceeds the AN4488 recommendation of one 100 nF per VDD pin plus a 4.7 uF bulk capacitor, so bulk decoupling is adequate.

The VDDA pin (pin 13) is powered from the +3.3VA rail, which is derived from +3.3V through a 100 ohm ferrite bead FB1. The +3.3VA rail is decoupled with one 10 nF ceramic (C7) and one 1 uF ceramic (C8). AN4488 recommends 1 uF plus 10 nF on VDDA, so this matches the requirement.

The two VCAP pins (31 and 47) each have a 2.2 uF ceramic capacitor to GND (C51 and C11 respectively). AN4488 specifies 2.2 uF ceramic on each VCAP pin, so this is correct.

The HSE oscillator uses a 16 MHz crystal (ABM8-16Mhz-B2-T1) connected between PH0 (pin 5, HSE_IN) and PH1 (pin 6, HSE_OUT). Two 26 pF load capacitors (C12, C13) are placed from each crystal pin to GND. The STM32F405 supports HSE crystals from 4 to 26 MHz, so 16 MHz is within range. The 26 pF load capacitors are on the high side for a typical 16 MHz crystal (most 16 MHz crystals specify 8-20 pF load capacitance); the actual required value depends on the specific crystal's load capacitance specification and PCB stray capacitance. If the crystal datasheet specifies a lower CL, these capacitors may overdamp the oscillator and slow start-up or prevent oscillation.

The NRST pin (pin 7) has a 100 nF capacitor (C10) to GND and a 10k pull-up resistor (R1) to +3.3V, with a push-button switch SW2 to GND. This matches the AN4488 recommendation of a 100 nF filter capacitor on NRST.

BOOT0 (pin 60) is connected through R2 (10k) to the common pin of slide switch S1. S1 pin 1 is tied to GND and pin 3 is tied to +3.3V, allowing the user to select boot mode. This is a correct implementation for selectable boot source.

SWD debug is available via J2: SWDIO on pin 2 (PA13) and SWCLK on pin 3 (PA14). J2 pin 1 provides +3.3V and pin 4 is GND. This is a standard 4-pin SWD header.

USB D+ and D- from the Type-C connector J1 connect directly to PA12 (pin 45) and PA11 (pin 44). The USB 2.0 specification requires 22 ohm series resistors on D+ and D- for impedance matching; these are absent in the schematic. The STM32F405 internal USB peripheral does not include integrated series resistors, so external resistors are expected.

UART5 TX (PC12, pin 53) and RX (PD2, pin 54) connect to J12 pins 4 and 3 respectively. No level translation is applied, so the external device must operate at 3.3V logic levels.

Eleven GPIO pins on U1 are intentionally unconnected in the schematic: PB9, PB8, PC14, PA3, PB11, PA2, PA4, PB0, PB12, PB1, and PA8. These are general-purpose I/O and leaving them unconnected is acceptable provided they are configured as inputs with internal pull-ups or pull-downs in firmware to avoid floating inputs and excess current consumption.

AI-Assisted — U10 is a TDK InvenSense ICM-42688-P 6-axis IMU configured for SPI communication. VDD (pin 8) and VDDIO (pin 5) are both connected to +3.3V, which is within the 1.71-3.6V operating range for both supply domains. The +3.3V rail provides adequate decoupling as described under U1. However, the ICM-42688-P datasheet recommends a dedicated 100 nF ceramic capacitor placed as close as possible to each of the VDD and VDDIO pins. No dedicated per-pin decoupling capacitors are visible for U10 specifically; the device relies on the shared +3.3V rail capacitors. For a high-performance IMU, dedicated local decoupling is strongly recommended to minimize supply noise coupling into the sensor.

The SPI interface uses SPI1: AP_SCLK (pin 13) on SPI1_SCK, AP_SDI (pin 14) on SPI1_MOSI, AP_SDO (pin 1) on SPI1_MISO, and AP_CS (pin 12) on ICM_CS (PC5). The AP_SDO/AP_AD0 pin is on the SPI1_MISO net, which is correct for 4-wire SPI mode. In SPI mode, this pin functions as data output; tying it to the MISO bus is the correct connection.

The INT1/INT output (pin 4) connects to U1 pin PB2 via the ICM_INT1 net, providing an interrupt path to the MCU.

Pins RESV_3 (pin 3), RESV_2 (pin 2), and RESV_10 (pin 10) are intentionally unconnected in the schematic. The ICM-42688-P datasheet states reserved pins should be left unconnected, so this is correct. Pin INT2/FSYNC/CLKIN (pin 9) is also intentionally unconnected, which is acceptable when the secondary interrupt, FSYNC, and external clock features are not used. RESV_7 (pin 7) and RESV_11 (pin 11) are tied to GND. The datasheet indicates reserved pins should be left floating; tying them to GND may be acceptable but deviates from the datasheet guidance. This should be reviewed against the latest datasheet errata.

AI-Assisted — U3 is a Bosch BMP388 barometric pressure sensor. VDD (pin 10) and VDDIO (pin 1) are both connected to +3.3V, within the specified 1.65-3.6V range for VDD and 1.2-3.6V range for VDDIO. Three VSS pins (3, 8, 9) are connected to GND. The BMP388 shares the +3.3V rail decoupling capacitors with U1 and other devices. The BMP388 datasheet recommends 100 nF on both VDD and VDDIO; dedicated local capacitors for U3 are not individually identifiable but the rail has ample ceramic decoupling.

The sensor is configured for I2C communication: SCK (pin 2) connects to I2C1_SCL and SDI (pin 4) connects to I2C1_SDA. Both I2C lines have 4.7k pull-up resistors to +3.3V (R14 and R15), which is appropriate for standard-mode and fast-mode I2C at 3.3V.

The SDO pin (pin 5) is tied to GND, which sets the I2C slave address to 0x76. This is a valid configuration.

The CSB pin (pin 6) is tied to +3.3V (visible on the +3.3V rail). Per the BMP388 datasheet, CSB high selects I2C mode, which is consistent with the I2C bus connections on SCK and SDI.

The INT output (pin 7) is intentionally unconnected in the schematic. The interrupt output is optional and the sensor can be operated in polling mode, so this is acceptable.

AI-Assisted — U4 is an Analog Devices ADXL375BCCZ high-g digital accelerometer. VDD_I/O (pin 1) is connected to +3.3V. The VS supply pin (pin 6) is powered through a 33 ohm resistor R16 from +3.3V, forming a filtered supply on the Net-(U4-VS) net. This net is decoupled with two capacitors to GND: C27 (10 uF tantalum) and C28 (100 nF ceramic). The ADXL375 datasheet recommends a 100 nF bypass capacitor on VS; the additional 10 uF tantalum provides extra bulk filtering. The 33 ohm series resistor with the bypass capacitors forms an RC low-pass filter on the analog supply, which is good practice for reducing digital noise coupling into the sensor. Three GND pins (2, 4, 5) are connected to GND.

The device is configured for 4-wire SPI: SCL/SCLK (pin 14) on SPI1_SCK, SDA/SDI/SDIO (pin 13) on the Net-(U4-SDA/SDI/SDIO) net, SDO/ALT_ADDRESS (pin 12) on SPI1_MISO, and CS (pin 7) on ADXL_CS (PC4). The CS pin is active-low, and it connects to U1 PA4 area via the ADXL_CS net through U2 (the OR gate), which is discussed below.

Notably, pin 13 (SDA/SDI/SDIO) does not connect directly to the SPI1_MOSI bus. Instead, it connects to the output of U2 (74AHC1G32 OR gate). U2 input pin 1 is on the ADXL_CS net and input pin 2 is on SPI1_MOSI. The OR gate output (pin 4) feeds U4 pin 13. This means the MOSI data is OR-ed with the CS signal before reaching the ADXL375 data input. When CS is high (deselected), the OR gate output is forced high regardless of MOSI state, which keeps the SDI pin high and prevents spurious data from being clocked in. When CS is low (selected), the OR gate passes the MOSI signal through. This is a valid technique to prevent bus contention issues on a shared SPI bus where the ADXL375 SDI pin might otherwise latch stray data.

Pins RESERVED (3, 11) and NC (10) are intentionally unconnected, which matches the ADXL375 datasheet requirement that reserved pins be left unconnected. INT1 (pin 8) and INT2 (pin 9) are also intentionally unconnected. The ADXL375 can operate without interrupt outputs if the host polls the status registers, so this is acceptable, though it means the MCU cannot use hardware interrupts for shock detection events.

AI-Assisted — U5 is a Winbond W25Q128JVSIQ 128 Mbit SPI NOR flash. VCC (pin 8) is connected to +3.3V, within the 2.7-3.6V operating range. GND (pin 4) is connected to GND. The +3.3V rail provides shared decoupling.

The SPI interface uses SPI2: CLK (pin 6) on SPI2_SCK, DI/IO0 (pin 5) on SPI2_MISO, DO/IO1 (pin 2) on SPI2_MOSI, and CS (pin 1) on FLASH_CS (PC15). The naming of DI and DO on the W25Q128 follows the flash device convention where DI is the data input to the flash (connected to the master's MOSI) and DO is the data output from the flash (connected to the master's MISO). In the schematic, pin 5 (DI/IO0) connects to SPI2_MISO and pin 2 (DO/IO1) connects to SPI2_MOSI. This appears to be a MOSI/MISO swap: the flash DI (data in) should connect to the MCU MOSI, and the flash DO (data out) should connect to the MCU MISO. As wired, data sent by the MCU on MOSI would arrive at the flash DO pin (which is an output), and the flash DI pin (which is an input) would be connected to the MCU MISO line. This would prevent communication. This is a critical wiring error that must be corrected.

The /WP (pin 3) is pulled high to +3.3V through R5 (10k), disabling write protection. The /HOLD/RESET (pin 7) is pulled high to +3.3V through R6 (10k), disabling the hold function. Both are correct for normal operation.

AI-Assisted — U9 is a HopeRF RFM95W-868S2 LoRa transceiver module operating at 868 MHz. The 3.3V supply pin (pin 13) is connected to +3.3V, within the 1.8-3.7V operating range. Three GND pins (1, 8, 10) are connected to GND. The module integrates a 32 MHz crystal, so no external crystal is required.

The SPI interface uses SPI2: SCK (pin 4) on SPI2_SCK, MOSI (pin 3) on SPI2_MOSI, MISO (pin 2) on SPI2_MISO, and NSS (pin 5) on LORA_CS (PC1). This SPI bus is shared with U5 (flash memory), with separate chip-select lines.

The RESET pin (pin 6) connects to LORA_RST (PC0 on U1), allowing the MCU to reset the module. The RFM95W has an internal pull-up on RESET, so no external pull-up is needed.

DIO0 (pin 14) connects to LORA_DIO0 (PA0) and DIO1 (pin 15) connects to LORA_DIO1 (PA1) on U1. These are the primary interrupt lines used for LoRa TX/RX done and timeout signaling. DIO5 (pin 7), DIO3 (pin 11), DIO2 (pin 16), and DIO4 (pin 12) are intentionally unconnected. DIO5 is used for ClkOut and DIO3/DIO4 for less common functions; leaving them unconnected is acceptable for a basic LoRa implementation.

The ANT pin (pin 9) connects to J7 (SMA coaxial connector) via the Net-(J7-In) net. No matching network components are visible between the module and the SMA connector. The RFM95W module typically includes an internal matching network for 50 ohm, and the SMA connector is a 50 ohm interface, so a direct connection is standard practice for this module. The PCB trace from U9 pin 9 to J7 must be designed as a 50 ohm controlled-impedance transmission line, and a ground plane keep-out under the antenna trace should be avoided (the ground plane should be continuous under the RF trace for microstrip).

AI-Assisted — U16 is a Texas Instruments LSF0102DCUR dual bidirectional level translator. VREF_A (pin 2) is connected to +3.3V, and VREF_B (pin 7) is connected to the Net-(U16-VREF_B) net. This net is supplied through R39 (200k) from +5V and decoupled with C33 (100 nF) to GND. The EN pin (pin 8) is also on this same net, so the enable voltage equals VREF_B.

The LSF0102 datasheet requires VREF_A to be the lower voltage reference. With VREF_A at 3.3V and VREF_B derived from +5V through a 200k resistor, the B-side voltage depends on the load current through R39. With no DC load, VREF_B would be near 5V. However, the LSF0102 is a switch-based translator that requires pull-up resistors on the higher-voltage side. The B-side signals connect to J3 pins 2 and 3 (via nets Net-(J3-Pin_2) and Net-(J3-Pin_3)). On Net-(J3-Pin_2), two 1k resistors (R40 and R41) pull up to +5V. On Net-(J3-Pin_3), one 1k resistor (R40) pulls up to +5V. These pull-ups are appropriate for the B-side of the LSF0102.

The A-side signals connect to USART1_RX (A1, pin 3) and USART1_TX (A2, pin 4) on U1. Both USART1_TX and USART1_RX have 1k pull-up resistors (R37 and R38) to +3.3V. The LSF0102 A-side also benefits from pull-ups, so this is correct.

GND (pin 1) is connected to GND. The EN pin being tied to VREF_B means the translator is enabled whenever VREF_B is powered, which is standard practice.

One concern: the 200k resistor R39 supplying VREF_B from +5V creates a very high source impedance for the reference voltage. Any leakage current or transient load on the VREF_B pin could cause the reference voltage to sag significantly. The LSF0102 VREF_B pin has minimal DC current draw (microamps), so under static conditions this may be acceptable, but during switching transients the 100 nF capacitor C33 must supply the charge. A lower-value resistor or a direct connection to +5V would provide a more robust reference.

AI-Assisted — U2 is a single 2-input OR gate (74AHC1G32) powered from +3.3V on VCC (pin 5) with GND on pin 3. The 74AHC1G32 operates from 2.0 to 5.5V, so 3.3V is within range. The +3.3V rail provides shared decoupling; no dedicated bypass capacitor is visible specifically for U2, but the rail has twelve 100 nF ceramics distributed among multiple devices.

Input pin 1 connects to ADXL_CS (PC4 on U1), and input pin 2 connects to SPI1_MOSI (PA7 on U1). The output (pin 4) drives U4 pin 13 (SDA/SDI/SDIO). As discussed under U4, this OR gate ensures that when the ADXL375 is deselected (CS high), the SDI input is held high, preventing unintended data latching. This is a valid and intentional design choice.

AI-Assisted — Six TLP291 optocouplers (U6, U7, U8, U11, U12, U13) are used in the pyrotechnic firing circuits. The TLP291 is not recommended for new designs by Toshiba; the TLP291(SE is the current replacement with identical electrical specifications.

Each optocoupler's LED anode (pin 1) connects through a 330 ohm series resistor to a MCU GPIO, and the LED cathode (pin 2) connects to GND. The phototransistor collector (pin 4) connects to VBAT+_PYRO, and the emitter (pin 3) connects through a 100 ohm resistor to the gate of an N-channel MOSFET (AO3400A). The specific mapping is: U6 driven by PYRO1 (PB5) through R19, controlling Q2; U7 driven by PYRO2 (PB4) through R22, controlling Q3; U8 driven by PYRO3 (PB3) through R25, controlling Q6; U11 driven by PYRO4 (PC11) through R28, controlling Q7; U12 driven by PYRO5 (PC10) through R31, controlling Q8; U13 driven by PYRO6 (PA15) through R34, controlling Q9.

With 3.3V MCU output, a TLP291 forward voltage of approximately 1.2V, and a 330 ohm resistor, the LED forward current is approximately (3.3 - 1.2) / 330 = 6.4 mA. At a minimum CTR of 50%, the phototransistor can sink at least 3.2 mA, which is sufficient to charge the MOSFET gate through the 100 ohm resistor. Each MOSFET gate also has a 10k pull-down resistor to GND (R21, R24, R27, R30, R33, R36), ensuring the gate is held low when the optocoupler is off.

The optocouplers provide galvanic isolation between the MCU-side 3.3V domain and the pyrotechnic battery supply (VBAT+_PYRO), which is appropriate for safety-critical pyrotechnic circuits.

AI-Assisted — J1 is a USB 2.0-only 16-pin Type-C receptacle. The VBUS pins (A4, A9, B4, B9) connect to the VBUS rail. CC1 (A5) has a 5.1k pull-down resistor R3 to GND, and CC2 (B5) has a 5.1k pull-down resistor R4 to GND. Per the USB Type-C specification, 5.1k pull-downs on CC1 and CC2 identify the port as a UFP (Upstream Facing Port / device), which is correct for a device that draws power from a USB host or charger.

SBU1 (A8) and SBU2 (B8) are intentionally unconnected, which is acceptable for USB 2.0 operation where SBU pins are not used.

D+ lines (A6, B6) are shorted together on the USB_D+ net and connect to U1 PA12. D- lines (A7, B7) are shorted together on the USB_D- net and connect to U1 PA11. As noted under U1, 22 ohm series resistors on D+ and D- are missing.

The VBUS rail feeds through Schottky diode D12 (SS14) to the Net-(D11-K) node, which also receives power from VBAT+ through Schottky diode D11 (SS14). This creates an OR-ing arrangement where the higher of VBUS or VBAT+ supplies the input to U17 (the 5V buck regulator). Three 10 uF ceramic capacitors (C15, C16, C17) decouple this node.

AI-Assisted — Per the STM32F405 datasheet (DS8626) and AN4879, PA9 is the pin natively dedicated to VBUS sensing for the OTG_FS peripheral. In this design, PA9 (U1 pin 42) is assigned to USART1_RX and is not connected to VBUS. The VBUS rail from J1 (pins A4, A9, B4, B9) feeds through Schottky diode D12 to the power input of regulator U17 but has no connection to any GPIO on U1 for sensing. Without VBUS sensing, the USB device stack cannot detect host attachment or detachment per the USB specification. If the device is always bus-powered and VBUS is guaranteed present whenever the MCU is running, VBUS sensing can be disabled in firmware (the STM32 HAL supports this). However, if the board can be powered independently of USB (which appears to be the case given the separate VBAT+ and VBAT+_PYRO battery rails), the absence of VBUS sensing means the firmware cannot determine when a USB host is connected.

No ESD protection device is present on the USB D+/D- lines between J1 and U1. ST AN4879 recommends ESD protection (such as a USBLC6) placed as close as possible to the USB receptacle. While the STM32F405 USB pins have some inherent ESD tolerance, an external TVS diode array is strongly recommended for USB compliance testing and field reliability, particularly for a connector that will be subject to hot-plug events.

AI-Assisted —

Device	Category	Finding	Severity
U5 (W25Q128JVSIQ)	Interface	SPI MOSI/MISO connections appear swapped: flash DI (pin 5) is on SPI2_MISO and flash DO (pin 2) is on SPI2_MOSI. Flash DI should connect to MCU MOSI and flash DO to MCU MISO. Communication will fail as wired.	High
U1 (STM32F405RGT6)	Clock	16 MHz HSE crystal with 26 pF load capacitors. Value is high for most 16 MHz crystals (typically 8-20 pF CL); may cause slow start-up or failure to oscillate depending on crystal specification.	Medium
U1 (STM32F405RGT6)	USB	USB D+ and D- connected directly to PA12 and PA11 without 22 ohm series resistors. USB 2.0 specification and ST AN4879 recommend 22 ohm series resistors for impedance matching.	Medium
U16 (LSF0102DCUR)	Power	VREF_A at 3.3V (low side), VREF_B derived from 5V through 200k resistor R39. 200k source impedance is very high for a reference voltage; transient performance may be degraded.	Medium
U6-U13 (TLP291)	Lifecycle	TLP291 is not recommended for new designs by Toshiba. TLP291(SE is the current replacement with identical specifications.	Medium
U10 (ICM-42688-P)	Power	VDD and VDDIO both on +3.3V, within 1.71-3.6V range. No dedicated local bypass capacitors visible for U10; relies on shared rail decoupling.	Low
U10 (ICM-42688-P)	Configuration	RESV_7 (pin 7) and RESV_11 (pin 11) tied to GND; datasheet recommends leaving reserved pins unconnected.	Low
U4 (ADXL375BCCZ)	Interrupt	INT1 and INT2 both intentionally unconnected. Shock events must be detected by polling, which adds latency for high-g event capture.	Low
U1 (STM32F405RGT6)	Power	VDD, VBAT, VDDA all correctly supplied at 3.3V with adequate decoupling. VCAP pins have correct 2.2 uF ceramics. VDDA filtered through ferrite bead with 10 nF + 1 uF bypass.	✓
U1 (STM32F405RGT6)	Configuration	NRST has 100 nF filter cap and 10k pull-up to 3.3V with reset button. BOOT0 selectable via slide switch S1 with 10k resistor.	✓
U1 (STM32F405RGT6)	Debug	SWD interface (SWDIO, SWCLK) correctly routed to 4-pin header J2 with power and ground.	✓
U10 (ICM-42688-P)	Interface	SPI1 bus correctly wired: SCLK, MOSI, MISO, and dedicated CS (ICM_CS on PC5) all connected.	✓
U10 (ICM-42688-P)	Interrupt	INT1 connected to MCU PB2 for interrupt-driven operation.	✓
U3 (BMP388)	Power	VDD and VDDIO on +3.3V, within specified ranges. Three VSS pins grounded.	✓
U3 (BMP388)	Interface	I2C mode correctly selected: CSB tied to 3.3V (I2C mode), SDO tied to GND (address 0x76). I2C1_SCL and I2C1_SDA have 4.7k pull-ups to 3.3V.	✓
U3 (BMP388)	Interrupt	INT pin (pin 7) intentionally unconnected. Sensor can be polled; acceptable for non-time-critical pressure readings.	✓
U4 (ADXL375BCCZ)	Power	VDD_I/O on +3.3V. VS supplied through 33 ohm filter resistor R16 with 10 uF tantalum and 100 nF ceramic bypass. Good analog supply filtering.	✓
U4 (ADXL375BCCZ)	Interface	SPI1 bus with OR gate U2 on SDI input to prevent spurious data when deselected. SDO on SPI1_MISO, SCLK on SPI1_SCK, CS on ADXL_CS.	✓
U4 (ADXL375BCCZ)	Configuration	RESERVED pins (3, 11) and NC pin (10) correctly left unconnected per datasheet.	✓
U5 (W25Q128JVSIQ)	Power	VCC on +3.3V within 2.7-3.6V range. GND connected.	✓
U5 (W25Q128JVSIQ)	Configuration	/WP pulled high via 10k R5, /HOLD pulled high via 10k R6. Correct for normal unrestricted operation.	✓
U9 (RFM95W-868S2)	Power	3.3V supply on pin 13, within 1.8-3.7V range. Three GND pins connected.	✓
U9 (RFM95W-868S2)	Interface	SPI2 bus correctly wired with dedicated LORA_CS chip select on PC1. RESET driven by MCU PC0.	✓
U9 (RFM95W-868S2)	Wireless	ANT pin connected directly to SMA connector J7. Module includes internal matching for 50 ohm. PCB trace must be 50 ohm controlled impedance.	✓
U9 (RFM95W-868S2)	Interrupt	DIO0 and DIO1 connected to MCU PA0 and PA1 for LoRa TX/RX done and timeout interrupts. DIO2-DIO5 unconnected; acceptable for standard LoRa operation.	✓
U16 (LSF0102DCUR)	Interface	A-side translates USART1_TX and USART1_RX from 3.3V MCU domain. B-side connects to J3 with 1k pull-ups to 5V. Pull-ups present on both sides as required by switch-based translator.	✓
U16 (LSF0102DCUR)	Configuration	EN tied to VREF_B net, enabling translator when B-side is powered.	✓
U2 (74AHC1G32)	Power	VCC on +3.3V, within 2.0-5.5V range. GND connected.	✓
U2 (74AHC1G32)	Function	OR gate used to gate SPI1_MOSI with ADXL_CS for U4 SDI input. Correct logic: CS high forces SDI high, CS low passes MOSI data.	✓
U6 (TLP291)	Pyro	LED driven at approximately 6.4 mA through 330 ohm R19 from 3.3V GPIO. Phototransistor collector on VBAT+_PYRO, emitter through 100 ohm R20 to Q2 gate with 10k pull-down R21. Correct optoisolated gate drive.	✓
U7 (TLP291)	Pyro	Same topology as U6 for PYRO2 channel. 330 ohm R22, 100 ohm R23, 10k pull-down R24, driving Q3.	✓
U8 (TLP291)	Pyro	Same topology as U6 for PYRO3 channel. 330 ohm R25, 100 ohm R26, 10k pull-down R27, driving Q6.	✓
U11 (TLP291)	Pyro	Same topology as U6 for PYRO4 channel. 330 ohm R28, 100 ohm R29, 10k pull-down R30, driving Q7.	✓
U12 (TLP291)	Pyro	Same topology as U6 for PYRO5 channel. 330 ohm R31, 100 ohm R32, 10k pull-down R33, driving Q8.	✓
U13 (TLP291)	Pyro	Same topology as U6 for PYRO6 channel. 330 ohm R34, 100 ohm R35, 10k pull-down R36, driving Q9.	✓

AI-Assisted —

References
74AHC1G32 (Nexperia / Diodes Inc / TI (multiple sources)) — Nexperia 74AHC1G32 datasheet Rev. 12, 19 Sep 2024 assets.nexperia.com/documents/data-sheet/74AHC_AHCT1G32.pdf
ADXL375BCCZ (Analog Devices) — ADXL375 datasheet Rev. B, Analog Devices, 32 pages www.analog.com/media/en/technical-documentation/data-shee...
BMP388 (Bosch Sensortec) — BMP388 datasheet BST-BMP388-DS001-07, Revision 1.7, November 2020, 59 pages www.bosch-sensortec.com/media/boschsensortec/downloads/da...
ICM-42688-P (TDK InvenSense) — ICM-42688-P datasheet ds-000347 v1.6, 06/20/2021, TDK InvenSense, 110 pages product.tdk.com/system/files/dam/doc/product/sensor/morti...
LSF0102DCUR (Texas Instruments) — TI LSF0102 datasheet, Rev. B; also Nexperia LSF0102 datasheet Rev. 3, Sep 2020 www.ti.com/lit/ds/symlink/lsf0102.pdf
RFM95W-868S2 (HopeRF (Shenzhen Hope Microelectronics) / RF Solutions (distributor brand)) — RFM95/96/97/98(W) Datasheet Version 2.0, hoperf.com (via cdn.sparkfun.com); GlobalSpec/DigiKey hosted datasheet cdn.sparkfun.com/assets/a/9/6/1/0/RFM95W-V2.0.pdf
STM32F405RGT6 (STMicroelectronics) — STM32F405xx/STM32F407xx Datasheet DS8626, st.com; AN4488 Rev 7 (Hardware Development App Note) www.st.com/resource/en/datasheet/stm32f405rg.pdf
TLP291 (Toshiba) — TLP291(SE datasheet, Rev.2.0, 2019-07-08; TLP291 datasheet 2014-09-22, RS-Online hosted PDF toshiba.semicon-storage.com/info/TLP291_datasheet_en_2014...

AI-Assisted — The design uses a single logic ground domain named GND that serves all digital, analog, power, and connector functions. There is no separate chassis ground or earth ground net visible in the schematic. All connector ground and shield pins — including the USB Type-C shell pin (J1 SH) — are connected directly to the logic GND net. This single-ground architecture is common in battery-powered or plastic-enclosure products but presents specific EMC considerations that must be addressed.

The analog supply rail +3.3VA is derived from the main +3.3V rail through a 100 ohm ferrite bead (FB1), with dedicated filtering (10 nF and 1 µF capacitors) on the analog side. This provides some isolation between the digital and analog power domains for the STM32F405 VDDA pin (U1 pin 13). However, the analog ground (VSSA, U1 pin 12) shares the same GND net as the digital ground (VSS, U1 pins 18 and 63), so the benefit of the ferrite bead is limited to power-side noise rejection. A split-ground approach with a single-point connection under the MCU would improve analog performance and reduce conducted noise coupling, but this is a layout decision not captured in the schematic.

The 5 V buck converter (U17, TPS563200) input is fed from a combined VBUS/VBAT+ rail through diode-ORing (D11 from VBAT+, D12 from VBUS). Three 10 µF ceramic capacitors (C15, C16, C17) filter the input node. The output is filtered through a 3.3 µH inductor (L2) with three 22 µF ceramic capacitors (C19, C20, C21) and one 10 µF tantalum (C53) on the +5V rail. A 0.1 µF bootstrap capacitor (C18) is present on the VBST pin. This is a standard configuration per the TPS563200 datasheet. The switching node (Net-(U17-SW)) has a 0.1 µF capacitor (C18 pin 2) which is the bootstrap capacitor — no additional snubber is shown. Depending on layout parasitics, the switching node may radiate; this is a layout-dependent concern.

The LoRa transceiver (U9, RFM95W-868S2) connects to an SMA edge-mount connector (J7) for the antenna. No filtering, matching network, or ESD protection is visible between U9 pin 9 (ANT) and J7 pin 1. The antenna port is a direct RF connection. For conducted emissions compliance per EN 55032 and radiated emissions per ETSI EN 300 220 (for 868 MHz ISM band), harmonic filtering is typically required between the transceiver and antenna. The RFM95W module may include an internal matching network, but external harmonic filtering (e.g., a low-pass filter at 868 MHz) is commonly needed to meet regulatory limits. The SMA connector shell (J7 pin 2, Ext) is on GND, which is correct for RF ground return.

The USB Type-C connector J1 has its shell/shield pin (SH) connected directly to the logic GND net. This means the schematic does not capture a dedicated shield grounding strategy. The shell shares the same net name as all other ground connections, so the layout tool has no net-level guidance to create a separate copper pour under the connector or to place bond components (resistor, capacitor) between the shield and logic ground. Per USB Type-C specification R2.5 Section 3.2.1, the receptacle shell shall be connected to the PCB ground plane, but the method of connection has ESD compliance implications under IEC 61000-4-2.

For a plastic enclosure (Scenario A), where no earth ground exists, the shield pour under J1 should be connected directly to the logic GND plane via dense via stitching. During an ESD event, the entire ground plane rises uniformly with the shell, keeping differential voltage across the USB data pins near zero. The schematic should use a dedicated net (e.g., SHIELD_GND_USB_C) for the shell pin, with a zero-ohm resistor or direct copper connection to GND documented as a schematic note, so the layout engineer understands the intent.

For a metal chassis with earth ground (Scenario B), the shield pour should be bonded mechanically to the chassis at the connector opening. An R||C isolation network (typically 1 Mohm in parallel with 4.7 nF rated at 2 kV or higher) between the shield pour and logic GND may be needed to prevent ESD energy from coupling directly into the logic ground plane. The schematic currently does not capture this option because the shell pin is on the same GND net as everything else. A dedicated SHIELD_GND net would allow the layout engineer to implement either scenario based on the enclosure design.

The screw terminal connectors (J4 through J6, J8 through J11, J13) connect to pyrotechnic firing circuits and servo power. These are high-current paths with inductive loads (pyro igniters, servo motors). No common-mode filtering or differential filtering is present on these lines. Depending on cable lengths, these connectors may act as antennas for conducted emissions (EN 55032 Class B) and may couple ESD transients (IEC 61000-4-2) or electrical fast transients (IEC 61000-4-4) into the board. The diodes D2, D3, D5, D8, D9, D10 (US1M, 1000 V 1 A rectifiers) on the pyro channels provide reverse-voltage clamping from VBAT+_PYRO, but these are slow-recovery diodes not suitable for ESD protection.

The I2C bus (I2C1_SCL, I2C1_SDA) is routed to the BMP388 pressure sensor (U3) with 4.7 kohm pull-ups to +3.3V (R14, R15). This bus does not leave the board through any connector, so external ESD protection is not required for I2C. The SPI buses (SPI1 and SPI2) similarly remain on-board, connecting to U4 (ADXL375), U5 (W25Q128), U9 (RFM95W), and U10 (ICM-42688-P).

AI-Assisted — Connector J1 is a USB 2.0-only 16-pin Type-C receptacle (GCT USB4110). This is a consumer-facing external connector that will be exposed to user touch and cable insertion/removal. It carries VBUS power (pins A4, A9, B4, B9), USB 2.0 data (D+ on pins A6/B6, D- on pins A7/B7), and CC configuration channels (CC1 on A5, CC2 on B5).

ESD Protection: There is no TVS diode array or ESD protection device visible on any of the USB signal lines (D+, D-, CC1, CC2) or VBUS. Per IEC 61000-4-2, external connectors accessible to users must withstand contact discharge of ±4 kV and air discharge of ±8 kV (Level 2 for consumer products, Level 4 for industrial at ±8 kV contact). The STM32F405 USB data pins (PA11, PA12) have internal ESD structures rated for the Human Body Model (HBM) per JEDEC JESD22-A114, typically 2 kV HBM, which is insufficient for system-level IEC 61000-4-2 compliance. A dedicated USB ESD protection device (e.g., USBLC6-2SC6 or TPD2E2U06) placed close to J1 is strongly recommended for the D+/D- pair.

The CC1 and CC2 pins each have a 5.1 kohm pull-down resistor to GND (R3, R4), which correctly identifies the port as a UFP (Upstream Facing Port) per USB Type-C specification. However, these pins are also exposed to ESD and have no TVS protection. The CC pins connect directly to the connector with no series resistance beyond the 5.1 kohm pull-downs, which provides some current limiting but does not clamp voltage transients.

VBUS has no TVS or transient voltage suppressor. The VBUS net feeds through Schottky diode D12 (SS14, 40 V 1 A) to the input of the TPS563200 buck converter. The SS14 provides some clamping at its reverse breakdown voltage but is not designed as an ESD protection device. A dedicated VBUS TVS (e.g., SMBJ5.0A or equivalent rated for IEC 61000-4-5 surge) would protect the downstream regulator.

The SBU1 (A8) and SBU2 (B8) pins are marked as designer-intentionally unconnected, which is acceptable for a USB 2.0-only implementation. These pins should still have ESD protection if the connector shell does not fully shield them, as they are physically present in the receptacle.

USB D+ and D- lines have no series resistors or common-mode choke. For USB 2.0 Full Speed (12 Mbps), a common-mode choke is recommended for EMC compliance per CISPR 32 / EN 55032 to reduce common-mode emissions on the cable. The absence of filtering may result in radiated emissions failures in the 100-500 MHz range, where USB 2.0 harmonics fall.

Shield grounding: As discussed in the EMC Architecture section, the shell pin (SH) is on the logic GND net. A dedicated SHIELD_GND_USB_C net is recommended so the bonding strategy can be explicitly captured for either plastic or metal enclosure scenarios.

AI-Assisted — Connector J7 is an edge-mount SMA connector (Samtec SMA-J-P-H-ST-EM1) used for the LoRa antenna connection to U9 (RFM95W-868S2). This is an external connector — the antenna will protrude from the enclosure or connect via a cable to an external antenna.

ESD Protection: There is no ESD protection device on the antenna line (Net-(J7-In)) between J7 pin 1 and U9 pin 9 (ANT). An external antenna is highly susceptible to ESD events, both from user contact and from electrostatic charge buildup on the antenna element itself. Per IEC 61000-4-2, antenna ports on consumer and industrial equipment must withstand system-level ESD. The RFM95W module's RF front end contains an LNA and PA that are sensitive to ESD damage. A gas discharge tube (GDT) or a low-capacitance TVS diode (e.g., PESD0402-140 or similar with capacitance below 0.5 pF to avoid detuning at 868 MHz) placed at J7 would provide protection without significantly affecting RF performance.

EMC: The direct connection from U9 to J7 with no external harmonic filter means that any spurious emissions or harmonics generated by the RFM95W transmitter will be radiated directly by the antenna. For ETSI EN 300 220-1 compliance (Short Range Devices in the 868 MHz band), spurious emissions must be below -36 dBm in the range 25 MHz to 1 GHz (excluding the operating band) and below -30 dBm above 1 GHz. A pi-network low-pass filter or SAW filter between U9 and J7 is typically required to meet these limits. The RFM95W module datasheet from HopeRF recommends an impedance matching network at the antenna port; the absence of any matching components suggests the SMA connector and antenna are assumed to be 50 ohm matched, but harmonic filtering is still needed.

The SMA connector shell (J7 pin 2, Ext) is connected to GND, providing the RF ground return path. This is correct for a coaxial connector.

AI-Assisted — These eight 2-pin screw terminal connectors (Phoenix 1771091) serve the pyrotechnic firing circuits and related power switching. J4 through J6 and J8 through J11 each connect one pin to VBAT+_PYRO (the pyro battery rail) and the other pin to the drain of an N-channel MOSFET (AO3400A) through a US1M rectifier diode. J13 connects to the drain of P-channel MOSFET Q5 (AO3401A), which switches VBAT+_PYRO to the pyro load.

These connectors are likely internal to the system (connecting to pyrotechnic igniters or e-matches inside a rocket or similar vehicle), but the wiring may run significant distances, making the cables susceptible to ESD pickup and acting as antennas for conducted emissions.

ESD Protection: No TVS or transient suppression is present on any screw terminal. The US1M diodes (D2, D3, D5, D8, D9, D10) are 1000 V 1 A general-purpose rectifiers used as flyback/reverse-polarity protection — their reverse recovery time (approximately 75 ns per the US1M datasheet) is too slow for ESD clamping. The AO3400A MOSFETs have a gate-source ESD rating of approximately 1 kV HBM, and the gate drive circuits include 10 kohm pull-down resistors to GND (R21, R24, R27, R30, R33, R36) and 100 ohm series gate resistors (R20, R23, R26, R29, R32, R35) which provide some transient current limiting. However, the drain pins are directly exposed to the screw terminals with no clamping.

For applications where these connectors are accessible during assembly or maintenance, a bidirectional TVS diode rated for the VBAT+_PYRO voltage (which appears to be an unregulated battery rail) would protect the MOSFETs from ESD and inductive kickback transients. The Schottky diodes D11 and D12 (SS14, 40 V) on the input power ORing circuit provide some voltage clamping but are not on the pyro output paths.

EMC: The pyro firing circuits switch significant current through inductive loads (wire runs to igniters). The switching transients from the AO3400A MOSFETs can generate conducted emissions on the cables. No filtering (common-mode choke, ferrite bead, or capacitor) is present on any screw terminal line. For compliance with EN 55032 Class B conducted emissions limits, filtering may be needed depending on cable length and switching characteristics. The US1M diodes provide some damping of inductive flyback but their slow recovery may cause ringing that generates emissions in the 1-30 MHz range.

AI-Assisted — Connectors J3 and J12 are 4-pin JST SH series horizontal SMD connectors (SM04B-SRSS-TB). These are small-pitch (1.0 mm) connectors typically used for board-to-board or board-to-module internal connections.

J3 carries +5V (pin 1), two level-shifted signals through U16 (LSF0102DCUR) on pins 2 and 3 (Net-(J3-Pin_2) and Net-(J3-Pin_3)), and GND (pin 4). The level translator U16 shifts between 3.3 V (VREF_A) and a voltage derived from +5V through a 200 kohm resistor R39 with a 2.2 µF capacitor C33 to GND on the VREF_B pin. The signal lines have 1 kohm series resistors (R40, R41) between +5V pull-ups and the connector pins, providing some current limiting.

J12 carries +5V (pin 1), GND (pin 2), UART5_RX (pin 3), and UART5_TX (pin 4). The UART signals connect directly to STM32F405 pins PD2 and PC12 with no series resistors or ESD protection.

These JST connectors are classified as internal connectors. If they remain inside a sealed enclosure with short cable runs (under 10 cm), ESD protection is generally not required. However, if J3 or J12 connect to external modules or sensors via cables that exit the enclosure, TVS protection on the signal lines would be warranted per IEC 61000-4-2. The UART lines on J12 are particularly vulnerable as they connect directly to the MCU with no series resistance.

The +5V power on J3 pin 1 and J12 pin 1 has no reverse polarity protection or current limiting at the connector. If these connectors are used for external peripherals, a PTC fuse or current-limiting device on the +5V output would prevent damage from short circuits.

AI-Assisted — Connector J2 is a 4-pin 2.54 mm pitch vertical SMD pin header carrying SWDIO (pin 2), SWCLK (pin 3), +3.3V (pin 1), and GND (pin 4). This is a debug/programming interface for the STM32F405 MCU.

This connector is classified as an internal development/debug interface. It is typically not accessible in production units and is often depopulated or covered. No ESD protection is present on SWDIO or SWCLK, which connect directly to U1 pins PA13 and PA14. For a debug port that is only used during development with short probe cables, this is acceptable. If the connector remains populated and accessible in the final product, low-capacitance TVS diodes would be advisable.

No filtering is present on the debug lines, which is standard practice for SWD interfaces where signal integrity at low frequencies (typically under 10 MHz) is not affected by TVS capacitance.

AI-Assisted — Four servo motor connectors (M1 through M4) use 3-pin 2.54 mm pitch vertical SMD pin headers. Each carries a PWM signal (pin 1), positive power from VBAT+_PYRO (pin 2), and GND (pin 3). The PWM signals (SERVO1 through SERVO4) connect directly to STM32F405 timer output pins PC6, PC7, PC8, and PC9.

Servo motors are inductive loads that generate back-EMF and switching noise. The PWM lines have no series resistors or filtering between the MCU pins and the connector. No TVS or clamping diodes are present on the PWM lines. Servo cables can be 15-30 cm long, acting as antennas for both emissions and susceptibility.

The VBAT+_PYRO power rail on pin 2 is an unregulated battery supply shared with the pyrotechnic circuits. Servo motor current draw (typically 200 mA to 1.5 A per servo under load) will cause voltage transients on this rail. No local decoupling is visible at the servo connectors. The shared power rail means pyro firing events will cause voltage dips visible to the servos, and servo stall current will affect pyro circuit voltage.

For EMC, the PWM signals at typical servo frequencies (50 Hz with 1-2 ms pulse widths) have significant harmonic content. Series ferrite beads or small series resistors (33-100 ohm) on the PWM lines close to the connector would reduce high-frequency emissions on the servo cables.

AI-Assisted — The six pyrotechnic channels use optocouplers (U6 through U8, U11 through U13, TLP291) to isolate the MCU-side control signals from the high-side pyro firing MOSFETs. The optocoupler LED side is driven through 330 ohm resistors (R19, R22, R25, R28, R31, R34) from the MCU GPIO pins, and the phototransistor side drives 100 ohm gate resistors (R20, R23, R26, R29, R32, R35) to the N-channel MOSFET gates.

This optocoupler isolation provides a galvanic barrier between the MCU domain and the pyro firing domain, which is good EMC practice. However, the isolation benefit is partially negated by the fact that both sides share the same GND net. The optocoupler emitter pins (pin 2 on U6-U8, U11-U13) and the MOSFET source pins (Q2, Q3, Q6-Q9 pin 2) are all on GND. True galvanic isolation would require separate ground domains for the pyro side, but this may be intentional for simplicity in a weight-constrained application.

The P-channel MOSFETs Q4 and Q5 (AO3401A) serve as high-side switches for VBAT+_PYRO. Q4 switches power to J5 (pin 2), and Q5 switches power to J13 (pin 2). Their gates are driven through 10 kohm pull-down resistors to GND (R17, R18) with no visible gate drive resistor for slew rate control. Fast switching of these MOSFETs into inductive cable loads can generate EMI. A small gate resistor (10-100 ohm) in series with the gate drive would reduce switching speed and associated emissions.

AI-Assisted — Several cross-cutting EMC and ESD concerns span multiple connectors and subsystems.

First, the design has no dedicated ESD protection on any connector. The USB Type-C port (J1) is the highest-risk interface as it is consumer-facing and must meet IEC 61000-4-2 Level 2 minimum (±4 kV contact, ±8 kV air). The SMA antenna connector (J7) is the second highest risk due to antenna exposure. The screw terminals and servo connectors present moderate risk depending on cable lengths and accessibility.

Second, the single GND domain means all ESD energy entering any connector is shared across the entire ground plane. There is no isolation between sensitive analog circuits (BMP388 pressure sensor U3, ICM-42688-P IMU U10, ADXL375 accelerometer U4) and connector ground pins. An ESD strike on J1 will cause ground bounce visible to all analog sensors. The ferrite bead FB1 on the +3.3VA rail provides some power-side isolation for U1 VDDA, but the ground side is common.

Third, the ADXL375 accelerometer (U4) has its VS (sensor supply) pin filtered through a 33 ohm resistor (R16) from +3.3V with two capacitors (C27 10 µF tantalum, C28 0.1 µF ceramic) to GND. This RC filter provides good high-frequency noise rejection for the sensor supply. The BMP388 (U3) and ICM-42688-P (U10) share the main +3.3V rail with no individual filtering beyond the bulk decoupling already on the rail.

Fourth, the crystal oscillator circuit (ABM8-16Mhz-B2-T1) uses 26 pF load capacitors (C12, C13) on HSE_IN and HSE_OUT. The crystal ground pins (pins 2 and 4) are on GND. No guard ring or isolation is captured in the schematic, but this is a layout concern. The 16 MHz crystal and its harmonics (32 MHz, 48 MHz, etc.) are common sources of radiated emissions; proper layout with short traces and ground plane under the crystal is essential.

Fifth, the W25Q128JVSIQ flash memory (U5) has its /WP and /HOLD pins pulled high to +3.3V through 10 kohm resistors (R5, R6). These are on-board signals with no connector exposure, so ESD is not a concern for these lines.

Sixth, the RGB LED (D1, ASMB-KTF0-0A306) is driven through resistors R7 (91 ohm), R8 (24 ohm), and R9 (47 ohm) from MCU GPIO pins PB15, PB14, and PB13. If the LED is visible through an opening in the enclosure, the light pipe or window does not create an ESD exposure path, so no protection is needed for the LED circuit.

Seventh, the buzzer (LS1, CMI-9705-0580-SMT-TR) is driven through NPN transistor Q1 (BC817) with a 1 kohm base resistor (R10) from MCU pin PC13. The flyback diode D4 (US1M) clamps the inductive kickback from the buzzer coil. This is an on-board component with no connector exposure.

AI-Assisted —

Connector	Finding	Risk
J1 (USB Type-C)	No ESD protection (TVS) on USB D+/D- lines. STM32F405 internal ESD rating (~2 kV HBM per STMicroelectronics datasheet DS9716) is insufficient for IEC 61000-4-2 system-level requirements (±4 kV contact, ±8 kV air). A dedicated USB ESD protection device is strongly recommended.	High
J7 (SMA Antenna)	No ESD protection on the 868 MHz antenna line between J7 and U9 (RFM95W). External antennas are exposed to ESD per IEC 61000-4-2. A low-capacitance TVS (sub-0.5 pF) or GDT is recommended to protect the RF front end.	High
J1 (USB Type-C)	No ESD protection on CC1 and CC2 pins. 5.1 kohm pull-down resistors (R3, R4) provide current limiting but no voltage clamping. Per USB Type-C specification, CC pins are exposed to user contact during cable insertion.	Medium
J1 (USB Type-C)	No TVS or surge protection on VBUS. Schottky diode D12 (SS14) provides reverse blocking but is not rated for IEC 61000-4-5 surge. TPS563200 input (U17 VIN) is exposed to VBUS transients.	Medium
J1 (USB Type-C)	No common-mode choke on USB D+/D- lines. May cause radiated emissions failures per EN 55032 Class B in the 100-500 MHz range from USB 2.0 signal harmonics.	Medium
J1 (USB Type-C)	Shell/shield pin (SH) is on the logic GND net with no dedicated SHIELD_GND net. The schematic does not capture shield bonding design intent for either plastic enclosure (direct bond) or metal chassis (R||C isolation) scenarios per IEC 61000-4-2 best practices.	Medium
J7 (SMA Antenna)	No harmonic filter between U9 (RFM95W) and J7. Spurious emissions may exceed ETSI EN 300 220-1 limits for 868 MHz Short Range Devices. A low-pass or SAW filter is typically required.	Medium
J4-J6, J8-J11 (Pyro Screw Terminals)	No TVS or ESD clamping on pyro output terminals. US1M diodes provide flyback protection but are too slow (~75 ns recovery per Vishay US1M datasheet) for ESD transient clamping. Risk depends on cable length and accessibility during handling.	Medium
M1-M4 (Servo Connectors)	No filtering or ESD protection on PWM signal lines (SERVO1-SERVO4) connecting directly to STM32F405 timer pins (PC6-PC9). Servo cables act as antennas; series ferrite beads or resistors at the connector would reduce emissions.	Medium
M1-M4 (Servo Connectors)	Servo power (VBAT+_PYRO) shared with pyrotechnic circuits. No local decoupling at servo connectors. Pyro firing transients and servo stall currents will mutually interfere on the shared rail.	Medium
All Connectors	Single GND domain with no chassis/earth ground separation. All ESD energy from any connector is distributed across the entire ground plane, affecting sensitive analog sensors (U3 BMP388, U4 ADXL375, U10 ICM-42688-P). Ground bounce from ESD events may cause sensor measurement errors.	Medium
J13 (Pyro Screw Terminal)	No TVS protection on the switched VBAT+_PYRO output through Q5 (AO3401A). Inductive load switching without fast clamping may generate conducted emissions on attached cables.	Low
J3 (JST SH 4-pin)	No ESD protection on level-shifted signals (U16 LSF0102DCUR outputs) or UART. Classified as internal connector; acceptable if cable length is under 10 cm and connector remains inside enclosure. 1 kohm series resistors (R40, R41) on the level-shifted lines provide limited current limiting.	Low
J12 (JST SH 4-pin)	No ESD protection or series resistance on UART5_TX (PC12) and UART5_RX (PD2) lines. These MCU pins are directly exposed to the connector. If J12 connects to an external module via cable, TVS protection is warranted per IEC 61000-4-2.	Low
J2 (SWD Debug Header)	No ESD protection on SWDIO (PA13) or SWCLK (PA14). Acceptable for a development-only debug port that is depopulated or covered in production. If accessible in the final product, low-capacitance TVS diodes are advisable.	Low
J7 (SMA Antenna)	SMA connector shell (J7 pin 2) is connected to GND, providing correct RF ground return for the coaxial interface.	✓
U1 (STM32F405)	VDDA (pin 13) is filtered from +3.3V through ferrite bead FB1 (100 ohm) with 10 nF (C7) and 1 µF (C8) decoupling on the +3.3VA rail. This meets STMicroelectronics AN4488 recommendations for analog supply filtering.	✓
U1 (STM32F405)	VCAP_1 (pin 31) and VCAP_2 (pin 47) each have a 2.2 µF ceramic capacitor (C51, C11) to GND. This meets the STM32F405 datasheet DS9716 requirement of 2.2 µF on each VCAP pin.	✓
U4 (ADXL375)	VS supply pin filtered through 33 ohm resistor (R16) with 10 µF tantalum (C27) and 0.1 µF ceramic (C28) decoupling. This RC filter provides good noise rejection per Analog Devices ADXL375 datasheet recommendations.	✓
J1 (USB Type-C)	CC1 and CC2 pull-down resistors R3 and R4 (5.1 kohm each to GND) correctly identify the port as a UFP per USB Type-C specification R2.5 Table 4-25.	✓