caiman Design Analysis

Job 0f916018

1 Design Summary

out of 100

Depth of review, as a baseline: 306 verified datasheet parameters applied and 241 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

Design Type	Flat (1 sheets)
Total Components	125
Total Pins	541
Total Nets	94
Total Test Points	0
Not Fitted (DNP)	6

Improve your score:

Correct reversed polarized capacitors +5
Add I2C pull-up resistors +4
One life-cycle error +1
Improve JTAG/I2C/SPI bus accessibility +1
Add ordering part numbers to resistors, inductors and capacitors +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1
Improve solder-joint testability (opens/shorts) +1

Points deducted for open High/Medium AI findings:

3 High, 5 Medium -8.5

AI findings to review:

Power findings — 1 High, 2 Medium, 21 Review
Memory findings — 7 Review
Functional findings — 2 High, 3 Medium, 3 Low, 8 Review
EMC/ESD findings — 13 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 10 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — The caiman design is a single-sheet board built around a high-performance Arm Cortex-M7 microcontroller. Around it sit three inertial and environmental sensors, a 2.4 GHz radio, a microSD card socket, addressable RGB indicators and a Hall-effect switch. Power comes in through high-current XT-series connectors, passes reverse-battery protection, and is converted by two fixed-output synchronous buck regulators that generate the +5V and +3V3 rails.

Processing Subsystem

U7 is an STMicroelectronics STM32F765VI in a 100-pin LQFP. Per the STMicroelectronics datasheet (Datasheet), it offers:

- a core clock of up to 216 MHz, delivering 462 DMIPS;
- 2048 KB of flash and 512 KB of SRAM, including 128 KB of data TCM;
- three 12-bit ADCs at up to 2.4 Msps and two 12-bit DACs;
- UARTs at up to 12.5 Mbit/s and SPI at up to 54 Mbit/s.

The core regulator runs from the internal LDO, with external stabilisation on VCAP_1 and VCAP_2. Two 3.2 × 2.5 mm four-pad crystals, Y1 and Y2, provide the board's clock references.

Sensing

A shared I2C bus from U7 carries three sensors:

- U5, an LPS22HB barometric pressure sensor at address 0x5C. It covers 260 hPa to 1260 hPa with 24-bit pressure output.
- U6, an LIS2MDL three-axis magnetometer at address 0x1E, with a ±49.152 gauss range.
- U8, an LSM6DSO six-axis IMU at address 0x6A. It offers accelerometer ranges up to ±16 g, gyroscope ranges up to ±2000 dps, and a 9 KB FIFO.

All three are STMicroelectronics parts (source: Tomachie). U3, a Melexis US1881 omnipolar-latching Hall-effect switch with an open-drain output, provides magnetic position or event sensing.

Wireless and Storage

U9 is a Nordic nRF24L01+ 2.4 GHz transceiver controlled by U7 over SPI. Per the Nordic Semiconductor datasheet (Datasheet), it supports:

- air data rates from 250 kbps to 2 Mbps;
- output power up to 0 dBm;
- receive sensitivity down to -94 dBm.

Its RF port is brought out as a 50 Ω single-ended path to the U.FL connector J14. J13, a Hirose microSD socket with card detect, is served by the MCU's SDMMC controller in 4-bit mode.

User Indicators

Three SK6812 addressable RGB LEDs (D2, D3, D4) provide status indication; each has 256-level PWM per colour and a single-wire 800 kHz interface. U10, a TI SN74LV1T34 single-gate level-translating buffer, is fitted on the board.

Power Architecture

The board has five rails: +BATT, VCC, +5V, +3V3 and GND.

- +5V is generated by U1, a Diodes Inc. AP63205 fixed 5 V buck regulator, through L1 (source: Tomachie).
- +3V3 is generated by U2, an AP63203 fixed 3.3 V buck regulator, through L2. Per the Diodes Inc. datasheet (Datasheet), both regulators accept 3.8 V to 32 V input and deliver 2 A continuous at 1.1 MHz with ±6 % frequency spread spectrum.

Power enters through J7 (XT30), J8 (XT60 male) and J9 (XT60 female). Input protection is provided by:

- U4, a TI LM74700 reverse-battery ideal-diode controller, rated 4 V to 60 V operating (source: Tomachie);
- D1, a 600 W SMBJ33CA bidirectional TVS;
- DZ1, an MMSZ5245 15 V zener.

The power path also carries a P-channel MOSFET (Q1) and Q2, an AOS AON6262E 60 V, 40 A N-channel MOSFET with a typical RDS(on) of 4.8 mΩ at VGS 10 V (Datasheet).

Interfaces and Mechanical

Off-board connectivity uses JST-GH connectors:

- J2 and J5 are six-way; J2 carries UART7 together with the sensor I2C bus.
- J3 is four-way and carries UART4.
- J10 and J12 are four-way and extend the sensor I2C bus.
- J11 is four-way and carries a second, independent I2C controller.

Two three-way 2.54 mm headers, J1 and J4, complete the I/O. Four plated M4 mounting holes (H1 to H4) are connected to a board net.

Temperature Rating

The AP63203/AP63205, the sensors, the nRF24L01+ and the SK6812 are rated −40 °C to +85 °C ambient. The LM74700 and SN74LV1T34 extend to +125 °C. The STM32F765VI's temperature-grade digit is not fixed in the schematic: grade 6 covers −40 °C to +85 °C and grade 7 covers −40 °C to +105 °C at maximum dissipation. The board's operating range is therefore −40 °C to +85 °C.

1.2 Processed Sheets

#	Sheet Name
1	caiman.kicad_sch

1.3 Structured DNP (Not Fitted)

Parts marked do-not-populate at the part level, outside of assembly variants. They remain present in the netlist but are not assembled.

Status	RefDes	Part Type	Value	Footprint
DNP	J6	Conn_01x04_Pin	Conn_01x04_Pin	Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical
DNP	J15	Conn_01x03_Pin	Conn_01x03_Pin	Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
DNP	R25	2.2k	2.2k	Resistor_SMD:R_0402_1005Metric
DNP	R28	2.2k	2.2k	Resistor_SMD:R_0402_1005Metric
DNP	R29	2.2k	2.2k	Resistor_SMD:R_0402_1005Metric
DNP	R31	2.2k	2.2k	Resistor_SMD:R_0402_1005Metric

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
22 SMT footprints do not follow IPC-7351B naming
8 footprints (connectors, specialty) — compliance unknown

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	51	C45, C50, C16, C29, C25, C20, C15, C39 (+43 more)	✓
Resistors	Values in VALUE or Resistance	27	R8, R23, R4, R2, R18, R26, R10, R24 (+19 more)	✓
Inductors	Values in VALUE or Inductance	5	L5, L3, L1, L2, L4	✓
Crystals	Values in VALUE or Frequency	2	Y1, Y2	✓

2.1 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the MANUFACTURER part number. This check decodes the manufacturer part number and compares the two. A distributor catalogue number is a different thing and cannot be used here - an LCSC C-number or a Digi-Key -ND number identifies a stock item, it encodes no capacitance, voltage or tolerance, so there is nothing in it to check against. Where the two readings disagree both are shown and neither is assumed correct: if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose numbering scheme is not recognized are reported as not checked rather than passed.

83 of 83 fitted resistor/inductor/capacitor part(s) carry no ordering part number: C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, C13, C14, C15, C16, C17, C18, C19, C20 (+63 more). Without a part number the BOM cannot state what to buy, and none of the part-number cross-checks in this section can run for these parts. Add a manufacturer part number to each part in the library.

2.2 Capacitor Derating Check

Derating profile	Benign (controlled office)
Maximum ambient	40 °C
Checks performed	0

A capacitor is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Every other derating check - for capacitors and for every other part class - is applied by the AI analysis within its report sections.

25 part(s) sit across a resolved power rail with no stated voltage rating and could not be checked: C11, C22, C23, C25, C26, C27, C3, C30, C31, C32, C33, C34, .... Record each rating in a Voltage property.

Derating Settings Used in This Analysis
Parameter	Value	Source	Applied
capacitor_voltage_pct	30% (70)	Quanterion 2nd ed. Table 2.3-1 p37 / Table 3.1-4 p49 - ceramic film mica glass	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_voltage_pct	20% (80)	Quanterion 2nd ed. Table 2.3-1 p37	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_mno2_voltage_pct	50% (50)	Quanterion 2nd ed. Table 2.3-1 p37 standard-process MnO2	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	20% (80)	Quanterion 2nd ed. Table 2.3-1 p37 polymer / enhanced MnO2 / niobium	Applied by the AI analysis where the rating is in evidence
capacitor_ripple_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	not stated by this scheme	Not applied - the AI is not given this parameter
capacitor_temperature_margin_c	10 °C	Quanterion 2nd ed. Table 2.3-1 p37 Tmax-10 (ceramic film)	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_temperature_margin_c	20 °C	Quanterion 2nd ed. Table 2.3-1 p37 Tmax-20	Applied by the AI analysis where the rating is in evidence
resistor_power_pct	30% (70)	Quanterion 2nd ed. Table 2.3-1 p41 film chip	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	not stated by this scheme	Not applied - the AI is not given this parameter
resistor_temperature_margin_c	24 °C	Quanterion 2nd ed. Table 2.3-1 p41 film chip Tmax-24	Applied by the AI analysis where the rating is in evidence
inductor_continuous_current_pct	10% (90)	Quanterion 2nd ed. Table 3.12-3 p113 inductor current (DC) 90 % (Severe); s3.12.4 p113 90 % for all magnetics when the hot-spot temperature is not known	Applied by the AI analysis where the rating is in evidence
inductor_surge_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 magnetics surge <100 %	Not applied - the AI is not given this parameter
inductor_continuous_voltage_pct	10% (90)	Quanterion 2nd ed. s3.12.4 p113 90 % for all magnetics when the hot-spot temperature is not known	Applied by the AI analysis where the rating is in evidence
inductor_surge_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 voltage surge <100 %	Not applied - the AI is not given this parameter
inductor_dielectric_withstand_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	not stated by this scheme	Not applied - the AI is not given this parameter
inductor_temperature_margin_c	25 °C	Quanterion 2nd ed. Table 2.3-1 p39 hot spot Tmax-25	Applied by the AI analysis where the rating is in evidence
diode_reverse_voltage_pct	20% (80)	Quanterion 2nd ed. Table 2.3-1 p38 / Table 3.5 p88	Applied by the AI analysis where the rating is in evidence
diode_average_forward_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p38 forward current <100 %	Not applied - the AI is not given this parameter
diode_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p38 HF / Schottky / PIN / TVS rows <100 %	Not applied - the AI is not given this parameter
diode_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. Table 3.20-4 p174 formula 0.75(Tjmax-25)+20 = 115 C at 150 C	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. Table 2.3-1 p38 Tj 115 C	Applied by the AI analysis where the rating is in evidence
zener_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p38 regulator / reference diodes PD <100 %	Not applied - the AI is not given this parameter
zener_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. as diodes	Applied by the AI analysis where the rating is in evidence
zener_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. as diodes	Applied by the AI analysis where the rating is in evidence
mosfet_vds_pct	20% (80)	Quanterion 2nd ed. Table 3.20-4 p174 breakdown VDS	Applied by the AI analysis where the rating is in evidence
mosfet_vgs_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - VGS not listed	Not applied - the AI is not given this parameter
mosfet_continuous_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - no current row for transistors	Not applied - the AI is not given this parameter
mosfet_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 3.20-4 p174 PD <100 %	Not applied - the AI is not given this parameter
mosfet_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. Table 3.20-4 p174 formula (115 C at 150 C)	Applied by the AI analysis where the rating is in evidence
mosfet_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. Table 3.20-4 p174	Applied by the AI analysis where the rating is in evidence
bjt_vce_pct	20% (80)	Quanterion 2nd ed. Table 3.20-4 p174 breakdown VCE	Applied by the AI analysis where the rating is in evidence
bjt_continuous_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - no current row for transistors	Not applied - the AI is not given this parameter
bjt_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 3.20-4 p174 PD <100 %	Not applied - the AI is not given this parameter
bjt_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. as MOSFET	Applied by the AI analysis where the rating is in evidence
bjt_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. as MOSFET	Applied by the AI analysis where the rating is in evidence
regulator_input_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - microcircuits carry no supply-voltage row	Not applied - the AI is not given this parameter
regulator_output_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 linear microcircuits output current <100 %	Not applied - the AI is not given this parameter
regulator_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 linear PD <100 %	Not applied - the AI is not given this parameter
regulator_junction_temperature_margin_c	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 3.14-3 p122 states one fixed junction figure and no margin below the maximum of the part	Not applied - the AI is not given this parameter
regulator_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. Table 3.14-3 p122 linear microcircuits Tj 115 C whatever the rating of the part	Applied by the AI analysis where the rating is in evidence
ic_output_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 output / drive current <100 %	Not applied - the AI is not given this parameter
ic_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 2.3-1 p39 linear PD <100 %	Not applied - the AI is not given this parameter
ic_junction_temperature_margin_c	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. Table 3.14-3 p122 states one fixed junction figure and no margin below the maximum of the part	Not applied - the AI is not given this parameter
ic_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. Table 3.14-3 p122 digital and linear microcircuits Tj 115 C whatever the rating of the part (VHLSI 85 C not carried)	Applied by the AI analysis where the rating is in evidence
connector_current_per_contact_pct	15% (85)	Quanterion 2nd ed. Table 2.3-1 p37	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	Quanterion 2nd ed. - stated as % of dielectric withstand (80 %) not of working voltage	Not applied - the AI is not given this parameter
connector_temperature_margin_c	25 °C	Quanterion 2nd ed. Table 2.3-1 p37 insert Tmax-25	Applied by the AI analysis where the rating is in evidence
tvs_junction_temperature_margin_c	35 °C	Quanterion 2nd ed. as diodes	Applied by the AI analysis where the rating is in evidence
tvs_junction_temperature_cap_c	115 °C	Quanterion 2nd ed. as diodes	Applied by the AI analysis where the rating is in evidence

2.3 Part Lifecycle and Silicon Errata

Status as found on the manufacturer's website by the AI enrichment run, on the date shown; the page read is linked. Silicon errata: whether the manufacturer publishes an errata sheet for the part - its presence only. No errata document is read or analysed, and no action is implied by its existence.

Item	Lifecycle	Silicon errata	Status
U9 (nRF24L01P)	Not recommended for new designs, as of 2026-10-02	None found on the manufacturer's website, as of 2026-10-02	High
D1 (SMBJ33CA)	There isn't a life-cycle marking on the datasheet obtained 2026-10-09	—
D2, D3, D4 (SK6812)	There isn't a life-cycle marking on the datasheet obtained 2026-08-24	—
DZ1 (MMSZ5245)	There isn't a life-cycle marking on the datasheet obtained 2026-10-02	—
Q2 (AON6262E)	Active, as of 2026-10-02	—
U1 (AP63205WU)	There isn't a life-cycle marking on the datasheet obtained 2026-10-02	Not determined
U2 (AP63203WU)	There isn't a life-cycle marking on the datasheet obtained 2026-10-02	Not determined
U3 (US1881)	Active, as of 2026-10-02	None found on the manufacturer's website, as of 2026-10-02
U4 (LM74700)	Active, as of 2026-10-16	None found on the manufacturer's website, as of 2026-10-16
U5 (LPS22HBTR)	Active, as of 2026-10-02	None found on the manufacturer's website, as of 2026-10-02
U6 (LIS2MDLTR)	Active, as of 2026-10-02	None found on the manufacturer's website, as of 2026-10-02
U7 (STM32F765VITx)	There isn't a life-cycle marking on the datasheet obtained 2026-10-02	Errata sheet published: STM32F76xxx and STM32F77xxx device errata
U8 (LSM6DSO)	Active, as of 2026-10-16	None found on the manufacturer's website, as of 2026-10-16
U10 (SN74LV1T34DBV)	Active Production, as of 2026-10-02	None found on the manufacturer's website, as of 2026-10-02

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

21 unconnected pin(s) found:

21 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
D4_4	DOUT	Output	SK6812	Net-(D4-DOUT)
J5_2	Pin_2	Passive	Conn_01x04_Pin	TX1
J5_3	Pin_3	Passive	Conn_01x04_Pin	RX1
R16_2	~	Passive	22 ohm	SWDIO
R17_2	~	Passive	22 ohm	SWCLK
R18_2	~	Passive	22 ohm	SWO
U5_7	INT_DRDY	Bidirectional	LPS22HBTR	BAR_INT
U6_2	NC	Unknown	LIS2MDLTR	-	No net
U6_7	INT/DRDY/SDO	Bidirectional	LIS2MDLTR	MAG_INT
U6_11	NC	Unknown	LIS2MDLTR	-	No net
U6_12	NC	Unknown	LIS2MDLTR	-	No net
U7_51	PB12	Bidirectional	STM32F765VITx	UART5_RX
U7_52	PB13	Bidirectional	STM32F765VITx	UART5_TX
U7_53	PB14	Bidirectional	STM32F765VITx	USART1_TX
U7_54	PB15	Bidirectional	STM32F765VITx	USART1_RX
U7_55	PD8	Bidirectional	STM32F765VITx	USART3_TX
U7_56	PD9	Bidirectional	STM32F765VITx	USART3_RX
U7_97	PE0	Bidirectional	STM32F765VITx	UART8_RX
U7_98	PE1	Bidirectional	STM32F765VITx	UART8_TX
U8_4	INT1	Output	LSM6DSO	IMU_INT
U10_1	NC	Unknown	SN74LV1T34DBV	-	No net

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden pins of any electrical type stacked behind visible pins in the symbol.

Implied Net Connections
Component	Type	Pin	Net	Status
U7	STM32F765VITx	26 (VSS)	GND	Fail — hidden pin not visible on schematic
U7	STM32F765VITx	49 (VSS)	GND	Fail — hidden pin not visible on schematic
U7	STM32F765VITx	74 (VSS)	GND	Fail — hidden pin not visible on schematic
U7	STM32F765VITx	99 (VSS)	GND	Fail — hidden pin not visible on schematic

3.3 Open-Collector Pull-up Audit

Examined 0 candidate pin(s) on 0 net(s).

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation	Severity
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires pin 1, the cathode, on the left with the footprint at zero rotation. Tomachie calls out symbols that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, initial ATE test generation from a netlist of only pins 1 and 2 will fail, or a novice may wrongly indict a correct part — consistency is the least-expensive path for everyone who handles the PCB.
D1 SMBJ33CA bidirectional · symbol_graphic	Pin 1 (K): GND Pin 2 (A): Net-(D1-A)	Description says bidirectional, but the symbol has anode/cathode (A/K) pins — verify part/symbol	Medium
DZ1 MMSZ5245 unidirectional · pin_names	Pin 1 (K): +BATT Pin 2 (A): Net-(DZ1-A)	Consistent
D2 SK6812 array · multi-pin	Pin 1 (VSS): GND Pin 2 (DIN): Net-(D2-DIN) Pin 3 (VDD): +5V Pin 4 (DOUT): Net-(D2-DOUT)	4-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.	Information
D4 SK6812 array · multi-pin	Pin 1 (VSS): GND Pin 2 (DIN): Net-(D3-DOUT) Pin 3 (VDD): +5V Pin 4 (DOUT): Net-(D4-DOUT)	4-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.	Information
D3 SK6812 array · multi-pin	Pin 1 (VSS): GND Pin 2 (DIN): Net-(D2-DOUT) Pin 3 (VDD): +5V Pin 4 (DOUT): Net-(D3-DOUT)	4-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.	Information

3.5 Polarized Capacitor Orientation

Capacitor	Connections	Polarity	Severity
Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
C48	Pin 1 (+): +5V Pin 2: GND
C11	Pin 1 (+): GND Pin 2: +BATT	Pin 1 is the positive terminal per IPC-7351B/7251 (square pad, silkscreen "+") but it is on GND — the assembled part will be reversed. The symbol most likely draws "+" on pin 2; correct it so pin 1 is positive.	High

3.6 Power Symbols That Connect Nothing

1 power symbol placement(s) connect nothing: the placed symbol has no library definition in the schematic file, or its definition has no power pin. A power symbol joins all same-named rails across the design; an inert one leaves them separate. Where the last column lists more than one net, those nets were meant to be one rail and are NOT connected. Restore the power symbol's library definition (re-place it from a maintained library) and verify the rails merge.

Power Net	Library Cell	Placements	Nets Left Separate
Logo_Open_Hardware_Large	Graphic:Logo_Open_Hardware_Large	1 (caiman.kicad_sch)	-

3.7 Checks Not Performed

Items this report did not check, with the reason. None of these is a finding against the design - an item that was not checked says nothing about it either way.

Note 3: The figure these checks need was not taken from the part's datasheet, so they were not performed. This is a limitation of the analysis, not a finding on the design.

Checks the AI review could not perform are listed at Review severity in each AI section's Findings table, each naming the input that was missing.

Item	Not checked	Notes
Part Number vs Stated Values	The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.
Capacitors and resistors (datasheets and parameter curves)	Datasheets for capacitors and resistors, and the parameter curves they carry (ripple current, derating against temperature, DC bias, a jumper's temperature rise), are obtained on the premium tier only. This standard-tier run reads a datasheet already on file and otherwise states no rating for these parts. The exception is a capacitor on a regulator's input or output rail: this tier obtains its datasheet and curves as well.
U1 (AP63205WU)	Loop stability limit with 470 µF electrolytic in parallel with the ceramic output capacitors (maximum output capacitance and ESR range for internal compensation)	See note 3
D1 (SMBJ33CA)	Breakdown voltage against the J7 charge-input voltage (VBR minimum for the 33CA variant)	See note 3
U7 (STM32F765VITx)	SDMMC peripheral alternate-function assignment of PC8, PC9, PC10, PC11, PC12 and PD2 (alternate function mapping table)	See note 3
U7 (STM32F765VITx)	Maximum SDMMC clock frequency against the card bus speed (SDMMC_CK maximum frequency)	See note 3
U8 (LSM6DSO)	I2C slave address selected by SDO/SA0 tied to GND, and its uniqueness on I2C2 (7-bit I2C address for SA0 = 0)	See note 3
U6 (LIS2MDLTR)	I2C slave address and its uniqueness on I2C2 (7-bit I2C address)	See note 3
U7 (STM32F765VITx)	BOOT0 level that selects boot from main flash (BOOT0 boot-mode table)	See note 3
U7 (STM32F765VITx)	ESD robustness of PD12, PD13, PB6, PB7, PB10, PB11, PA11, PA12, PE7 and PE8 against discharges entering unprotected on J1, J2, J3, J4, J10, J11 and J12 (ESD HBM/CDM rating of I/O pins)	See note 3
U7 (STM32F765VITx)	Current into U7_16 PC1 through R6 100 kΩ during transients on J7, and series resistor sizing on the unprotected connector pins (Injected current limit IINJ per I/O pin)	See note 3
U9 (nRF24L01P)	Withstand of U9_12 ANT1 and U9_13 ANT2 to discharges coupled from J14 through C38 (ESD HBM rating of the RF pins)	See note 3

3.8 Summary

Total NO_ERC markers in design	51
Pins needing attention (warnings)	21
Pins for information only	0

4 Power Overview

Power rails	5
Power management sources identified	5

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
Rail	Voltage	Source	Consumers
+5V	5.00V	U1 AP63205WU	U10 (SN74LV1T34DBV), U2 (AP63203WU)
+3V3	3.30V	U2 AP63203WU	U5 (LPS22HBTR), U6 (LIS2MDLTR), U8 (LSM6DSO), U9 (nRF24L01P)
+BATT	-	J8 External	U3 (US1881), U4 (LM74700)
GND	-	U8 LSM6DSO	-
VCC	-	J9 External	U1 (AP63205WU)

4.1.1 Rail Voltage Annotation

2 power input(s) into this board were identified - the supplies it takes in at a connector, a terminal or a module socket. Every part on and downstream of each one is judged against what it carries, so the analysis needs its full characterization: whether it is AC or DC, its nominal voltage, the band it operates over, and any level outside normal operation the design must survive.

The preferred way to state a rail's voltage is to record it in the design itself, where it travels with the schematic, survives every re-run, and can be read by anyone who opens the design: add VOLTAGE_NOM, VOLTAGE_MIN and VOLTAGE_MAX properties to the rail's net class directive, and VOLTAGE_EXCURSION_MAX for a survivable level outside normal operation.

You will be prompted to enter each input's nominal, minimum and maximum operating voltage - and, where one exists, the survivable excursion level - before the AI review starts.

Rail	Required information
+BATT	State whether this input is AC or DC, its nominal voltage, and the minimum and maximum it operates over. For example: DC, nominal 5.0 V, minimum 4.75 V, maximum 5.25 V; or for a battery, DC, minimum 3.0 V, maximum 4.2 V. If it can reach a higher sustained level outside normal operation - a charging overvoltage or a jump-start the design must survive but need not function at - state that separately as the excursion maximum; it is never treated as an operating voltage.
VCC	State whether this input is AC or DC, its nominal voltage, and the minimum and maximum it operates over. For example: DC, nominal 5.0 V, minimum 4.75 V, maximum 5.25 V; or for a battery, DC, minimum 3.0 V, maximum 4.2 V. If it can reach a higher sustained level outside normal operation - a charging overvoltage or a jump-start the design must survive but need not function at - state that separately as the excursion maximum; it is never treated as an operating voltage.

Rail

Required information

+BATT

State whether this input is AC or DC, its nominal voltage, and the minimum and maximum it operates over. For example: DC, nominal 5.0 V, minimum 4.75 V, maximum 5.25 V; or for a battery, DC, minimum 3.0 V, maximum 4.2 V. If it can reach a higher sustained level outside normal operation - a charging overvoltage or a jump-start the design must survive but need not function at - state that separately as the excursion maximum; it is never treated as an operating voltage.

VCC

4.2 Regulator Enable Pull Resistors

3 regulator enable pin(s) examined for what drives them and which way they are pulled. 0 pulled toward the enabling level while a power output drives the net.

	Finding	Severity
RegulatorU2 [AP63203WU] Enable pinU2_2 (EN) (enabled high) Net+5V Driven by- Pull-up- Pull-down-	The enable is wired to +5V; the regulator is always enabled.	Information
RegulatorU4 [LM74700] Enable pinU4_3 (EN) (enabled high) NetNet-(D1-A) Driven byJ7_2 (Pin_2), R6 -> VCHG Pull-up- Pull-down-	Driven by the pins listed; no pull resistor is fitted.	Information
RegulatorU1 [AP63205WU] Enable pinU1_2 (EN) (enabled high) NetNet-(U1-EN) Driven by- Pull-upR1 100k -> VCC Pull-down-	No driver on the net; the pull resistor sets the level.	Information

4.3 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.3.1 Power Tree Overview

AI-Assisted — The battery enters on J8 (XT60) as +BATT. A charger plugged into J7 (XT30) reaches +BATT through an ideal-diode stage: U4 (LM74700) drives N-channel MOSFET Q2 (AON6262E). The bidirectional TVS D1 (SMBJ33CA) and C9 (0.1 µF) sit on the J7 side, on net Net-(D1-A).

+BATT feeds the Hall switch U3 (US1881), the R4/R5 battery-sense divider into U7_15 PC0, and the source of P-channel MOSFET Q1. Q1 is the magnetic on/off switch. Its drain is VCC, which leaves the board on J9 (XT60, ESC power) and feeds U1 (AP63205WU, fixed 5 V buck).

+5V supplies the SK6812 LEDs D2 to D4, the level shifter U10, the off-board headers J2, J3 and J5, and the input of U2 (AP63203WU, fixed 3.3 V buck). +3V3 supplies U5, U6, U8, U9, the SD socket J13 and the I2C headers J10 to J12. It is also intended to supply the MCU U7, but those supply pins are not connected to it (see the MCU supply subsection). The charge input is sensed by R6/R7 into U7_16 PC1.

Neither the battery voltage on +BATT/VCC nor the charger voltage on J7 is stated anywhere in the schematic. Every rating on those nets therefore remains open. No series fuse is drawn on J8 or J7; that protection is expected in the battery lead and the charger harness.

The power-up order is:
Battery connected at J8: +BATT rises, U3 is powered, and R3 holds Q1 off.
Magnet present: U3_3 sinks Net-(DZ1-A), Q1 turns on, and VCC and J9 come up.
U1_2 EN is already high through R1 and its internal pull-up. U1 starts above its 3.5 V typical rising UVLO and ramps +5V over its 4 ms soft-start.
U2 has EN and VIN both on +5V. It starts once +5V passes its 3.70 V maximum rising UVLO, which is during U1's soft-start, and ramps +3V3 over 4 ms.

4.3.2 Charge Input Ideal Diode (U4, Q2, D1)

AI-Assisted — U4 ANODE and EN share Net-(D1-A), so the controller is always enabled when a charger is present. The LM74700 datasheet (Texas Instruments, source: Tomachie) shows EN tied to ANODE for always-on operation.

Q2 is oriented as the datasheet requires: its source is on ANODE, its drain on CATHODE (+BATT) and its gate on GATE. Its body diode therefore conducts from J7 toward the battery. When the charger is removed or shorted, U4 blocks reverse current from the battery within 0.75 µs maximum.

The gate drive sits at VCAP minus ANODE. It is capped by the charge-pump turn-off level of 13.9 V maximum, below the AON6262E VGS rating of ±20 V (Alpha & Omega datasheet). This also satisfies the LM74700 requirement for a MOSFET VGS rating of at least 15 V.

C10 (0.1 µF) runs from VCAP to ANODE. That meets the 0.1 µF minimum and is well above 10 × Ciss: AON6262E Ciss is 1650 pF, so 10 × Ciss is 16.5 nF. C9 (0.1 µF) exceeds the 22 nF minimum input capacitance, and C11 (47 µF) on CATHODE exceeds the 0.1 µF minimum output capacitance.

D1 is the optional SMBJ33CA shown in the datasheet's 12 V application, placed at the point of entry on J7. The protected parts tolerate the following: U4 ANODE to ground ±65 V absolute maximum, and Q2 VDS 60 V. The SMBJ33CA clamping voltage is not in the data. D1 is a bidirectional part drawn with a symbol that uses anode/cathode pin names; either orientation is electrically correct.

Q2 conduction loss and junction temperature need the charge current through J7, which the schematic does not state.

4.3.3 Magnetic Power Switch (Q1, U3, DZ1)

AI-Assisted — Q1 is a high-side P-channel switch. R3 (10 kΩ) ties the gate net Net-(DZ1-A) to +BATT, which holds Q1 off. U3 OUTPUT is an open-drain stage that pulls the gate net low when a magnetic field is present. The 10 kΩ pull-up matches the US1881 typical application (Melexis datasheet, page 10).

DZ1 (MMSZ5245, 15 V) has its cathode on +BATT (the source) and its anode on the gate. That orientation is consistent and limits Q1 VGS to the zener voltage: 14.25 to 15.75 V at 8.5 mA (onsemi datasheet).

While U3 is asserted, VGS equals +BATT minus U3's output saturation of 0.5 V maximum at 20 mA. Nothing limits current between DZ1 and U3_3. If +BATT exceeds 14.25 V, DZ1 conducts from +BATT directly into the U3 output, and the current is bounded only by that output stage. U3's absolute maximum output current is 50 mA. Whether this happens depends on the battery voltage, which is not stated.

Q1 carries no part number, so its VDS, VGS and drain-current ratings are unknown. That matters because Q1 carries the whole ESC current on J9 as well as U1's input.

U3 is powered from +BATT at all times. Its recommended supply range is 3.5 to 24 V (absolute maximum 28 V), and it draws up to 5 mA permanently, whether Q1 is on or off. Its only bypass is the 47 µF electrolytic C11; the datasheet application circuit places 100 nF close to the device.

R2 (15 kΩ, VCC to GND) bleeds VCC and J9 down once Q1 opens.

4.3.4 AP63205WU 5 V Buck (U1)

AI-Assisted — U1_3 IN is on VCC and U1_4 GND is on GND, so both have a DC path. FB senses +5V directly, as the fixed-output part requires, giving 4.95 to 5.05 V (Diodes Inc. AP63205 datasheet, source: Tomachie, page 5).

C1 (100 nF) is connected between BST and SW as required. L1 is 3.3 µH, inside the datasheet's approximate 2.2 to 10 µH range; Table 3 uses 4.7 µH.

The only input capacitor is C3, 10 µF in 0603, equal to the Table 3 value. The text recommends more than 10 µF for most applications. C3's voltage rating is not stated, and its DC-bias loss at the unknown battery voltage is not applied.

The output capacitance on +5V is 2 × 22 µF plus 10 µF ceramic, plus the 470 µF electrolytic C48, plus 4 × 0.1 µF, for 524.4 µF nominal. DC-bias loss on the ceramics is not applied. The datasheet calls 22 to 68 µF ceramic sufficient for most applications and states no upper limit. However, the LC corner moves from about 13.2 kHz (3.3 µH with 44 µF) to about 3.8 kHz with C48 fitted. The internally compensated loop has not been characterised with that capacitance.

Soft-start current into the output is 524.4 µF × 5 V / 4 ms = 0.66 A, well below the 2.5 A minimum high-side current limit.

The known +5V load is about 0.155 A:
- U2 input current, 0.152 A, using U2's estimated 90 % efficiency.
- SK6812 static current, 3 × 1 mA.

This excludes the LED colour drive current and the off-board loads on J2, J3 and J5. The total is well inside the 2 A rating. U1's dissipation, its inductor ripple and L1's peak current all depend on the VCC input voltage, which is not stated.

4.3.5 AP63203WU 3.3 V Buck (U2)

AI-Assisted — U2_3 IN is on +5V and U2_4 GND is on GND. EN sits on +5V for automatic start-up, and FB senses +3V3 directly, giving 3.27 to 3.33 V (Diodes Inc. datasheet, page 5). C2 (100 nF) is connected between BST and SW.

The input on +5V has C6 (10 µF) plus C4 and C5 (22 µF each) and C48. That covers the 10 µF reference input capacitor.

L2 is 2.2 µH, where Table 2 uses 3.9 µH. At 5 V in, 3.3 V out and 1.1 MHz, the ripple is ΔIL = 3.3 × (1 − 3.3/5) / (2.2 µH × 1.1 MHz) = 0.464 A peak-to-peak. With 3.9 µH it would be 0.262 A.

The output capacitance (caps_to_gnd) totals 74.111 µF nominal, mostly C7 and C8 (22 µF each) and C30 and C44 (10 µF each). That is above the datasheet's 22 to 68 µF sufficiency range; DC-bias loss is not applied.

The known +3V3 load is about 0.207 A, assuming U7 is rewired:
- U7: 193 mA typical at 216 MHz with all peripherals enabled.
- U9: 13.5 mA in RX.
- U8: 0.55 mA.
- U6: 0.2 mA.
- U5: 12 µA.

This excludes the SD card on J13 and the modules on J10 to J12. L2's peak current is then 0.207 + 0.232 = 0.44 A.

The manufacturer's example curve (VIN = 12 V, VOUT = 3.3 V, AP63200, page 6) reads 90.0 % efficiency at 0.207 A. That gives about 76 mW of loss. With θJA of 89 °C/W, the estimated junction temperature is 40 + 6.8 = 46.8 °C.

4.3.6 MCU Supply Connection and Load Decoupling

AI-Assisted — Every U7 supply pin other than VCAP is wired in series with its decoupling capacitor instead of having the capacitor shunted to ground:
- U7_50 VDD connects only to C12 pin 1, whose pin 2 is on +3V3.
- U7_27, U7_11, U7_100 and U7_75 have the same arrangement through C13, C15, C16 and C18.
- U7_21 VDDA connects through C14.
- U7_6 VBAT connects through C17.
- U7_20 VREF+ connects through C19 and C21.

None of these pins has a DC path to any supply, so the STM32F765 receives no power. Its only connection to +3V3 is through the pull-ups on its I/O, such as R8 on NRST. The fix is to tie each pin net to +3V3 and return the capacitor's other terminal to GND. That arrangement gives the 100 nF per VDD/VSS pair called for in the STMicroelectronics datasheet (Datasheet, page 106).

After that rework, VDDA would have only C14. The datasheet lists 100 nF plus 1 µF between VDDA and VSSA, and the 1 µF part on the board (C21) is placed on VREF+. VCAP_1 and VCAP_2 are correct: each has 2.2 µF to GND (C42, C45).

The other loads meet their datasheet decoupling:
- U9 has 10 nF (C33) and 1 nF (C34) on +3V3, with 4.7 µF bulk available on the rail. DVDD has 33 nF (C41). VDD_PA has 2.2 nF (C35) and 4.7 pF (C36), matching the Nordic reference circuit (Datasheet).
- U6 has 220 nF (C29) on C1.
- U5, U6 and U8 share the 100 nF parts on +3V3.
- The four 0.1 µF capacitors on +5V (C47, C49, C50, C51) provide the 100 nF per SK6812 shown in that datasheet's application circuit.

4.4 Observations

AI-Assisted — The decisive defect is the series-wired MCU decoupling, which leaves U7 unpowered; nothing on the board works until it is corrected.

The second structural gap is that no battery voltage or charger voltage is stated. These parts can only be judged once that voltage is known:
- U3: 24 V recommended supply.
- U1: 32 V recommended input (35 V absolute maximum).
- Q2: 60 V VDS, which is 48 V under the Benign (controlled office) derating selected for this schematic analysis (mosfet_vds_pct = 80).
- DZ1: its 14.25 V minimum breakdown, which decides whether it conducts into U3 when Q1 is on.
- The two sense dividers: with a ratio of 0.2126 and VREF+ at 3.3 V, their full scale is 15.52 V.

No capacitor on the board carries a voltage rating. Under the selected derating:
- On +5V, a ceramic needs at least 7.2 V rating (5.05 V / 0.7), and the electrolytic C48 at least 6.3 V (5.05 V / 0.8). A 10 V or higher part covers both.
- On +3V3, a 6.3 V ceramic is sufficient.

VCC is exposed to ESC switching transients through J9, with only C3 and C11 as filtering. Q1 is a generic symbol with no part number, so it cannot be rated against the ESC current.

4.5 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.5.1	U7 (STM32F765VITx), C12, C13, C14, C15, C16, C17, C18, C19, C21	+3V3	U7_11, U7_27, U7_50, U7_75, U7_100 VDD, U7_21 VDDA, U7_6 VBAT and U7_20 VREF+ each sit on a net whose only other member is a capacitor plate; that capacitor's other plate is on +3V3. No supply pin has a DC path, so the MCU is unpowered. Rework: connect each pin net to +3V3 and move each capacitor's +3V3 plate to GND. This gives 100 nF per VDD/VSS pair (STMicroelectronics datasheet p.106).	High
4.5.2	+BATT, VCC (J8, J9)	+BATT, VCC	The battery voltage entering on J8 is not specified, so these ratings cannot be checked against it: Q2 VDS 60 V (48 V under mosfet_vds_pct = 80), U4 CATHODE 60 V recommended, U3 VDD 24 V recommended, U1 VIN 32 V recommended, and C3 and C11. Annotate +BATT with a net class stating the battery voltage.	Medium
4.5.3	Net-(D1-A) (J7)	Net-(D1-A)	The charger voltage entering on J7 is not specified, so these cannot be checked against it: D1 working voltage, U4 ANODE 60 V recommended, Q2, C9 and C10. Annotate the net with a net class stating the charge voltage.	Medium
4.5.4	U7 (STM32F765VITx)	+3V3	After the rework, VDDA has only C14 (100 nF). The datasheet (p.106) lists 100 nF plus 1 µF between VDDA and VSSA; the board's 1 µF part, C21, is placed on VREF+. Add 1 µF on VDDA.	Review
4.5.5	U1, C3	VCC	The input capacitor is C3, 10 µF in 0603. That equals the Table 3 value, while the text recommends more than 10 µF ceramic for most applications. Its voltage rating is not stated, and DC-bias loss at the unknown battery voltage is not applied.	Review
4.5.6	U1, C4, C5, C6, C48	+5V	Output capacitance is 2 × 22 µF + 10 µF ceramic + 470 µF electrolytic (C48) + 4 × 0.1 µF = 524.4 µF nominal, against the 22 to 68 µF ceramic the datasheet calls sufficient (p.14). C48 lowers the L1 output corner from about 13.2 kHz to about 3.8 kHz in an internally compensated loop. Measure the +5V load-step response with C48 fitted.	Review
4.5.7	U2, L2	+3V3	L2 is 2.2 µH; Table 2 of the AP63203 datasheet (p.13) uses 3.9 µH. Ripple is 3.3 × (1 − 3.3/5) / (2.2 µH × 1.1 MHz) = 0.464 A peak-to-peak, against 0.262 A with 3.9 µH.	Review
4.5.8	L1, L2	+5V, +3V3	Neither inductor states a current rating. Isat must be judged against the maximum high-side current limit of 3.1 A (AP63203/AP63205 datasheet p.5). The L2 peak at the known load is 0.44 A; the L1 peak depends on the VCC voltage. Add Isat and Irms properties.	Review
4.5.9	U1	VCC	Dissipation and junction temperature are not computed because the VCC input voltage is not stated.	Review
4.5.10	U2	+3V3	U2 is rated 2 A. The known load is 0.207 A: U7 193 mA once rewired, U9 13.5 mA, U8 0.55 mA, U6 0.2 mA, U5 12 µA. This excludes J13 and J10 to J12. Check that the total stays below 2 A.	Review
4.5.11	U1	+5V	U1 is rated 2 A. The known load is 0.155 A: U2 input 0.152 A and SK6812 static current 3 mA. This excludes the LED colour current and the J2, J3 and J5 off-board loads. Check that the total stays below 2 A.	Review
4.5.12	D1 (SMBJ33CA)	Net-(D1-A)	D1 protects U4 ANODE (65 V absolute maximum, LM74700 p.5) and Q2 VDS (60 V, AON6262E p.1). Check that D1's maximum clamping voltage at its surge current stays below 60 V. The SMBJ33CA clamping voltage was not available at report generation time.	Review
4.5.13	D1 (SMBJ33CA)	Net-(D1-A)	D1 is a bidirectional TVS, so either orientation is correct. Its symbol uses unidirectional K/A pin names; use a bidirectional symbol.	Review
4.5.14	Q2 (AON6262E)	Net-(D1-A), +BATT	The J7 charge current through Net-(D1-A) cannot be calculated, so Q2 conduction loss and junction temperature are not checked. It can be stated with free text on the schematic page as: Net-(D1-A) load current : <value>.	Review
4.5.15	Q1	+BATT, VCC	Q1 has no part number or value on the schematic. State it so VDS, VGS and drain current can be checked against +BATT and the ESC load on J9.	Review
4.5.16	DZ1, U3, Q1	Net-(DZ1-A)	DZ1 orientation is consistent (cathode at +BATT). With U3_3 asserted, Q1 VGS = +BATT − 0.5 V, limited by DZ1 to 14.25 to 15.75 V. Above 14.25 V, DZ1 conducts into U3_3 with no series resistor, bounded only by U3's 50 mA absolute-maximum output current (p.6). If the battery can exceed 14.25 V, add a resistor between U3_3 and Net-(DZ1-A) that limits the current to U3's 20 mA VOL condition, and keep the R3 divider ratio above Q1's full-enhancement VGS.	Review
4.5.17	U3 (US1881)	+BATT	The only bypass is C11, a 47 µF electrolytic. The US1881 application circuit (p.10) places 100 nF close to the device.	Review
4.5.18	U3, R4, R5	+BATT	U3 draws up to 5 mA (p.7) from the battery permanently, whether Q1 is on or off, in addition to the R4/R5 divider. This is a continuous drain with the vehicle switched off.	Review
4.5.19	R4/R5, R6/R7	+BATT, Net-(D1-A)	The VBAT (to U7_15 PC0) and VCHG (to U7_16 PC1) dividers both have a ratio of 0.2126, giving 15.52 V full scale with VREF+ at 3.3 V. Check that the maximum battery and charger voltages stay below 15.52 V.	Review
4.5.20	R2, R3	VCC, +BATT	No power rating is stated for either 0603 resistor. At the conventional 0.1 W, resistor_power_pct = 70 permits 70 mW, reached by R2 (15 kΩ) at 32.4 V and by R3 (10 kΩ, while U3 holds the gate low) at 26.5 V. State their power ratings.	Review
4.5.21	C4, C5, C6, C47, C48, C49, C50, C51	+5V	Voltage rating not stated in the schematic data. At 5.05 V, a ceramic must be rated at least 7.2 V (capacitor_voltage_pct = 70) and the electrolytic C48 at least 6.3 V (80 %). State 10 V or higher in a Voltage property.	Review
4.5.22	C7, C8, C22, C23, C25, C26, C27, C30, C31, C32, C33, C34, C40, C43, C44	+3V3	Voltage rating not stated in the schematic data. At 3.33 V, a ceramic must be rated at least 4.76 V (capacitor_voltage_pct = 70); 6.3 V or higher is sufficient. State it in a Voltage property.	Review
4.5.23	C3, C11, C9, C10	VCC, +BATT, Net-(D1-A)	Voltage rating not stated in the schematic data for capacitors on the battery and charger nets.	Review
4.5.24	VCC (J9)	VCC	No transient suppressor is fitted on VCC where the ESC connects at J9; only C3 and C11 filter it. U1 VIN is rated 35 V DC and 40 V for 400 ms absolute maximum (AP63205 p.4). Consider a clamp on VCC rated against those limits.	Review
4.5.25	U7, C42, C45	Net-(U7-VCAP_1), Net-(U7-VCAP_2)	U7_48 VCAP_1 and U7_73 VCAP_2 each have 2.2 µF to GND (C42, C45), as required with the internal regulator on (STMicroelectronics datasheet p.106, p.112).	✓
4.5.26	U1 (AP63205WU)	VCC / GND	U1_3 IN is on VCC, fed from +BATT through Q1; U1_4 GND is on GND. Both have a DC path.	✓
4.5.27	U2 (AP63203WU)	+5V / GND	U2_3 IN is on +5V, the output of U1; U2_4 GND is on GND. Both have a DC path.	✓
4.5.28	U1 (AP63205WU)	+5V	FB connects directly to +5V as the fixed-output part requires; output 4.95 to 5.05 V (Diodes Inc. AP63205 datasheet p.5).	✓
4.5.29	U2 (AP63203WU)	+3V3	FB connects directly to +3V3; output 3.27 to 3.33 V (Diodes Inc. AP63203 datasheet p.5).	✓
4.5.30	U1, C1	Net-(U1-BST)	C1 100 nF ceramic is connected between U1_6 BST and U1_5 SW, as required (AP63205 datasheet).	✓
4.5.31	U2, C2	Net-(U2-BST)	C2 100 nF is connected between U2_6 BST and U2_5 SW, as required (AP63203 datasheet p.14).	✓
4.5.32	U1, R1	VCC	U1_2 EN is pulled to VCC through R1 100 kΩ, alongside the internal 1.5 µA pull-up. The datasheet permits EN tied to VIN or left open for automatic start-up (AP63205 datasheet p.2, p.10-11).	✓
4.5.33	U2	+5V	U2_2 EN is tied to +5V for automatic start-up (AP63203 datasheet p.2).	✓
4.5.34	U2, C6, C4, C5	+5V	U2 input has C6 10 µF plus C4 and C5 22 µF and C48 470 µF on +5V, covering the 10 µF reference input capacitor (AP63203 datasheet p.13).	✓
4.5.35	U2, C7, C8, C30, C44	+3V3	Output capacitance is 74.111 µF nominal, above the 22 to 68 µF sufficiency range (AP63203 datasheet p.14). DC-bias loss is not applied.	✓
4.5.36	U1, L1	+5V	L1 3.3 µH is inside the approximate 2.2 to 10 µH range (AP63205 datasheet p.13); Table 3 uses 4.7 µH.	✓
4.5.37	U1	+5V	Soft-start current into the output is 524.4 µF × 5 V / 4 ms = 0.66 A, below the 2.5 A minimum high-side current limit (AP63205 datasheet p.5).	✓
4.5.38	U2	+3V3	Estimated junction temperature is 46.8 °C: 90.0 % efficiency at 0.207 A read from the manufacturer's example curve Efficiency vs. Output Current, VIN = 12V, VOUT = 3.3V (AP63200, p.6), about 76 mW loss, and θJA 89 °C/W. This is below the 115 °C limit of the Benign (controlled office) derating.	✓
4.5.39	U4, C9	Net-(D1-A)	C9 0.1 µF from ANODE to GND meets the 22 nF minimum input capacitance (LM74700 datasheet p.17).	✓
4.5.40	U4, C10	Net-(U4-VCAP)	C10 0.1 µF from VCAP to ANODE meets the 0.1 µF minimum and the 10 × Ciss requirement: AON6262E Ciss 1650 pF gives 16.5 nF (LM74700 p.17).	✓
4.5.41	U4, C11	+BATT	C11 47 µF on CATHODE meets the 0.1 µF minimum output capacitance (LM74700 p.17).	✓
4.5.42	U4	Net-(D1-A)	U4_3 EN is tied to ANODE for always-on operation, which the datasheet permits (LM74700 p.3, p.11).	✓
4.5.43	Q2 (AON6262E), U4	Net-(Q2-G)	Q2 source is on ANODE, drain on CATHODE and gate on U4 GATE (LM74700 p.3). The applied VGS is at most the 13.9 V charge-pump turn-off level (p.7), within the ±20 V VGS rating and the at-least-15 V rating requirement.	✓
4.5.44	U3 (US1881), R3	Net-(DZ1-A)	The R3 10 kΩ pull-up from U3_3 OUTPUT to +BATT matches the 10 kΩ pull-up in the US1881 application circuit (Melexis datasheet p.10).	✓
4.5.45	U9 (nRF24L01P), C33, C34, C41, C35, C36	+3V3	VDD has 10 nF (C33) and 1 nF (C34) plus 4.7 µF on the rail, DVDD has 33 nF (C41), and VDD_PA has 2.2 nF (C35) and 4.7 pF (C36), matching the Nordic reference circuit (p.66-67).	✓
4.5.46	U6 (LIS2MDLTR), C29	Net-(U6-C1)	U6_5 C1 has 220 nF (C29) to GND, as required (ST datasheet p.13).	✓
4.5.47	D2, D3, D4 (SK6812), C47, C49, C50, C51	+5V	There are four 0.1 µF capacitors on +5V for three LEDs and U10, matching the 100 nF per LED in the SK6812 application circuit (p.7).	✓
4.5.48	U2	+5V	U2's 3.70 V maximum rising UVLO (p.5) is below U1's 4.95 V minimum output, so +3V3 starts reliably during U1's soft-start.	✓

4.6 Citations

AI-Assisted —

References
AON6262E (Alpha & Omega Semiconductor (AOS)) — datasheet www.aosmd.com/sites/default/files/res/datasheets/AON6262E...
AP63203 (Diodes Incorporated) — datasheet www.mouser.com/datasheet/2/115/AP63200_AP63201_AP63203_AP...
MMSZ5245 (onsemi) — datasheet www.mouser.com/datasheet/2/308/MMSZ5221ET1_D-1773609.pdf
SK6812 (LED COLOR (www.szledcolor.com)) — datasheet cdn-shop.adafruit.com/product-files/1138/SK6812+LED+datas...
SMBJ (Kyocera AVX) — datasheet, cited pages 1,2,3 datasheets.kyocera-avx.com/tvsdiodes.pdf
STM32F765VI (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/stm32f765vi.pdf
US1881 (Melexis) — datasheet www.mouser.com/datasheet/2/734/US1881_Datasheet_Melexis-2...
nRF24L01P (Nordic Semiconductor ASA) — datasheet datasheet.lcsc.com/datasheet/pdf/1f70bc6ad7df407cb308db24...

5 Connector Pinouts

Total connectors

5.1 J1 Conn_01x03_Pin

J1 - Conn_01x03_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	NC
3	Pin_3	THRR

5.2 J2 Conn_01x04_Pin (I2C)

J2 - Conn_01x04_Pin (I2C)
Pin	Pin Name	Net	Notes
1	Pin_1	+5V
2	Pin_2	UART7_TX
3	Pin_3	UART7_RX
4	Pin_4	I2C2_SCL
5	Pin_5	I2C2_SDA
6	Pin_6	GND

5.3 J3 Conn_01x04_Pin (UART)

J3 - Conn_01x04_Pin (UART)
Pin	Pin Name	Net	Notes
1	Pin_1	+5V
2	Pin_2	UART4_TX
3	Pin_3	UART4_RX
4	Pin_4	GND

5.4 J4 Conn_01x03_Pin

J4 - Conn_01x03_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	NC
3	Pin_3	THRL

5.5 J5 Conn_01x04_Pin

J5 - Conn_01x04_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	+5V
2	Pin_2	TX1
3	Pin_3	RX1
4	Pin_4	NC
5	Pin_5	NC
6	Pin_6	GND

5.6 J6 Conn_01x04_Pin

J6 - Conn_01x04_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	NC
2	Pin_2	NC
3	Pin_3	NC
4	Pin_4	NC
5	Pin_5	NC
6	Pin_6	NC

5.7 J7 Conn_01x02_Pin

J7 - Conn_01x02_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	Net-(D1-A)

5.8 J8 Conn_01x02_Pin

J8 - Conn_01x02_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	+BATT

5.9 J9 Conn_01x02_Pin

J9 - Conn_01x02_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	VCC

5.10 J10 Conn_01x04_Pin (I2C)

J10 - Conn_01x04_Pin (I2C)
Pin	Pin Name	Net	Notes
1	Pin_1	+3V3
2	Pin_2	I2C2_SCL
3	Pin_3	I2C2_SDA
4	Pin_4	GND

5.11 J11 Conn_01x04_Pin (I2C)

J11 - Conn_01x04_Pin (I2C)
Pin	Pin Name	Net	Notes
1	Pin_1	+3V3
2	Pin_2	I2C1_SCL
3	Pin_3	I2C1_SDA
4	Pin_4	GND

5.12 J12 Conn_01x04_Pin (I2C)

J12 - Conn_01x04_Pin (I2C)
Pin	Pin Name	Net	Notes
1	Pin_1	+3V3
2	Pin_2	I2C2_SCL
3	Pin_3	I2C2_SDA
4	Pin_4	GND

5.13 J13 Micro_SD_Card

J13 - Micro_SD_Card
Pin	Pin Name	Net	Notes
1	DAT2	DAT2
2	DAT3/CD	DAT3
3	CMD	CMD
4	VDD	+3V3
5	CLK	CLK
6	VSS	GND
7	DAT0	DAT0
8	DAT1	DAT1
9	DET	SD_Detect
10	SHIELD	GND

5.14 J14 50 ohm

J14 - 50 ohm
Pin	Pin Name	Net	Notes
1	In	Antenna
2	Ext	GND

5.15 J15 Conn_01x03_Pin

J15 - Conn_01x03_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	NC
2	Pin_2	NC
3	Pin_3	NC

6 Indicator Documentation

3 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D2	SK6812	RGB	Net-(D2-DIN)	caiman.kicad_sch	Smart LED (serial), chain D2 -> D4, position 1 of 3
D4	SK6812	RGB	Net-(D3-DOUT)	caiman.kicad_sch	Smart LED (serial), chain D2 -> D4, position 3 of 3
D3	SK6812	RGB	Net-(D2-DOUT)	caiman.kicad_sch	Smart LED (serial), chain D2 -> D4, position 2 of 3

6.2 Indicator Testability

Bed-of-nails or flying probe access was not selected. Test point recommendations for indicators will not be applied.

7 Switch Documentation

No switches or push buttons found in design.

8 Low-Speed Serial Interfaces (LSSI)

Detected: 2 I2C, 1 SPI, 2 UART

8.1 I2C

I2C: U7
Topology: U7 » Targets (J11)
Signal	Net Name	Connector	Test Point	Target Pin
SCL (needs pull-up)	I2C1_SCL	J11_2	(none)	U7_92 (PB6)
SDA (needs pull-up)	I2C1_SDA	J11_3	(none)	U7_93 (PB7)
Controller	Industry Type	Description
U7	STM32F765VITx	STMicroelectronics Arm Cortex-M7 MCU, 2048KB flash, 512KB RAM, 216 MHz, 1.7-3.6V, 82 GPIO, LQFP100

I2C: U7 -> U5, U6, U8
Topology: U7 » Targets (U5, U6, U8, J10, J12, J2)
Signal	Net Name	Connector	Test Point	Target Pin
SCL (needs pull-up)	I2C2_SCL	J10_2, J12_2, J2_4	(none)	U5_2 (SCL/SPC), U6_1 (SCL/SPC), U7_46 (PB10), U8_13 (SCL)
SDA (needs pull-up)	I2C2_SDA	J10_3, J12_3, J2_5	(none)	U5_4 (SDA/SDI/SDO), U6_4 (SDA/SDI/SDO), U7_47 (PB11), U8_14 (SDA)
Address	Target	Industry Type	Description
0x5C (port I2C (SCL/SPC on I2C2_SCL), strap-set address, SDO/SA0=GND (low))	U5	LPS22HBTR
0x1E (port I2C (SCL/SPC on I2C2_SCL), fixed address)	U6	LIS2MDLTR
0x6A (port I2C (SCL on I2C2_SCL), strap-set address, SDO/SA0=GND (low))	U8	LSM6DSO
Controller	Industry Type	Description
U7	STM32F765VITx	STMicroelectronics Arm Cortex-M7 MCU, 2048KB flash, 512KB RAM, 216 MHz, 1.7-3.6V, 82 GPIO, LQFP100

I2C Pull-up Check
Net	Component	Status
I2C1_SDA		Pull-up not found on I2C1_SDA. This bus is mastered on-board by U7 and its addressable targets are off-board through J11; the interface standard for the attached device determines which side supplies the pull-up - confirm it is provided there.	-
I2C1_SCL		Pull-up not found on I2C1_SCL. This bus is mastered on-board by U7 and its addressable targets are off-board through J11; the interface standard for the attached device determines which side supplies the pull-up - confirm it is provided there.	-
I2C2_SDA		Pull-up on I2C2_SDA was not detected. A pull-up for basic I2C operation would be about 4.7K ohms. Even if an IC has internal pull-ups on its inputs, they are likely just for biasing the input high (47-100K ohms) and are not sufficient for I2C. We did not consult the datasheet for U5 but low-value resistors cost silicon area, so it is unlikely the IC has them.
I2C2_SCL		Pull-up on I2C2_SCL was not detected. A pull-up for basic I2C operation would be about 4.7K ohms. Even if an IC has internal pull-ups on its inputs, they are likely just for biasing the input high (47-100K ohms) and are not sufficient for I2C. We did not consult the datasheet for U5 but low-value resistors cost silicon area, so it is unlikely the IC has them.

8.2 SPI

SPI: U7, U9
Topology: U7, U9 » Targets ()
Signal	Net Name	Connector	Test Point
MOSI	MOSI	(none)	(none)
MISO	MISO	(none)	(none)
SCK	SCK	(none)	(none)
CS	CSN	(none)	(none)
Controller	Industry Type	Description
U7	STM32F765VITx	STMicroelectronics Arm Cortex-M7 MCU, 2048KB flash, 512KB RAM, 216 MHz, 1.7-3.6V, 82 GPIO, LQFP100
U9	nRF24L01P	nRF24L01+, Ultra low power 2.4GHz RF Transceiver, QFN20 4x4mm

8.3 UART

UART [UART4]: U7
Topology: U7 » Targets (J3)
Signal	Net Name	Connector	Test Point
TX	UART4_TX	J3_2	(none)
RX	UART4_RX	J3_3	(none)
Controller	Industry Type	Description
U7	STM32F765VITx	STMicroelectronics Arm Cortex-M7 MCU, 2048KB flash, 512KB RAM, 216 MHz, 1.7-3.6V, 82 GPIO, LQFP100

UART [UART7]: U7
Topology: U7 » Targets (J2)
Signal	Net Name	Connector	Test Point
TX	UART7_TX	J2_2	(none)
RX	UART7_RX	J2_3	(none)
Controller	Industry Type	Description
U7	STM32F765VITx	STMicroelectronics Arm Cortex-M7 MCU, 2048KB flash, 512KB RAM, 216 MHz, 1.7-3.6V, 82 GPIO, LQFP100

8.4 LSSI DFT Analysis

4 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
CS	CSN	(none)	SPI: U7
MISO	MISO	(none)	SPI: U7
MOSI	MOSI	(none)	SPI: U7
SCK	SCK	(none)	SPI: U7

9 High-Speed Serial Interfaces (HSSI)

1 single-ended controlled impedance signal(s)

9.1 Controlled Impedance Signals

Single-ended signals requiring controlled impedance. Grouped by target impedance value.

50 Ohm Signals
Net Name	Impedance Class	Notes
Antenna	RF_50Ohm

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 J13 SDMMC Connector

J13 (Micro_SD_Card) - SDMMC Connector Interface [4-bit]
Signal	Pin Name	Pin #	Net Name	Test Point	Source IC
CARD_DETECT	DET	9	SD_Detect	-	U7_62
CLOCK	CLK	5	CLK	-	U7_80
CMD	CMD	3	CMD	-	U7_83
DATA_0	DAT0	7	DAT0	-	U7_65
DATA_1	DAT1	8	DAT1	-	U7_66
DATA_2	DAT2	1	DAT2	-	U7_78
DATA_3	DAT3/CD	2	DAT3	-	U7_79
Direct programming via test points is not needed since SD cards can be pre-programmed and inserted

10.2 AI-Assisted Analysis

10.2.1 microSD Card Interface (J13) to STM32F765 (U7)

AI-Assisted — The only memory device is a microSD card in J13, a Hirose DM3AT-SF-PEJM5 socket. J13 has no datasheet entry, so every row that depends on the card or socket is at review severity at most.

The interface is a 4-bit point-to-point bus with no branches or stubs. J13 DAT0, DAT1, DAT2 and DAT3/CD reach U7 PC8, PC9, PC10 and PC11. J13 CMD reaches U7 PD2, and J13 CLK reaches U7 PC12. Each of the six lines passes through its own 22 Ω series resistor: R21, R23, R24, R26, R19 and R27.

The series resistors are justified by the host's edge rate. U7 GPIO outputs switch in 2.5 ns at the fastest output-speed setting into 10 pF, and in 4 ns into 30 pF (STMicroelectronics STM32F765VI datasheet p.161, Datasheet). These resistors damp ringing on the short card traces. Whether they work as source termination depends on placement near U7, which layout must preserve.

The card is powered from +3V3 (U2, 3.27 to 3.33 V). U7 I/O shares this rail once its VDD pins are joined to +3V3, as the power review requires. Because both sides run from one rail, no level translation is needed.

10.2.2 Pull-ups, Card Detect and Socket Power

AI-Assisted — R11, R13, R14, R9 and R10 are 10 kΩ resistors from CMD, DAT0, DAT1, DAT2 and DAT3 to +3V3. Each sits on the card side of its series resistor. CLK has no pull-up.

The high level holds with margin. At the 1 µA maximum U7 input leakage (p.157), each pull-up drops 10 mV, giving 3.26 V at the 3.27 V rail minimum. That is well above U7's VIH minimum of 0.7 × VDD, which is 2.29 V on the same rail.

The low level also holds. When U7 drives a line low it sinks 3.33 V / 10 kΩ = 0.33 mA. That is far below the 8 mA at which VOL is at most 0.4 V (p.159), so the line sits under the 0.98 V VIL maximum (0.3 × VDD, p.156). The extra drop across the 22 Ω resistor at this current is 7.3 mV.

R10 holds DAT3/CD high, so card presence is sensed mechanically on J13_9 DET rather than through DAT3. DET sits on SD_Detect with R15 10 kΩ to +3V3 and is read by U7 PD15. Its open-switch level is 3.26 V, inside U7's input limits. Whether DET closes to the shield on insertion or on removal is set by the socket, so the firmware polarity of PD15 depends on the DM3AT switch sense.

J13_4 VDD is wired directly to +3V3. J13_6 VSS and J13_10 SHIELD are both on GND.

10.3 Observations

AI-Assisted — Three robustness and testability points remain on the card side. None is a wiring error.

The socket is user-accessible, but none of the seven card nets (CMD, CLK, DAT0 to DAT3, SD_Detect) carries an ESD suppressor. Only the 22 Ω series resistors stand between a discharge into the card contacts and the U7 pins. A low-capacitance ESD array on the card side of the series resistors would clamp a discharge before it reaches U7. Its clamping voltage would have to sit below U7's I/O absolute maximum of min(VDD + 3.6 V, 5.5 V) (p.107).

J13 VDD is hard-wired to +3V3. The host therefore cannot power-cycle a card that has locked up. Recovery requires cycling the whole board, and hot insertion loads +3V3 directly. A load switch on J13 VDD, controlled by a spare U7 output, would give firmware a card power-cycle path. Adding it is a design decision for the designer.

The design summary states no test points on the board, and none of the seven card nets carries one. Bare-board and in-circuit access to the SD bus therefore depends on probing the socket contacts or the 22 Ω resistor pads.

The U7 power-pin wiring defect and the absence of J13 current from the +3V3 load budget are reported in the power review. They are not repeated here.

10.4 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.4.1	microSD (J13)	Card detect	The DET switch sense (closed on insertion or on removal) is set by the DM3AT socket. Check the firmware polarity of PD15 against the socket's switch definition.	Review
10.4.2	microSD (J13)	Card supply	J13_4 VDD is on +3V3, 3.27 to 3.33 V (U2). Check that this is inside the card supply range.	Review
10.4.3	microSD (J13)	Signal levels	U7 VOH is at least VDD − 0.4 V at −8 mA, which is 2.87 V at the 3.27 V rail minimum (STMicroelectronics STM32F765VI datasheet p.159). Check that the card's VIH on CMD, CLK and DAT0 to DAT3 is compatible.	Review
10.4.4	microSD (J13)	Signal levels	U7 VIH minimum is 0.7 × VDD, which is 2.33 V at the 3.33 V rail maximum (STMicroelectronics STM32F765VI datasheet p.157). Check that the card's VOH on CMD and DAT0 to DAT3 is compatible.	Review
10.4.5	microSD (J13)	ESD	None of the seven card nets carries an ESD suppressor at the user-accessible socket. A low-capacitance ESD array on the card side of the 22 Ω resistors, clamping below U7's I/O absolute maximum of min(VDD + 3.6 V, 5.5 V) (STMicroelectronics STM32F765VI datasheet p.107), would protect U7.	Review
10.4.6	microSD (J13)	Card supply	J13 VDD is hard-wired to +3V3, so firmware cannot power-cycle a locked card and insertion loads +3V3 directly. A U7-controlled load switch on J13 VDD would add a recovery path.	Review
10.4.7	microSD (J13)	Testability	None of the seven card nets carries a test point; the design states no test points board-wide. Bus access for test depends on the socket contacts or the series resistor pads.	Review
10.4.8	microSD (J13)	SDMMC CLK	CLK has R27 22 Ω in series and no pull-up. The card clock is driven push-pull by U7 PC12 at all times.	Info
10.4.9	microSD (J13)	Card detect	R10 10 kΩ holds DAT3/CD high, so presence is sensed on the mechanical J13_9 DET switch rather than through DAT3. Using DAT3 sensing instead would need DAT3 left without a strong pull-up.	Info
10.4.10	microSD (J13)	SDMMC 4-bit	J13 DAT0, DAT1, DAT2, DAT3/CD, CMD and CLK each reach a separate U7 pin (PC8, PC9, PC10, PC11, PD2, PC12) on a point-to-point 4-bit bus with no stubs or shared nets.	✓
10.4.11	microSD (J13)	SDMMC 4-bit	All six bus lines carry 22 Ω series resistors (R21, R23, R24, R26, R19, R27). These damp U7 edges of 2.5 ns into 10 pF at the highest speed setting (STMicroelectronics STM32F765VI datasheet p.161). Placement near U7 is a layout requirement.	✓
10.4.12	microSD (J13)	SDMMC pull-ups	R11, R13, R14, R9 and R10 are 10 kΩ from CMD and DAT0 to DAT3 to +3V3. At the 1 µA maximum U7 leakage the high level is 3.26 V, above the 2.29 V VIH minimum (0.7 × 3.27 V) (STMicroelectronics STM32F765VI datasheet p.157).	✓
10.4.13	microSD (J13)	SDMMC pull-ups	The 10 kΩ pull-ups load a U7 low output with 0.33 mA, far below the 8 mA at which VOL is at most 0.4 V. That is under the 0.98 V VIL maximum (STMicroelectronics STM32F765VI datasheet p.156, p.159).	✓
10.4.14	microSD (J13)	Card detect	J13_9 DET is on SD_Detect with R15 10 kΩ from SD_Detect to +3V3, read by U7 PD15. The open-switch level is 3.26 V, above the 2.29 V VIH minimum (STMicroelectronics STM32F765VI datasheet p.157).	✓
10.4.15	microSD (J13)	Socket ground	J13_6 VSS and J13_10 SHIELD are both on GND.	✓

10.5 Citations

AI-Assisted —

References
STM32F765VI (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/stm32f765vi.pdf

11 Functional Analysis

8 device(s) to review across 3 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
Y1	CRYSTAL	25MHz	Four pin crystal, GND on pins 2 and 3, small symbol	-	-
Y2	CRYSTAL	16MHz	Four pin crystal, GND on pins 2 and 3, small symbol	-	-
U3	DEVICE	US1881	High Sensitivity Micropower Omnipolar Hall-Effect Switch, SIP-3	-	-
U5	DEVICE	LPS22HBTR		I2C	-
U6	DEVICE	LIS2MDLTR		I2C	-
U7	DEVICE	STM32F765VITx	STMicroelectronics Arm Cortex-M7 MCU, 2048KB flash, 512KB RAM, 216 MHz, 1.7-3.6V, 82 GPIO, LQFP100	I2C, SPI, UART [UART4], UART [UART7]	-
U8	DEVICE	LSM6DSO		I2C	-
U9	WIRELESS	nRF24L01P	nRF24L01+, Ultra low power 2.4GHz RF Transceiver, QFN20 4x4mm	SPI	-

11.1 Reset-Time Strap Configuration

Each device below takes part of its start-up configuration from resistors the board fits on pins it samples at reset. Every setting is resolved against that device's own datasheet tables - the combination this board selects, and whether the datasheet marks that combination reserved or invalid.

RefDes	Configuration	This Board Selects	Read From	Status
U9	nRF24L01P	No reset-time straps: probe: the pages show no reset-time configuration		✓

RefDes	Pin	Read From	Sets
U7	BOOT0 (U7_94)	open (on no net - unconnected)	boot memory space - the datasheet tabulates no modes for this pin
U7	PDR_ON		not a pin of this symbol
U7	BYPASS_REG		not a pin of this symbol

11.2 Functional Analysis

11.2.1 STM32F765VITx Microcontroller (U7) and 25 MHz HSE Crystal (Y1)

AI-Assisted — U7 runs from +3V3, which U2 holds at 3.27 to 3.33 V. That is inside the 1.7 to 3.6 V VDD range in the STMicroelectronics datasheet (Datasheet, p.109). The wiring of the VDD, VDDA, VBAT and VREF+ pins and of the VCAP capacitors is covered in the power review and is not repeated here.

NRST has R8 (10 kΩ) to +3V3 and C20 (100 nF) to GND, in addition to its permanent internal pull-up (p.162).

The programming path is the main problem. SWDIO, SWCLK and SWO each end at the far pad of R16, R17 or R18 (22 Ω), so U7 PA13, PA14 and PB3 reach no connector. NRST appears on no connector either. U7_94 BOOT0 is unconnected in the schematic and has no pull to either level, so the boot memory space it selects at reset (p.73) is undefined. Together these leave no defined way to load firmware into U7.

On the serial ports, J5 carries the nets TX1 and RX1, while U7 PB14 and PB15 carry USART1_TX and USART1_RX. The names differ, so the J5 port is not joined to U7.

The HSE oscillator uses Y1 at 25 MHz, inside the 4 to 26 MHz HSE band the datasheet characterises (p.114). C24 (18 pF) and C28 (18 pF) each go from one Y1 pin to ground. Seen across the crystal through ground they give CL = 18 × 18 / (18 + 18) = 9 pF, plus pin and board stray.

R12 (47 kΩ) sits in series between PH1-OSC_OUT and Y1. The datasheet allows an optional, resonator-dependent drive resistor at this position (p.137). However, 47 kΩ against C28 forms a low-pass with a corner of 1/(2π × 47 kΩ × 18 pF) = 188 kHz. At 25 MHz the reactance of C28 is 354 Ω, so the drive reaching the crystal is attenuated by about 133 times (42 dB). That attenuation is taken directly out of the oscillator loop gain.

11.2.2 nRF24L01+ Transceiver (U9) and 16 MHz Crystal (Y2)

AI-Assisted — U9 VDD (U9_7, U9_15, U9_18) is on +3V3 at 3.27 to 3.33 V. That is inside the 1.9 to 3.6 V operating range and below the 3.6 V absolute maximum in the Nordic datasheet (Datasheet, pp.18-19). Supply, DVDD and VDD_PA decoupling are covered in the power review.

IREF has R20 (22 kΩ) to GND, as pages 11 and 66-67 require.

The RF output follows the single-ended 50 Ω reference network on pages 64 and 66-67:
- L4 (8.2 nH) bridges ANT1 and ANT2.
- L3 (2.7 nH) feeds ANT1 from VDD_PA, giving both antenna pins their DC path.
- L5 (3.9 nH) and C38 (1.5 pF) run in series from ANT2 to the Antenna net.
- C37 (1 pF) shunts the Antenna net to ground at J14, whose shell is on GND.

Y2 is 16 MHz, matching the required crystal frequency (p.25). C39 and C46 (22 pF each) go from XC1 and XC2 to ground. Across the crystal through ground they give 22 × 22 / (22 + 22) = 11 pF plus stray, which suits the 12 pF crystal of the reference design inside the 8 to 16 pF window. R22 (1 MΩ) is fitted across XC1 and XC2. Page 67 marks that resistor as not mounted for the nRF24L01+ and keeps it only for nRF24L01 compatibility.

The SPI and control lines run point to point to U7: CSN to PA3, SCK to PA5, MOSI to PA7, MISO to PA6, CE to PA4, and the active-low IRQ to PA2. Both parts share +3V3, and the logic levels have margin in both directions:
- U7 VOH is at least VDD − 0.4 V (2.87 V at a 3.27 V rail), against the nRF24L01+ VIH of 0.7 × VDD.
- The nRF24L01+ VOH is at least VDD − 0.3 V (2.97 V), against the U7 VIH of 2.33 V.

CSN has no external pull-up, and the datasheet states no internal pull on it. Whether CSN stays deselected before firmware runs therefore depends on the reset state of U7 PA3.

11.2.3 Barometer, Magnetometer and IMU on I2C2 (U5, U6, U8)

AI-Assisted — All three sensors take VDD and VDD_IO from +3V3 at 3.27 to 3.33 V, inside each part's supply range:
- LPS22HB: 1.7 to 3.6 V.
- LIS2MDL: 1.71 to 3.6 V.
- LSM6DSO: VDD 1.71 to 3.6 V and VDDIO 1.62 to 3.6 V.

The datasheets are from STMicroelectronics (source: Tomachie). The 100 nF ceramic decoupling each part asks for is present on +3V3, as are the 4.7 µF optional for the LPS22HB and the 10 µF the LIS2MDL names.

Each part has its CS pin tied to +3V3, which the states tables define as I²C enabled.
- U5: RES goes to GND as required, and SDO/SA0 to GND selects address 0x5C (LPS22HB p.24).
- U6: the three NC pins are internally unconnected and are left open, which the datasheet permits.
- U8: SDx and SCx are tied to GND, which is the Mode 1 connection. OCS_Aux and SDO_Aux are left open as Mode 1 allows, and SDO/SA0 is on GND.

The bus itself is the problem. I2C2_SCL and I2C2_SDA join U7 PB10 and PB11 to U5, U6 and U8 and leave the board on J2, J10 and J12. Neither net carries a pull-up resistor, although the page has an "I2C Pull-Up" block note. The LIS2MDL datasheet requires an external pull-up to Vdd_IO (p.15), and the LSM6DSO datasheet specifies 10 kΩ (p.35). U7's internal pull-ups are 30 to 50 kΩ (STMicroelectronics STM32F765VI datasheet p.157), three to five times weaker than that figure.

The interrupt outputs reach no other pin. BAR_INT (U5_7), MAG_INT (U6_7) and IMU_INT (U8_4) each connect only to their own sensor, so firmware must poll all three sensors.

11.2.4 US1881 Hall-Effect Switch (U3)

AI-Assisted — U3 is the magnetic power switch. Its supply is +BATT, and its open-drain output drives Net-(DZ1-A), the gate of Q1. R3 (10 kΩ) pulls that net to +BATT, which matches the Melexis application circuit (Datasheet, p.10). The battery-voltage ratings, the DZ1 clamp current and the decoupling of U3 are covered in the power review.

The library description calls U3 an omnipolar switch, but the datasheet describes latch behaviour. In the UA (SIP-3, TO-92 footprint) package the output goes low when the field exceeds BOP (0.5 to 9.5 mT, south pole at the branded face), which turns Q1 on. It goes high only when the field falls below BRP (−9.5 to −0.5 mT, north pole). The output keeps its state when the magnet is removed (pp.6-7). The operating magnet therefore has to present one pole to switch the board on and the opposite pole to switch it off.

The part number carries no temperature suffix. Even the narrowest grade, E (−40 to 85 °C), covers the 40 °C design ambient.

11.3 Findings

AI-Assisted —

#	Device	Finding	Severity
11.3.1	STM32F765VITx (U7)	SWDIO, SWCLK and SWO end at R16, R17 and R18 (22 Ω) with no other member, so U7 PA13, PA14 and PB3 reach no connector or test point. NRST is on no connector either. U7 cannot be programmed or debugged over SWD as drawn. Route SWDIO, SWCLK, SWO, NRST, +3V3 and GND to a debug connector.	High
11.3.2	U5, U6, U8 (I2C2)	I2C2_SCL and I2C2_SDA join U7 PB10/PB11, U5, U6 and U8 and leave on J2, J10 and J12, with no pull-up resistor on either net. The LIS2MDL datasheet (p.15) requires an external pull-up to Vdd_IO, and the LSM6DSO datasheet (p.35) specifies 10 kΩ. Add 10 kΩ from each net to +3V3.	High
11.3.3	STM32F765VITx (U7)	U7_94 BOOT0 is unconnected in the schematic and has no resistor to either level. BOOT0 selects the boot memory space at reset (STMicroelectronics datasheet p.73), so the boot source is undefined. Tie BOOT0 through a resistor to the level that selects the memory the firmware is built for, and bring it to a test point or the debug connector.	Medium
11.3.4	STM32F765VITx (U7), J5	J5_2 (net TX1) and J5_3 (net RX1) reach no other pin. U7 PB14 (USART1_TX) and PB15 (USART1_RX) also reach nothing. Because the net names differ, the J5 receiver port is not connected to U7. Rename the J5 nets to the U7 UART nets the firmware uses.	Medium
11.3.5	R12, Y1 (U7 HSE)	R12 (47 kΩ) in series from PH1-OSC_OUT to Y1 forms a 188 kHz low-pass with C28 (18 pF). At 25 MHz it attenuates the drive into C28's 354 Ω reactance by about 133 times (42 dB), removing that much oscillator loop gain. The datasheet calls this drive resistor optional and resonator-dependent (p.137). Replace R12 with a 0 Ω link, or with a value at or below C28's 354 Ω reactance chosen against Y1's drive-level rating.	Medium
11.3.6	LPS22HBTR (U5)	U5_7 INT_DRDY is on BAR_INT, which reaches no U7 pin, so firmware must poll the sensor. Route BAR_INT to a spare U7 GPIO.	Low
11.3.7	LIS2MDLTR (U6)	U6_7 INT/DRDY is on MAG_INT, which reaches no U7 pin, so firmware must poll the sensor. Route MAG_INT to a spare U7 GPIO.	Low
11.3.8	LSM6DSO (U8)	U8_4 INT1 is on IMU_INT, which reaches no U7 pin, so firmware must poll the sensor. Route IMU_INT to a spare U7 GPIO.	Low
11.3.9	STM32F765VITx (U7)	UART5_TX/RX (PB13/PB12), USART3_TX/RX (PD8/PD9) and UART8_TX/RX (PE1/PE0) are labelled nets carrying only the U7 pin. No connector or device reaches them.	Review
11.3.10	STM32F765VITx (U7), J11	I2C1_SCL (PB6) and I2C1_SDA (PB7) reach only J11 pins 2 and 3 and have no pull-up. The pull-ups must come from the assembly mating with J11, or from U7's 30 to 50 kΩ internal pull-ups (STMicroelectronics datasheet p.157).	Review
11.3.11	Y1, C24, C28 (U7 HSE)	C24 and C28 (18 pF each, pin to ground) give CL = 18 × 18 / (18 + 18) = 9 pF across Y1 through ground, plus pin and board stray. Check this against Y1's specified load capacitance.	Review
11.3.12	Y2, C39, C46 (U9)	Y2 is 16 MHz, as required. C39 and C46 (22 pF each, pin to ground) give 11 pF across the crystal through ground plus stray, consistent with the 12 pF crystal of the reference design and inside the 8 to 16 pF window (Nordic datasheet pp.25, 66-67). Check this against Y2's specified load capacitance.	Review
11.3.13	R22 (U9)	R22 (1 MΩ) is fitted across XC1 and XC2. The Nordic datasheet (p.67) marks this resistor as not mounted for the nRF24L01+ and optional only for nRF24L01 backward compatibility.	Review
11.3.14	nRF24L01P (U9)	CSN has no external pull-up, and the nRF24L01+ datasheet states no internal pull on CSN. Check that U7 PA3's reset state holds CSN deselected until firmware configures it.	Review
11.3.15	LIS2MDLTR (U6)	100 nF and 10 µF are on +3V3. The STMicroelectronics datasheet (p.13) names a 10 µF aluminium capacitor near U6_9 VDD, while the board's 10 µF parts (C30, C44) are ceramic.	Review
11.3.16	US1881 (U3)	The library description calls U3 an omnipolar switch, but the Melexis datasheet describes a latch. The UA output goes low (Q1 on) when the field exceeds BOP of 0.5 to 9.5 mT (south pole), and goes high only when it falls below BRP of −9.5 to −0.5 mT (north pole). The state is held with the field removed (pp.6-7). The magnet must present opposite poles to switch the board on and off.	Review
11.3.17	STM32F765VITx (U7), Y1	Y1 at 25 MHz is inside the 4 to 26 MHz HSE band characterised in the STMicroelectronics datasheet (p.114).	✓
11.3.18	STM32F765VITx (U7)	NRST has R8 (10 kΩ) to +3V3 and C20 (100 nF) to GND, in addition to the permanent internal pull-up (STMicroelectronics datasheet p.162).	✓
11.3.19	STM32F765VITx (U7)	U7_8 PC14-OSC32_IN and U7_9 PC15-OSC32_OUT are unconnected in the schematic. The LSE is unused, so the 32.768 kHz crystal and load capacitors of datasheet pp.137-138 are not needed.	✓
11.3.20	STM32F765VITx (U7)	Temperature grade 6 is rated −40 to 85 °C ambient at full power dissipation, which covers the 40 °C design ambient (STMicroelectronics datasheet p.110).	✓
11.3.21	nRF24L01P (U9)	VDD on +3V3 (3.27 to 3.33 V) is inside the 1.9 to 3.6 V operating range and below the 3.6 V absolute maximum (Nordic datasheet pp.18-19).	✓
11.3.22	nRF24L01P (U9), R20	U9_16 IREF has R20 (22 kΩ) to GND, as required (Nordic datasheet pp.11, 66-67).	✓
11.3.23	nRF24L01P (U9), L3, L4, L5, C37, C38, J14	The matching network matches the 50 Ω reference on pp.64 and 66-67. L4 (8.2 nH) bridges ANT1 and ANT2, and L3 (2.7 nH) gives the DC path to VDD_PA. L5 (3.9 nH) and C38 (1.5 pF) run in series to the Antenna net, and C37 (1 pF) shunts it at J14.	✓
11.3.24	nRF24L01P (U9), U7	CSN, SCK, MOSI, MISO, CE and IRQ run point to point to U7 PA3, PA5, PA7, PA6, PA4 and PA2. Both parts are on +3V3. U7 VOH of at least 2.87 V and the nRF24L01+ VOH of at least 2.97 V each exceed the other part's VIH of 0.7 × VDD (2.33 V at 3.33 V). Both VOL figures (0.4 V and 0.3 V) are below the 0.98 V VIL.	✓
11.3.25	LPS22HBTR (U5)	VDD and VDD_IO are on +3V3 (1.7 to 3.6 V range), and 100 nF plus 4.7 µF are on the rail. CS is tied to +3V3, which selects I²C, and RES is tied to GND as required. SDO/SA0 on GND selects address 0x5C (STMicroelectronics datasheet p.24).	✓
11.3.26	LIS2MDLTR (U6)	VDD and VDD_IO are on +3V3 (1.71 to 3.6 V range), and CS is tied to +3V3, which enables I²C. U6_2, U6_11 and U6_12 are NC pins, internally unconnected, and are left open, which the datasheet permits.	✓
11.3.27	LSM6DSO (U8)	VDD and VDDIO are on +3V3 within 1.71 to 3.6 V and 1.62 to 3.6 V, with 100 nF on the rail (p.35). CS is tied to +3V3, which selects I²C. SDx and SCx are tied to GND, the Mode 1 connection. OCS_Aux and SDO_Aux are left open, as Mode 1 permits. SDO/SA0 is on GND.	✓
11.3.28	US1881 (U3)	Even the narrowest temperature grade, E (−40 to 85 °C), covers the 40 °C design ambient (Melexis datasheet p.6).	✓

11.4 Citations

AI-Assisted —

References
AON6262E (Alpha & Omega Semiconductor (AOS)) — datasheet www.aosmd.com/sites/default/files/res/datasheets/AON6262E...
AP63203 (Diodes Incorporated) — datasheet www.mouser.com/datasheet/2/115/AP63200_AP63201_AP63203_AP...
MMSZ5245 (onsemi) — datasheet www.mouser.com/datasheet/2/308/MMSZ5221ET1_D-1773609.pdf
SK6812 (LED COLOR (www.szledcolor.com)) — datasheet cdn-shop.adafruit.com/product-files/1138/SK6812+LED+datas...
SMBJ (Kyocera AVX) — datasheet, cited pages 1,2,3 datasheets.kyocera-avx.com/tvsdiodes.pdf
STM32F765VI (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/stm32f765vi.pdf
US1881 (Melexis) — datasheet www.mouser.com/datasheet/2/734/US1881_Datasheet_Melexis-2...
nRF24L01P (Nordic Semiconductor ASA) — datasheet datasheet.lcsc.com/datasheet/pdf/1f70bc6ad7df407cb308db24...

12 Designer Annotated Nets

Annotated signals

Designer-placed annotation markers on nets that are not already analyzed as HSSI differential pairs or Memory Bus signals.

Designer Annotations
Net Name	Annotation	Impedance	Notes
VCC	PWR_HIGH
+3V3	PWR_LOW
+5V	PWR_LOW
GND	PWR_LOW

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J13	Micro_SD_Card	J13: Shield pins SHIELD share the logic GND net, so the shield-bond strategy is not captured as design intent.	Assign a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD) so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MΩ \|\| 4.7 nF (≥2 kV) from the shield net to logic GND. IEC 61000-4-2.

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed: 7 connector-facing signal(s). 0 protected, 7 unprotected, 0 to review, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
DAT2	J13	No ESD Protection
DAT3	J13	No ESD Protection
DAT1	J13	No ESD Protection
CMD	J13	No ESD Protection
DAT0	J13	No ESD Protection
SD_Detect	J13	No ESD Protection
CLK	J13	No ESD Protection

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture

AI-Assisted — The caiman board has one ground domain, GND, a digital return. There is no chassis or earth net and no part connected between grounds, so every connector return and the J13 card-socket shield sit on logic GND. That suits a battery-powered vehicle controller with no earth reference. The designer's notes on the sheet name its functions: battery connector, ESC power and PWM, RC receiver, RF communication, SD card and spare I2C/leak detection. Only J13 has a shell terminal. The J14 outer conductor (J14_2 Ext) is the RF return on GND. The symbols of J1, J2, J3, J4, J7, J10, J11 and J12 carry no shell pin. Filtering exists on two interfaces only: the six microSD lines through 22 Ω series resistors, and the RF port through the Nordic reference network. None of the signal nets on J1, J2, J3, J4, J10, J11 or J12 carries a series resistor, ferrite, capacitor or clamp; each runs straight to U7, U5, U6 or U8 pins. Emissions are judged against CISPR 32 / EN 55032 Class B, and the 2.4 GHz radio against ETSI EN 301 489-1/-17 and EN 300 328 (FCC Part 15). Immunity is judged against EN 55035, whose IEC 61000-4-2 test applies 4 kV contact and 8 kV air at user-accessible points. The likely field failures are ESD coupling into unbuffered MCU and sensor pins, and radiated emission from unshielded harnesses carrying fast edges and ESC return current.

13.3.2 Power Entry: J7, J8 and J9

AI-Assisted — J7 is an XT30 vertical power connector. J7_2 sits on Net-(D1-A), which also holds D1 SMBJ33CA (D1_1 on GND), C9 0.1 µF, U4_6 ANODE, U4_3 EN, the Q2 source pins and R6 100 kΩ to VCHG. D1 is the clamp on that contact, and nothing stands in series between J7_2 and D1. D1 therefore takes the surge first and is the last clamp before U4 ANODE and Q2. The power review already covers D1's clamping level against Q2 and U4 and its unidirectional pin names. U7_16 PC1 sees J7 only through R6 100 kΩ, which limits pin current to about 0.33 mA at 33 V.

On J8, +BATT has DZ1 as its only diode. DZ1's anode is on Net-(DZ1-A), so it acts as Q1's gate clamp rather than a shunt to GND. A positive surge on +BATT raises the Q2 drain above its source. That reverse-biases the body diode, and U4 holds the gate off, so D1 never sees a J8 transient. The battery voltage is not stated, so any +BATT clamp standoff must be chosen against it.

On J9, VCC feeds U1's switching input with only C3 and C11 as filtering. U1's input ripple current therefore returns along the ESC harness, which then acts as a radiating loop.

13.3.3 ESC PWM Headers: J1 and J4

AI-Assisted — J1 and J4 are vertical 2.54 mm 1x03 headers. Pin 3 carries THRR or THRL straight to U7_59 PD12 or U7_60 PD13, pin 1 is GND and pin 2 is unconnected. The headers sit on an ESC harness that also routes motor switching current, and the far end is the ESC, so these are cabled ports. U7 drives the cable unterminated. At OSPEEDR = 11 the edge is 2.5 ns maximum into 10 pF (STMicroelectronics STM32F765VI datasheet p.161, Datasheet). Such edges put harmonics well into the CISPR 32 radiated band, while ESC PWM rates need nothing faster than the OSPEEDR = 00 setting, which gives 100 ns maximum into 50 pF (p.160). A discharge to the harness reaches the MCU pin with no series impedance. A series resistor at each header pin, together with the slow speed setting, would slow the edge into the cable and limit current into U7's internal clamp during an IEC 61000-4-2 event. The ESC supply returns through J9_1 GND, while the PWM references J1_1 and J4_1. Motor current sharing those paths shifts the reference the ESC input sees, which shows up as ground bounce and false pulses.

13.3.4 JST GH Peripheral Connectors: J2, J3, J10, J11, J12

AI-Assisted — These are 1.25 mm JST GH vertical connectors for off-board sensors, the RC receiver and spare buses. They are wire-to-board ports whose exposure depends on whether each harness leaves the enclosure. I2C2 leaves the board on three of them, J2, J10 and J12. A strike on any one of them reaches all four bus members at once: U7_46/U7_47, U5_2/U5_4, U6_1/U6_4 and U8_13/U8_14. The three sensors are each rated 2 kV HBM (STMicroelectronics LPS22HB datasheet p.14, LIS2MDL datasheet p.11, LSM6DSO datasheet p.15, source: Tomachie). HBM is a component-handling test, however, and its waveform and source impedance differ from IEC 61000-4-2, so no system margin follows from it. The sensor control-pin absolute maximum is Vdd_IO + 0.3 V, which is 3.63 V at the 3.33 V rail maximum. I2C1 on J11, UART7 on J2 and UART4 on J3 reach U7 pins with no series element either. J10, J11 and J12 export +3V3, and J2 and J3 export +5V, with no series element. A harness short on +5V also takes down +3V3, because U2 is fed from +5V. The bulk capacitance on +3V3 does absorb ESD charge arriving on those supply pins.

13.3.5 microSD Socket: J13

AI-Assisted — J13_10 SHIELD and J13_6 VSS are both on GND. A microSD socket takes no cable from a second device at a different static potential. A direct, low-inductance shield bond to logic GND is therefore acceptable here, and the dedicated-shield-net and R||C bond guidance for cabled connectors does not apply. The memory-bus review has already reported the absence of an ESD suppressor on the seven card nets, together with the 22 Ω series resistors R19, R21, R23, R24, R26 and R27. Those resistors sit between the card contacts and U7, add a little series impedance to a discharge at the card, and slow the U7 edges that would otherwise radiate from the socket.

13.3.6 RF Port: J14

AI-Assisted — J14 is a vertical U.FL connector feeding a 50 Ω antenna lead. The Antenna net holds C37 1 pF to GND and C38 1.5 pF in series to L5 3.9 nH, L4 8.2 nH across ANT1 and ANT2, and L3 2.7 nH to U9_11 VDD_PA. This is the network shown in the Nordic nRF24L01+ reference (datasheet pp.64, 66-67, Datasheet). C38 blocks DC but passes the fast edge of a discharge into U9_12 ANT1 and U9_13 ANT2. The port carries no clamp. Whether that matters depends on whether the antenna or its lead is reachable from outside the enclosure. Apart from the reference matching network, no harmonic filter is fitted between C38 and J14. Conducted spurious and harmonic emissions are therefore set by U9 and that network, and are judged at product level against EN 300 328 and FCC Part 15.247.

13.4 Observations

AI-Assisted — Across all the connectors, the only transient clamp fitted is D1 on J7, and the only signal filtering is the SD series resistors and the RF network. That is common on hobby-level vehicle boards whose harnesses stay inside a sealed hull. For a consumer product that must pass EN 55035, each externally reachable port needs a defined path for discharge current: a series resistor plus a low-capacitance array to GND on signal pins, and a TVS on power pins. Without that path, the current flows into U7, U5, U6 and U8 pins. In a non-conductive enclosure with no chassis, the charge lands on the board either way; the protection changes where it enters and the waveform, not the destination. The largest radiated-emission risks are the fast unterminated PWM edges on J1 and J4, the ESC and battery leads carrying U1's input ripple, and the 2.4 GHz harmonics at J14. The single GND domain needs no change. Only connector shields would ever come off the plane, and the one shield here, J13, is correctly bonded directly.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J14	The Antenna net carries C37 1 pF to GND and C38 1.5 pF in series to L5, L4 and L3, with no ESD clamp. A discharge to the antenna couples through C38 into U9_12 ANT1 and U9_13 ANT2. Where the antenna or its lead is user-accessible, an ESD device specified for 2.4 GHz insertion loss at J14 would keep the strike off U9. IEC 61000-4-2; ETSI EN 301 489-17.	Review
13.5.2	J14	Apart from the Nordic reference matching network (datasheet pp.64, 66-67), no harmonic filter is fitted between C38 and J14. Harmonic and spurious emissions are judged at product level against EN 300 328 and FCC Part 15.247.	Review
13.5.3	J7	Net-(D1-A) carries no fuse between J7_2 and D1, so a sustained over-voltage from the charger above D1's breakdown holds D1 in conduction with nothing in its path to open. A fuse or PTC on the J7 side of D1, rated for the charge current, would give D1 a series element that opens.	Review
13.5.4	J8	The only diode on +BATT is DZ1, wired from +BATT to Net-(DZ1-A) as Q1's gate clamp rather than to GND, so a transient entering on J8 is absorbed only by C11 47 µF. Q2 does not pass it to D1, because a drain-high surge reverse-biases the body diode and U4 holds the gate off. A TVS at J8 with standoff above the battery voltage and clamping below Q2's 60 V VDS (AOS AON6262E datasheet p.1, Datasheet) would cover this entry. The battery voltage is not stated, so the standoff must be chosen against it.	Review
13.5.5	J9	VCC from the ESC lead feeds U1's switching input with only C3 and C11 as filtering, so U1's input ripple current returns along the J9 harness and radiates from it. An LC or ferrite filter between J9 and C3 would keep that current on the board. CISPR 32 radiated emissions.	Review
13.5.6	J1, J4	THRR and THRL run from J1_3 and J4_3 directly to U7_59 PD12 and U7_60 PD13, with no series resistor or clamp. The edge is 2.5 ns into 10 pF at OSPEEDR = 11 (STMicroelectronics STM32F765VI datasheet p.161, Datasheet). The ESC harness radiates its harmonics, and a strike reaches the pin unattenuated. OSPEEDR = 00 in firmware (100 ns maximum into 50 pF, p.160) plus a series resistor at each header pin would slow the edge and limit current into U7's clamp. CISPR 32; IEC 61000-4-2.	Review
13.5.7	J1, J4, J9	The ESC supply returns via J9_1 GND, while THRR and THRL reference J1_1 and J4_1 GND. Motor current shared between these returns shifts the PWM reference at the ESC (ground bounce). Bring the header GND returns to the same point as J9_1, and run each PWM wire paired with its GND.	Review
13.5.8	J2, J10, J12	I2C2_SCL and I2C2_SDA leave the board on three connectors and reach U5, U6, U8 and U7_46/U7_47 with no series resistor or clamp. U5, U6 and U8 are 2 kV HBM parts (STMicroelectronics LPS22HB p.14, LIS2MDL p.11, LSM6DSO p.15, source: Tomachie). HBM and IEC 61000-4-2 use different waveforms and source impedances, so no system margin can be stated. A low-capacitance TVS array to GND plus series resistors at the connectors would keep strikes off all four devices.	Review
13.5.9	J11	I2C1_SCL and I2C1_SDA run from J11_2 and J11_3 directly to U7_92 PB6 and U7_93 PB7, with no series resistor or clamp. Where the J11 harness is externally reachable, a series resistor and low-capacitance TVS array to GND would limit discharge current into U7. IEC 61000-4-2.	Review
13.5.10	J2, J3	UART7 (J2_2/J2_3 to U7_38 PE8/U7_37 PE7) and UART4 (J3_2/J3_3 to U7_71 PA12/U7_70 PA11) connect directly, with no series resistor or clamp. A series resistor at each pin would limit discharge and contention current into U7, with a TVS array to GND where the harness leaves the enclosure. IEC 61000-4-2.	Review
13.5.11	J10, J11, J12	+3V3 is exported on pin 1 of each connector with no series element. A harness short or strike lands directly on the rail shared by U5, U6, U8, U9 and U7. A resettable fuse or current limiter in series with the off-board +3V3 pins would isolate harness faults from the MCU rail.	Review
13.5.12	J2, J3	+5V is exported on pin 1 of J2 and J3 with no series element. A harness short collapses +5V and, through U2, +3V3. A resettable fuse or current limiter in series with each off-board +5V pin would isolate harness faults from both rails.	Review
13.5.13	J2	J2 carries the value Conn_01x04_Pin on a six-pin JST GH BM06B-GHS-TBT footprint with a six-pin symbol; the label disagrees with the part. This belongs to the functional/BOM review.	Review
13.5.14	All connectors	Single ground domain GND. There is no chassis net and no part between grounds; every connector return and the J13 shield sit on logic GND, consistent with a battery-powered product with no earth reference. CISPR 32; EN 55035.	Info
13.5.15	J1, J4	Pin 2 of both headers is unconnected, so an ESC with a BEC cannot back-feed its supply onto the board; only PWM and GND are exchanged. Wiring pin 2 to a rail would let the ESC supply drive that rail.	Info
13.5.16	J13	J13_10 SHIELD is on GND directly. A microSD socket takes no cable from a second device at another potential, so a direct low-inductance shield bond to logic GND is acceptable and no dedicated shield net or R\|\|C bond is needed. IEC 61000-4-2.	✓
13.5.17	J14	J14_2 Ext (U.FL outer conductor) is on GND, the correct RF return for the 50 Ω feed into U9's matching network (Nordic nRF24L01+ datasheet pp.64, 66-67, Datasheet).	✓
13.5.18	J7	J7_2 on Net-(D1-A) has D1 SMBJ33CA to GND with no series element ahead of it, so D1 is the first and last clamp before U4_6 ANODE and the Q2 source. This is the placement TI shows for the optional SMBJ33CA in the LM74700 12-V reference (TI LM74700 datasheet Fig. 10-2, p.14, source: Tomachie). IEC 61000-4-2; IEC 61000-4-5.	✓
13.5.19	D2, D3, D4	SK6812 pin 1 VSS is on GND and pin 3 VDD on +5V, matching the datasheet pin functions. The device is rated 4000 V ESD and has built-in reverse-polarity protection (SK6812 datasheet p.3, Datasheet). The LEDs sit on no connector.	✓

13.6 Citations

AI-Assisted —

References
AON6262E (Alpha & Omega Semiconductor (AOS)) — datasheet www.aosmd.com/sites/default/files/res/datasheets/AON6262E...
MMSZ5245 (onsemi) — datasheet www.mouser.com/datasheet/2/308/MMSZ5221ET1_D-1773609.pdf
SK6812 (LED COLOR (www.szledcolor.com)) — datasheet cdn-shop.adafruit.com/product-files/1138/SK6812+LED+datas...
STM32F765VI (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/stm32f765vi.pdf
nRF24L01P (Nordic Semiconductor ASA) — datasheet datasheet.lcsc.com/datasheet/pdf/1f70bc6ad7df407cb308db24...

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on LSSI buses	Yes	Place test points on every LSSI bus signal (JTAG, SWD, I2C, I3C, MDIO, SPI, QSPI, UART) that has none
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Insert on feedback pins	Yes	Place a test point on each regulator feedback / set net that has none, so its divider can be checked
Insert on power-good nets	No	Place a test point on each used power-good net that has none and no boundary scan
Insert on NVM programming nets	No	Place test points on the nets used to program on-board memory (QSPI, etc.)
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target solder-joint testability	0%	Insert TPs in priority order until this shorts/opens solder-joint testability % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	Manual	Visual inspection for polarity, placement, and solder
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	None	No automated test equipment
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	None	No physical probe access to test points
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	No	Unpowered shorts and opens detection via probe access
Passives	No	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.x	IEEE 1149.1-2013 / 1149.6-2015 / 1149.10-2017 full boundary scan suite
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Pre-programmed	Chips arrive pre-programmed; no programming access needed
Environment
Test environment	volume_production	Volume production: fixture-based, AOI/AXI, throughput-optimized

14.2 Power Rail Test Point Check

Power rails found	5
Rails with TPs	5
Rails without TPs	0
With designer annotation	4

Parts adjudicated as TH: J2 (Conn_01x04_Pin), J12 (Conn_01x04_Pin), J9 (Conn_01x02_Pin), J10 (Conn_01x04_Pin), J11 (Conn_01x04_Pin), J8 (Conn_01x02_Pin), J7 (Conn_01x02_Pin), J3 (Conn_01x04_Pin), J5 (Conn_01x04_Pin). Their description and footprint do not say how they mount, so the mounting was looked up. If any is wrong, state SMT or TH/THT/THRU in the part's description.

10 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+3V3	PWR_LOW	J10_1, J11_1, J12_1 (through-hole)	✓
+5V	PWR_LOW	J2_1, J3_1, J5_1 (through-hole)	✓
+BATT		J8_2 (through-hole)	✓
GND	PWR_LOW	H1_1, H2_1, H3_1, H4_1, J1_1, J10_4, J11_4, J12_4, J2_6, J3_4, J4_1, J5_6, J7_1, J8_1, J9_1 (through-hole)	✓
VCC	PWR_HIGH	J9_2 (through-hole)	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP3	GND	caiman.kicad_sch
TP6	GND	caiman.kicad_sch
TP7	GND	caiman.kicad_sch
TP8	GND	caiman.kicad_sch
TP9	GND	caiman.kicad_sch
TP10	GND	caiman.kicad_sch

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP1	MOSI	caiman.kicad_sch
TP2	CSN	caiman.kicad_sch
TP4	MISO	caiman.kicad_sch
TP5	SCK	caiman.kicad_sch

14.3 Unconnected 2-Pin Passives

Fitted 2-pin passives (capacitors, resistors, inductors) with a pin that reaches no net. These may be intentional unused or spare footprints, but each is pointed out for review.

IC	Type	Issue
R18	22 ohm	Pin R18.2 connects only to J6, which this variant does not fit - the passive is fitted but serves no circuit on this board.
R16	22 ohm	Pin R16.2 connects only to J6, which this variant does not fit - the passive is fitted but serves no circuit on this board.
R17	22 ohm	Pin R17.2 connects only to J6, which this variant does not fit - the passive is fitted but serves no circuit on this board.

14.4 Current Test Points

Total test points

No test points found in design.

14.5 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.6 Inspection

Total: 115 components, 426 of 434 pins with inspection coverage.

14.6.1 Manual Optical

Solder joint coverage is analyzed as if AOI were available. Manual inspection may not detect all opens or shorts present.

Package Identified from the Footprint Name (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251, but each one names its package: a chip size code (0201 or larger) or a package name such as SOT, SOIC or QFP. These solder joints count toward inspection coverage.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Package_QFP
LQFP-100_14x14mm_P0.5mm			QFP (Quad Flat Pack)	Footprint	1	100	U7
Package_TO_SOT_SMD
SOT-23-5			SOT (Small Outline Transistor)	Footprint	1	5	U10
SOT-23-6			SOT (Small Outline Transistor)	Footprint	1	6	U4
TSOT-23-6			SOT (Small Outline Transistor)	Footprint	2	12	U1, U2
Capacitor_SMD
C_0402_1005Metric			Chip Passive	Footprint size	35	70	C12, C13, C14, C15, C16, C17, C18, C19 ...+27 more
C_0603_1608Metric			Chip Passive	Footprint size	14	28	C1, C10, C2, C3, C4, C47, C49, C5 ...+6 more
Inductor_SMD
L_0402_1005Metric			Chip Passive	Footprint size	3	6	L3, L4, L5
Resistor_SMD
R_0402_1005Metric			Chip Passive	Footprint size	19	38	R10, R11, R12, R13, R14, R15, R16, R17 ...+11 more
R_0603_1608Metric			Chip Passive	Footprint size	8	16	R1, R2, R3, R30, R4, R5, R6, R7
PCM_Diode_SMD_AKL
D_SOD-123F_Zener			SOD (Diode Package)	Footprint	1	2	DZ1
Subtotal: 85 components, 283 pins
Opens only (leads visible, shorts unreliable)
Package_SO
PowerPAK_SO-8L_Single			SOIC/SOP	Footprint	1	5	Q1
Subtotal: 1 components, 5 pins

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Package_TO_SOT_SMD
TDSON-8-1			SOT (Small Outline Transistor)	Designator	1	5	Q2
PCM_Capacitor_SMD_AKL
CP_Elec_8x10			Chip Passive	Designator	2	4	C11, C48
PCM_Inductor_SMD_AKL
L_Wuerth_MAPI-4020			Chip Passive	Designator	2	4	L1, L2
LED_SMD
LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm			SOD (Diode Package)	Designator	3	12	D2, D3, D4
PCM_Diode_SMD_Handsoldering_AKL
D_SMB_TVS			SOD (Diode Package)	Designator	1	2	D1
Subtotal: 9 components, 27 pins
Opens only (leads visible, shorts unreliable)
Package_TO_SOT_THT
TO-92			SOIC/SOP	Designator	1	3	U3
Subtotal: 1 components, 3 pins
Presence check (manual verification)
Connector_AMASS
AMASS_XT30UPB-M_1x02_P5.0mm_Vertical			Connector	Designator	1	2	J7
AMASS_XT60-F_1x02_P7.20mm_Vertical			Connector	Designator	1	2	J9
AMASS_XT60-M_1x02_P7.20mm_Vertical			Connector	Designator	1	2	J8
Connector_Card
microSD_HC_Hirose_DM3AT-SF-PEJM5			Connector	Designator	1	10	J13
Connector_Coaxial
U.FL_Hirose_U.FL-R-SMT-1_Vertical			Connector	Designator	1	2	J14
Connector_JST
JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical			Connector	Designator	4	16	J10, J11, J12, J3
JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical			Connector	Designator	2	12	J2, J5
Connector_PinHeader_2.54mm
PinHeader_1x03_P2.54mm_Vertical			Connector	Designator	2	6	J1, J4
Subtotal: 13 components, 52 pins

14.6.2 AXI

Package Identified from the Footprint Name (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251, but each one names its package (QFN, DFN, BGA or LGA). These hidden joints count toward X-ray inspection coverage.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Package_LGA
LGA-12_2x2mm_P0.5mm			LGA (Land Grid Array)	Footprint	1	12	U6
LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y			LGA (Land Grid Array)	Footprint	1	14	U8
ST_HLGA-10_2x2mm_P0.5mm_LayoutBorder3x2y			LGA (Land Grid Array)	Footprint	1	10	U5
Package_DFN_QFN
QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm			QFN/DFN (No-Lead)	Footprint	1	20	U9
Subtotal: 4 components, 56 pins

14.6.3 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library symbol lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
Crystal
Crystal_SMD_3225-4Pin_3.2x2.5mm	Oscillator / Crystal	Designator	2	8	Y1, Y2
Subtotal: 2 components, 8 pins

14.7 Solder-Joint Testability

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.7.1 Solder-Joint Testability Summary

Solder-Joint Testability Summary (451 solder joints)
Test Method	Opens	Shorts
X-ray (AXI)	56 (12.4%)	56 (12.4%)
Optical (AOI)	288 (63.9%)	283 (62.7%)
Electrical
Powered-off Testing	0 (0.0%)	0 (0.0%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	43 (9.5%)	43 (9.5%)
Total	94 (20.8%)	221 (49.0%)
Total Solder-Joint Testability	365 (80.9%)	404 (89.6%)
No coverage	86 (19.1%)	47 (10.4%)

14.7.2 Untestable Solder Joints (46)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
D2_2	Net-(D2-DIN)
D2_4	Net-(D2-DOUT)
U3_3	Net-(DZ1-A)
D4_2	Net-(D3-DOUT)
D4_4	Net-(D4-DOUT)
R28_1
R28_2
J6_1
J6_2
J6_3
J6_4
J6_5
J6_6
J4_2
J4_3	THRL
J15_1
J15_2
J15_3
D3_2	Net-(D2-DOUT)
D3_4	Net-(D3-DOUT)
Y1_1	Net-(U7-PH0)
Y1_4	Net-(C28-Pad2)
Y2_1	Net-(U9-XC2)
Y2_4	Net-(U9-XC1)
D1_2	Net-(D1-A)
L1_1	Net-(U1-SW)
J13_9	SD_Detect
J1_2
J1_3	THRR
L2_1	Net-(U2-SW)
J14_1	Antenna
Q2_1	Net-(D1-A)
Q2_2	Net-(D1-A)
Q2_3	Net-(D1-A)
Q2_4	Net-(Q2-G)
R31_1
R31_2
J7_2	Net-(D1-A)
R29_1
R29_2
R25_1
R25_2
J5_2	TX1
J5_3	RX1
J5_4
J5_5

14.7.3 Per-Solder-Joint Testability Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
C45_1	GND	●	●	●	◐	-	-
C45_2	Net-(U7-VCAP_2)	-	-	●	◐	-	-
R8_1	NRST	-	-	●	◐	-	-
R8_2	+3V3	●	●	●	◐	-	-
C50_1	GND	-	●	●	◐	-	-
C50_2	+5V	-	●	●	◐	-	-
C16_1	Net-(C16-Pad1)	-	-	●	◐	-	-
C16_2	+3V3	●	●	●	◐	-	-
D2_1	GND	-	●	-	-	-	-
D2_2	Net-(D2-DIN)	-	-	-	-	-	-
D2_3	+5V	-	●	-	-	-	-
D2_4	Net-(D2-DOUT)	-	-	-	-	-	-
J2_1	+5V	-	●	-	-	-	-
J2_2	UART7_TX	●	◐	-	-	-	-
J2_3	UART7_RX	●	◐	-	-	-	-
J2_4	I2C2_SCL	●	◐	-	-	-	-
J2_5	I2C2_SDA	●	◐	-	-	-	-
J2_6	GND	-	●	-	-	-	-
J12_1	+3V3	-	●	-	-	-	-
J12_2	I2C2_SCL	●	◐	-	-	-	-
J12_3	I2C2_SDA	●	◐	-	-	-	-
J12_4	GND	-	●	-	-	-	-
R23_1	Net-(U7-PC9)	-	-	●	◐	-	-
R23_2	DAT1	●	◐	●	◐	-	-
C29_1	GND	●	●	●	◐	-	-
C29_2	Net-(U6-C1)	-	-	●	◐	-	-
J9_1	GND	-	●	-	-	-	-
J9_2	VCC	-	●	-	-	-	-
C25_1	+3V3	-	●	●	◐	-	-
C25_2	GND	-	●	●	◐	-	-
R4_1	VBAT	-	●	●	◐	-	-
R4_2	+BATT	-	●	●	◐	-	-
C20_1	GND	●	●	●	◐	-	-
C20_2	NRST	-	-	●	◐	-	-
C15_1	Net-(C15-Pad1)	-	-	●	◐	-	-
C15_2	+3V3	●	●	●	◐	-	-
C39_1	Net-(U9-XC1)	-	-	●	◐	-	-
C39_2	GND	●	●	●	◐	-	-
U3_1	+BATT	●	●	-	-	-	-
U3_2	GND	-	●	-	-	-	-
U3_3	Net-(DZ1-A)	-	-	-	-	-	-
R2_1	VCC	-	●	●	◐	-	-
R2_2	GND	-	●	●	◐	-	-
Q1_1	+BATT	-	●	●	-	-	-
Q1_2	+BATT	-	●	●	-	-	-
Q1_3	+BATT	-	●	●	-	-	-
Q1_4	Net-(DZ1-A)	-	-	●	-	-	-
Q1_5	VCC	-	●	●	-	-	-
D4_1	GND	-	●	-	-	-	-
D4_2	Net-(D3-DOUT)	-	-	-	-	-	-
D4_3	+5V	-	●	-	-	-	-
D4_4	Net-(D4-DOUT)	-	-	-	-	-	-
R28_1		-	-	-	-	-	-
R28_2		-	-	-	-	-	-
C49_1	GND	-	●	●	◐	-	-
C49_2	+5V	-	●	●	◐	-	-
J10_1	+3V3	-	●	-	-	-	-
J10_2	I2C2_SCL	●	◐	-	-	-	-
J10_3	I2C2_SDA	●	◐	-	-	-	-
J10_4	GND	-	●	-	-	-	-
L5_1	Net-(U9-ANT2)	-	-	●	◐	-	-
L5_2	Net-(C38-Pad1)	-	-	●	◐	-	-
R18_1	Net-(U7-PB3)	-	-	●	◐	-	-
R18_2	SWO	-	-	●	◐	-	-
C4_1	GND	-	●	●	◐	-	-
C4_2	+5V	-	●	●	◐	-	-
J6_1		-	-	-	-	-	-
J6_2		-	-	-	-	-	-
J6_3		-	-	-	-	-	-
J6_4		-	-	-	-	-	-
J6_5		-	-	-	-	-	-
J6_6		-	-	-	-	-	-
C12_1	Net-(C12-Pad1)	-	-	●	◐	-	-
C12_2	+3V3	●	●	●	◐	-	-
U5_1	+3V3	-	●	-	-	●	◐
U5_10	+3V3	-	●	-	-	●	◐
U5_2	I2C2_SCL	●	◐	-	-	●	◐
U5_3	GND	-	●	-	-	●	◐
U5_4	I2C2_SDA	●	◐	-	-	●	◐
U5_5	GND	-	●	-	-	●	◐
U5_6	+3V3	-	●	-	-	●	◐
U5_7	BAR_INT	-	-	-	-	●	◐
U5_8	GND	-	●	-	-	●	◐
U5_9	GND	-	●	-	-	●	◐
R26_1	Net-(U7-PC11)	-	-	●	◐	-	-
R26_2	DAT3	●	◐	●	◐	-	-
J4_1	GND	-	●	-	-	-	-
J4_2		-	-	-	-	-	-
J4_3	THRL	-	-	-	-	-	-
C5_1	GND	-	●	●	◐	-	-
C5_2	+5V	-	●	●	◐	-	-
R10_1	+3V3	●	●	●	◐	-	-
R10_2	DAT3	●	◐	●	◐	-	-
J11_1	+3V3	-	●	-	-	-	-
J11_2	I2C1_SCL	●	◐	-	-	-	-
J11_3	I2C1_SDA	●	◐	-	-	-	-
J11_4	GND	-	●	-	-	-	-
C23_1	+3V3	-	●	●	◐	-	-
C23_2	GND	-	●	●	◐	-	-
R24_1	Net-(U7-PC10)	-	-	●	◐	-	-
R24_2	DAT2	●	◐	●	◐	-	-
J15_1		-	-	-	-	-	-
J15_2		-	-	-	-	-	-
J15_3		-	-	-	-	-	-
R20_1	Net-(U9-IREF)	-	-	●	◐	-	-
R20_2	GND	●	●	●	◐	-	-
C9_1	Net-(D1-A)	-	-	●	◐	-	-
C9_2	GND	●	●	●	◐	-	-
D3_1	GND	-	●	-	-	-	-
D3_2	Net-(D2-DOUT)	-	-	-	-	-	-
D3_3	+5V	-	●	-	-	-	-
D3_4	Net-(D3-DOUT)	-	-	-	-	-	-
R16_1	Net-(U7-PA13)	-	-	●	◐	-	-
R16_2	SWDIO	-	-	●	◐	-	-
C6_1	GND	-	●	●	◐	-	-
C6_2	+5V	-	●	●	◐	-	-
C1_1	Net-(U1-SW)	-	-	●	◐	-	-
C1_2	Net-(U1-BST)	-	-	●	◐	-	-
Y1_1	Net-(U7-PH0)	-	-	-	-	-	-
Y1_2	GND	-	●	-	-	-	-
Y1_3	GND	-	●	-	-	-	-
Y1_4	Net-(C28-Pad2)	-	-	-	-	-	-
C10_1	Net-(U4-VCAP)	-	-	●	◐	-	-
C10_2	Net-(D1-A)	-	-	●	◐	-	-
C44_1	GND	-	●	●	◐	-	-
C44_2	+3V3	-	●	●	◐	-	-
C17_1	Net-(U7-VBAT)	-	-	●	◐	-	-
C17_2	+3V3	●	●	●	◐	-	-
L3_1	Net-(U9-ANT1)	-	-	●	◐	-	-
L3_2	Net-(U9-VDD_PA)	-	-	●	◐	-	-
C38_1	Net-(C38-Pad1)	-	-	●	◐	-	-
C38_2	Antenna	-	-	●	◐	-	-
C21_1	Net-(U7-VREF+)	-	-	●	◐	-	-
C21_2	+3V3	●	●	●	◐	-	-
C41_1	GND	●	●	●	◐	-	-
C41_2	Net-(U9-DVDD)	-	-	●	◐	-	-
U10_1		-	-	●	◐	-	-
U10_2	LED	-	-	●	◐	-	-
U10_3	GND	-	●	●	◐	-	-
U10_4	Net-(U10-Y)	-	-	●	◐	-	-
U10_5	+5V	-	●	●	◐	-	-
C27_1	GND	-	●	●	◐	-	-
C27_2	+3V3	-	●	●	◐	-	-
R7_1	VCHG	-	-	●	◐	-	-
R7_2	GND	●	●	●	◐	-	-
R17_1	Net-(U7-PA14)	-	-	●	◐	-	-
R17_2	SWCLK	-	-	●	◐	-	-
C43_1	GND	-	●	●	◐	-	-
C43_2	+3V3	-	●	●	◐	-	-
C8_1	GND	-	●	●	◐	-	-
C8_2	+3V3	-	●	●	◐	-	-
Y2_1	Net-(U9-XC2)	-	-	-	-	-	-
Y2_2	GND	-	●	-	-	-	-
Y2_3	GND	-	●	-	-	-	-
Y2_4	Net-(U9-XC1)	-	-	-	-	-	-
C24_1	GND	●	●	●	◐	-	-
C24_2	Net-(U7-PH0)	-	-	●	◐	-	-
C37_1	GND	-	●	●	◐	-	-
C37_2	Antenna	-	-	●	◐	-	-
U7_1		-	-	●	◐	-	-
U7_10	GND	●	●	●	◐	-	-
U7_100	Net-(C16-Pad1)	-	-	●	◐	-	-
U7_11	Net-(C15-Pad1)	-	-	●	◐	-	-
U7_12	Net-(U7-PH0)	-	-	●	◐	-	-
U7_13	Net-(U7-PH1)	-	-	●	◐	-	-
U7_14	NRST	-	-	●	◐	-	-
U7_15	VBAT	-	●	●	◐	-	-
U7_16	VCHG	-	-	●	◐	-	-
U7_17		-	-	●	◐	-	-
U7_18		-	-	●	◐	-	-
U7_19	GND	●	●	●	◐	-	-
U7_2		-	-	●	◐	-	-
U7_20	Net-(U7-VREF+)	-	-	●	◐	-	-
U7_21	Net-(U7-VDDA)	-	-	●	◐	-	-
U7_22		-	-	●	◐	-	-
U7_23		-	-	●	◐	-	-
U7_24	IRQ	-	-	●	◐	-	-
U7_25	CSN	-	-	●	◐	-	-
U7_26	GND	●	●	●	◐	-	-
U7_27	Net-(C13-Pad1)	-	-	●	◐	-	-
U7_28	CE	-	-	●	◐	-	-
U7_29	SCK	-	-	●	◐	-	-
U7_3		-	-	●	◐	-	-
U7_30	MISO	-	-	●	◐	-	-
U7_31	MOSI	-	-	●	◐	-	-
U7_32		-	-	●	◐	-	-
U7_33		-	-	●	◐	-	-
U7_34		-	-	●	◐	-	-
U7_35		-	-	●	◐	-	-
U7_36		-	-	●	◐	-	-
U7_37	UART7_RX	●	◐	●	◐	-	-
U7_38	UART7_TX	●	◐	●	◐	-	-
U7_39		-	-	●	◐	-	-
U7_4		-	-	●	◐	-	-
U7_40		-	-	●	◐	-	-
U7_41		-	-	●	◐	-	-
U7_42		-	-	●	◐	-	-
U7_43		-	-	●	◐	-	-
U7_44		-	-	●	◐	-	-
U7_45		-	-	●	◐	-	-
U7_46	I2C2_SCL	●	◐	●	◐	-	-
U7_47	I2C2_SDA	●	◐	●	◐	-	-
U7_48	Net-(U7-VCAP_1)	-	-	●	◐	-	-
U7_49	GND	●	●	●	◐	-	-
U7_5		-	-	●	◐	-	-
U7_50	Net-(C12-Pad1)	-	-	●	◐	-	-
U7_51	UART5_RX	-	-	●	◐	-	-
U7_52	UART5_TX	-	-	●	◐	-	-
U7_53	USART1_TX	-	-	●	◐	-	-
U7_54	USART1_RX	-	-	●	◐	-	-
U7_55	USART3_TX	-	-	●	◐	-	-
U7_56	USART3_RX	-	-	●	◐	-	-
U7_57		-	-	●	◐	-	-
U7_58		-	-	●	◐	-	-
U7_59	THRR	-	-	●	◐	-	-
U7_6	Net-(U7-VBAT)	-	-	●	◐	-	-
U7_60	THRL	-	-	●	◐	-	-
U7_61		-	-	●	◐	-	-
U7_62	SD_Detect	-	-	●	◐	-	-
U7_63	LED	-	-	●	◐	-	-
U7_64		-	-	●	◐	-	-
U7_65	Net-(U7-PC8)	-	-	●	◐	-	-
U7_66	Net-(U7-PC9)	-	-	●	◐	-	-
U7_67		-	-	●	◐	-	-
U7_68		-	-	●	◐	-	-
U7_69		-	-	●	◐	-	-
U7_7		-	-	●	◐	-	-
U7_70	UART4_RX	●	◐	●	◐	-	-
U7_71	UART4_TX	●	◐	●	◐	-	-
U7_72	Net-(U7-PA13)	-	-	●	◐	-	-
U7_73	Net-(U7-VCAP_2)	-	-	●	◐	-	-
U7_74	GND	●	●	●	◐	-	-
U7_75	Net-(C18-Pad1)	-	-	●	◐	-	-
U7_76	Net-(U7-PA14)	-	-	●	◐	-	-
U7_77		-	-	●	◐	-	-
U7_78	Net-(U7-PC10)	-	-	●	◐	-	-
U7_79	Net-(U7-PC11)	-	-	●	◐	-	-
U7_8		-	-	●	◐	-	-
U7_80	Net-(U7-PC12)	-	-	●	◐	-	-
U7_81		-	-	●	◐	-	-
U7_82		-	-	●	◐	-	-
U7_83	Net-(U7-PD2)	-	-	●	◐	-	-
U7_84		-	-	●	◐	-	-
U7_85		-	-	●	◐	-	-
U7_86		-	-	●	◐	-	-
U7_87		-	-	●	◐	-	-
U7_88		-	-	●	◐	-	-
U7_89	Net-(U7-PB3)	-	-	●	◐	-	-
U7_9		-	-	●	◐	-	-
U7_90		-	-	●	◐	-	-
U7_91		-	-	●	◐	-	-
U7_92	I2C1_SCL	●	◐	●	◐	-	-
U7_93	I2C1_SDA	●	◐	●	◐	-	-
U7_94		-	-	●	◐	-	-
U7_95		-	-	●	◐	-	-
U7_96		-	-	●	◐	-	-
U7_97	UART8_RX	-	-	●	◐	-	-
U7_98	UART8_TX	-	-	●	◐	-	-
U7_99	GND	●	●	●	◐	-	-
C47_1	GND	-	●	●	◐	-	-
C47_2	+5V	-	●	●	◐	-	-
C3_1	GND	-	●	●	◐	-	-
C3_2	VCC	-	●	●	◐	-	-
C22_1	+3V3	-	●	●	◐	-	-
C22_2	GND	-	●	●	◐	-	-
C28_1	GND	●	●	●	◐	-	-
C28_2	Net-(C28-Pad2)	-	-	●	◐	-	-
U8_1	GND	-	●	-	-	●	◐
U8_10		-	-	-	-	●	◐
U8_11		-	-	-	-	●	◐
U8_12	+3V3	-	●	-	-	●	◐
U8_13	I2C2_SCL	●	◐	-	-	●	◐
U8_14	I2C2_SDA	●	◐	-	-	●	◐
U8_2	GND	-	●	-	-	●	◐
U8_3	GND	-	●	-	-	●	◐
U8_4	IMU_INT	-	-	-	-	●	◐
U8_5	+3V3	-	●	-	-	●	◐
U8_6	GND	-	●	-	-	●	◐
U8_7	GND	-	●	-	-	●	◐
U8_8	+3V3	-	●	-	-	●	◐
U8_9		-	-	-	-	●	◐
C36_1	Net-(U9-VDD_PA)	-	-	●	◐	-	-
C36_2	GND	●	●	●	◐	-	-
U2_1	+3V3	●	●	●	◐	-	-
U2_2	+5V	-	●	●	◐	-	-
U2_3	+5V	-	●	●	◐	-	-
U2_4	GND	-	●	●	◐	-	-
U2_5	Net-(U2-SW)	-	-	●	◐	-	-
U2_6	Net-(U2-BST)	-	-	●	◐	-	-
R27_1	Net-(U7-PC12)	-	-	●	◐	-	-
R27_2	CLK	●	◐	●	◐	-	-
R13_1	DAT0	●	◐	●	◐	-	-
R13_2	+3V3	●	●	●	◐	-	-
D1_1	GND	-	●	-	-	-	-
D1_2	Net-(D1-A)	-	-	-	-	-	-
L1_1	Net-(U1-SW)	-	-	-	-	-	-
L1_2	+5V	●	●	-	-	-	-
J13_1	DAT2	●	◐	-	-	-	-
J13_10	GND	-	●	-	-	-	-
J13_2	DAT3	●	◐	-	-	-	-
J13_3	CMD	●	◐	-	-	-	-
J13_4	+3V3	-	●	-	-	-	-
J13_5	CLK	●	◐	-	-	-	-
J13_6	GND	-	●	-	-	-	-
J13_7	DAT0	●	◐	-	-	-	-
J13_8	DAT1	●	◐	-	-	-	-
J13_9	SD_Detect	-	-	-	-	-	-
C35_1	Net-(U9-VDD_PA)	-	-	●	◐	-	-
C35_2	GND	●	●	●	◐	-	-
R15_1	SD_Detect	-	-	●	◐	-	-
R15_2	+3V3	●	●	●	◐	-	-
R6_1	VCHG	-	-	●	◐	-	-
R6_2	Net-(D1-A)	-	-	●	◐	-	-
C13_1	Net-(C13-Pad1)	-	-	●	◐	-	-
C13_2	+3V3	●	●	●	◐	-	-
U9_1	CE	-	-	-	-	●	◐
U9_10	Net-(U9-XC1)	-	-	-	-	●	◐
U9_11	Net-(U9-VDD_PA)	-	-	-	-	●	◐
U9_12	Net-(U9-ANT1)	-	-	-	-	●	◐
U9_13	Net-(U9-ANT2)	-	-	-	-	●	◐
U9_14	GND	●	●	-	-	●	◐
U9_15	+3V3	-	●	-	-	●	◐
U9_16	Net-(U9-IREF)	-	-	-	-	●	◐
U9_17	GND	●	●	-	-	●	◐
U9_18	+3V3	-	●	-	-	●	◐
U9_19	Net-(U9-DVDD)	-	-	-	-	●	◐
U9_2	CSN	-	-	-	-	●	◐
U9_20	GND	●	●	-	-	●	◐
U9_3	SCK	-	-	-	-	●	◐
U9_4	MOSI	-	-	-	-	●	◐
U9_5	MISO	-	-	-	-	●	◐
U9_6	IRQ	-	-	-	-	●	◐
U9_7	+3V3	-	●	-	-	●	◐
U9_8	GND	●	●	-	-	●	◐
U9_9	Net-(U9-XC2)	-	-	-	-	●	◐
J1_1	GND	-	●	-	-	-	-
J1_2		-	-	-	-	-	-
J1_3	THRR	-	-	-	-	-	-
C46_1	Net-(U9-XC2)	-	-	●	◐	-	-
C46_2	GND	●	●	●	◐	-	-
C7_1	GND	-	●	●	◐	-	-
C7_2	+3V3	-	●	●	◐	-	-
U4_1	Net-(U4-VCAP)	-	-	●	◐	-	-
U4_2	GND	●	●	●	◐	-	-
U4_3	Net-(D1-A)	-	-	●	◐	-	-
U4_4	+BATT	-	●	●	◐	-	-
U4_5	Net-(Q2-G)	-	-	●	◐	-	-
U4_6	Net-(D1-A)	-	-	●	◐	-	-
C30_1	+3V3	-	●	●	◐	-	-
C30_2	GND	-	●	●	◐	-	-
C14_1	Net-(U7-VDDA)	-	-	●	◐	-	-
C14_2	+3V3	●	●	●	◐	-	-
U1_1	+5V	●	●	●	◐	-	-
U1_2	Net-(U1-EN)	-	-	●	◐	-	-
U1_3	VCC	●	●	●	◐	-	-
U1_4	GND	-	●	●	◐	-	-
U1_5	Net-(U1-SW)	-	-	●	◐	-	-
U1_6	Net-(U1-BST)	-	-	●	◐	-	-
R5_1	GND	-	●	●	◐	-	-
R5_2	VBAT	-	●	●	◐	-	-
R3_1	+BATT	●	●	●	◐	-	-
R3_2	Net-(DZ1-A)	-	-	●	◐	-	-
R14_1	DAT1	●	◐	●	◐	-	-
R14_2	+3V3	●	●	●	◐	-	-
R19_1	Net-(U7-PD2)	-	-	●	◐	-	-
R19_2	CMD	●	◐	●	◐	-	-
C19_1	Net-(U7-VREF+)	-	-	●	◐	-	-
C19_2	+3V3	●	●	●	◐	-	-
L2_1	Net-(U2-SW)	-	-	-	-	-	-
L2_2	+3V3	●	●	-	-	-	-
C48_1	+5V	-	●	-	-	-	-
C48_2	GND	-	●	-	-	-	-
C26_1	+3V3	-	●	●	◐	-	-
C26_2	GND	-	●	●	◐	-	-
C32_1	GND	-	●	●	◐	-	-
C32_2	+3V3	-	●	●	◐	-	-
J14_1	Antenna	-	-	-	-	-	-
J14_2	GND	-	●	-	-	-	-
R21_1	Net-(U7-PC8)	-	-	●	◐	-	-
R21_2	DAT0	●	◐	●	◐	-	-
R1_1	Net-(U1-EN)	-	-	●	◐	-	-
R1_2	VCC	●	●	●	◐	-	-
R30_1	Net-(U10-Y)	-	-	●	◐	-	-
R30_2	Net-(D2-DIN)	-	-	●	◐	-	-
Q2_1	Net-(D1-A)	-	-	-	-	-	-
Q2_2	Net-(D1-A)	-	-	-	-	-	-
Q2_3	Net-(D1-A)	-	-	-	-	-	-
Q2_4	Net-(Q2-G)	-	-	-	-	-	-
Q2_5	+BATT	-	●	-	-	-	-
R12_1	Net-(U7-PH1)	-	-	●	◐	-	-
R12_2	Net-(C28-Pad2)	-	-	●	◐	-	-
C51_1	GND	-	●	●	◐	-	-
C51_2	+5V	-	●	●	◐	-	-
C31_1	+3V3	-	●	●	◐	-	-
C31_2	GND	-	●	●	◐	-	-
C34_1	+3V3	-	●	●	◐	-	-
C34_2	GND	-	●	●	◐	-	-
R31_1		-	-	-	-	-	-
R31_2		-	-	-	-	-	-
R11_1	+3V3	●	●	●	◐	-	-
R11_2	CMD	●	◐	●	◐	-	-
C42_1	Net-(U7-VCAP_1)	-	-	●	◐	-	-
C42_2	GND	●	●	●	◐	-	-
J8_1	GND	-	●	-	-	-	-
J8_2	+BATT	-	●	-	-	-	-
J7_1	GND	-	●	-	-	-	-
J7_2	Net-(D1-A)	-	-	-	-	-	-
R29_1		-	-	-	-	-	-
R29_2		-	-	-	-	-	-
R25_1		-	-	-	-	-	-
R25_2		-	-	-	-	-	-
J3_1	+5V	-	●	-	-	-	-
J3_2	UART4_TX	●	◐	-	-	-	-
J3_3	UART4_RX	●	◐	-	-	-	-
J3_4	GND	-	●	-	-	-	-
R9_1	+3V3	●	●	●	◐	-	-
R9_2	DAT2	●	◐	●	◐	-	-
C11_1	GND	-	●	-	-	-	-
C11_2	+BATT	-	●	-	-	-	-
U6_1	I2C2_SCL	●	◐	-	-	●	◐
U6_10	+3V3	-	●	-	-	●	◐
U6_11		-	-	-	-	●	◐
U6_12		-	-	-	-	●	◐
U6_2		-	-	-	-	●	◐
U6_3	+3V3	-	●	-	-	●	◐
U6_4	I2C2_SDA	●	◐	-	-	●	◐
U6_5	Net-(U6-C1)	-	-	-	-	●	◐
U6_6	GND	●	●	-	-	●	◐
U6_7	MAG_INT	-	-	-	-	●	◐
U6_8	GND	●	●	-	-	●	◐
U6_9	+3V3	-	●	-	-	●	◐
C33_1	+3V3	-	●	●	◐	-	-
C33_2	GND	-	●	●	◐	-	-
R22_1	Net-(U9-XC1)	-	-	●	◐	-	-
R22_2	Net-(U9-XC2)	-	-	●	◐	-	-
C2_1	Net-(U2-SW)	-	-	●	◐	-	-
C2_2	Net-(U2-BST)	-	-	●	◐	-	-
C40_1	GND	-	●	●	◐	-	-
C40_2	+3V3	-	●	●	◐	-	-
L4_1	Net-(U9-ANT1)	-	-	●	◐	-	-
L4_2	Net-(U9-ANT2)	-	-	●	◐	-	-
J5_1	+5V	-	●	-	-	-	-
J5_2	TX1	-	-	-	-	-	-
J5_3	RX1	-	-	-	-	-	-
J5_4		-	-	-	-	-	-
J5_5		-	-	-	-	-	-
J5_6	GND	-	●	-	-	-	-
C18_1	Net-(C18-Pad1)	-	-	●	◐	-	-
C18_2	+3V3	●	●	●	◐	-	-
DZ1_1	+BATT	-	●	●	◐	-	-
DZ1_2	Net-(DZ1-A)	-	-	●	◐	-	-

14.8 PCOLA/SOQ Testability

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.8.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	43.9%	0.0%	0.0%	10.5%	0.0%	25.5%	21.7%	0.0%
Optical Inspection (AOI)	78.3%	8.7%	43.5%	0.0%	37.4%	32.6%	33.2%	33.2%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	1.7%	6.5%	6.5%	6.5%
Combined	89.1%	8.7%	43.5%	10.5%	39.1%	46.5%	52.9%	39.6%

14.8.2 PCB Device/Pin Count

Devices (PCOLA): 115
Pins (SOQ): 434

14.8.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	38192 / 100,000	38.2%
SOQ	46352 / 100,000	46.4%
Combined	42272 / 100,000	42.3%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	10888 / 100,000	15707 / 100,000
Optical/X-ray Inspection	33913 / 100,000	39439 / 100,000
Combined (max)	38192 / 100,000	46352 / 100,000

14.8.4 PCOLA (115 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
80%	U6	LIS2MDLTR / LGA-12_2x2mm_P0.5mm	IC	●	●	●	◐	◐	AOI, AXI, LSSI, Powered_Off
80%	U8	LSM6DSO / LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y	IC	●	●	●	◐	◐	AOI, AXI, LSSI, Powered_Off
80%	U5	LPS22HBTR / ST_HLGA-10_2x2mm_P0.5mm_LayoutBorder3x2y	IC	●	●	●	◐	◐	AOI, AXI, LSSI, Powered_Off
80%	U7	STM32F765VITx / LQFP-100_14x14mm_P0.5mm	IC	●	●	●	◐	◐	AOI, LSSI, Powered_Off
70%	U9	nRF24L01P / QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm	IC	●	●	●	○	◐	AOI, AXI, Powered_Off
70%	U4	LM74700 / SOT-23-6	IC	●	●	●	○	◐	AOI, Powered_Off
70%	U10	SN74LV1T34DBV / SOT-23-5	IC	●	●	●	○	◐	AOI, Powered_Off
70%	Q1	Q_PMOS-E_Generic_SSSGD / PowerPAK_SO-8L_Single	Transistor	●	●	●	○	◐	AOI, Powered_Off
70%	U1	AP63205WU / TSOT-23-6	IC	●	●	●	○	◐	AOI, Powered_Off
70%	U2	AP63203WU / TSOT-23-6	IC	●	●	●	○	◐	AOI, Powered_Off
40%	C45	2.2uF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R8	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C50	0.1uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C16	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C33	10nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R22	1M / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI
40%	C2	100nF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI
40%	R23	22ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C29	220nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C40	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C25	4.7uF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R4	100k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C20	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C15	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C39	22pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	L4	8.2nH / L_0402_1005Metric	Inductor	●	○	◐	—	◐	AOI
40%	R2	15k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C18	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C49	0.1uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	L5	3.9nH / L_0402_1005Metric	Inductor	●	○	◐	—	◐	AOI
40%	R18	22 ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI
40%	C4	22uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C12	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R26	22ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C5	22uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R10	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C23	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R24	22ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R20	22k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C9	0.1uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R16	22 ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI
40%	C6	10uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C1	100nF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI
40%	C10	0.1uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI
40%	C44	10uf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C17	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	L3	2.7nH / L_0402_1005Metric	Inductor	●	○	◐	—	◐	AOI
40%	C38	1.5pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI
40%	C21	1uF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C41	33nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C27	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R7	27k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R17	22 ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI
40%	C43	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C8	22uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C24	18pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C37	1pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C47	0.1uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C3	10uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C22	4.7uf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C28	18pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C36	4.7pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R27	22ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R13	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C35	2.2nF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R15	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R6	100k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI
40%	C13	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C46	22pF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C7	22uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C30	10uf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C14	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R5	27k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R3	10k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R14	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R19	22ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	C19	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C42	2.2uF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C26	100nF / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C32	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R21	22ohm / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R1	100k / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	R30	330 / R_0603_1608Metric	Resistor	●	○	◐	—	◐	AOI
40%	R12	47k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI
40%	C51	0.1uF / C_0603_1608Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C31	100nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	C34	1nf / C_0402_1005Metric	Capacitor	●	○	◐	—	◐	AOI, Powered_Off
40%	R11	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
40%	DZ1	MMSZ5245 / D_SOD-123F_Zener	Diode	●	○	◐	○	◐	AOI, Powered_Off
40%	R9	10k / R_0402_1005Metric	Resistor	●	○	◐	—	◐	AOI, Powered_Off
10%	D2	SK6812 / LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm *	Diode	◐	○	○	○	○	Powered_Off
10%	J2	Conn_01x04_Pin / JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J12	Conn_01x04_Pin / JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J9	Conn_01x02_Pin / AMASS_XT60-F_1x02_P7.20mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	U3	US1881 / TO-92 *	IC	◐	○	○	○	○	Powered_Off
10%	D4	SK6812 / LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm *	Diode	◐	○	○	○	○	Powered_Off
10%	J13	Micro_SD_Card / microSD_HC_Hirose_DM3AT-SF-PEJM5 *	Connector	◐	○	○	—	○	Powered_Off
10%	Y2	16MHz / Crystal_SMD_3225-4Pin_3.2x2.5mm *	Other	◐	○	○	○	○	Powered_Off
10%	J11	Conn_01x04_Pin / JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	C48	470uF / CP_Elec_8x10 *	Capacitor	◐	○	○	—	○	Powered_Off
10%	Y1	25MHz / Crystal_SMD_3225-4Pin_3.2x2.5mm *	Other	◐	○	○	○	○	Powered_Off
10%	J8	Conn_01x02_Pin / AMASS_XT60-M_1x02_P7.20mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J7	Conn_01x02_Pin / AMASS_XT30UPB-M_1x02_P5.0mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J3	Conn_01x04_Pin / JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	D1	SMBJ33CA / D_SMB_TVS *	Diode	◐	○	○	○	○	Powered_Off
10%	C11	47uF / CP_Elec_8x10 *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J10	Conn_01x04_Pin / JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J14	50 ohm / U.FL_Hirose_U.FL-R-SMT-1_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J4	Conn_01x03_Pin / PinHeader_1x03_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	L1	3.3uH / L_Wuerth_MAPI-4020 *	Inductor	◐	○	○	—	○	Powered_Off
10%	D3	SK6812 / LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm *	Diode	◐	○	○	○	○	Powered_Off
10%	Q2	AON6262E / TDSON-8-1 *	Transistor	◐	○	○	○	○	Powered_Off
10%	J5	Conn_01x04_Pin / JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	J1	Conn_01x03_Pin / PinHeader_1x03_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	L2	2.2uH / L_Wuerth_MAPI-4020 *	Inductor	◐	○	○	—	○	Powered_Off

14.8.5 SOQ (434 solder joints)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
67%	C45_1	GND	◐	●	◐
67%	U5_2	I2C2_SCL	◐	●	◐
67%	U8_14	I2C2_SDA	◐	●	◐
67%	R8_2	+3V3	◐	●	◐
67%	U5_4	I2C2_SDA	◐	●	◐
67%	U8_13	I2C2_SCL	◐	●	◐
67%	C28_1	GND	◐	●	◐
67%	C16_2	+3V3	◐	●	◐
67%	R9_2	DAT2	◐	●	◐
67%	R9_1	+3V3	◐	●	◐
67%	C42_2	GND	◐	●	◐
67%	R11_2	CMD	◐	●	◐
67%	R11_1	+3V3	◐	●	◐
67%	U7_49	GND	◐	●	◐
67%	U7_37	UART7_RX	◐	●	◐
67%	U7_26	GND	◐	●	◐
67%	R7_2	GND	◐	●	◐
67%	R1_2	VCC	◐	●	◐
67%	R21_2	DAT0	◐	●	◐
67%	R26_2	DAT3	◐	●	◐
67%	U9_20	GND	◐	●	◐
67%	C19_2	+3V3	◐	●	◐
67%	U9_17	GND	◐	●	◐
67%	R23_2	DAT1	◐	●	◐
67%	C29_1	GND	◐	●	◐
67%	U9_14	GND	◐	●	◐
67%	R19_2	CMD	◐	●	◐
67%	R14_2	+3V3	◐	●	◐
67%	U7_10	GND	◐	●	◐
67%	C17_2	+3V3	◐	●	◐
67%	R10_1	+3V3	◐	●	◐
67%	R10_2	DAT3	◐	●	◐
67%	C20_1	GND	◐	●	◐
67%	C13_2	+3V3	◐	●	◐
67%	U7_19	GND	◐	●	◐
67%	C15_2	+3V3	◐	●	◐
67%	U7_38	UART7_TX	◐	●	◐
67%	C39_2	GND	◐	●	◐
67%	R15_2	+3V3	◐	●	◐
67%	R14_1	DAT1	◐	●	◐
67%	R3_1	+BATT	◐	●	◐
67%	U7_46	I2C2_SCL	◐	●	◐
67%	U7_47	I2C2_SDA	◐	●	◐
67%	U7_71	UART4_TX	◐	●	◐
67%	R24_2	DAT2	◐	●	◐
67%	C21_2	+3V3	◐	●	◐
67%	U1_3	VCC	◐	●	◐
67%	R20_2	GND	◐	●	◐
67%	U1_1	+5V	◐	●	◐
67%	C14_2	+3V3	◐	●	◐
67%	U4_2	GND	◐	●	◐
67%	C46_2	GND	◐	●	◐
67%	C41_1	GND	◐	●	◐
67%	C9_2	GND	◐	●	◐
67%	C36_2	GND	◐	●	◐
67%	C35_2	GND	◐	●	◐
67%	R13_2	+3V3	◐	●	◐
67%	U9_8	GND	◐	●	◐
67%	R13_1	DAT0	◐	●	◐
67%	R27_2	CLK	◐	●	◐
67%	U7_99	GND	◐	●	◐
67%	U7_93	I2C1_SDA	◐	●	◐
67%	U7_92	I2C1_SCL	◐	●	◐
67%	U7_74	GND	◐	●	◐
67%	C24_1	GND	◐	●	◐
67%	C12_2	+3V3	◐	●	◐
67%	U7_70	UART4_RX	◐	●	◐
67%	U2_1	+3V3	◐	●	◐
67%	U6_1	I2C2_SCL	◐	●	◐
67%	U6_4	I2C2_SDA	◐	●	◐
67%	U6_6	GND	◐	●	◐
67%	U6_8	GND	◐	●	◐
67%	C18_2	+3V3	◐	●	◐
50%	J2_2	UART7_TX	◐	●	○
50%	J2_3	UART7_RX	◐	●	○
50%	J2_4	I2C2_SCL	◐	●	○
50%	J2_5	I2C2_SDA	◐	●	○
50%	J12_2	I2C2_SCL	◐	●	○
50%	J12_3	I2C2_SDA	◐	●	○
50%	R23_1	Net-(U7-PC9)	◐	◐	◐
50%	C29_2	Net-(U6-C1)	◐	◐	◐
50%	C25_1	+3V3	◐	◐	◐
50%	C25_2	GND	◐	◐	◐
50%	R4_1	VBAT	◐	◐	◐
50%	R4_2	+BATT	◐	◐	◐
50%	C20_2	NRST	◐	◐	◐
50%	C15_1	Net-(C15-Pad1)	◐	◐	◐
50%	C39_1	Net-(U9-XC1)	◐	◐	◐
50%	U3_1	+BATT	◐	●	○
50%	R2_1	VCC	◐	◐	◐
50%	R2_2	GND	◐	◐	◐
50%	Q1_1	+BATT	◐	◐	◐
50%	Q1_2	+BATT	◐	◐	◐
50%	Q1_3	+BATT	◐	◐	◐
50%	Q1_5	VCC	◐	◐	◐
50%	C49_1	GND	◐	◐	◐
50%	C49_2	+5V	◐	◐	◐
50%	J10_2	I2C2_SCL	◐	●	○
50%	J10_3	I2C2_SDA	◐	●	○
50%	L5_1	Net-(U9-ANT2)	◐	◐	◐
50%	L5_2	Net-(C38-Pad1)	◐	◐	◐
50%	R18_1	Net-(U7-PB3)	◐	◐	◐
50%	R18_2	SWO	◐	◐	◐
50%	C4_1	GND	◐	◐	◐
50%	C4_2	+5V	◐	◐	◐
50%	C12_1	Net-(C12-Pad1)	◐	◐	◐
50%	U5_1	+3V3	◐	◐	◐
50%	U5_10	+3V3	◐	◐	◐
50%	U5_3	GND	◐	◐	◐
50%	U5_5	GND	◐	◐	◐
50%	U5_6	+3V3	◐	◐	◐
50%	U5_7	BAR_INT	◐	◐	◐
50%	U5_8	GND	◐	◐	◐
50%	U5_9	GND	◐	◐	◐
50%	R26_1	Net-(U7-PC11)	◐	◐	◐
50%	C5_1	GND	◐	◐	◐
50%	C5_2	+5V	◐	◐	◐
50%	J11_2	I2C1_SCL	◐	●	○
50%	J11_3	I2C1_SDA	◐	●	○
50%	C23_1	+3V3	◐	◐	◐
50%	C23_2	GND	◐	◐	◐
50%	R24_1	Net-(U7-PC10)	◐	◐	◐
50%	R20_1	Net-(U9-IREF)	◐	◐	◐
50%	C9_1	Net-(D1-A)	◐	◐	◐
50%	R16_1	Net-(U7-PA13)	◐	◐	◐
50%	R16_2	SWDIO	◐	◐	◐
50%	C6_1	GND	◐	◐	◐
50%	C6_2	+5V	◐	◐	◐
50%	C1_1	Net-(U1-SW)	◐	◐	◐
50%	C1_2	Net-(U1-BST)	◐	◐	◐
50%	C10_1	Net-(U4-VCAP)	◐	◐	◐
50%	C10_2	Net-(D1-A)	◐	◐	◐
50%	C44_1	GND	◐	◐	◐
50%	C44_2	+3V3	◐	◐	◐
50%	C17_1	Net-(U7-VBAT)	◐	◐	◐
50%	L3_1	Net-(U9-ANT1)	◐	◐	◐
50%	L3_2	Net-(U9-VDD_PA)	◐	◐	◐
50%	C38_1	Net-(C38-Pad1)	◐	◐	◐
50%	C38_2	Antenna	◐	◐	◐
50%	C21_1	Net-(U7-VREF+)	◐	◐	◐
50%	C41_2	Net-(U9-DVDD)	◐	◐	◐
50%	U10_1		◐	◐	◐
50%	U10_2	LED	◐	◐	◐
50%	U10_3	GND	◐	◐	◐
50%	U10_4	Net-(U10-Y)	◐	◐	◐
50%	U10_5	+5V	◐	◐	◐
50%	C27_1	GND	◐	◐	◐
50%	C27_2	+3V3	◐	◐	◐
50%	R7_1	VCHG	◐	◐	◐
50%	R17_1	Net-(U7-PA14)	◐	◐	◐
50%	R17_2	SWCLK	◐	◐	◐
50%	C43_1	GND	◐	◐	◐
50%	C43_2	+3V3	◐	◐	◐
50%	C8_1	GND	◐	◐	◐
50%	C8_2	+3V3	◐	◐	◐
50%	C24_2	Net-(U7-PH0)	◐	◐	◐
50%	C37_1	GND	◐	◐	◐
50%	C37_2	Antenna	◐	◐	◐
50%	U7_1		◐	◐	◐
50%	U7_100	Net-(C16-Pad1)	◐	◐	◐
50%	U7_11	Net-(C15-Pad1)	◐	◐	◐
50%	U7_12	Net-(U7-PH0)	◐	◐	◐
50%	U7_13	Net-(U7-PH1)	◐	◐	◐
50%	U7_14	NRST	◐	◐	◐
50%	U7_15	VBAT	◐	◐	◐
50%	U7_16	VCHG	◐	◐	◐
50%	U7_17		◐	◐	◐
50%	U7_18		◐	◐	◐
50%	U7_2		◐	◐	◐
50%	U7_20	Net-(U7-VREF+)	◐	◐	◐
50%	U7_21	Net-(U7-VDDA)	◐	◐	◐
50%	U7_23		◐	◐	◐
50%	U7_24	IRQ	◐	◐	◐
50%	U7_25	CSN	◐	◐	◐
50%	U7_27	Net-(C13-Pad1)	◐	◐	◐
50%	U7_28	CE	◐	◐	◐
50%	U7_29	SCK	◐	◐	◐
50%	U7_3		◐	◐	◐
50%	U7_30	MISO	◐	◐	◐
50%	U7_31	MOSI	◐	◐	◐
50%	U7_32		◐	◐	◐
50%	U7_33		◐	◐	◐
50%	U7_34		◐	◐	◐
50%	U7_35		◐	◐	◐
50%	U7_36		◐	◐	◐
50%	U7_39		◐	◐	◐
50%	U7_4		◐	◐	◐
50%	U7_40		◐	◐	◐
50%	U7_41		◐	◐	◐
50%	U7_42		◐	◐	◐
50%	U7_43		◐	◐	◐
50%	U7_44		◐	◐	◐
50%	U7_45		◐	◐	◐
50%	U7_48	Net-(U7-VCAP_1)	◐	◐	◐
50%	U7_5		◐	◐	◐
50%	U7_50	Net-(C12-Pad1)	◐	◐	◐
50%	U7_51	UART5_RX	◐	◐	◐
50%	U7_52	UART5_TX	◐	◐	◐
50%	U7_53	USART1_TX	◐	◐	◐
50%	U7_54	USART1_RX	◐	◐	◐
50%	U7_55	USART3_TX	◐	◐	◐
50%	U7_56	USART3_RX	◐	◐	◐
50%	U7_57		◐	◐	◐
50%	U7_58		◐	◐	◐
50%	U7_59	THRR	◐	◐	◐
50%	U7_6	Net-(U7-VBAT)	◐	◐	◐
50%	U7_60	THRL	◐	◐	◐
50%	U7_61		◐	◐	◐
50%	U7_62	SD_Detect	◐	◐	◐
50%	U7_63	LED	◐	◐	◐
50%	U7_64		◐	◐	◐
50%	U7_65	Net-(U7-PC8)	◐	◐	◐
50%	U7_66	Net-(U7-PC9)	◐	◐	◐
50%	U7_67		◐	◐	◐
50%	U7_68		◐	◐	◐
50%	U7_69		◐	◐	◐
50%	U7_7		◐	◐	◐
50%	DZ1_2	Net-(DZ1-A)	◐	◐	◐
50%	U7_72	Net-(U7-PA13)	◐	◐	◐
50%	U7_73	Net-(U7-VCAP_2)	◐	◐	◐
50%	U7_75	Net-(C18-Pad1)	◐	◐	◐
50%	U7_76	Net-(U7-PA14)	◐	◐	◐
50%	U7_77		◐	◐	◐
50%	U7_78	Net-(U7-PC10)	◐	◐	◐
50%	U7_79	Net-(U7-PC11)	◐	◐	◐
50%	U7_8		◐	◐	◐
50%	U7_80	Net-(U7-PC12)	◐	◐	◐
50%	U7_81		◐	◐	◐
50%	U7_82		◐	◐	◐
50%	U7_83	Net-(U7-PD2)	◐	◐	◐
50%	U7_84		◐	◐	◐
50%	U7_85		◐	◐	◐
50%	U7_86		◐	◐	◐
50%	U7_87		◐	◐	◐
50%	U7_88		◐	◐	◐
50%	U7_89	Net-(U7-PB3)	◐	◐	◐
50%	U7_9		◐	◐	◐
50%	U7_90		◐	◐	◐
50%	U7_91		◐	◐	◐
50%	U7_94		◐	◐	◐
50%	U7_95		◐	◐	◐
50%	U7_96		◐	◐	◐
50%	U7_97	UART8_RX	◐	◐	◐
50%	U7_98	UART8_TX	◐	◐	◐
50%	C47_1	GND	◐	◐	◐
50%	C47_2	+5V	◐	◐	◐
50%	C3_1	GND	◐	◐	◐
50%	C3_2	VCC	◐	◐	◐
50%	C22_1	+3V3	◐	◐	◐
50%	C22_2	GND	◐	◐	◐
50%	C28_2	Net-(C28-Pad2)	◐	◐	◐
50%	U8_1	GND	◐	◐	◐
50%	U8_10		◐	◐	◐
50%	U8_11		◐	◐	◐
50%	U8_12	+3V3	◐	◐	◐
50%	U8_2	GND	◐	◐	◐
50%	U8_3	GND	◐	◐	◐
50%	U8_4	IMU_INT	◐	◐	◐
50%	U8_5	+3V3	◐	◐	◐
50%	U8_6	GND	◐	◐	◐
50%	U8_7	GND	◐	◐	◐
50%	U8_8	+3V3	◐	◐	◐
50%	U8_9		◐	◐	◐
50%	C36_1	Net-(U9-VDD_PA)	◐	◐	◐
50%	U7_22		◐	◐	◐
50%	U2_2	+5V	◐	◐	◐
50%	U2_3	+5V	◐	◐	◐
50%	U2_4	GND	◐	◐	◐
50%	U2_5	Net-(U2-SW)	◐	◐	◐
50%	U2_6	Net-(U2-BST)	◐	◐	◐
50%	R27_1	Net-(U7-PC12)	◐	◐	◐
50%	L1_2	+5V	◐	●	○
50%	J13_1	DAT2	◐	●	○
50%	J13_2	DAT3	◐	●	○
50%	J13_3	CMD	◐	●	○
50%	J13_5	CLK	◐	●	○
50%	J13_7	DAT0	◐	●	○
50%	J13_8	DAT1	◐	●	○
50%	C35_1	Net-(U9-VDD_PA)	◐	◐	◐
50%	R15_1	SD_Detect	◐	◐	◐
50%	R6_1	VCHG	◐	◐	◐
50%	R6_2	Net-(D1-A)	◐	◐	◐
50%	C13_1	Net-(C13-Pad1)	◐	◐	◐
50%	U9_1	CE	◐	◐	◐
50%	U9_10	Net-(U9-XC1)	◐	◐	◐
50%	U9_11	Net-(U9-VDD_PA)	◐	◐	◐
50%	U9_12	Net-(U9-ANT1)	◐	◐	◐
50%	U9_13	Net-(U9-ANT2)	◐	◐	◐
50%	U9_15	+3V3	◐	◐	◐
50%	U9_16	Net-(U9-IREF)	◐	◐	◐
50%	U9_18	+3V3	◐	◐	◐
50%	U9_19	Net-(U9-DVDD)	◐	◐	◐
50%	U9_2	CSN	◐	◐	◐
50%	U9_3	SCK	◐	◐	◐
50%	U9_4	MOSI	◐	◐	◐
50%	U9_5	MISO	◐	◐	◐
50%	U9_6	IRQ	◐	◐	◐
50%	U9_7	+3V3	◐	◐	◐
50%	U9_9	Net-(U9-XC2)	◐	◐	◐
50%	R12_2	Net-(C28-Pad2)	◐	◐	◐
50%	C46_1	Net-(U9-XC2)	◐	◐	◐
50%	C7_1	GND	◐	◐	◐
50%	C7_2	+3V3	◐	◐	◐
50%	U4_1	Net-(U4-VCAP)	◐	◐	◐
50%	U4_3	Net-(D1-A)	◐	◐	◐
50%	U4_4	+BATT	◐	◐	◐
50%	U4_5	Net-(Q2-G)	◐	◐	◐
50%	U4_6	Net-(D1-A)	◐	◐	◐
50%	C30_1	+3V3	◐	◐	◐
50%	C30_2	GND	◐	◐	◐
50%	C14_1	Net-(U7-VDDA)	◐	◐	◐
50%	U1_2	Net-(U1-EN)	◐	◐	◐
50%	U1_4	GND	◐	◐	◐
50%	U1_5	Net-(U1-SW)	◐	◐	◐
50%	U1_6	Net-(U1-BST)	◐	◐	◐
50%	R5_1	GND	◐	◐	◐
50%	R5_2	VBAT	◐	◐	◐
50%	R3_2	Net-(DZ1-A)	◐	◐	◐
50%	R19_1	Net-(U7-PD2)	◐	◐	◐
50%	C19_1	Net-(U7-VREF+)	◐	◐	◐
50%	L2_2	+3V3	◐	●	○
50%	C26_1	+3V3	◐	◐	◐
50%	C26_2	GND	◐	◐	◐
50%	C32_1	GND	◐	◐	◐
50%	C32_2	+3V3	◐	◐	◐
50%	R21_1	Net-(U7-PC8)	◐	◐	◐
50%	R1_1	Net-(U1-EN)	◐	◐	◐
50%	R30_1	Net-(U10-Y)	◐	◐	◐
50%	R30_2	Net-(D2-DIN)	◐	◐	◐
50%	R12_1	Net-(U7-PH1)	◐	◐	◐
50%	C51_1	GND	◐	◐	◐
50%	C51_2	+5V	◐	◐	◐
50%	C31_1	+3V3	◐	◐	◐
50%	C31_2	GND	◐	◐	◐
50%	C34_1	+3V3	◐	◐	◐
50%	C34_2	GND	◐	◐	◐
50%	C42_1	Net-(U7-VCAP_1)	◐	◐	◐
50%	J3_2	UART4_TX	◐	●	○
50%	J3_3	UART4_RX	◐	●	○
50%	C45_2	Net-(U7-VCAP_2)	◐	◐	◐
50%	U6_10	+3V3	◐	◐	◐
50%	U6_11		◐	◐	◐
50%	U6_12		◐	◐	◐
50%	U6_2		◐	◐	◐
50%	U6_3	+3V3	◐	◐	◐
50%	R8_1	NRST	◐	◐	◐
50%	U6_5	Net-(U6-C1)	◐	◐	◐
50%	C50_1	GND	◐	◐	◐
50%	U6_7	MAG_INT	◐	◐	◐
50%	C50_2	+5V	◐	◐	◐
50%	U6_9	+3V3	◐	◐	◐
50%	C33_1	+3V3	◐	◐	◐
50%	C33_2	GND	◐	◐	◐
50%	R22_1	Net-(U9-XC1)	◐	◐	◐
50%	R22_2	Net-(U9-XC2)	◐	◐	◐
50%	C2_1	Net-(U2-SW)	◐	◐	◐
50%	C2_2	Net-(U2-BST)	◐	◐	◐
50%	C40_1	GND	◐	◐	◐
50%	C40_2	+3V3	◐	◐	◐
50%	L4_1	Net-(U9-ANT1)	◐	◐	◐
50%	L4_2	Net-(U9-ANT2)	◐	◐	◐
50%	C18_1	Net-(C18-Pad1)	◐	◐	◐
50%	C16_1	Net-(C16-Pad1)	◐	◐	◐
50%	DZ1_1	+BATT	◐	◐	◐
33%	Q1_4	Net-(DZ1-A)	○	◐	◐
17%	J1_1	GND	◐	○	○
17%	J13_6	GND	◐	○	○
17%	J14_2	GND	◐	○	○
17%	J11_4	GND	◐	○	○
17%	J12_1	+3V3	◐	○	○
17%	J4_1	GND	◐	○	○
17%	J2_6	GND	◐	○	○
17%	D3_3	+5V	◐	○	○
17%	D1_1	GND	◐	○	○
17%	Y1_2	GND	◐	○	○
17%	U3_2	GND	◐	○	○
17%	J9_2	VCC	◐	○	○
17%	Y2_3	GND	◐	○	○
17%	Q2_5	+BATT	◐	○	○
17%	J9_1	GND	◐	○	○
17%	J10_1	+3V3	◐	○	○
17%	J12_4	GND	◐	○	○
17%	J11_1	+3V3	◐	○	○
17%	D4_3	+5V	◐	○	○
17%	C48_1	+5V	◐	○	○
17%	C48_2	GND	◐	○	○
17%	Y2_2	GND	◐	○	○
17%	J2_1	+5V	◐	○	○
17%	J5_1	+5V	◐	○	○
17%	J5_6	GND	◐	○	○
17%	D2_3	+5V	◐	○	○
17%	J8_1	GND	◐	○	○
17%	J8_2	+BATT	◐	○	○
17%	J7_1	GND	◐	○	○
17%	D3_1	GND	◐	○	○
17%	J3_1	+5V	◐	○	○
17%	J13_10	GND	◐	○	○
17%	J10_4	GND	◐	○	○
17%	J3_4	GND	◐	○	○
17%	D2_1	GND	◐	○	○
17%	C11_1	GND	◐	○	○
17%	C11_2	+BATT	◐	○	○
17%	D4_1	GND	◐	○	○
17%	J13_4	+3V3	◐	○	○
17%	Y1_3	GND	◐	○	○
0%	J14_1	Antenna	○	○	○
0%	J1_3	THRR	○	○	○
0%	Q2_1	Net-(D1-A)	○	○	○
0%	Q2_2	Net-(D1-A)	○	○	○
0%	Q2_3	Net-(D1-A)	○	○	○
0%	Q2_4	Net-(Q2-G)	○	○	○
0%	D3_2	Net-(D2-DOUT)	○	○	○
0%	D4_4	Net-(D4-DOUT)	○	○	○
0%	D1_2	Net-(D1-A)	○	○	○
0%	L1_1	Net-(U1-SW)	○	○	○
0%	D2_4	Net-(D2-DOUT)	○	○	○
0%	Y1_1	Net-(U7-PH0)	○	○	○
0%	J7_2	Net-(D1-A)	○	○	○
0%	J4_3	THRL	○	○	○
0%	U3_3	Net-(DZ1-A)	○	○	○
0%	L2_1	Net-(U2-SW)	○	○	○
0%	Y2_1	Net-(U9-XC2)	○	○	○
0%	J4_2		○	○	○
0%	D4_2	Net-(D3-DOUT)	○	○	○
0%	Y2_4	Net-(U9-XC1)	○	○	○
0%	J5_2	TX1	○	○	○
0%	J5_3	RX1	○	○	○
0%	J5_4		○	○	○
0%	J5_5		○	○	○
0%	Y1_4	Net-(C28-Pad2)	○	○	○
0%	D2_2	Net-(D2-DIN)	○	○	○
0%	J13_9	SD_Detect	○	○	○
0%	D3_4	Net-(D3-DOUT)	○	○	○
0%	J1_2		○	○	○

14.8.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Component Properties

Schematic library symbol quality analysis.

15.1 Library Symbol Grades

Grading schematic library symbol quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Symbol Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U1	C	6	2	2	1	0	0	0	0	1	AP63205WU
U2	C	6	2	2	1	0	0	0	0	1	AP63203WU
U4	B	6	2	2	1	0	0	0	0	1	LM74700
U9	B	20	9	4	2	0	0	0	0	5	nRF24L01P
U6	B	12	4	4	0	4	0	0	0	0	LIS2MDLTR
U7	B	100	11	3	0	82	0	0	0	4	STM32F765VITx
U10	A	5	2	2	1	0	0	0	0	0	SN74LV1T34DBV
U3	A	3	2	0	0	1	0	0	0	0	US1881
U5	A	10	4	1	0	5	0	0	0	0	LPS22HBTR
U8	A	14	4	2	2	6	0	0	0	0	LSM6DSO

15.1.1 Library Quality Summary

Total ICs evaluated	10
Grade A (excellent)	4 (40.0%)
Grade B (good)	4 (40.0%)
Grade C (fair)	2 (20.0%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	0 (0.0%)
OVERALL LIBRARY QUALITY	A (3.56/4.00)

15.2 Component Library Validation

The shared part-number check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Checking for generic/incomplete library symbols using statistical patterns.

Library Symbol Issues (4 symbols)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
AP63203WU	AP63203WU	-	U2	6	P:1 Pwr:2 I:2 O:1	Power-named pins not typed as Power - library pin types incomplete [SW=Output, BST=Passive]
AP63205WU	AP63205WU	-	U1	6	P:1 Pwr:2 I:2 O:1	Power-named pins not typed as Power - library pin types incomplete [SW=Output, BST=Passive]
LIS2MDLTR	LIS2MDLTR	-	U6	12	Pwr:4 Bi:4 ?:4	33% of pins are Unknown type
STM32F765VITx	STM32F765VITx	-	U7	100	P:4 Pwr:11 Bi:82 I:3	Pin 10 (VSS) at same location as pin 26 (VSS); Pin 10 (VSS) at same location as pin 49 (VSS); Pin 10 (VSS) at same location as pin 74 (VSS); Pin 10 (VSS) at same location as pin 99 (VSS); Pin 26 (VSS) at same location as pin 49 (VSS); Pin 26 (VSS) at same location as pin 74 (VSS); Pin 26 (VSS) at same location as pin 99 (VSS); Pin 49 (VSS) at same location as pin 74 (VSS); Pin 49 (VSS) at same location as pin 99 (VSS); Pin 74 (VSS) at same location as pin 99 (VSS); Power-named pins not typed as Power - library pin types incomplete [VREF+=Input, VSS=Passive, VSS=Passive, VSS=Passive, VSS=Passive]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library symbol

Power-named pins not typed as Power: Library pin types incomplete

15.3 Symbol vs Datasheet Pin Table

Each symbol's pin numbers are compared with the pin table of its datasheet. A datasheet pin the symbol lacks is a warning only when the datasheet calls it electrical; a pin the datasheet marks NC or mechanical, or a symbol pin the table does not list, is shown for information. An exposed pad is never counted as a mismatch, whether the symbol names it or numbers it one past the last pin. Where it was numbered, the row suggests giving it a name, because a bare number does not tell a reader what the pin is.

15 parts compared with their datasheet: 15 agree, 0 differ.

Every symbol compared matches its datasheet's pin table.

15.4 Shielded Connector Symbol Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.5 I/O Bank Power

U7 STM32F765VITx: 3 I/O banks checked against the vendor package file; 94 of 94 symbol pin names agree with it

U7 bank VDD (): supply balls of one bank on different nets - Net-(C16-Pad1): 100; Net-(C15-Pad1): 11; Net-(C13-Pad1): 27; Net-(C12-Pad1): 50; Net-(C18-Pad1): 75

15.6 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
D2	SK6812	4	Footprint	LED_SMD:LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm
D3	SK6812	4	Footprint	LED_SMD:LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm
D4	SK6812	4	Footprint	LED_SMD:LED_SK6812_PLCC4_5.0x5.0mm_P3.2mm
J1	-	3	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
J2	-	6	Footprint	Connector_JST:JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical
J3	-	4	Footprint	Connector_JST:JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical
J4	-	3	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
J5	-	6	Footprint	Connector_JST:JST_GH_BM06B-GHS-TBT_1x06-1MP_P1.25mm_Vertical
J6	-	6	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x06_P2.54mm_Vertical
J10	-	4	Footprint	Connector_JST:JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical
J11	-	4	Footprint	Connector_JST:JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical
J12	-	4	Footprint	Connector_JST:JST_GH_BM04B-GHS-TBT_1x04-1MP_P1.25mm_Vertical
J13	-	10	Footprint	Connector_Card:microSD_HC_Hirose_DM3AT-SF-PEJM5
J15	-	3	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
Q1	-	5	Footprint	Package_SO:PowerPAK_SO-8L_Single
Q2	AON6262E	5	Footprint	Package_TO_SOT_SMD:TDSON-8-1
U1	AP63205WU	6	Footprint	Package_TO_SOT_SMD:TSOT-23-6
U2	AP63203WU	6	Footprint	Package_TO_SOT_SMD:TSOT-23-6
U3	US1881	3	Footprint	Package_TO_SOT_THT:TO-92
U4	LM74700	6	Footprint	Package_TO_SOT_SMD:SOT-23-6
U5	LPS22HBTR	10	Footprint	Package_LGA:ST_HLGA-10_2x2mm_P0.5mm_LayoutBorder3x2y
U6	LIS2MDLTR	12	Footprint	Package_LGA:LGA-12_2x2mm_P0.5mm
U7	STM32F765VITx	100	Footprint	Package_QFP:LQFP-100_14x14mm_P0.5mm
U8	LSM6DSO	14	Footprint	Package_LGA:LGA-14_3x2.5mm_P0.5mm_LayoutBorder3x4y
U9	nRF24L01P	20	Footprint	Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
U10	SN74LV1T34DBV	5	Footprint	Package_TO_SOT_SMD:SOT-23-5
Y1	-	4	Footprint	Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm
Y2	-	4	Footprint	Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm

15.7 IC Pin Electrical Properties

Unique IC symbols	10
Total IC instances	10

IC Library Symbols
Industry Name	Library Name	RefDes	Notes
AP63203WU	AP63203WU	U2
AP63205WU	AP63205WU	U1
LIS2MDLTR	LIS2MDLTR	U6
LM74700	LM74700	U4
LPS22HBTR	LPS22HBTR	U5
LSM6DSO	LSM6DSO	U8
SN74LV1T34DBV	SN74LV1T34DBV	U10
STM32F765VITx	STM32F765VITx	U7
US1881	US1881	U3
nRF24L01P	nRF24L01P	U9

15.7.1 AP63203WU (AP63203WU)

Pin	Pin Name	Electrical
1	FB	Input
2	EN	Input
3	IN	Power In
4	GND	Power In
5	SW	Output
6	BST	Passive

15.7.2 AP63205WU (AP63205WU)

Pin	Pin Name	Electrical
1	FB	Input
2	EN	Input
3	IN	Power In
4	GND	Power In
5	SW	Output
6	BST	Passive

15.7.3 LIS2MDLTR (LIS2MDLTR)

Pin	Pin Name	Electrical
1	SCL/SPC	Bidirectional
2	NC	Unknown
3	CS	Bidirectional
4	SDA/SDI/SDO	Bidirectional
5	C1	Unknown
6	GND	Power In
7	INT/DRDY/SDO	Bidirectional
8	GND	Power In
9	VDD	Power In
10	VDD_IO	Power In
11	NC	Unknown
12	NC	Unknown

15.7.4 LM74700 (LM74700)

Pin	Pin Name	Electrical
1	VCAP	Passive
2	GND	Power In
3	EN	Input
4	CATHODE	Input
5	GATE	Output
6	ANODE	Power In

15.7.5 LPS22HBTR (LPS22HBTR)

Pin	Pin Name	Electrical
1	VDD_IO	Power In
2	SCL/SPC	Bidirectional
3	RES	Unknown
4	SDA/SDI/SDO	Bidirectional
5	SDO/SA0	Bidirectional
6	CS	Bidirectional
7	INT_DRDY	Bidirectional
8	GND	Power In
9	GND	Power In
10	VDD	Power In

15.7.6 LSM6DSO (LSM6DSO)

Pin	Pin Name	Electrical
1	SDO/SA0	Bidirectional
2	SDx	Bidirectional
3	SCx	Bidirectional
4	INT1	Output
5	VDDIO	Power In
6	GND	Power Out
7	GND	Power Out
8	VDD	Power In
9	INT2	Output
10	OCS_Aux	Bidirectional
11	SDO_Aux	Bidirectional
12	CS	Input
13	SCL	Input
14	SDA	Bidirectional

15.7.7 SN74LV1T34DBV (SN74LV1T34DBV)

Pin	Pin Name	Electrical
1	NC	Unknown
2	A	Input
3	GND	Power In
4	Y	Output
5	VCC	Power In

15.7.8 STM32F765VITx (STM32F765VITx)

Pin	Pin Name	Electrical
1	PE2	Bidirectional
2	PE3	Bidirectional
3	PE4	Bidirectional
4	PE5	Bidirectional
5	PE6	Bidirectional
6	VBAT	Power In
7	PC13	Bidirectional
8	PC14	Bidirectional
9	PC15	Bidirectional
10	VSS	Power In
11	VDD	Power In
12	PH0	Bidirectional
13	PH1	Bidirectional
14	NRST	Input
15	PC0	Bidirectional
16	PC1	Bidirectional
17	PC2	Bidirectional
18	PC3	Bidirectional
19	VSSA	Power In
20	VREF+	Input
21	VDDA	Power In
22	PA0	Bidirectional
23	PA1	Bidirectional
24	PA2	Bidirectional
25	PA3	Bidirectional
26	VSS	Passive
27	VDD	Power In
28	PA4	Bidirectional
29	PA5	Bidirectional
30	PA6	Bidirectional
31	PA7	Bidirectional
32	PC4	Bidirectional
33	PC5	Bidirectional
34	PB0	Bidirectional
35	PB1	Bidirectional
36	PB2	Bidirectional
37	PE7	Bidirectional
38	PE8	Bidirectional
39	PE9	Bidirectional
40	PE10	Bidirectional
41	PE11	Bidirectional
42	PE12	Bidirectional
43	PE13	Bidirectional
44	PE14	Bidirectional
45	PE15	Bidirectional
46	PB10	Bidirectional
47	PB11	Bidirectional
48	VCAP_1	Power Out
49	VSS	Passive
50	VDD	Power In
51	PB12	Bidirectional
52	PB13	Bidirectional
53	PB14	Bidirectional
54	PB15	Bidirectional
55	PD8	Bidirectional
56	PD9	Bidirectional
57	PD10	Bidirectional
58	PD11	Bidirectional
59	PD12	Bidirectional
60	PD13	Bidirectional
61	PD14	Bidirectional
62	PD15	Bidirectional
63	PC6	Bidirectional
64	PC7	Bidirectional
65	PC8	Bidirectional
66	PC9	Bidirectional
67	PA8	Bidirectional
68	PA9	Bidirectional
69	PA10	Bidirectional
70	PA11	Bidirectional
71	PA12	Bidirectional
72	PA13	Bidirectional
73	VCAP_2	Power Out
74	VSS	Passive
75	VDD	Power In
76	PA14	Bidirectional
77	PA15	Bidirectional
78	PC10	Bidirectional
79	PC11	Bidirectional
80	PC12	Bidirectional
81	PD0	Bidirectional
82	PD1	Bidirectional
83	PD2	Bidirectional
84	PD3	Bidirectional
85	PD4	Bidirectional
86	PD5	Bidirectional
87	PD6	Bidirectional
88	PD7	Bidirectional
89	PB3	Bidirectional
90	PB4	Bidirectional
91	PB5	Bidirectional
92	PB6	Bidirectional
93	PB7	Bidirectional
94	BOOT0	Input
95	PB8	Bidirectional
96	PB9	Bidirectional
97	PE0	Bidirectional
98	PE1	Bidirectional
99	VSS	Passive
100	VDD	Power In

15.7.9 US1881 (US1881)

Pin	Pin Name	Electrical
1	VDD	Power In
2	GND	Power In
3	OUTPUT	Bidirectional

15.7.10 nRF24L01P (nRF24L01P)

Pin	Pin Name	Electrical
1	CE	Input
2	CSN	Input
3	SCK	Input
4	MOSI	Input
5	MISO	Output
6	IRQ	Output
7	VDD	Power In
8	VSS	Power In
9	XC2	Passive
10	XC1	Passive
11	VDD_PA	Power Out
12	ANT1	Passive
13	ANT2	Passive
14	VSS	Power In
15	VDD	Power In
16	IREF	Passive
17	VSS	Power In
18	VDD	Power In
19	DVDD	Power Out
20	VSS	Power In