Generated by Tomachie v3.84 2026-07-13 04:55:45
Copyright © 2026 Tomachie LLC. All rights reserved.

KINK-box Design Analysis

1 Design Summary

75
out of 100
Design TypeHierarchical (2 sheets)
Total Components106
Total Pins401
Total Nets88
Total Test Points0
Not Fitted (DNP)1
Improve your score:
Points deducted for open High/Medium AI findings:
AI findings to review:
AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.
Based on user-selected TP insertion settings, 8 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.
The inserted test point count is unusually high because Optical (AOI) and X-ray (AXI) inspection contributes no coverage — none of the footprint names are recognized as IPC-7351B or IPC-7251 compliant. Repair the library footprint names to follow IPC naming and resubmit; the inserted test point count will drop to typical levels.

1.1 Design Overview

AI-Assisted — The schematic describes a compact USB-C-powered stereo audio playback and amplification board built around an ESP32-S3-WROOM-1 wireless module, a Texas Instruments PCM5100A stereo audio DAC, and a Texas Instruments TPA3118D2 class-D power amplifier. Audio originates in the ESP32-S3, streams over an I2S link (bit clock, word clock and data) to the PCM5100A, which produces a 2.1 VRMS line-level stereo output, and is then presented both to a switched 3-pole TRS headphone/line jack (J1) and to the TPA3118D2 for loudspeaker drive. The design is contained on two hierarchical sheets (KINK-box and logic).

Processing and Wireless Subsystem
The ESP32-S3-WROOM-1 (U202) provides the 2.4 GHz Wi-Fi 802.11 b/g/n and Bluetooth 5 LE connectivity and hosts the application. Its native USB D+/D- lines are brought out through series resistors to the USB-C receptacle, and general-purpose I/O drives the front-panel controls: four RGB-illuminated momentary pushbuttons (SW1–SW4), a discrete tactile switch (SW5), and a multidirectional navigation switch (SW6). BOOT/BOOTSEL strapping and per-button debouncing capacitors are provided at the module.

Audio Signal Chain
The PCM5100A DAC (U2) operates from 3.3 V on its analog, charge-pump and digital supplies and uses its internal charge pump (flying capacitor on CAPP/CAPM) to generate its negative rail; recommended 470 Ω series / shunt output filtering feeds the TRS jack. The TPA3118D2 (U3) is a 4.5–26 V class-D amplifier capable of 30 W into 8 Ω; it is configured for stereo drive with LC reconstruction filtering through the Würth WE-CMDC common-mode chokes (FL1, FL2) to the two side-entry speaker terminal blocks (J2, J3). Gain/mode, PLIMIT, MUTE, SDZ and modulation-mode selection are set by the surrounding resistor network.

USB Type-C and Power Delivery
The USB-C receptacle (J201) provides USB 2.0 data and a Power Delivery sink interface. A WCH CH221K USB-PD/Type-C sink controller (U1) negotiates bus voltage; its CFG pin is programmed through a 47K resistor to VDD, which per the CH221K datasheet selects a 12 V PD request. Negotiated VBUS becomes the board's +12V rail.

Power Tree
Two supply rails are distributed. The +12V rail is sourced from the negotiated USB-C VBUS and directly powers the TPA3118D2 output and analog stages. The +3V3 rail is generated on the KINK-box sheet by the ROHM BD33FC0FP-E2 fixed 3.3 V LDO (U4), whose input is the +12V rail; +3V3 supplies the ESP32-S3, the PCM5100A and the control-side pull-ups. A CUI P7805-2000R-S switching regulator (U5) is present as a do-not-install alternate on the same input/output nets and is not fitted in the default build; expressing this pop/de-pop option through the eCAD tool's variant feature would keep the test netlist unambiguous.

Temperature Ratings
The narrowest operating window among the active devices is set by the BD33FC0FP-E2 (-25 °C to +85 °C) and the PCM5100A (-25 °C to +85 °C operating), with the CH221K rated -40 °C to +105 °C and the WE-CMDC choke rated to +125 °C. The assembly's usable ambient range is therefore bounded to approximately -25 °C to +85 °C.

Boundary Scan
Boundary-scan evaluation covered the programmable devices on the board — the ESP32-S3-WROOM-1 module (U202) is the only device with a test access port. No matched boundary-scan model was applied to any device on this board; adding the correct model for U202 would increase interconnect test coverage. Refer to the Design-for-Test section for full detail. No device on this board carries a TEN pin, so JEDEC Connectivity Test Mode does not apply here.

1.2 Processed Sheets

#Sheet Name
1KINK-box.kicad_sch
2logic.kicad_sch

1.3 Structured DNP (Not Fitted)

Parts marked do-not-populate at the part level, outside of assembly variants. They remain present in the netlist but are not assembled.
StatusRefDesPart TypeValueFootprint
DNPU5P7805-2000R-SP7805-2000R-SConverter_DCDC:Converter_DCDC_RECOM_R-78HB-0.5L_THT

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint NamingStatus
12 SMT footprints do not follow IPC-7351B naming
3 footprints (connectors, specialty) — compliance unknown
3 footprints could not be classified for inspection

1.5 Incorrect BOM Settings

The following components have part types associated with non-BOM items (fiducials, mounting holes, test pads) but are not marked as excluded from the BOM in the schematic library. The default is parts with reference designators are BOM parts to populate on the PCB, so the "Include in BOM" setting needs to be false either in the component library or overriding within the schematic instance. This affects downstream processes that rely on the BOM or check for populated parts.
RefDesPart TypeIssue
H103MountingHoleMissing BOM exclusion flag
H104MountingHoleMissing BOM exclusion flag
H105MountingHoleMissing BOM exclusion flag
H106MountingHoleMissing BOM exclusion flag

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Value Property Check
TypeCheckCountComponentsStatus
CapacitorsValues in VALUE or Capacitance41C10, C206, C12, C18, C26, C23, C13, C20 (+33 more)✓
ResistorsValues in VALUE or Resistance42R16, R13, R30, R32, R3, R15, R18, R27 (+34 more)✓
Ferrite BeadsValues in VALUE or Impedance2FL1, FL2✓

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

2 unconnected pin(s) found:
2 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.
Refdes_PinPin FunctionPin PropertyDevice TypeNet NameNotes
U202_24GPIO47/SPICLK_P/SUBSPICLK_P_DIFFBidirectionalESP32-S3-WROOM-1UART_TX_{main}
U202_25GPIO48/SPICLK_N/SUBSPICLK_N_DIFFBidirectionalESP32-S3-WROOM-1UART_RX_{main}

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden power pins stacked behind visible pins in the symbol.

Implied Net Connections
ComponentTypePinNetStatus
U3TPA3118D2DAPR31 (PVCC)+12VFail — hidden pin not visible on schematic
U3TPA3118D2DAPR32 (PVCC)+12VFail — hidden pin not visible on schematic
U3TPA3118D2DAPR22 (GND)GNDFail — hidden pin not visible on schematic
U3TPA3118D2DAPR19 (PVCC)+12VFail — hidden pin not visible on schematic
U3TPA3118D2DAPR25 (GND)GNDFail — hidden pin not visible on schematic
U3TPA3118D2DAPR28 (GND)GNDFail — hidden pin not visible on schematic

3.3 Open-Collector Pull-up Audit

Examined 1 candidate pin(s) on 1 net(s). 1 passing.
These open-collector / open-drain outputs have a resistor pull-up to a power rail. The pull-up resistor and rail are shown for reference.
NetOC Pin(s)Pull-upRailStatus
Logic/PGU1_3 (PG)R3+3V3✓

3.4 Polarized Capacitor Orientation

Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
CapacitorConnectionsPolaritySeverity
C23
865060663013		Pin 1 (+): +12V
Pin 2: GND

3.5 Summary

Total NO_ERC markers in design15
Pins needing attention (warnings)2
Pins for information only0

4 Power Overview

Power rails3
Power management sources identified1
Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.
Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
RailVoltageSourceConsumers
+12V12.00VJ201
External		U1 (CH221K),
U3 (TPA3118D2DAPR),
U4 (BD33FC0FP-E2),
U5 (P7805-2000R-S)
+3V33.30VU4
BD33FC0FP-E2		U2 (PCM5100A),
U202 (https://mou.sr/3vuXydS),
U5 (P7805-2000R-S)
GND-J1
External		-

4.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.2.1 Power Tree Overview

AI-Assisted — The USB-C receptacle J201 is the only board power input. The CH221K PD sink (U1) programs a 12 V request (CFG resistor R1 = 47 kΩ, CH221K datasheet page 3 gives 47 kΩ = 12 V), so VBUS becomes the on-board +12V rail. +12V feeds the TPA3118D2 class-D amplifier (U3) and the amplifier decoupling/bulk network directly, and it feeds the BD33FC0 linear regulator (U4), which produces the +3V3 rail for the PCM5100A DAC (U2) and the ESP32-S3 module (U202). The chain is +12V → U4 → +3V3. A do-not-install alternate regulator U5 (P7805) is wired across the same U4 input and output nodes; U4 is the fitted source. Ground is a single reference tied to the connector shell/chassis. Sequencing is implicit: VBUS attaches at 5 V, U1 negotiates 12 V, and because U4 is the no-enable BDxxFC0FP-E2 package (VCC/GND/VO only), +3V3 tracks +12V. The ESP32-S3 EN pin is held to +3V3, and the amplifier SDZ is held high (enabled) with MUTE pulled to +3V3 (muted) until the MCU releases it.

4.2.2 USB-C Power Delivery Input (U1 CH221K)

AI-Assisted — U1 negotiates 12 V correctly through the 47 kΩ CFG resistor. Two supply-connectivity problems remain. First, the VDD pin (pin 1) is a member of the +12V rail. The CH221K datasheet (page 5) rates VDD absolute maximum at 5.8 V, and the part carries an internal shunt ("parallel") regulator that clamps VDD to 3.3 V with only 30 mA sink capability (page 6). VDD is therefore meant to be fed through a series current-limiting resistor from VBUS, not tied directly to it; a direct 12 V connection exceeds the 5.8 V absolute maximum and over-drives the internal shunt. Second, the CFG programming resistor R1 returns to the +12V rail rather than to the VDD pin the datasheet specifies for the CFG-to-VDD ladder (page 3). The CC1/CC2 nets connect only J201 and U1 with no 5.1 kΩ Rd resistors, which the CH221K reference schematic (page 4) lists as required external components for CC. The ~PG open-drain output is pulled to +3V3 by R3 (47 kΩ, confirmed), an acceptable pull-up, but the net reaches no monitor input, so power-good is not observable on the board.

4.2.3 +3.3 V Regulator (U4 BD33FC0) and Alternate (U5)

AI-Assisted — U4 input is 12 V, inside the 4.3–26.5 V range (ROHM BD33FC0 datasheet page 8), and its fixed output is 3.267–3.333 V, suiting every 3.3 V load. Input decoupling requirement CIN = 2.2 µF (page 26) and output COUT = 1 µF (page 26) are both met by the rail ceramics (30.2 µF X7R on +3V3; 502.2 µF on +12V). The concern is thermal: the LDO drops 12 V − 3.3 V = 8.7 V. The ESP32-S3-WROOM-1 draws Wi-Fi transmit peaks near 500 mA; at a modest 0.35 A continuous the dissipation is 8.7 V × 0.35 A ≈ 3.0 W. In TO-252, θJA is 20.8 °C/W on a 2s2p board and 115.3 °C/W on a 1-layer board (page 9). On 2s2p at 85 °C ambient Tj ≈ 148 °C, right at the 150 °C limit; on thin copper it is untenable. This rail needs generous copper or a switching pre-regulator. The do-not-install alternate U5 is a P7805 5 V module (CUI datasheet page 1) wired with its output on the +3V3 net; if ever populated it would drive the 3.3 V rail to 5 V and damage all 3.3 V loads. U4 is the fitted default. Capture this option in the eCAD variant feature and, if an alternate is truly intended, use a 3.3 V module.

4.2.4 Class-D Amplifier Power (U3 TPA3118D2)

AI-Assisted — The 12 V supply is within the TPA3118D2 4.5–26 V range. PVCC bulk/decoupling is well provided (C23 470 µF/50 V polar plus 10 µF and 100 nF ceramics, 502 µF total), meeting the two-100 µF bulk recommendation (datasheet page 27). MODSEL and AM0–AM2 tied to GND select BD modulation with AM-frequency avoidance — a valid filterless configuration — and SDZ tied to FAULTZ through the 22 kΩ pull-up R21 to +12V is the datasheet auto-recovery scheme. The critical defect is GVDD (pin 7), the internally generated gate-drive supply output, tied to GND. The datasheet (page 16) requires a 1 µF X7R decoupling capacitor from GVDD to GND, not a ground connection; grounding this output shorts the internal gate-supply regulator and the output bridge cannot switch. The four bootstrap capacitors C15–C18 are 100 nF; the datasheet (page 16) specifies 220 nF X5R rated ≥16 V — they are undersized. The output-filter shunt capacitors C19–C22 are 680 nF rated 10 V, placed at the speaker nodes that swing to PVCC (12 V); the 10 V rating is insufficient and should be ≥25 V. PLIMIT is tied to +12V rather than to GVDD; this effectively removes the power limit (page 15 recommends tying to GVDD for no-limit) and works but is non-standard.

4.3 Observations

AI-Assisted — The PCM5100A supply pins (AVDD, CPVDD, DVDD) all sit on +3V3, within the 3.2–3.46 V, 3.1–3.46 V and 3.1–3.46 V windows respectively (datasheet page 6), with 10 µF + 100 nF decoupling and the charge-pump network (C2 flying 2.2 µF, C3 VNEG 2.2 µF, C5/C6 LDOO) per page 26. The DAC line outputs carry the 470 Ω series resistors (R4/R5) but omit the datasheet-recommended 2.2 nF shunt to AGND (page 8), a minor filter shortfall. The +12V electrolytic C23 is correctly oriented (positive to +12V) and 50 V-rated, a comfortable derating on 12 V. The 10 µF ceramics C201/C203/C204 (H/I groups) carry no voltage rating in the schematic. There is no board-level TVS or fuse on VBUS; the USB-C source is current-limited, but transient protection on the 12 V input and the D+/D- lines (only series 22R R230/R231 present) is worth considering.

4.4 Findings

AI-Assisted —
DeviceRailObservationSeverity
U1 (CH221K)+12VVDD (pin 1) tied directly to 12 V VBUS; VDD abs max is 5.8 V (datasheet p.5) and it uses a 3.3 V internal shunt (30 mA sink, p.6) — a series current-limit resistor from VBUS is required, direct connection over-voltages the pin.High
U3 (TPA3118D2)+12VGVDD (pin 7) tied to GND — internal gate-drive regulator output shorted; datasheet (p.16) requires a 1 µF X7R decoupling cap to GND, not a ground connection. Output bridge cannot switch.High
U1 (CH221K)CC1/CC2CC nets carry only J201 and U1 with no 5.1 kΩ Rd resistors the reference schematic lists as required (datasheet p.4).Medium
U1 (CH221K)+12VCFG resistor R1 (47 kΩ = 12 V request, datasheet p.3) returns to the +12V rail instead of the VDD pin the datasheet specifies for the CFG ladder.Medium
U4 (BD33FC0)+3V38.7 V linear drop feeds ESP32-S3 (Wi-Fi peaks ~500 mA); ~3 W at 0.35 A gives Tj ≈ 148 °C on 2s2p (θJA 20.8 °C/W, p.9) at 85 °C ambient — marginal, untenable on thin copper.Medium
U5 (P7805, DNI)+3V3Do-not-install alternate is a 5 V module (CUI datasheet p.1) wired onto the +3V3 net; if populated it drives the rail to 5 V and damages 3.3 V loads. U4 is the fitted source; express the option via the eCAD variant feature and use a 3.3 V part if an alternate is intended.Medium
U3 (TPA3118D2)OutputsBootstrap caps C15–C18 are 100 nF; datasheet (p.16) specifies 220 nF X5R ≥16 V — undersized.Medium
U3 (TPA3118D2)OutputsOutput-filter caps C19–C22 680 nF rated 10 V on a 12 V-supply class-D output that swings to PVCC (12 V) — under-rated; use ≥25 V.Medium
U2 (PCM5100A)OutputsOUTL/OUTR have 470 Ω series (R4/R5) but the datasheet-recommended 2.2 nF shunt to AGND (p.8) is absent.Low
U1 (CH221K)+3V3~PG open-drain pulled to +3V3 via R3 47 kΩ (pull-up confirmed) but not routed to any monitor input — power-good not observable.Review
U3 (TPA3118D2)+12VPLIMIT (pin 6) tied to +12V rather than GVDD; effectively no power limit (datasheet p.15 recommends GVDD for no-limit) — functional but non-standard.Review
C201/C203/C204+12V/+3V310 µF ceramics (H/I groups) have no voltage rating stated in the schematic.Review
J201 (USB-C)+12VNo board-level TVS/fuse on VBUS (source is current-limited); D+/D- carry only series 22R R230/R231, no ESD clamps.Review
U4 (BD33FC0)+12V/+3V3Vin 12 V within 4.3–26.5 V; fixed Vout 3.267–3.333 V suits all 3.3 V loads (datasheet p.8).✓
U4 (BD33FC0)+12VInput decoupling CIN 2.2 µF requirement (datasheet p.26) met by rail ceramics.✓
U4 (BD33FC0)+3V3Output COUT ≥1 µF (datasheet p.26) met by 30.2 µF X7R ceramic on the rail.✓
U3 (TPA3118D2)+12VPVCC bulk/decoupling (470 µF + 10 µF×3 + 100 nF, 502 µF) meets two-100 µF bulk recommendation (datasheet p.27).✓
U3 (TPA3118D2)+12VSDZ tied to FAULTZ with R21 22 kΩ pull-up to +12V — datasheet auto-recovery configuration, valid.✓
U3 (TPA3118D2)GNDMODSEL and AM0–AM2 tied to GND — BD-modulation with AM avoidance, valid filterless configuration.✓
U2 (PCM5100A)+3V3AVDD/CPVDD/DVDD on 3.3 V within datasheet ranges (p.6); 10 µF + 100 nF decoupling per pin present.✓
U2 (PCM5100A)+3V3Charge-pump flying cap C2 2.2 µF, VNEG C3 2.2 µF, LDOO C5/C6 per datasheet p.26.✓
C23 (865060663013)+12V470 µF/50 V electrolytic, positive terminal to +12V — correctly oriented, good derating on 12 V.✓

4.5 Citations

AI-Assisted —
References
BD33FC0 (ROHM) — datasheet
fscdn.rohm.com/en/products/databook/datasheet/ic/power/li...
CH221K (WCH (wch.cn)) — datasheet, cited pages 1,2,3
components101.com/sites/default/files/component_datasheet...
P7805-2000R-S (CUI Inc) — datasheet
nl.mouser.com/datasheet/2/670/p78_2000r_s-3070500.pdf
PCM5100A (Texas Instruments) — datasheet
www.ti.com/lit/ds/symlink/pcm5100a.pdf
TPA3118D2 (Texas Instruments) — datasheet
www.ti.com/lit/ds/symlink/tpa3118d2.pdf

5 Connector Pinouts

Total connectors4

5.1 J1 PJ-328A0-B

J1 - PJ-328A0-B
PinPin NameNetNotes
RNet-(J1-PadR)
RNLogic/AUD_R
SGND
TNet-(J1-PadT)
TNLogic/AUD_L

5.2 J2 QT02CSF83H0000G

J2 - QT02CSF83H0000G
PinPin NameNetNotes
11Net-(C22-Pad1)
22Net-(C21-Pad1)

5.3 J3 QT02CSF83H0000G

J3 - QT02CSF83H0000G
PinPin NameNetNotes
11Net-(C19-Pad1)
22Net-(C20-Pad1)

5.4 J201 https://mou.sr/463mreb

J201 - https://mou.sr/463mreb (https://mou.sr/463mreb) [640-USB4500030A]
PinPin NameNetNotes
A1GNDGND
A4VBUS+12V
A5CC1Net-(J201-CC1)
A6DP1ESPUSB_D+
A7DN1ESPUSB_D-
A8SBU1NC
A9VBUS+12V
A12GNDGND
B1GNDGND
B4VBUS+12V
B5CC2Net-(J201-CC2)
B6DP2ESPUSB_D+
B7DN2ESPUSB_D-
B8SBU2NC
B9VBUS+12V
B12GNDGND
S1SHELLGND
S1SHELLGND
S1SHELLGND
S1SHELLGND

6 Indicator Documentation

No indicator devices (LED*, LD*, D* LEDs) found in design.

7 Switch Documentation

6 switch(es) found in design.

7.1 Switch Configurations

A B
SW1 Contact Pairs (465M111172501)
ContactPin ANet APin BNet BWhen OpenWhen ClosedNotes
1LC+3V3L2Net-(SW1-GREEN)SIGNALHIGH
21GND2Logic/BTN1SIGNALLOW
SW1 All Pins
Pin #Pin NameNetPaired WithType
LCLC+3V3L2CONTACT
11GND2CONTACT
L2GREENNet-(SW1-GREEN)LCCONTACT
22Logic/BTN11CONTACT
L1REDNet-(SW1-RED)--
L3BLUENet-(SW1-BLUE)--
SW2 Contact Pairs (465M111172501)
ContactPin ANet APin BNet BWhen OpenWhen ClosedNotes
1LC+3V3L2Net-(SW2-GREEN)SIGNALHIGH
21GND2Logic/BTN2SIGNALLOW
SW2 All Pins
Pin #Pin NameNetPaired WithType
LCLC+3V3L2CONTACT
11GND2CONTACT
L2GREENNet-(SW2-GREEN)LCCONTACT
22Logic/BTN21CONTACT
L1REDNet-(SW2-RED)--
L3BLUENet-(SW2-BLUE)--
SW3 Contact Pairs (465M111172501)
ContactPin ANet APin BNet BWhen OpenWhen ClosedNotes
1LC+3V3L2Net-(SW3-GREEN)SIGNALHIGH
21GND2Logic/BTN3SIGNALLOW
SW3 All Pins
Pin #Pin NameNetPaired WithType
LCLC+3V3L2CONTACT
11GND2CONTACT
L2GREENNet-(SW3-GREEN)LCCONTACT
22Logic/BTN31CONTACT
L1REDNet-(SW3-RED)--
L3BLUENet-(SW3-BLUE)--
SW4 Contact Pairs (465M111172501)
ContactPin ANet APin BNet BWhen OpenWhen ClosedNotes
1LC+3V3L2Net-(SW4-GREEN)SIGNALHIGH
21GND2Logic/BTN4SIGNALLOW
SW4 All Pins
Pin #Pin NameNetPaired WithType
LCLC+3V3L2CONTACT
11GND2CONTACT
L2GREENNet-(SW4-GREEN)LCCONTACT
22Logic/BTN41CONTACT
L1REDNet-(SW4-RED)--
L3BLUENet-(SW4-BLUE)--
SW5 Contact Pairs (KMR223GLFG)
ContactPin ANet APin BNet BWhen OpenWhen ClosedNotes
12GND1Net-(R204-Pad2)SIGNALLOW
SW5 All Pins
Pin #Pin NameNetPaired WithType
22GND1CONTACT
11Net-(R204-Pad2)2CONTACT
SW6 Contact Pairs (SW_NAV_PLMG5)
ContactPin ANet APin BNet BWhen OpenWhen ClosedNotes
11Logic/DOWN7GNDSIGNALLOW
22Logic/DOWN6GNDSIGNALLOW
SW6 All Pins
Pin #Pin NameNetPaired WithType
1Logic/DOWN7CONTACT
2Logic/DOWN6CONTACT
7GND1CONTACT
6GND2CONTACT
5Logic/MENU--
4Logic/UP--
3Logic/UP--

8 Low-Speed Serial Interfaces (LSSI)

Detected: 1 UART

8.1 UART

UART [UART]: U202
Topology: U202 » Targets ()
SignalNet NameConnectorTest Point
TXUART_TX_{main}(none)(none)
RXUART_RX_{main}(none)(none)
ControllerIndustry TypeDescription
U202 356-EP32S3WROOM1N8R82.4 GHz WiFi (802.11 b/g/n) and Bluetooth ® 5 (LE) module Built around ESP32S3 series of SoCs,
Xtensa ® dualcore 32bit LX7 microprocessor Flash up to 16 MB,
PSRAM up to 8 MB 36 GPIOs,
rich set of peripherals Onboard PCB antenna

8.2 LSSI DFT Analysis

2 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.
During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.
Missing Test Points
SignalNet NameConnectorInterface
RXUART_RX_{main}(none)UART
TXUART_TX_{main}(none)UART

9 High-Speed Serial Interfaces (HSSI)

No controlled impedance nets detected in design.

10 Memory Interface Analysis

No memory devices with detectable bus interfaces found.

11 Functional Analysis

4 device(s) to review across 3 category(ies)

Device Inventory
RefDesCategoryPart NumberDescriptionInterfacesHSSI
U2ADC_DACPCM5100A2.1 VRMS, 100dB Audio Stereo DAC with PLL and 32-bit, 384kHz PCM Interface, TSSOP-20--
U1DEVICECH221KUSB-PD & Type-C & Fast Charge Power Sink Controller, SOT-23-6--
U3DEVICETPA3118D2DAPR30-W stereo, 60-W mono, 4.5- to 26-V supply, analog input Class-D audio amplifier--
U202WIRELESShttps://mou.sr/3vuXydS2.4 GHz WiFi (802.11 b/g/n) and Bluetooth ® 5 (LE) module Built around ESP32S3 series of SoCs, Xtensa ® dualcore 32bit LX7 microprocessor Flash up to 16 MB, PSRAM up to 8 MB 36 GPIOs, rich set of peripherals Onboard PCB antennaUART [UART]-

11.1 Functional Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

11.1.1 USB Power-Delivery Sink Controller U1 (CH221K)

AI-Assisted — U1 VDD (pin 1) is tied directly to the +12V rail (VBUS). The CH221K VDD absolute maximum is 5.8 V (WCH datasheet, page 5), and its internal parallel shunt regulator holds VDD at 3.3 V typ while sinking up to 30 mA, meaning VDD is intended to be fed from VBUS through an external series dropping resistor. No such resistor exists on this net, so once U1 negotiates the 12 V PD contract the VDD pin is driven to 12 V — more than double the absolute maximum — and the part is destroyed; even at the initial 5 V VBUS the design leans on the abs-max ceiling. A series resistor from +12V to VDD sized for <30 mA into the 3.3 V shunt, or a separate regulated supply for VDD, is required. CFG (pin 6) is set by R1 = 47K, which requests 12 V per the CFG table (page 3), consistent with the +12V rail. CC1/CC2 (pins 4/5) connect only to the USB-C receptacle and U1 with no 5.1 kΩ Rd pull-downs, which the reference schematic (page 4) shows on each CC line; absent Rd the sink presence may not be detected. PG (pin 3) is an open-drain output correctly pulled up by R3 to +3V3, well within the 13.5 V PG rating. VDD bypass (1 µF) is available on the +12V rail.

11.1.2 Class-D Audio Amplifier U3 (TPA3118D2)

AI-Assisted — PVCC/AVCC on +12V sit inside the 4.5–26 V supply range, and the +12V rail carries 502.2 µF of bulk (470 µF electrolytic C23 plus ceramics), satisfying the input-capacitor recommendation. The critical defect is GVDD (pin 7), which is tied directly to GND. GVDD is an internally generated gate-drive supply that must have a 1 µF X7R decoupling capacitor to GND (datasheet pages 4/16); shorting it to ground collapses the gate supply and prevents output-stage operation — high severity. As a consequence the GAIN/SLV divider is incomplete: R18 (5K6) forms only the bottom leg to GND with no top resistor to GVDD, so the gain/master-slave state cannot be programmed per Table 1. The four bootstrap capacitors C15–C18 are each 100nF, but the datasheet (page 16) specifies 220nF X5R to the respective output nodes; the fitted value is undersized. PLIMIT (pin 6) is tied to +12V rather than to GVDD as the datasheet recommends for the no-limit configuration. MODSEL=GND selects BD modulation, AM0–AM2=GND set AM-avoidance, SDZ is pulled to +12V with FAULTZ shorted to SDZ for automatic fault recovery, and MUTE is held high through R20 to +3V3 for a default-muted state until GPIO45 drives it — all valid. The four AC-coupled differential inputs use 220nF series caps, and the outputs feed a 9 µH common-mode choke plus 680nF LC network matching the L=10 µH/C=680 nF filter reference.

11.1.3 Stereo Audio DAC U2 (PCM5100A)

AI-Assisted — AVDD, CPVDD and DVDD (pins 8/1/20) all sit on +3V3, within the 3.1–3.46 V supply window and satisfying CPVDD's 3.3 V requirement (page 27). The charge-pump flying capacitor C2 is 2.2µF across CAPP/CAPM, VNEG is decoupled by C3 (2.2µF), and LDOO carries C5 (100nF) plus C6 (10µF) — all per the datasheet. XSMT is pulled to +3V3 by R9 for un-mute; DEMP, FLT and FMT are grounded for de-emphasis off, normal-latency filter and I2S format. SCK (pin 12) is tied to GND, which after 16 LRCK periods starts the internal PLL to derive the system clock from BCK — the intended 3-wire I2S/PCM mode, consistent with the module driving only BCK/LRCK/DIN via series resistors R6/R7/R8. The line outputs OUTL/OUTR use the recommended 470R series resistors R4/R5, but the accompanying 2.2 nF shunt to AGND of the recommended output filter (pages 8/26) is not fitted; this is a filtering refinement rather than a functional fault.

11.1.4 Wireless Module U202 (ESP32-S3-WROOM-1)

AI-Assisted — The module 3V3 pin runs from +3V3 (within the module's 3.0–3.6 V window) and the rail provides 100nF plus 10µF decoupling. GPIO0/BOOT is correctly conditioned with pull-up R19 to +3V3, a 100nF cap, and the boot button SW5 through R204 to GND. Native USB is wired from the USB-C receptacle J201 D+/D- through 22R series resistors R230/R231 to GPIO20 (D+) and GPIO19 (D-). I2S master signals (GPIO14 BCK, GPIO15 LRCK, GPIO16 DATA) drive U2 through series resistors, and GPIO45 controls the amplifier MUTE. EN (pin 3) is tied straight to +3V3 with no series/RC delay network — functional but a soft RC start is preferable for clean power-up sequencing. The UART_TX_main (GPIO47) and UART_RX_main (GPIO48) nets contain only the module pins, with no on-board peer or connector shown, so this UART has no destination on this sheet. The onboard PCB antenna needs no external matching network.

11.2 Findings

AI-Assisted —
DeviceFindingSeverity
U1 (CH221K)VDD (pin 1) tied directly to +12V; exceeds 5.8 V absolute maximum (WCH datasheet p.5) — series dropping resistor to the internal 3.3 V shunt, or a separate VDD supply, is requiredHigh
U3 (TPA3118D2)GVDD (pin 7) tied directly to GND; gate-drive supply must have a 1 µF cap to GND (datasheet p.4/16) — short disables the output stageHigh
U1 (CH221K)CC1/CC2 connect only to J201 and U1 with no 5.1 kΩ Rd pull-downs shown as required in the reference schematic (datasheet p.4)Medium
U3 (TPA3118D2)Bootstrap caps C15–C18 are 100nF; datasheet p.16 requires 220nF X5R to each output nodeMedium
U3 (TPA3118D2)GAIN/SLV divider incomplete — R18 (5K6) to GND only, no top resistor to GVDD, so gain/master-slave state per Table 1 is not programmedMedium
U3 (TPA3118D2)PLIMIT (pin 6) tied to +12V rather than to GVDD as datasheet p.15 recommends for the no-limit configurationLow
U2 (PCM5100A)OUTL/OUTR carry the recommended 470R series (R4/R5) but not the 2.2 nF shunt to AGND of the output filter (datasheet p.8/26)Review
U202 (ESP32-S3-WROOM-1)EN tied directly to +3V3 with no RC start network — functional; soft RC start preferredReview
U202 (ESP32-S3-WROOM-1)UART_TX_main/UART_RX_main (GPIO47/48) reach only the module — no on-board peer or connector shownReview
U1 (CH221K)CFG set by R1=47K from +12V, selecting a 12 V PD request per CFG table (datasheet p.3)✓
U1 (CH221K)PG open-drain pulled up by R3 to +3V3, within 13.5 V PG rating (datasheet p.5)✓
U1 (CH221K)VDD 1 µF bypass available on +12V rail (datasheet p.2)✓
U3 (TPA3118D2)PVCC/AVCC on +12V within 4.5–26 V range; 502.2 µF bulk on rail meets input-cap guidance (datasheet p.27/28)✓
U3 (TPA3118D2)MODSEL=GND (BD mode), AM0–AM2=GND, SDZ pulled to +12V with FAULTZ→SDZ auto-recovery, MUTE default-high via R20 to +3V3 — valid configuration (datasheet pin behavior)✓
U3 (TPA3118D2)Differential inputs AC-coupled with 220nF; outputs use 9 µH choke + 680nF LC matching L=10 µH/C=680 nF reference (datasheet p.5)✓
U2 (PCM5100A)AVDD/CPVDD/DVDD on +3V3 within 3.1–3.46 V window; CPVDD 3.3 V requirement met (datasheet p.6/27)✓
U2 (PCM5100A)CAPP/CAPM flying cap C2=2.2µF, VNEG C3, LDOO C5+C6 decoupling per datasheet p.26/27✓
U2 (PCM5100A)XSMT pulled high (R9); DEMP/FLT/FMT grounded; SCK grounded for internal-PLL 3-wire I2S mode — valid (datasheet pin behavior)✓
U2 (PCM5100A)I2S BCK/LRCK/DIN driven from U202 via series resistors R6/R7/R8✓
U202 (ESP32-S3-WROOM-1)3V3 supply within module range with 100nF + 10µF rail decoupling✓
U202 (ESP32-S3-WROOM-1)GPIO0/BOOT with R19 pull-up, 100nF cap and SW5 boot button correctly configured✓
U202 (ESP32-S3-WROOM-1)Native USB from J201 D+/D- through 22R series R230/R231 to GPIO20/GPIO19✓
U202 (ESP32-S3-WROOM-1)Onboard PCB antenna, no external matching network required✓

11.3 Citations

AI-Assisted —
References
BD33FC0 (ROHM) — datasheet
fscdn.rohm.com/en/products/databook/datasheet/ic/power/li...
CH221K (WCH (wch.cn)) — datasheet, cited pages 1,2,3
components101.com/sites/default/files/component_datasheet...
P7805-2000R-S (CUI Inc) — datasheet
nl.mouser.com/datasheet/2/670/p78_2000r_s-3070500.pdf
PCM5100A (Texas Instruments) — datasheet
www.ti.com/lit/ds/symlink/pcm5100a.pdf
TPA3118D2 (Texas Instruments) — datasheet
www.ti.com/lit/ds/symlink/tpa3118d2.pdf

12 Designer Annotated Nets

No designer-annotated nets found.

13 EMC & ESD Protection Checks

Checks run1
Passed0
Issues found1
EMC Check Summary
CheckIssuesStatus
Connector Shell Grounding1

13.1 Connector Shell Grounding

RefDesTypeIssueRecommendationSeverity
J201USB4500-03-0-AJ201 (https://mou.sr/463mreb) [640-USB4500030A]: Shell pins connected directly to logic GND which masks design intent for layout.Per USB Type-C Specification R2.5, Section 3.2.1: the receptacle shell shall be connected to the PCB ground plane — this is a directive to prevent a floating shell, not a directive to ignore IEC 61000-4-2 ESD requirements and mandate a direct short. Place shell/shield tabs on a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD). This net represents the copper pour under the shielded connector. For plastic enclosed products with no earth ground, add a schematic note for dense via stitching of the shield copper pours to the ground plane with no isolation network. For earth ground connected products, review if the product requires R||C isolation of shields from logic GND to meet ESD compliance (IEC 61000-4-2).

13.2 EMC & ESD Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

13.2.1 EMC Architecture — Grounding, Filtering and Shielding Overview

AI-Assisted — The board uses a single ground domain (GND) that also carries the chassis tag; there is no separated chassis/signal split and no single-point bond network on the schematic. All shielded/mechanical returns share this net: the USB-C shell (J201 S1) and the audio-jack sleeve (J1 S) both land on GND. Power enters through USB-C VBUS, negotiated to 12 V by the CH221K sink controller U1 (CFG set by R1 47K to +12V), and is bulk-decoupled with 502.2µF on the +12V rail (C23 470µF electrolytic plus MLCCs) — adequate reservoir for conducted-immunity per EN 55035/IEC 61000-4-2. The class-D amplifier U3 (TPA3118D2) outputs are filtered before leaving the enclosure: each bridge pair passes through common-mode chokes FL1/FL2 (Würth 744238701, 700Ω @ 100MHz, 4A) into a 680nF-to-GND LC stage (C19–C22), suppressing the switching-edge harmonics that would otherwise radiate from speaker leads under CISPR 32. USB2.0 data lines carry 22R series elements (R230/R231). No board-level TVS/ESD arrays are present on any external port. The schematic does not capture a shield-bonding strategy: every shielded connector shares the logic GND net name, so a layout tool has no net-level guidance to separate copper pours or place explicit bond components.

13.2.2 J201 — USB Type-C Receptacle (external, consumer-facing)

AI-Assisted — J201 is a 24-pin USB-C receptacle used as an external power/data port: VBUS drives the +12V rail via USB-PD, CC1/CC2 route to the CH221K controller U1, and DP1/DN1 reach the ESP32-S3 native USB pins (U202 pins 13/14) through 22R series resistors R230/R231. SBU pins A8/B8 are left unconnected intentionally, correct for a USB2-only sink. The high-speed pairs and CC lines carry no on-board TVS/ESD array on the schematic; a USB-facing consumer port is subject to IEC 61000-4-2 ±8 kV contact / ±15 kV air, so a low-capacitance ESD array on DP/DN and clamping on CC/VBUS warrants investigation (do not treat as a hard defect). The shell S1 is tied to logic GND. Per USB-C R2.5 §3.2.1 the receptacle shell must reference the PCB ground; because S1 shares the main GND net, the intended bond is not expressed as design intent. Recommend a dedicated SHIELD_GND_TYPE_C net so pour separation and bond components are explicit. Plastic-enclosure devices bond the shield pour directly to logic GND by dense via stitching (common-mode rise keeps pin-to-pin differential near zero); metal-chassis products may instead require a 1 MΩ || 4.7 nF (≥2 kV) isolation to earth. Enclosure type is not shown, so both apply.

13.2.3 J1 — Stereo TRS Audio Jack (external)

AI-Assisted — J1 is a 3-pole switched TRS jack forming an external audio port; tip/ring connect through 470R series resistors R4/R5 from the PCM5100A DAC outputs, and the switched TN/RN poles route to the amplifier input chain. The sleeve S is on GND, which is correct — the sleeve is the audio signal return, not a cable shield, so it properly belongs on the signal ground and no dedicated shield net is required for it. No TVS is present on tip/ring. A user-accessible audio jack is an ESD entry point under IEC 61000-4-2; the 470R series resistance limits but does not clamp a strike, so a low-capacitance clamp on tip/ring is worth investigating for CISPR 35 audio-port immunity. Reported as an observation, not a defect.

13.2.4 J2 / J3 — Speaker Output Terminal Blocks (external wiring)

AI-Assisted — J2 and J3 are 2-position terminal blocks carrying the bridge-tied class-D speaker outputs to external cabling. Each channel is filtered by a common-mode choke (FL1/FL2, 700Ω @ 100MHz, 4A rated) and a 680nF-to-GND stage (C19–C22), a proper filtered class-D output that attenuates the PWM switching spectrum before it reaches speaker leads — the dominant radiated-emissions risk for a class-D amplifier under CISPR 32. The 4A choke rating suits the TPA3118D2 power level at a 12 V supply. Terminal blocks are unshielded and carry no TVS; speaker cables are long and can couple ESD/surge back into the output stage, so an output clamp is an optional robustness improvement (observation only, not a defect). No shield pins exist on these connectors, so no dedicated shield net applies.

13.3 Observations

AI-Assisted — The design uses one merged ground; for a plastic-enclosure consumer product this is the correct ESD sink and needs only a documented direct shield-to-GND bond, while a metal-chassis variant may need R||C shield isolation to earth — the enclosure is not shown, so the shield-bond intent should be captured as dedicated per-connector SHIELD_GND nets rather than left on the common GND name. No board-level TVS exists on any external port (USB-C data/CC/VBUS, audio jack, speaker terminals); each is an IEC 61000-4-2 exposure surface worth an ESD-array investigation, none rises to a functional error. The +12V bulk reservoir and the class-D output LC/common-mode filter are sound EMC features. The C23 470µF aluminium electrolytic on +12V is correctly oriented (positive terminal on the higher-potential side). U5 (P7805) is marked do-not-install and U4 (BD33FC0FP LDO) is the fitted +3V3 source; expressing that alternative through the eCAD variant feature would keep the netlist unambiguous.

13.4 Findings

AI-Assisted —
ConnectorFindingSeverity
J201USB-C shell S1 shares the logic GND net; shield-bond strategy not captured as design intent. Recommend a dedicated SHIELD_GND_TYPE_C net per USB-C R2.5 §3.2.1 to give layout pour/bond guidance.Medium
J201No on-board TVS/ESD array on DP1/DN1, CC1/CC2 or VBUS; user-facing USB port per IEC 61000-4-2 (±8 kV contact). Low-capacitance array worth investigation — observation, not a defect.Review
J1External TRS audio port has no TVS on tip/ring; 470R series (R4/R5) limits but does not clamp ESD per IEC 61000-4-2 / CISPR 35. Investigation suggested — observation.Review
J2/J3Unshielded terminal blocks with no output TVS; long speaker cables may couple ESD/surge. Optional clamp — observation, not a defect.Review
GeneralSingle merged GND/chassis domain; shield-bond intent should be captured per-connector. Both plastic (direct via-stitch bond) and metal-chassis (R||C 1 MΩ||4.7 nF ≥2 kV) scenarios apply — enclosure not shown.Review
J201VBUS/+12V bulk decoupling 502.2µF (C23 470µF + MLCCs) adequate for conducted immunity per EN 55035.✓
J201SBU pins A8/B8 unconnected — correct for a USB2-only sink (USB Type-C R2.5).✓
J20122R series resistors R230/R231 on ESP32 native USB DP/DN — consistent with ESP32-S3 datasheet USB guidance.✓
J1Sleeve S correctly on signal GND (audio return, not a cable shield); no separate shield net required.✓
J2/J3Class-D speaker outputs filtered by common-mode chokes FL1/FL2 (700Ω @ 100MHz, 4A) and 680nF LC stage (C19–C22); attenuates PWM harmonics on speaker leads per CISPR 32.✓
J2/J3FL1/FL2 4A rating suits TPA3118D2 output current at 12 V supply (TPA3118D2 datasheet).✓
GeneralC23 470µF aluminium electrolytic on +12V correctly oriented, positive terminal on higher potential (manufacturer polarity convention).✓

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

OptionSettingDescription
Test Point Insertion
Insert on power railsYesPlace test points on power rail nets in schematic
Insert on all netsNoExtend TP insertion to signal nets beyond power rails
Exclude HSSI netsYesExclude HSSI/differential pair nets from TP insertion
Exclude DRAM netsYesExclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)YesExclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)NoExclude nets with partial boundary scan opens coverage
Exclude BSCAN shortsNoExclude nets with boundary scan shorts coverage
GND test points6Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ0%Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage0%Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance0.000 ohmLower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance1.000 ohmUpper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
OpticalAOIAutomated Optical Inspection of visible solder joints
AXIYesAutomated X-ray Inspection of hidden solder joints (BGA, QFN)
ATENoneNo automated test equipment
Test Access
JTAG/LSSI ConnectorYesConnector access to JTAG, SPI, I2C buses
IO ConnectorsNoIO connectors available for external stimulus/observation
TP AccessNoneNo physical probe access to test points
LoopbackNoneNo loopback cables
Test Types
Powered-Off Shorts/OpensNoUnpowered shorts and opens detection via probe access
PassivesNoR, C, L value measurement via probe or fixture access
Active AnalogNoVoltage regulator, reference, and op-amp output verification
Non-BSCAN DigitalNoDigital ICs without boundary scan: pin observability analysis
Boundary Scan1149.1IEEE 1149.1-2013 structural boundary scan
LSSINoJTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG FunctionalNoFunctional verification beyond structural scan
Require Rail TPs for Diode TestNoRequire TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices—Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate StimulusNoCount boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default MethodDirectProgram via direct pin access; TPs on flash data/control lines
Environment
Test environmentlabPrototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found3
Rails with TPs0
Rails without TPs3
3 power rail(s) need test points in the submitted design.
8 test point(s) inserted in modified output. Download modified schematics to see placements.
Power Rail Coverage
Net NameAnnotationTest PointStatus
+12V- NEEDS TP
+3V3- NEEDS TP
GND- NEEDS TP
Inserted Test Points (Modified Output)
Test PointNetSheet
TP1+12Vlogic.kicad_sch
TP2+3V3logic.kicad_sch
TP3GNDlogic.kicad_sch
TP4GNDlogic.kicad_sch
TP5GNDlogic.kicad_sch
TP6GNDlogic.kicad_sch
TP7GNDlogic.kicad_sch
TP8GNDlogic.kicad_sch

14.3 Current Test Points

Total test points0
No test points found in design.

14.4 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.5 Inspection

Total: 100 components, 306 of 339 pins with inspection coverage.

14.5.1 AOI

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
FootprintSize (mil)Pkg TypeClassificationMethodCountPinsRefdes
Opens + Shorts (all joints visible)
Package_TO_SOT_SMD
SOT-23-6SOT (Small Outline Transistor)Footprint16U1
0_NRD_footprints
CP_Wurth_WCAP-ASLL-D16L17Chip PassiveDesignator12C23
L_Wurth_WE-CMDC-7060Chip PassiveDesignator28FL1, FL2
Capacitor_SMD
C_0603_1608MetricChip PassiveDesignator2958C10, C11, C12, C13, C15, C16, C17, C18 ...+21 more
C_0805_2012MetricChip PassiveDesignator48C2, C203, C204, C3
C_1206_3216MetricChip PassiveDesignator48C1, C14, C24, C25
C_1210_3225MetricChip PassiveDesignator36C201, C208, C6
Resistor_SMD
R_0603_1608MetricChip PassiveDesignator4284R1, R10, R11, R12, R13, R14, R15, R16 ...+34 more
Subtotal: 86 components, 180 pins
Opens only (leads visible, shorts unreliable)
Package_SO
HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mmSOIC/SOPFootprint133U3
TSSOP-20_4.4x6.5mm_P0.65mmSOIC/SOPFootprint120U2
Package_TO_SOT_SMD
TO-252-2SOIC/SOPDesignator13U4
_projectlib
ESP32-S3-WROOM-1SOIC/SOPDesignator141U202
Subtotal: 4 components, 97 pins
Presence check (manual verification)
0_NRD_footprints
PJ-328A0-BConnectorDesignator15J1
QT02CSF83H0000GConnectorDesignator24J2, J3
_projectlib
USB_C_Receptacle_USB4500-03-0-AConnectorDesignator120J201
Subtotal: 4 components, 29 pins

14.5.2 Unclassified Components

These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
FootprintSize (mil)Pkg TypeClassificationMethodCountPinsRefdes
0_NRD_footprints
SW_PLMG5-GHUnclassifiedUnknown17SW6
SW_Push_1P1T_NO_CK_KMR2UnclassifiedUnknown12SW5
SW_Wurth_WS-PBTL_465M111172501UnclassifiedUnknown424SW1, SW2, SW3, SW4
Subtotal: 6 components, 33 pins

14.6 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.6.1 Fault Coverage Summary

Fault Coverage Summary (342 pins)
Test MethodOpensShorts
X-ray (AXI)0 (0.0%)0 (0.0%)
Optical (AOI)0 (0.0%)0 (0.0%)
Electrical
   Powered-off Testing--
   Boundary Scan0 (0.0%)0 (0.0%)
   LSSI--
   Total57 (16.7%)123 (36.0%)
Total Fault Coverage57 (16.7%)123 (36.0%)
No coverage285 (83.3%)219 (64.0%)

14.6.2 Uncovered Pins (219)

These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
Pin ⇅Net ⇅
C10_1Net-(C10-Pad1)
C10_2Net-(C10-Pad2)
R16_1Net-(C10-Pad2)
R16_2Logic/LINP
C12_1Logic/LINN
C18_2Net-(U3-OUTNL)
C18_1Net-(U3-BSNL)
R13_1Net-(C7-Pad2)
R13_2Logic/RINN
R30_2Logic/BTN3_G
R30_1Net-(SW3-GREEN)
J2_2Net-(C21-Pad1)
J2_1Net-(C22-Pad1)
R32_2Logic/BTN3
SW4_L2Net-(SW4-GREEN)
SW4_2Logic/BTN4
SW4_L1Net-(SW4-RED)
SW4_L3Net-(SW4-BLUE)
R3_2Logic/PG
J1_TNLogic/AUD_L
J1_TNet-(J1-PadT)
J1_RNLogic/AUD_R
J1_RNet-(J1-PadR)
R15_1Net-(C10-Pad1)
C13_1Logic/LINP
R18_1Net-(U3-GAIN{slash}SLV)
C20_1Net-(C20-Pad1)
SW1_L2Net-(SW1-GREEN)
SW1_2Logic/BTN1
SW1_L1Net-(SW1-RED)
SW1_L3Net-(SW1-BLUE)
R27_2Logic/BTN2_B
R27_1Net-(SW2-BLUE)
R204_1Logic/ESP_BOOTSEL
R204_2Net-(R204-Pad2)
C4_1Net-(C4-Pad1)
C4_2Net-(C4-Pad2)
R231_1Net-(U202-GPIO19{slash}U1RTS{slash}ADC2_CH8{slash}CLK_OUT2{slash}USB_D-)
R231_2ESPUSB_D-
R38_2Logic/UP
C29_1Logic/BTN3
R19_2Logic/ESP_BOOTSEL
C2_2Net-(U2-CAPM)
C2_1Net-(U2-CAPP)
R24_2Logic/BTN1_R
R24_1Net-(SW1-RED)
C21_1Net-(C21-Pad1)
R4_1Net-(U2-OUTL)
R4_2Net-(J1-PadT)
R23_2Logic/BTN1_G
R23_1Net-(SW1-GREEN)
C27_1Logic/BTN1
U202_10
U202_11
U202_12
U202_13Net-(U202-GPIO19{slash}U1RTS{slash}ADC2_CH8{slash}CLK_OUT2{slash}USB_D-)
U202_14Net-(U202-GPIO20{slash}U1CTS{slash}ADC2_CH9{slash}CLK_OUT1{slash}USB_D+)
U202_15
U202_16
U202_17
U202_18
U202_19Logic/BTN1_G
U202_20Logic/BTN1_R
U202_21Logic/BTN1_B
U202_22Logic/I2S0_CLK
U202_23
U202_24UART_TX_{main}
U202_25UART_RX_{main}
U202_26Logic/MUTE
U202_27Logic/ESP_BOOTSEL
U202_28
U202_29
U202_30
U202_31Logic/BTN2_R
U202_32Logic/BTN2_G
U202_33Logic/BTN2_B
U202_34Logic/BTN3_R
U202_35Logic/BTN3_G
U202_36Logic/BTN3_B
U202_37Logic/BTN4_R
U202_38Logic/BTN4_G
U202_39Logic/BTN4_B
U202_4Logic/DOWN
U202_5Logic/UP
U202_6Logic/MENU
U202_7
U202_8Logic/I2S0_WS
U202_9Logic/I2S0_DATA
R5_1Net-(U2-OUTR)
R5_2Net-(J1-PadR)
SW2_L2Net-(SW2-GREEN)
SW2_2Logic/BTN2
SW2_L1Net-(SW2-RED)
SW2_L3Net-(SW2-BLUE)
C42_1Logic/UP
R36_2Logic/BTN4
SW6_1Logic/DOWN
SW6_2Logic/DOWN
SW6_5Logic/MENU
SW6_4Logic/UP
SW6_3Logic/UP
C22_1Net-(C22-Pad1)
R1_2Net-(U1-CFG)
C28_1Logic/BTN2
C19_1Net-(C19-Pad1)
FL1_4Net-(U3-OUTPL)
FL1_3Net-(C20-Pad1)
FL1_2Net-(U3-OUTNL)
FL1_1Net-(C19-Pad1)
R31_2Logic/BTN3_B
R31_1Net-(SW3-BLUE)
U2_17Net-(U2-XSMT)
U2_18Net-(U2-LDOO)
U2_5Net-(U2-VNEG)
U2_6Net-(U2-OUTL)
U2_7Net-(U2-OUTR)
U2_13Net-(U2-BCK)
U2_15Net-(U2-LRCK)
U2_14Net-(U2-DIN)
U2_2Net-(U2-CAPP)
U2_4Net-(U2-CAPM)
R28_2Logic/BTN2
SW5_1Net-(R204-Pad2)
R14_2Net-(C10-Pad1)
R14_1Logic/AUD_L
C30_1Logic/BTN4
J3_2Net-(C20-Pad1)
J3_1Net-(C19-Pad1)
R29_2Logic/BTN3_R
R29_1Net-(SW3-RED)
R20_2Logic/MUTE
R7_1Logic/I2S0_DATA
R7_2Net-(U2-DIN)
R10_2Net-(C4-Pad1)
R10_1Logic/AUD_R
FL2_4Net-(U3-OUTPR)
FL2_3Net-(C21-Pad1)
FL2_2Net-(U3-OUTNR)
FL2_1Net-(C22-Pad1)
R12_1Net-(C4-Pad2)
R12_2Logic/RINP
R8_1Logic/I2S0_CLK
R8_2Net-(U2-BCK)
C43_1Logic/DOWN
R230_1Net-(U202-GPIO20{slash}U1CTS{slash}ADC2_CH9{slash}CLK_OUT1{slash}USB_D+)
R230_2ESPUSB_D+
C41_1Logic/MENU
C6_1Net-(U2-LDOO)
C15_2Net-(U3-OUTPR)
C15_1Net-(U3-BSPR)
R25_2Logic/BTN2_R
R25_1Net-(SW2-RED)
R6_1Logic/I2S0_WS
R6_2Net-(U2-LRCK)
R2_2Logic/BTN1
R26_2Logic/BTN2_G
R26_1Net-(SW2-GREEN)
C8_1Logic/RINN
R35_2Logic/BTN4_B
R35_1Net-(SW4-BLUE)
R33_2Logic/BTN4_R
R33_1Net-(SW4-RED)
C5_1Net-(U2-LDOO)
C9_1Logic/RINP
SW3_L2Net-(SW3-GREEN)
SW3_2Logic/BTN3
SW3_L1Net-(SW3-RED)
SW3_L3Net-(SW3-BLUE)
C17_2Net-(U3-OUTPL)
C17_1Net-(U3-BSPL)
U1_6Net-(U1-CFG)
U1_5Net-(J201-CC2)
U1_4Net-(J201-CC1)
U1_3Logic/PG
J201_A5Net-(J201-CC1)
J201_A6ESPUSB_D+
J201_A7ESPUSB_D-
J201_A8
J201_B5Net-(J201-CC2)
J201_B6ESPUSB_D+
J201_B7ESPUSB_D-
J201_B8
J201_S1GND
J201_S1GND
J201_S1GND
R22_2Logic/BTN1_B
R22_1Net-(SW1-BLUE)
R9_2Net-(U2-XSMT)
R40_2Logic/DOWN
R11_1Net-(C4-Pad1)
R17_1Net-(C11-Pad2)
R17_2Logic/LINN
R21_2Logic/SDZ
R34_2Logic/BTN4_G
R34_1Net-(SW4-GREEN)
C207_1Logic/ESP_BOOTSEL
C16_2Net-(U3-OUTNR)
C16_1Net-(U3-BSNR)
U3_16
U3_5Logic/RINN
U3_4Logic/RINP
U3_3Logic/SDZ
U3_2Logic/SDZ
U3_30Net-(U3-BSPR)
U3_26Net-(U3-BSNR)
U3_21Net-(U3-OUTNL)
U3_20Net-(U3-BSNL)
U3_27Net-(U3-OUTNR)
U3_23Net-(U3-OUTPL)
U3_24Net-(U3-BSPL)
U3_29Net-(U3-OUTPR)
U3_8Net-(U3-GAIN{slash}SLV)
U3_12Logic/MUTE
U3_11Logic/LINN
U3_10Logic/LINP
C3_1Net-(U2-VNEG)
C7_2Net-(C7-Pad2)
R39_2Logic/MENU
C11_2Net-(C11-Pad2)

14.6.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅Net ⇅E Opens ⇅E Shorts ⇅O Opens ⇅O Shorts ⇅X Opens ⇅X Shorts ⇅
C10_1Net-(C10-Pad1)------
C10_2Net-(C10-Pad2)------
R16_1Net-(C10-Pad2)------
R16_2Logic/LINP------
C206_1+3V3-●----
C206_2GND-●----
C12_2GND●●----
C12_1Logic/LINN------
C18_2Net-(U3-OUTNL)------
C18_1Net-(U3-BSNL)------
R13_1Net-(C7-Pad2)------
R13_2Logic/RINN------
R30_2Logic/BTN3_G------
R30_1Net-(SW3-GREEN)------
J2_2Net-(C21-Pad1)------
J2_1Net-(C22-Pad1)------
U5_3+3V3●●----
U5_2GND-●----
U5_1+12V-●----
R32_1+3V3-●----
R32_2Logic/BTN3------
C26_1+12V-●----
C26_2GND-●----
SW4_LC+3V3-●----
SW4_1GND-●----
SW4_L2Net-(SW4-GREEN)------
SW4_2Logic/BTN4------
SW4_L1Net-(SW4-RED)------
SW4_L3Net-(SW4-BLUE)------
R3_1+3V3●●----
R3_2Logic/PG------
J1_TNLogic/AUD_L------
J1_TNet-(J1-PadT)------
J1_SGND-●----
J1_RNLogic/AUD_R------
J1_RNet-(J1-PadR)------
C23_2GND-●----
C23_1+12V-●----
R15_2GND-●----
R15_1Net-(C10-Pad1)------
C13_2GND●●----
C13_1Logic/LINP------
R18_2GND●●----
R18_1Net-(U3-GAIN{slash}SLV)------
C20_1Net-(C20-Pad1)------
C20_2GND-●----
SW1_LC+3V3-●----
SW1_1GND-●----
SW1_L2Net-(SW1-GREEN)------
SW1_2Logic/BTN1------
SW1_L1Net-(SW1-RED)------
SW1_L3Net-(SW1-BLUE)------
R27_2Logic/BTN2_B------
R27_1Net-(SW2-BLUE)------
R204_1Logic/ESP_BOOTSEL------
R204_2Net-(R204-Pad2)------
C4_1Net-(C4-Pad1)------
C4_2Net-(C4-Pad2)------
R231_1Net-(U202-GPIO19{slash}U1RTS{slash}ADC2_CH8{slash}CLK_OUT2{slash}USB_D-)------
R231_2ESPUSB_D-------
R38_1+3V3●●----
R38_2Logic/UP------
C29_2GND-●----
C29_1Logic/BTN3------
R19_1+3V3●●----
R19_2Logic/ESP_BOOTSEL------
C202_1+12V-●----
C202_2GND-●----
C2_2Net-(U2-CAPM)------
C2_1Net-(U2-CAPP)------
C201_1+12V-●----
C201_2GND-●----
C203_1+3V3-●----
C203_2GND-●----
R24_2Logic/BTN1_R------
R24_1Net-(SW1-RED)------
C21_1Net-(C21-Pad1)------
C21_2GND-●----
R4_1Net-(U2-OUTL)------
R4_2Net-(J1-PadT)------
R23_2Logic/BTN1_G------
R23_1Net-(SW1-GREEN)------
C27_2GND-●----
C27_1Logic/BTN1------
U202_1GND●●----
U202_10------
U202_11------
U202_12------
U202_13Net-(U202-GPIO19{slash}U1RTS{slash}ADC2_CH8{slash}CLK_OUT2{slash}USB_D-)------
U202_14Net-(U202-GPIO20{slash}U1CTS{slash}ADC2_CH9{slash}CLK_OUT1{slash}USB_D+)------
U202_15------
U202_16------
U202_17------
U202_18------
U202_19Logic/BTN1_G------
U202_2+3V3●●----
U202_20Logic/BTN1_R------
U202_21Logic/BTN1_B------
U202_22Logic/I2S0_CLK------
U202_23------
U202_24UART_TX_{main}------
U202_25UART_RX_{main}------
U202_26Logic/MUTE------
U202_27Logic/ESP_BOOTSEL------
U202_28------
U202_29------
U202_3+3V3●●----
U202_30------
U202_31Logic/BTN2_R------
U202_32Logic/BTN2_G------
U202_33Logic/BTN2_B------
U202_34Logic/BTN3_R------
U202_35Logic/BTN3_G------
U202_36Logic/BTN3_B------
U202_37Logic/BTN4_R------
U202_38Logic/BTN4_G------
U202_39Logic/BTN4_B------
U202_4Logic/DOWN------
U202_5Logic/UP------
U202_6Logic/MENU------
U202_7------
U202_8Logic/I2S0_WS------
U202_9Logic/I2S0_DATA------
U202_40GND●●----
U202_41GND●●----
R5_1Net-(U2-OUTR)------
R5_2Net-(J1-PadR)------
SW2_LC+3V3-●----
SW2_1GND-●----
SW2_L2Net-(SW2-GREEN)------
SW2_2Logic/BTN2------
SW2_L1Net-(SW2-RED)------
SW2_L3Net-(SW2-BLUE)------
C42_2GND●●----
C42_1Logic/UP------
R36_1+3V3-●----
R36_2Logic/BTN4------
SW6_1Logic/DOWN------
SW6_2Logic/DOWN------
SW6_7GND-●----
SW6_6GND-●----
SW6_5Logic/MENU------
SW6_4Logic/UP------
SW6_3Logic/UP------
C1_2GND-●----
C1_1+12V-●----
C22_1Net-(C22-Pad1)------
C22_2GND-●----
R1_1+12V●●----
R1_2Net-(U1-CFG)------
C28_2GND-●----
C28_1Logic/BTN2------
C19_1Net-(C19-Pad1)------
C19_2GND-●----
U4_1+12V-●----
U4_2GND-●----
U4_3+3V3●●----
FL1_4Net-(U3-OUTPL)------
FL1_3Net-(C20-Pad1)------
FL1_2Net-(U3-OUTNL)------
FL1_1Net-(C19-Pad1)------
C14_2GND-●----
C14_1+12V-●----
R31_2Logic/BTN3_B------
R31_1Net-(SW3-BLUE)------
C204_1+3V3-●----
C204_2GND-●----
U2_17Net-(U2-XSMT)------
U2_10GND●●----
U2_12GND●●----
U2_8+3V3●●----
U2_18Net-(U2-LDOO)------
U2_5Net-(U2-VNEG)------
U2_6Net-(U2-OUTL)------
U2_7Net-(U2-OUTR)------
U2_3GND●●----
U2_13Net-(U2-BCK)------
U2_11GND●●----
U2_15Net-(U2-LRCK)------
U2_14Net-(U2-DIN)------
U2_20+3V3●●----
U2_2Net-(U2-CAPP)------
U2_4Net-(U2-CAPM)------
U2_19GND●●----
U2_16GND●●----
U2_1+3V3●●----
U2_9GND●●----
R28_1+3V3-●----
R28_2Logic/BTN2------
SW5_2GND-●----
SW5_1Net-(R204-Pad2)------
R14_2Net-(C10-Pad1)------
R14_1Logic/AUD_L------
C30_2GND-●----
C30_1Logic/BTN4------
J3_2Net-(C20-Pad1)------
J3_1Net-(C19-Pad1)------
R29_2Logic/BTN3_R------
R29_1Net-(SW3-RED)------
R20_1+3V3●●----
R20_2Logic/MUTE------
R7_1Logic/I2S0_DATA------
R7_2Net-(U2-DIN)------
R10_2Net-(C4-Pad1)------
R10_1Logic/AUD_R------
FL2_4Net-(U3-OUTPR)------
FL2_3Net-(C21-Pad1)------
FL2_2Net-(U3-OUTNR)------
FL2_1Net-(C22-Pad1)------
R12_1Net-(C4-Pad2)------
R12_2Logic/RINP------
R8_1Logic/I2S0_CLK------
R8_2Net-(U2-BCK)------
C43_2GND●●----
C43_1Logic/DOWN------
C208_1+3V3-●----
C208_2GND-●----
C25_1+12V-●----
C25_2GND-●----
R230_1Net-(U202-GPIO20{slash}U1CTS{slash}ADC2_CH9{slash}CLK_OUT1{slash}USB_D+)------
R230_2ESPUSB_D+------
C41_2GND●●----
C41_1Logic/MENU------
C6_1Net-(U2-LDOO)------
C6_2GND●●----
C205_2GND-●----
C205_1+3V3-●----
C15_2Net-(U3-OUTPR)------
C15_1Net-(U3-BSPR)------
R25_2Logic/BTN2_R------
R25_1Net-(SW2-RED)------
R6_1Logic/I2S0_WS------
R6_2Net-(U2-LRCK)------
R2_1+3V3-●----
R2_2Logic/BTN1------
R26_2Logic/BTN2_G------
R26_1Net-(SW2-GREEN)------
C8_2GND●●----
C8_1Logic/RINN------
R35_2Logic/BTN4_B------
R35_1Net-(SW4-BLUE)------
R33_2Logic/BTN4_R------
R33_1Net-(SW4-RED)------
C5_1Net-(U2-LDOO)------
C5_2GND●●----
C9_2GND●●----
C9_1Logic/RINP------
SW3_LC+3V3-●----
SW3_1GND-●----
SW3_L2Net-(SW3-GREEN)------
SW3_2Logic/BTN3------
SW3_L1Net-(SW3-RED)------
SW3_L3Net-(SW3-BLUE)------
C17_2Net-(U3-OUTPL)------
C17_1Net-(U3-BSPL)------
U1_6Net-(U1-CFG)------
U1_5Net-(J201-CC2)------
U1_4Net-(J201-CC1)------
U1_3Logic/PG------
U1_2GND-●----
U1_1+12V●●----
C24_1+12V-●----
C24_2GND-●----
J201_A1GND-●----
J201_A12GND-●----
J201_A4+12V-●----
J201_A5Net-(J201-CC1)------
J201_A6ESPUSB_D+------
J201_A7ESPUSB_D-------
J201_A8------
J201_A9+12V-●----
J201_B1GND-●----
J201_B12GND-●----
J201_B4+12V-●----
J201_B5Net-(J201-CC2)------
J201_B6ESPUSB_D+------
J201_B7ESPUSB_D-------
J201_B8------
J201_B9+12V-●----
J201_S1GND------
J201_S1GND------
J201_S1GND------
J201_S1GND-●----
R22_2Logic/BTN1_B------
R22_1Net-(SW1-BLUE)------
R9_1+3V3●●----
R9_2Net-(U2-XSMT)------
R40_1+3V3●●----
R40_2Logic/DOWN------
R11_2GND-●----
R11_1Net-(C4-Pad1)------
R17_1Net-(C11-Pad2)------
R17_2Logic/LINN------
R21_1+12V●●----
R21_2Logic/SDZ------
R34_2Logic/BTN4_G------
R34_1Net-(SW4-GREEN)------
C207_2GND●●----
C207_1Logic/ESP_BOOTSEL------
C16_2Net-(U3-OUTNR)------
C16_1Net-(U3-BSNR)------
U3_16------
U3_15GND●●----
U3_14GND●●----
U3_13GND●●----
U3_7GND●●----
U3_6+12V●●----
U3_5Logic/RINN------
U3_4Logic/RINP------
U3_3Logic/SDZ------
U3_2Logic/SDZ------
U3_31+12V●●----
U3_32+12V●●----
U3_30Net-(U3-BSPR)------
U3_26Net-(U3-BSNR)------
U3_22GND●●----
U3_21Net-(U3-OUTNL)------
U3_20Net-(U3-BSNL)------
U3_19+12V●●----
U3_1GND●●----
U3_25GND●●----
U3_28GND●●----
U3_27Net-(U3-OUTNR)------
U3_23Net-(U3-OUTPL)------
U3_18+12V●●----
U3_17+12V●●----
U3_24Net-(U3-BSPL)------
U3_29Net-(U3-OUTPR)------
U3_8Net-(U3-GAIN{slash}SLV)------
U3_12Logic/MUTE------
U3_11Logic/LINN------
U3_10Logic/LINP------
U3_9GND●●----
U3_33GND●●----
C3_2GND●●----
C3_1Net-(U2-VNEG)------
C7_1GND●●----
C7_2Net-(C7-Pad2)------
R39_1+3V3●●----
R39_2Logic/MENU------
C11_1GND●●----
C11_2Net-(C11-Pad2)------

14.7 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.7.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Test MethodPCOLASOpensSolder Quality
Electrical Test31.5%0.0%0.0%0.0%0.0%17.7%16.7%0.0%
Optical Inspection (AOI)0.0%0.0%0.0%0.0%0.0%0.0%0.0%0.0%
X-Ray Inspection (AXI)0.0%0.0%0.0%0.0%0.0%0.0%0.0%0.0%
Combined31.5%0.0%0.0%0.0%0.0%17.7%16.7%0.0%

14.7.2 PCB Device/Pin Count

Devices (PCOLA): 100
Pins (SOQ): 336

14.7.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
DimensionScoreCoverage
PCOLA6300 / 100,0006.3%
SOQ11458 / 100,00011.5%
Combined8879 / 100,0008.9%
Electrical vs Inspection
SourcePCOLA ScoreSOQ Score
Electrical Test6300 / 100,00011458 / 100,000
Optical/X-ray Inspection0 / 100,0000 / 100,000
Combined (max)6300 / 100,00011458 / 100,000

14.7.4 PCOLA (100 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅RefDes ⇅Type / Footprint ⇅Class ⇅P ⇅C ⇅O ⇅L ⇅A ⇅Method ⇅
10%J1PJ-328A0-B / PJ-328A0-B *Connector◐○○—○Powered_Off
10%R910K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C206100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C12220nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C8220nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C5100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C9220nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%SW3465M111172501 / SW_Wurth_WS-PBTL_465M111172501 *Switch◐○○○○Powered_Off
10%R3247K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C26100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%SW4465M111172501 / SW_Wurth_WS-PBTL_465M111172501 *Switch◐○○○○Powered_Off
10%R347K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C29100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C23470uF / CP_Wurth_WCAP-ASLL-D16L17 *Capacitor◐○○—○Powered_Off
10%R1510K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C13220nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R185K6 / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C20680nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%SW1465M111172501 / SW_Wurth_WS-PBTL_465M111172501 *Switch◐○○○○Powered_Off
10%U1CH221K / SOT-23-6 *IC◐○○○○Powered_Off
10%C2410uF / C_1206_3216Metric *Capacitor◐○○—○Powered_Off
10%J201USB4500-03-0-A / USB_C_Receptacle_USB4500-03-0-A *Connector◐○○—○Powered_Off
10%C111uF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R3847K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%R4047K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%R1922K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C202100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R1110K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C20110uF / C_1210_3225Metric *Capacitor◐○○—○Powered_Off
10%C20310uF / C_0805_2012Metric *Capacitor◐○○—○Powered_Off
10%R2122K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C21680nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C207100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%U3TPA3118D2DAPR / HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm *IC◐○○○○Powered_Off
10%C27100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%U202ESP32-S3-WROOM-1 / ESP32-S3-WROOM-1 *IC◐○○○○Powered_Off
10%C32.2uF / C_0805_2012Metric *Capacitor◐○○—○Powered_Off
10%SW2465M111172501 / SW_Wurth_WS-PBTL_465M111172501 *Switch◐○○○○Powered_Off
10%C42100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R3647K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%SW6SW_NAV_PLMG5 / SW_PLMG5-GH *Switch◐○○○○Powered_Off
10%C11uF / C_1206_3216Metric *Capacitor◐○○—○Powered_Off
10%C22680nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R147K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C28100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C19680nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%U4BD33FC0FP / TO-252-2 *IC◐○○○○Powered_Off
10%C71uF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C141uF / C_1206_3216Metric *Capacitor◐○○—○Powered_Off
10%R3947K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C20410uF / C_0805_2012Metric *Capacitor◐○○—○Powered_Off
10%U2PCM5100A / TSSOP-20_4.4x6.5mm_P0.65mm *IC◐○○○○Powered_Off
10%R2847K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%SW5KMR223GLFG / SW_Push_1P1T_NO_CK_KMR2 *Switch◐○○○○Powered_Off
10%C30100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R2022K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
10%C43100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C20810uF / C_1210_3225Metric *Capacitor◐○○—○Powered_Off
10%C2510uF / C_1206_3216Metric *Capacitor◐○○—○Powered_Off
10%C41100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%C610uF / C_1210_3225Metric *Capacitor◐○○—○Powered_Off
10%C205100nF / C_0603_1608Metric *Capacitor◐○○—○Powered_Off
10%R247K / R_0603_1608Metric *Resistor◐○○—○Powered_Off
0%R161K0 / R_0603_1608Metric *Resistor○○○—○
0%C18100nF / C_0603_1608Metric *Capacitor○○○—○
0%R131K0 / R_0603_1608Metric *Resistor○○○—○
0%R30220R / R_0603_1608Metric *Resistor○○○—○
0%J2QT02CSF83H0000G / QT02CSF83H0000G *Connector○○○—○
0%R27220R / R_0603_1608Metric *Resistor○○○—○
0%R2041K0 / R_0603_1608Metric *Resistor○○○—○
0%C41uF / C_0603_1608Metric *Capacitor○○○—○
0%R23122R / R_0603_1608Metric *Resistor○○○—○
0%C101uF / C_0603_1608Metric *Capacitor○○○—○
0%C22.2uF / C_0805_2012Metric *Capacitor○○○—○
0%R24220R / R_0603_1608Metric *Resistor○○○—○
0%R4470R / R_0603_1608Metric *Resistor○○○—○
0%R23220R / R_0603_1608Metric *Resistor○○○—○
0%R5470R / R_0603_1608Metric *Resistor○○○—○
0%FL1744238701 / L_Wurth_WE-CMDC-7060 *Ferrite○○○—○
0%R31220R / R_0603_1608Metric *Resistor○○○—○
0%R1410K / R_0603_1608Metric *Resistor○○○—○
0%R23022R / R_0603_1608Metric *Resistor○○○—○
0%C17100nF / C_0603_1608Metric *Capacitor○○○—○
0%R7470R / R_0603_1608Metric *Resistor○○○—○
0%R1010K / R_0603_1608Metric *Resistor○○○—○
0%FL2744238701 / L_Wurth_WE-CMDC-7060 *Ferrite○○○—○
0%R22220R / R_0603_1608Metric *Resistor○○○—○
0%C15100nF / C_0603_1608Metric *Capacitor○○○—○
0%R25220R / R_0603_1608Metric *Resistor○○○—○
0%R6470R / R_0603_1608Metric *Resistor○○○—○
0%R171K0 / R_0603_1608Metric *Resistor○○○—○
0%R121K0 / R_0603_1608Metric *Resistor○○○—○
0%R34220R / R_0603_1608Metric *Resistor○○○—○
0%R8470R / R_0603_1608Metric *Resistor○○○—○
0%C16100nF / C_0603_1608Metric *Capacitor○○○—○
0%J3QT02CSF83H0000G / QT02CSF83H0000G *Connector○○○—○
0%R35220R / R_0603_1608Metric *Resistor○○○—○
0%R33220R / R_0603_1608Metric *Resistor○○○—○
0%R29220R / R_0603_1608Metric *Resistor○○○—○
0%R26220R / R_0603_1608Metric *Resistor○○○—○

14.7.5 SOQ (336 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅Pin ⇅Net ⇅S ⇅O ⇅Q ⇅
50%U2_10GND◐●○
50%R38_1+3V3◐●○
50%R1_1+12V◐●○
50%U202_41GND◐●○
50%U2_3GND◐●○
50%U2_11GND◐●○
50%C12_2GND◐●○
50%C11_1GND◐●○
50%R19_1+3V3◐●○
50%U2_19GND◐●○
50%U2_16GND◐●○
50%U2_1+3V3◐●○
50%U2_9GND◐●○
50%C43_2GND◐●○
50%C6_2GND◐●○
50%R20_1+3V3◐●○
50%C41_2GND◐●○
50%C8_2GND◐●○
50%C5_2GND◐●○
50%C9_2GND◐●○
50%U1_1+12V◐●○
50%U3_31+12V◐●○
50%R9_1+3V3◐●○
50%R40_1+3V3◐●○
50%R21_1+12V◐●○
50%U202_3+3V3◐●○
50%R3_1+3V3◐●○
50%C207_2GND◐●○
50%U3_15GND◐●○
50%C42_2GND◐●○
50%U3_14GND◐●○
50%U3_13GND◐●○
50%U3_7GND◐●○
50%U3_6+12V◐●○
50%U3_32+12V◐●○
50%U3_22GND◐●○
50%U3_19+12V◐●○
50%C13_2GND◐●○
50%U3_1GND◐●○
50%R18_2GND◐●○
50%U202_1GND◐●○
50%U3_25GND◐●○
50%U4_3+3V3◐●○
50%U3_28GND◐●○
50%U3_18+12V◐●○
50%U2_20+3V3◐●○
50%U3_17+12V◐●○
50%U2_12GND◐●○
50%U3_9GND◐●○
50%U3_33GND◐●○
50%C3_2GND◐●○
50%C7_1GND◐●○
50%U2_8+3V3◐●○
50%U202_2+3V3◐●○
50%R39_1+3V3◐●○
50%U202_40GND◐●○
17%C29_2GND◐○○
17%C206_1+3V3◐○○
17%C206_2GND◐○○
17%C14_2GND◐○○
17%SW2_LC+3V3◐○○
17%C202_1+12V◐○○
17%C202_2GND◐○○
17%SW2_1GND◐○○
17%C201_2GND◐○○
17%R32_1+3V3◐○○
17%C203_1+3V3◐○○
17%C26_1+12V◐○○
17%C26_2GND◐○○
17%SW4_LC+3V3◐○○
17%SW4_1GND◐○○
17%C203_2GND◐○○
17%C28_2GND◐○○
17%C14_1+12V◐○○
17%C21_2GND◐○○
17%C201_1+12V◐○○
17%J1_SGND◐○○
17%C19_2GND◐○○
17%R36_1+3V3◐○○
17%C23_2GND◐○○
17%C23_1+12V◐○○
17%R15_2GND◐○○
17%C27_2GND◐○○
17%U4_1+12V◐○○
17%U4_2GND◐○○
17%SW1_LC+3V3◐○○
17%SW1_1GND◐○○
17%SW6_6GND◐○○
17%C204_1+3V3◐○○
17%C204_2GND◐○○
17%C1_2GND◐○○
17%C1_1+12V◐○○
17%C22_2GND◐○○
17%J201_B9+12V◐○○
17%C25_2GND◐○○
17%SW5_2GND◐○○
17%R11_2GND◐○○
17%SW6_7GND◐○○
17%C205_2GND◐○○
17%C205_1+3V3◐○○
17%R2_1+3V3◐○○
17%C30_2GND◐○○
17%R28_1+3V3◐○○
17%C208_1+3V3◐○○
17%C20_2GND◐○○
17%SW3_LC+3V3◐○○
17%SW3_1GND◐○○
17%U1_2GND◐○○
17%C208_2GND◐○○
17%C24_1+12V◐○○
17%C24_2GND◐○○
17%J201_A1GND◐○○
17%J201_A12GND◐○○
17%J201_A4+12V◐○○
17%J201_A9+12V◐○○
17%C25_1+12V◐○○
17%J201_B12GND◐○○
17%J201_B4+12V◐○○
17%J201_B1GND◐○○
0%U202_20Logic/BTN1_R○○○
0%U202_21Logic/BTN1_B○○○
0%U202_22Logic/I2S0_CLK○○○
0%U202_23○○○
0%U202_24UART_TX_{main}○○○
0%U202_25UART_RX_{main}○○○
0%U202_26Logic/MUTE○○○
0%U202_27Logic/ESP_BOOTSEL○○○
0%U202_28○○○
0%U202_29○○○
0%U202_30○○○
0%U202_31Logic/BTN2_R○○○
0%U202_32Logic/BTN2_G○○○
0%U202_33Logic/BTN2_B○○○
0%U202_34Logic/BTN3_R○○○
0%U202_35Logic/BTN3_G○○○
0%U202_36Logic/BTN3_B○○○
0%U202_37Logic/BTN4_R○○○
0%U202_38Logic/BTN4_G○○○
0%U202_39Logic/BTN4_B○○○
0%U202_4Logic/DOWN○○○
0%U202_5Logic/UP○○○
0%U202_6Logic/MENU○○○
0%U202_7○○○
0%U202_8Logic/I2S0_WS○○○
0%U202_9Logic/I2S0_DATA○○○
0%R5_1Net-(U2-OUTR)○○○
0%R5_2Net-(J1-PadR)○○○
0%SW2_2Logic/BTN2○○○
0%SW2_L1Net-(SW2-RED)○○○
0%SW2_L3Net-(SW2-BLUE)○○○
0%C42_1Logic/UP○○○
0%R36_2Logic/BTN4○○○
0%SW6_1Logic/DOWN○○○
0%SW6_2Logic/DOWN○○○
0%SW6_5Logic/MENU○○○
0%SW6_4Logic/UP○○○
0%SW6_3Logic/UP○○○
0%C22_1Net-(C22-Pad1)○○○
0%R1_2Net-(U1-CFG)○○○
0%C28_1Logic/BTN2○○○
0%C19_1Net-(C19-Pad1)○○○
0%FL1_4Net-(U3-OUTPL)○○○
0%FL1_3Net-(C20-Pad1)○○○
0%FL1_2Net-(U3-OUTNL)○○○
0%FL1_1Net-(C19-Pad1)○○○
0%R31_2Logic/BTN3_B○○○
0%R31_1Net-(SW3-BLUE)○○○
0%U2_17Net-(U2-XSMT)○○○
0%SW2_L2Net-(SW2-GREEN)○○○
0%U2_5Net-(U2-VNEG)○○○
0%U2_6Net-(U2-OUTL)○○○
0%U2_7Net-(U2-OUTR)○○○
0%C10_2Net-(C10-Pad2)○○○
0%U2_13Net-(U2-BCK)○○○
0%R16_1Net-(C10-Pad2)○○○
0%U2_15Net-(U2-LRCK)○○○
0%U2_14Net-(U2-DIN)○○○
0%R16_2Logic/LINP○○○
0%U2_2Net-(U2-CAPP)○○○
0%U2_4Net-(U2-CAPM)○○○
0%C12_1Logic/LINN○○○
0%C18_2Net-(U3-OUTNL)○○○
0%C18_1Net-(U3-BSNL)○○○
0%R13_1Net-(C7-Pad2)○○○
0%R13_2Logic/RINN○○○
0%R28_2Logic/BTN2○○○
0%R30_2Logic/BTN3_G○○○
0%SW5_1Net-(R204-Pad2)○○○
0%R14_2Net-(C10-Pad1)○○○
0%R14_1Logic/AUD_L○○○
0%R30_1Net-(SW3-GREEN)○○○
0%C30_1Logic/BTN4○○○
0%J3_2Net-(C20-Pad1)○○○
0%J3_1Net-(C19-Pad1)○○○
0%R29_2Logic/BTN3_R○○○
0%R29_1Net-(SW3-RED)○○○
0%J2_2Net-(C21-Pad1)○○○
0%R20_2Logic/MUTE○○○
0%R7_1Logic/I2S0_DATA○○○
0%R7_2Net-(U2-DIN)○○○
0%R10_2Net-(C4-Pad1)○○○
0%R10_1Logic/AUD_R○○○
0%FL2_4Net-(U3-OUTPR)○○○
0%FL2_3Net-(C21-Pad1)○○○
0%FL2_2Net-(U3-OUTNR)○○○
0%FL2_1Net-(C22-Pad1)○○○
0%R12_1Net-(C4-Pad2)○○○
0%R12_2Logic/RINP○○○
0%R8_1Logic/I2S0_CLK○○○
0%R8_2Net-(U2-BCK)○○○
0%U2_18Net-(U2-LDOO)○○○
0%C43_1Logic/DOWN○○○
0%J2_1Net-(C22-Pad1)○○○
0%R32_2Logic/BTN3○○○
0%SW4_L2Net-(SW4-GREEN)○○○
0%SW4_2Logic/BTN4○○○
0%R230_1Net-(U202-GPIO20{slash}U1CTS{slash}ADC2_CH9{slash}CLK_OUT1{slash}USB_D+)○○○
0%R230_2ESPUSB_D+○○○
0%SW4_L1Net-(SW4-RED)○○○
0%C41_1Logic/MENU○○○
0%C6_1Net-(U2-LDOO)○○○
0%SW4_L3Net-(SW4-BLUE)○○○
0%R3_2Logic/PG○○○
0%J1_TNLogic/AUD_L○○○
0%C15_2Net-(U3-OUTPR)○○○
0%C15_1Net-(U3-BSPR)○○○
0%R25_2Logic/BTN2_R○○○
0%R25_1Net-(SW2-RED)○○○
0%R6_1Logic/I2S0_WS○○○
0%R6_2Net-(U2-LRCK)○○○
0%J1_TNet-(J1-PadT)○○○
0%R2_2Logic/BTN1○○○
0%R26_2Logic/BTN2_G○○○
0%R26_1Net-(SW2-GREEN)○○○
0%J1_RNLogic/AUD_R○○○
0%C8_1Logic/RINN○○○
0%R35_2Logic/BTN4_B○○○
0%R35_1Net-(SW4-BLUE)○○○
0%R33_2Logic/BTN4_R○○○
0%R33_1Net-(SW4-RED)○○○
0%C5_1Net-(U2-LDOO)○○○
0%J1_RNet-(J1-PadR)○○○
0%R15_1Net-(C10-Pad1)○○○
0%C9_1Logic/RINP○○○
0%C13_1Logic/LINP○○○
0%R18_1Net-(U3-GAIN{slash}SLV)○○○
0%SW3_L2Net-(SW3-GREEN)○○○
0%SW3_2Logic/BTN3○○○
0%SW3_L1Net-(SW3-RED)○○○
0%SW3_L3Net-(SW3-BLUE)○○○
0%C17_2Net-(U3-OUTPL)○○○
0%C17_1Net-(U3-BSPL)○○○
0%U1_6Net-(U1-CFG)○○○
0%U1_5Net-(J201-CC2)○○○
0%U1_4Net-(J201-CC1)○○○
0%U1_3Logic/PG○○○
0%C20_1Net-(C20-Pad1)○○○
0%C10_1Net-(C10-Pad1)○○○
0%SW1_L2Net-(SW1-GREEN)○○○
0%SW1_2Logic/BTN1○○○
0%SW1_L1Net-(SW1-RED)○○○
0%SW1_L3Net-(SW1-BLUE)○○○
0%R27_2Logic/BTN2_B○○○
0%J201_A5Net-(J201-CC1)○○○
0%J201_A6ESPUSB_D+○○○
0%J201_A7ESPUSB_D-○○○
0%J201_A8○○○
0%R27_1Net-(SW2-BLUE)○○○
0%R204_1Logic/ESP_BOOTSEL○○○
0%R204_2Net-(R204-Pad2)○○○
0%C4_1Net-(C4-Pad1)○○○
0%J201_B5Net-(J201-CC2)○○○
0%J201_B6ESPUSB_D+○○○
0%J201_B7ESPUSB_D-○○○
0%J201_B8○○○
0%C4_2Net-(C4-Pad2)○○○
0%J201_S1GND○○○
0%R22_2Logic/BTN1_B○○○
0%R22_1Net-(SW1-BLUE)○○○
0%R231_1Net-(U202-GPIO19{slash}U1RTS{slash}ADC2_CH8{slash}CLK_OUT2{slash}USB_D-)○○○
0%R9_2Net-(U2-XSMT)○○○
0%R231_2ESPUSB_D-○○○
0%R40_2Logic/DOWN○○○
0%R38_2Logic/UP○○○
0%R11_1Net-(C4-Pad1)○○○
0%R17_1Net-(C11-Pad2)○○○
0%R17_2Logic/LINN○○○
0%C29_1Logic/BTN3○○○
0%R21_2Logic/SDZ○○○
0%R34_2Logic/BTN4_G○○○
0%R34_1Net-(SW4-GREEN)○○○
0%R19_2Logic/ESP_BOOTSEL○○○
0%C207_1Logic/ESP_BOOTSEL○○○
0%C16_2Net-(U3-OUTNR)○○○
0%C16_1Net-(U3-BSNR)○○○
0%U3_16○○○
0%C2_2Net-(U2-CAPM)○○○
0%C2_1Net-(U2-CAPP)○○○
0%R24_2Logic/BTN1_R○○○
0%R24_1Net-(SW1-RED)○○○
0%C21_1Net-(C21-Pad1)○○○
0%U3_5Logic/RINN○○○
0%U3_4Logic/RINP○○○
0%U3_3Logic/SDZ○○○
0%U3_2Logic/SDZ○○○
0%R4_1Net-(U2-OUTL)○○○
0%R4_2Net-(J1-PadT)○○○
0%U3_30Net-(U3-BSPR)○○○
0%U3_26Net-(U3-BSNR)○○○
0%R23_2Logic/BTN1_G○○○
0%U3_21Net-(U3-OUTNL)○○○
0%U3_20Net-(U3-BSNL)○○○
0%R23_1Net-(SW1-GREEN)○○○
0%C27_1Logic/BTN1○○○
0%U202_10○○○
0%U202_11○○○
0%U3_27Net-(U3-OUTNR)○○○
0%U3_23Net-(U3-OUTPL)○○○
0%U202_12○○○
0%U202_13Net-(U202-GPIO19{slash}U1RTS{slash}ADC2_CH8{slash}CLK_OUT2{slash}USB_D-)○○○
0%U3_24Net-(U3-BSPL)○○○
0%U3_29Net-(U3-OUTPR)○○○
0%U3_8Net-(U3-GAIN{slash}SLV)○○○
0%U3_12Logic/MUTE○○○
0%U3_11Logic/LINN○○○
0%U3_10Logic/LINP○○○
0%U202_14Net-(U202-GPIO20{slash}U1CTS{slash}ADC2_CH9{slash}CLK_OUT1{slash}USB_D+)○○○
0%U202_15○○○
0%U202_16○○○
0%C3_1Net-(U2-VNEG)○○○
0%U202_17○○○
0%C7_2Net-(C7-Pad2)○○○
0%U202_18○○○
0%R39_2Logic/MENU○○○
0%U202_19Logic/BTN1_G○○○
0%C11_2Net-(C11-Pad2)○○○

14.7.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

MethodPCOLASOpensQ
AOIFullFullFull—PartialPartialPartialPartial
AXI————PartialPartialPartialPartial
JTAG/BSCANFullFullFullPartial—FullFull—
BSCAN_PassivesFullFullFullFull—FullFull—
I2CPartialPartial—Partial—PartialPartial—
SPIPartialPartial—Partial—PartialPartial—
UART———Partial————
Passive_MeasFullFullFullFull—FullFull—
Powered_OffPartial————PartialFull—

15 Component Properties

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
GradeRatingDescription
AExcellentHas Power pins AND properly typed I/O pins (>=90% typed)
BGood>=70% typed OR (>=50% typed AND has Power)
CFairMix of typed and Passive pins (>=40% typed)
DPoorMostly Passive with few typed pins (>=10% typed)
FFailAll pins Passive/Unknown (<10% typed, no ERC)
IC Library Model Grades (sorted worst to best)
RefDesGrdPinsPwrInOutIOOCOEHiZPasPart NumberCreator
U2C2058200005PCM5100A
U1B621021000CH221K
U202B41210360002ESP32-S3-WROOM-1
U3B331112910000TPA3118D2DAPR
U4A330000000BD33FC0FP
U5A330000000P7805-2000R-S

15.1.1 Library Quality Summary

Total ICs evaluated6
Grade A (excellent)2 (33.3%)
Grade B (good)3 (50.0%)
Grade C (fair)1 (16.7%)
Grade D (poor)0 (0.0%)
Grade F (fail)0 (0.0%)
OVERALL LIBRARY QUALITYA (3.77/4.00)

15.2 Component Library Validation

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (4 models)
Library NameIndustry NamePart NumberRefDesPinsDistributionIssues
CH221KCH221K-U16Pwr:2 Bi:2 I:1 OC:1 No Industry Name property - BOM and procurement tools require this field
ESP32-S3-WROOM-1https://mou.sr/3vuXydS 356-EP32S3WROOM1N8R8U20241P:2 Pwr:2 Bi:36 I:1 Pin 1 (GND) at same location as pin 40 (GND); Pin 1 (GND) at same location as pin 41 (GND); Pin 40 (GND) at same location as pin 41 (GND); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Passive, GND=Passive]
PCM5100APCM5100A-U220P:5 Pwr:5 I:8 O:2 No Industry Name property - BOM and procurement tools require this field
TPA3118D2DAPRTPA3118D2DAPR-U333Pwr:11 Bi:1 I:12 O:9 Pin 31 (PVCC) at same location as pin 32 (PVCC); Pin 31 (PVCC) at same location as pin 19 (PVCC); Pin 31 (PVCC) at same location as pin 18 (PVCC); Pin 32 (PVCC) at same location as pin 19 (PVCC); Pin 32 (PVCC) at same location as pin 18 (PVCC); Pin 22 (GND) at same location as pin 25 (GND); Pin 22 (GND) at same location as pin 28 (GND); Pin 22 (GND) at same location as pin 9 (GND); Pin 19 (PVCC) at same location as pin 18 (PVCC); Pin 25 (GND) at same location as pin 28 (GND); Pin 25 (GND) at same location as pin 9 (GND); Pin 28 (GND) at same location as pin 9 (GND)

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Shielded Connector Model Quality

Shielded connectors with missing pin names0
All shielded connectors have proper pin names for EMC analysis.

15.4 Footprints and Other Models

Components with model data15
Component Model Assignments
RefDesIndustry NamePinsModel TypeModel
FL17442387014Footprint0_NRD_footprints:L_Wurth_WE-CMDC-7060
FL27442387014Footprint0_NRD_footprints:L_Wurth_WE-CMDC-7060
J1PJ-328A0-B5Footprint0_NRD_footprints:PJ-328A0-B
J201https://mou.sr/463mreb20Footprint_projectlib:USB_C_Receptacle_USB4500-03-0-A
SW1465M1111725016Footprint0_NRD_footprints:SW_Wurth_WS-PBTL_465M111172501
SW2465M1111725016Footprint0_NRD_footprints:SW_Wurth_WS-PBTL_465M111172501
SW3465M1111725016Footprint0_NRD_footprints:SW_Wurth_WS-PBTL_465M111172501
SW4465M1111725016Footprint0_NRD_footprints:SW_Wurth_WS-PBTL_465M111172501
SW6PLMG5-GH-V-T/R 7Footprint0_NRD_footprints:SW_PLMG5-GH
U1CH221K6FootprintPackage_TO_SOT_SMD:SOT-23-6
U2PCM5100A20FootprintPackage_SO:TSSOP-20_4.4x6.5mm_P0.65mm
U3TPA3118D2DAPR33FootprintPackage_SO:HTSSOP-32-1EP_6.1x11mm_P0.65mm_EP5.2x11mm_Mask4.11x4.36mm
U4BD33FC0FP-E23FootprintPackage_TO_SOT_SMD:TO-252-2
U5P7805-2000R-S3FootprintConverter_DCDC:Converter_DCDC_RECOM_R-78HB-0.5L_THT
U202https://mou.sr/3vuXydS41Footprint_projectlib:ESP32-S3-WROOM-1

15.5 IC Pin Electrical Properties

Unique IC models6
Total IC instances6
IC Library Models
Industry NameLibrary NameRefDesNotes
BD33FC0FP-E2BD33FC0FPU4
CH221KCH221KU1
https://mou.sr/3vuXydSESP32-S3-WROOM-1U202
P7805-2000R-SP7805-2000R-SU5
PCM5100APCM5100AU2
TPA3118D2DAPRTPA3118D2DAPRU3

15.5.1 BD33FC0FP (BD33FC0FP-E2)

PinPin NameElectricalNotes
1VCCPower In
2GNDPower In
3VOPower Out

15.5.2 CH221K (CH221K)

PinPin NameElectricalNotes
1VDDPower In
2GNDPower In
3PGOpen Collector
4CC1Bidirectional
5CC2Bidirectional
6CFGInput

15.5.3 ESP32-S3-WROOM-1 (https://mou.sr/3vuXydS)

PinPin NameElectricalNotes
1GNDPower In
23V3Power In
3ENInput
4GPIO4/TOUCH4/ADC1_CH3Bidirectional
5GPIO5/TOUCH5/ADC1_CH4Bidirectional
6GPIO6/TOUCH6/ADC1_CH5Bidirectional
7GPIO7/TOUCH7/ADC1_CH6Bidirectional
8GPIO15/U0RTS/ADC2_CH4/XTAL_32K_PBidirectional
9GPIO16/U0CTS/ADC2_CH5/XTAL_32K_NBidirectional
10GPIO17/U1TXD/ADC2_CH6Bidirectional
11GPIO18/U1RXD/ADC2_CH7/CLK_OUT3Bidirectional
12GPIO8/TOUCH8/ADC1_CH7/SUBSPICS1Bidirectional
13GPIO19/U1RTS/ADC2_CH8/CLK_OUT2/USB_D-Bidirectional
14GPIO20/U1CTS/ADC2_CH9/CLK_OUT1/USB_D+Bidirectional
15GPIO3/TOUCH3/ADC1_CH2Bidirectional
16GPIO46Bidirectional
17GPIO9/TOUCH9/ADC1_CH8/FSPIHD/SUBSPIHDBidirectional
18GPIO10/TOUCH10/ADC1_CH9/FSPICS0/FSPIIO4/SUBSPICS0Bidirectional
19GPIO11/TOUCH11/ADC2_CH0/FSPID/FSPIIO5/SUBSPIDBidirectional
20GPIO12/TOUCH12/ADC2_CH1/FSPICLK/FSPIIO6/SUBSPICLKBidirectional
21GPIO13/TOUCH13/ADC2_CH2/FSPIQ/FSPIIO7/SUBSPIQBidirectional
22GPIO14/TOUCH14/ADC2_CH3/FSPIWP/FSPIDQS/SUBSPIWPBidirectional
23GPIO21Bidirectional
24GPIO47/SPICLK_P/SUBSPICLK_P_DIFFBidirectional
25GPIO48/SPICLK_N/SUBSPICLK_N_DIFFBidirectional
26GPIO45Bidirectional
27GPIO0/BOOTBidirectional
28SPIIO6/GPIO35/FSPID/SUBSPIDBidirectional
29SPIIO7/GPIO36/FSPICLK/SUBSPICLKBidirectional
30SPIDQS/GPIO37/FSPIQ/SUBSPIQBidirectional
31GPIO38/FSPIWP/SUBSPIWPBidirectional
32MTCK/GPIO39/CLK_OUT3/SUBSPICS1Bidirectional
33MTDO/GPIO40/CLK_OUT2Bidirectional
34MTDI/GPIO41/CLK_OUT1Bidirectional
35MTMS/GPIO42Bidirectional
36U0RXD/GPIO44/CLK_OUT2Bidirectional
37U0TXD/GPIO43/CLK_OUT1Bidirectional
38GPIO2/TOUCH2/ADC1_CH1Bidirectional
39GPIO1/TOUCH1/ADC1_CH0Bidirectional
40GNDPassive
41GNDPassive

15.5.4 P7805-2000R-S (P7805-2000R-S)

PinPin NameElectricalNotes
1INPower In
2GNDPower In
3OUTPower Out

15.5.5 PCM5100A (PCM5100A)

PinPin NameElectricalNotes
1CPVDDPassive
2CAPPPassive
3CPGNDPower In
4CAPMPassive
5VNEGPassive
6OUTLOutput
7OUTROutput
8AVDDPower In
9AGNDPower In
10DEMPInput
11FLTInput
12SCKInput
13BCKInput
14DINInput
15LRCKInput
16FMTInput
17XSMTInput
18LDOOPassive
19DGNDPower In
20DVDDPower In

15.5.6 TPA3118D2DAPR (TPA3118D2DAPR)

PinPin NameElectricalNotes
1MODSELInput
2SDZInput
3FAULTZOutput
4RINPInput
5RINNInput
6PLIMITInput
7GVDDPower In
8GAIN/SLVInput
9GNDPower In
10LINPInput
11LINNInput
12MUTEInput
13AM2Input
14AM1Input
15AM0Input
16SYNCBidirectional
17AVCCPower In
18PVCCPower In
19PVCCPower In
20BSNLOutput
21OUTNLOutput
22GNDPower In
23OUTPLOutput
24BSPLOutput
25GNDPower In
26BSNROutput
27OUTNROutput
28GNDPower In
29OUTPROutput
30BSPROutput
31PVCCPower In
32PVCCPower In
33POWERPADPower In
Generated by Tomachie v3.84 2026-07-13 04:55:45
https://tomachie.com