11-10028cricket-node-hwB Design Analysis

Job 5a57b27e

1 Design Summary

out of 100

Depth of review, as a baseline: 415 verified datasheet parameters applied and 298 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

CCA_CODENAME	cricket-node
CCA_DESCRIPTION	cricket-node
CCA_PART_NUMBER	10-10028
CCA_TITLE	cricket-node
ENGINEER	E. Hughes
PCB_CODENAME	cricket-node
PCB_DATE	2025-05-27
PCB_DESCRIPTION	cricket-node
PCB_MIXDOWN	B
PCB_PART_NUMBER	11-10028
SCH_DATE	2025-05-27
STATUS	PROTOTYPE
Active Variant	B (variant 1)
Design Type	Flat (1 sheets)
Total Components	153
Total Pins	454
Total Nets	118
Total Test Points	27
Project Variants	1
Analyzed variant	B

Improve your score:

Improve fault coverage (opens/shorts) +4
3 life-cycle errors +1
Add test points on indicator signals +1
Improve schematic library models +1
Move component values to VALUE property +1
Reconcile part numbers with the values on the schematic +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1

Points deducted for open High/Medium AI findings:

0 High, 8 Medium -4

AI findings to review:

Power findings — 7 Medium, 1 Low, 22 Review
HSSI findings — 5 Review
Memory findings — 9 Review
Functional findings — 1 Low, 16 Review
EMC/ESD findings — 1 Medium, 1 Low, 10 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 9 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — - external non-volatile storage in both QSPI flash and SPI FRAM
- a digital-input Class D audio amplifier
- a LIN bus transceiver
- a USB 2.0 Type-C receptacle
- a wide-input synchronous buck converter with two current-limited load switches

External wiring terminates on six 3.5 mm pitch wire-pad fields:

- J1 and J2: 4-position, sized for 18 AWG
- J3: 6-position, 22 AWG
- J4: 4-position, 22 AWG
- J5: 3-position, 22 AWG
- J6: 2-position, 22 AWG

Processing and Wireless

U5 is the nRF52840-QIAA in the 73-pin aQFN package. It integrates:

- a 64 MHz Arm Cortex-M4 with FPU
- a 2.4 GHz radio supporting Bluetooth LE and IEEE 802.15.4, with −95 dBm sensitivity at 1 Mbps and up to +8 dBm transmit power
- a full-speed USB device controller
- a 12-bit, 200 ksps ADC

These figures are from the Nordic datasheet.

The device is clocked from two crystals:

- X1: a 32 MHz, 8 pF crystal with ±10 ppm tolerance and ±10 ppm stability over −30 °C to +85 °C (ECS datasheet, source: Tomachie).
- X2: a 32.768 kHz, 9 pF crystal with ±20 ppm tolerance for the low-frequency clock (NDK datasheet).

Memory

U12 is a 64 Mbit Macronix MX25R6435F serial flash connected to the nRF52840 QSPI controller in 4-bit mode. It operates from 1.65 V to 3.6 V and is rated for 100,000 erase/program cycles. In its default ultra-low-power mode it supports 33 MHz single-I/O and 8 MHz quad-I/O reads (Macronix datasheet).

U13 is an Infineon/Cypress FM25L16B 16 Kbit SPI FRAM. Its key ratings are:

- operation up to 20 MHz from 2.7 V to 3.6 V
- 10^14 write-cycle endurance
- 10-year data retention at 85 °C

These values are from the Cypress datasheet, source: Tomachie.

Audio

U14 is a Maxim MAX98357A filterless Class D mono amplifier. It accepts I2S, left-justified or 8-slot TDM audio without a master clock, at sample rates from 8 kHz to 96 kHz. It runs from a 2.5 V to 5.5 V supply and has five pin-selectable gain steps between 3 dB and 15 dB. Output power is 3.2 W into 4 Ω at 10% THD+N (Maxim datasheet).

LIN Interface

U2 is an NXP TJA1021T/20, the normal-slope variant, supporting up to 20 kBd. Its supply ratings are:

- VBAT static range of 5.5 V to 27 V
- VBAT absolute maximum of 40 V
- ±40 V bus-pin tolerance

It also provides Sleep and Standby modes with an INH output for regulator control (NXP datasheet, source: Tomachie).

D4 is a Nexperia PESD1IVN24 TVS with a 24 V standoff, and the board also fits PESD5V0S1BA TVS diodes.

USB Type-C

J8 is a vertical USB4145 USB 2.0 Type-C receptacle carrying two differential pairs. U15, a Nexperia PRTR5V0U2X low-capacitance rail-clamp array, provides ESD protection on the data lines.

Signal Conditioning and Control

- Level translation: four TI SN74LV1T34 single-bit buffers (U3, U4, U9, U10). Each runs from 1.6 V to 5.5 V and has a 5 V-tolerant reduced-threshold input (TI datasheet).
- Analog: U11 is a single 1.9 MHz TLV271 operational amplifier.
- Switching: small-signal switching uses BSS84 P-channel, 2N7002P N-channel and BSS138K N-channel MOSFETs.
- Power switching: Q6 is a 40 V, 6.4 A ZXMP4A16G P-channel MOSFET.

Power Architecture

U7 is a Diodes AP64352 synchronous buck converter. Its main characteristics are:

- 3.8 V to 40 V input, with a 42 V DC and 45 V (400 ms) absolute maximum
- 3.5 A continuous output
- 5 A typical peak current limit
- 0.8 V ±1% reference
- programmable switching frequency from 100 kHz to 2.2 MHz

These values are from the Diodes datasheet, source: Tomachie. U7 generates rail NetC14_1 through L4, a Sumida CDRH103R 6.8 µH inductor rated 3.60 A for temperature rise and 3.84 A for saturation.

U1 and U8 are Diodes AP22804AW5-7 load switches. The A suffix makes the enable active-high. Each operates from 2.7 V to 5.5 V and offers:

- 2.5 A continuous current with 50 mΩ typical on-resistance
- a 3.0 A typical current limit
- reverse-current blocking
- an open-drain fault flag

These values are from the Diodes datasheet.

The nRF52840 internal regulators produce two further rails:

- VDD, from the DCCH stage through L1
- NetC10_2, from the DCC stage through L3 and L2

The board also distributes +VIN, +VIN-PROTECT, +5v0 and +VBUS, all returned to a common GND.

Debug and User Interface

J7 is a TC2030 Tag-Connect footprint that provides SWD access to U5. Two indicator LEDs are fitted: red D15 and green D16. The design carries 27 test points.

Temperature Ratings

Most active devices are rated −40 °C to +85 °C:

- U5, U12, U13, U14
- U7 (ambient rating)
- U1 and U8

The SN74LV1T34 buffers extend to +125 °C.

Two parts set narrower limits:

- X1 is rated from −30 °C.
- U11 is the TLV271CW5-7 C-grade device, rated 0 °C to +70 °C (Diodes datasheet). It therefore sets the narrowest ambient range on the board.

1.2 Processed Sheets

#	Sheet Name
1	cricket-node-hw--top-level_B

1.3 Variants

#	Variant	DNP	ALT
0	Base (all components)	-	-
1	B (analyzed)	1	0

1.3.1 B

Status	RefDes	Part Type	Alt Part	Footprint
DNP	J9	CORTEX-DEBUG		FTSH-105-05-F-DV

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
3 of 35 unique footprints are IPC-7351B or IPC-7251	✓
31 SMT footprints do not follow IPC-7351B naming
1 footprints (connectors, specialty) — compliance unknown

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Ferrite beads on inductor designators (L5, L6): the Description indicates a ferrite bead, but the part uses an inductor (L) designator. Use an FB or FL designator. A ferrite value is an impedance at a frequency (e.g. 600R@100MHz), not an inductance.

No .bomdoc was supplied with this design. Highly recommended when a .bomdoc exists that it be included with the upload.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	28	C26, C27, C15, C8, C5, C14, C6, C11 (+20 more)	✓
Resistors	Values in VALUE or Resistance	38	R36, R37, R33, R9, R12, R11, R8, R10 (+30 more)	✓
Inductors	Values in VALUE or Inductance	3	L2, L1, L3	✓
Inductors	VALUE holds both the magnitude and a current rating (e.g. "6.8uH 3.84A"). Tomachie has already separated the two and uses the magnitude as the value, so the analysis and the AI read a clean value — the misinterpretation risk is low. This is a cleanliness note: move the current rating into a named Current property for downstream BOM/ICT/AOI tools and a self-describing schematic. (L4 currently has VALUE="6.8 uH 3.84A")	1	L4
Ferrite Beads	VALUE holds a part number, not an impedance. When the value is expressed as impedance@frequency (e.g. 600R@100MHz) and a separate MPN field carries the part number, the analysis is more deterministic. (L5 currently has VALUE="MPZ2012S221AT000")	2	L5, L6
Oscillators	Values in VALUE or Frequency	2	X1, X2	✓

2.1 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the MANUFACTURER part number. This check decodes the manufacturer part number and compares the two. A distributor catalogue number is a different thing and cannot be used here - an LCSC C-number or a Digi-Key -ND number identifies a stock item, it encodes no capacitance, voltage or tolerance, so there is nothing in it to check against. Where the two readings disagree both are shown and neither is assumed correct: if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose numbering scheme is not recognized are reported as not checked rather than passed.

Part Number	Decoded from Part Number	Stated on Schematic	What Differs	Count	Components	Status
CDRH103RNP-6R8NC-B Manufacturer Part Number / Sumida CDRH103RNP	6.8uH +/-30%	6.8uH 20%: L4	Tolerance: part number +/-30%, schematic 20%	1	L4	Mismatch
ERJ-3EKF1003V Manufacturer Part Number / Panasonic ERJ-3EK	100k +/-1% 0603	100kΩ ±1%: R1, R2, R8, R14, R19, R20, R21, R23 (+5 more)	Nothing - all stated values agree	13	R1, R2, R8, R14, R19, R20, R21, R23 (+5 more)	✓ Match
ERJ-3EKF1002V Manufacturer Part Number / Panasonic ERJ-3EK	10k +/-1% 0603	10kΩ ±1%: R3, R4, R11, R18, R25, R28	Nothing - all stated values agree	6	R3, R4, R11, R18, R25, R28	✓ Match
GCM155R71H104KE02D Manufacturer Part Number / Murata	100nF 50V +/-10% 0402	0.1µF 50V ±10%: C1, C2, C3, C4, C17, C18	Nothing - all stated values agree	6	C1, C2, C3, C4, C17, C18	✓ Match
ERJ-3EKF1000V Manufacturer Part Number / Panasonic ERJ-3EK	100R +/-1% 0603	100Ω ±1%: R9, R12, R27, R30, R32	Nothing - all stated values agree	5	R9, R12, R27, R30, R32	✓ Match
ERJ-3EKF1004V Manufacturer Part Number / Panasonic ERJ-3EK	1M +/-1% 0603	1MΩ ±1%: R5, R6, R10, R29	Nothing - all stated values agree	4	R5, R6, R10, R29	✓ Match
GCJ188R91H104KA01D Manufacturer Part Number / Murata	100nF 50V +/-10% 0603	0.1µF 50V ±10%: C5, C25, C26, C28	Nothing - all stated values agree	4	C5, C25, C26, C28	✓ Match
GCM1555C1H8R0DA16D Manufacturer Part Number / Murata	8pF 50V +/-0.5pF (+/-6.25%) 0402	8pF 50V ±0.5pF: C21, C22, C23, C24	Nothing - all stated values agree	4	C21, C22, C23, C24	✓ Match
EEE-FK1A151P Manufacturer Part Number / Panasonic	150uF 10V	150µF 10V ±20%: C12, C13, C14	Nothing - all stated values agree	3	C12, C13, C14	✓ Match
ERJ-6GEY0R00V Manufacturer Part Number / Panasonic ERJ-6GEY	0R 0805	0Ω Jumper: R13, R15, R16	Nothing - all stated values agree	3	R13, R15, R16	✓ Match
ERJ-3EKF3300V Manufacturer Part Number / Panasonic ERJ-3EK	330R +/-1% 0603	330Ω ±1%: R34, R35	Nothing - all stated values agree	2	R34, R35	✓ Match
ERJ-3EKF5101V Manufacturer Part Number / Panasonic ERJ-3EK	5.1k +/-1% 0603	5.1kΩ ±1%: R36, R37	Nothing - all stated values agree	2	R36, R37	✓ Match
GCM155R71C473KA37D Manufacturer Part Number / Murata	47nF 16V +/-10% 0402	0.047µF 16V ±10%: C9, C10	Nothing - all stated values agree	2	C9, C10	✓ Match
GCM21BR71C475KA73K Manufacturer Part Number / Murata	4.7uF 16V +/-10% 0805	4.7µF 16V ±10%: C6, C20	Nothing - all stated values agree	2	C6, C20	✓ Match
MLZ1608M100WTD25 Manufacturer Part Number / TDK MLZ1608M	10uH	10uH: L1, L3	Nothing - all stated values agree	2	L1, L3	✓ Match
MPZ2012S221AT000 Manufacturer Part Number / TDK	220R 0805	220@100MHz ±25%: L5, L6	Nothing - all stated values agree	2	L5, L6	✓ Match
EEE-FK1V101P Manufacturer Part Number / Panasonic	100uF 35V	100µF 35V ±20%: C7	Nothing - all stated values agree	1	C7	✓ Match
ERJ-3EKF1001V Manufacturer Part Number / Panasonic ERJ-3EK	1k +/-1% 0603	1kΩ ±1%: R7	Nothing - all stated values agree	1	R7	✓ Match
ERJ-3EKF4992V Manufacturer Part Number / Panasonic ERJ-3EK	49.9k +/-1% 0603	49.9kΩ ±1%: R22	Nothing - all stated values agree	1	R22	✓ Match
ERJ-3EKF5233V Manufacturer Part Number / Panasonic ERJ-3EK	523k +/-1% 0603	523kΩ ±1%: R17	Nothing - all stated values agree	1	R17	✓ Match
GCJ32EC71H106KA01L Manufacturer Part Number / Murata	10uF 50V +/-10% 1210	10µF 50V ±10%: C8	Nothing - all stated values agree	1	C8	✓ Match
GCM1555C1H101FA16D Manufacturer Part Number / Murata	100pF 50V +/-1% 0402	100pF 50V ±1%: C19	Nothing - all stated values agree	1	C19	✓ Match
GCM1555C1H102FA16D Manufacturer Part Number / Murata	1nF 50V +/-1% 0402	1000pF 50V ±1%: C16	Nothing - all stated values agree	1	C16	✓ Match
GCM188R71C105KA64J Manufacturer Part Number / Murata	1uF 16V +/-10% 0603	1µF 16V ±10%: C11	Nothing - all stated values agree	1	C11	✓ Match
GCM188R72A103KA37J Manufacturer Part Number / Murata	10nF 100V +/-10% 0603	10000pF 100V ±10%: C15	Nothing - all stated values agree	1	C15	✓ Match
GCM21BR71A106KE22K Manufacturer Part Number / Murata	10uF 10V +/-10% 0805	10µF 10V ±10%: C27	Nothing - all stated values agree	1	C27	✓ Match
+1 more part number(s) cross-checked, all agree			Nothing - all stated values agree	1		✓ Match

2.2 Capacitor Derating Check

Derating profile	industrial
Maximum ambient	not stated - temperature margins not evaluable
Checks performed	17
Over-specified	7

A capacitor is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Every other derating check - for capacitors and for every other part class - is applied by the AI analysis within its report sections.

Derating applied: 30% (capacitor_aluminum_voltage_pct = 70), 20% (capacitor_voltage_pct = 80)

Status key: ↓ = Over-specified ✓ = Adequately rated

Derating is how much is taken off a part's catalogue rating. What remains is the most of that rating the part may be worked at - a 16 V capacitor derated 15% has a maximum permitted value of 13.6 V - and the part is correctly sized when the voltage its position applies stays within it, taken at the worst case of the rail's stated range. This judges DC working voltage only; ripple and switching transients are not included in the compared value.

Review: 7 part(s) carry a voltage rating far higher than needed. A lower-cost part can be used, down to the voltage indicated.

Part Voltage Rating vs Design Voltage
RefDes	Net Name	Rated Voltage	Max Permitted	Design Voltage	% of Rating	Sufficient Rating	Status
C26	+5v0	50.00 V	40.00 V	5.00 V	10.0%	16.00 V	↓
C4	VDD	50.00 V	40.00 V	3.30 V	6.6%	16.00 V	↓
C3	VDD	50.00 V	40.00 V	3.30 V	6.6%	16.00 V	↓
C2	VDD	50.00 V	40.00 V	3.30 V	6.6%	16.00 V	↓
C1	VDD	50.00 V	40.00 V	3.30 V	6.6%	16.00 V	↓
C28	VDD	50.00 V	40.00 V	3.30 V	6.6%	16.00 V	↓
C25	VDD	50.00 V	40.00 V	3.30 V	6.6%	16.00 V	↓
C27	+5v0	10.00 V	8.00 V	5.00 V	50.0%		✓
C12	+5v0	10.00 V	7.00 V	5.00 V	50.0%		✓
C13	+5v0	10.00 V	7.00 V	5.00 V	50.0%		✓
C14	NetC14_1	10.00 V	7.00 V	4.98 V	49.8%		✓
C7	+VIN-PROTECT	35.00 V	24.50 V	16.00 V (worst case of +VIN)	45.7%		✓
C8	+VIN-PROTECT	50.00 V	40.00 V	16.00 V (worst case of +VIN)	32.0%		✓
C6	VDD	16.00 V	12.80 V	3.30 V	20.6%		✓
C11	NetC10_2	16.00 V	12.80 V	1.30 V	8.1%		✓
C10	NetC10_2	16.00 V	12.80 V	1.30 V	8.1%		✓
C9	NetC10_2	16.00 V	12.80 V	1.30 V	8.1%		✓

Derating Settings Used in This Analysis
Parameter	Value	Source	Applied
capacitor_voltage_pct	20% (80)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Checked in the table above (13 part(s))
capacitor_aluminum_voltage_pct	30% (70)	SD-18	Checked in the table above (4 part(s))
capacitor_tantalum_mno2_voltage_pct	60% (40)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	30% (70)	ECSS	Applied by the AI analysis where the rating is in evidence
capacitor_temperature_margin_c	20 °C	ECSS, EEE-INST-002, SD-18	Not evaluable - no maximum ambient is stated
capacitor_aluminum_temperature_margin_c	25 °C	SD-18	Not evaluable - no maximum ambient is stated
resistor_power_pct	45% (55)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	25% (75)	ECSS, EEE-INST-002	Applied by the AI analysis where the rating is in evidence
resistor_temperature_margin_c	25 °C	ECSS, EEE-INST-002, SD-18	Not evaluable - no maximum ambient is stated
inductor_temperature_margin_c	25 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
diode_reverse_voltage_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_average_forward_current_pct	35% (65)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_power_dissipation_pct	50% (50)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
zener_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18	Applied by the AI analysis where the rating is in evidence
zener_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
mosfet_vds_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_vgs_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_continuous_current_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
bjt_vce_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_continuous_current_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
regulator_input_voltage_pct	25% (75)	ECSS, EEE-INST-002	Applied by the AI analysis where the rating is in evidence
regulator_output_current_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_power_dissipation_pct	50% (50)	EEE-INST-002, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
ic_output_current_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_power_dissipation_pct	50% (50)	EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
connector_current_per_contact_pct	40% (60)	ECSS, EEE-INST-002, MIL-STD-1547B	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
connector_temperature_margin_c	20 °C	ECSS, EEE-INST-002, MIL-STD-1547B	Not evaluable - no maximum ambient is stated
tvs_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated

2.3 Part Lifecycle and Silicon Errata

Status as found on the manufacturer's website by the AI enrichment run, on the date shown; the page read is linked. Silicon errata: whether the manufacturer publishes an errata sheet for the part - its presence only. No errata document is read or analysed, and no action is implied by its existence.

Item	Lifecycle	Silicon errata	Status
Q6 (ZXMP4A16GTA)	Not Recommended for New Designs (NRND), as of 2026-08-27	—	High
U2 (TJA1021T/20/CM,118)	End of Life, as of 2026-09-28	None found on the manufacturer's website, as of 2026-09-28	High
U5 (NRF52840-QIAA-R)	Not recommended for new designs, as of 2026-09-28 No replacement named; the manufacturer's current ordering codes in the same package (QI aQFN™ 7 x 7 73 0.5): nRF52840-QIAA-F-R, nRF52840-QIAA-F-T, nRF52840-QIAA-F-R7. Confirm any silicon or build differences before switching.	Not determined	High
D3, D6, D7 (BAS16-7-F)	The lifecycle status (NRND / obsolete) for this part is indeterminate from the datasheet - please review	—	Review
X2 (NX3215SA-32.768K-STD-MUA-9)	The datasheet obtained for this part number is from NIHON DEMPA KOGYO CO., LTD. (NDK); the schematic names NDK. NIHON DEMPA KOGYO CO., LTD. (NDK)'s lifecycle status (NRND / obsolete) does not apply to the part as specified, so its status could not be determined	—	Review
D1 (BZX84C12-7-F), D2, D9, D11 (BZX84B16-7-F)	Lifecycle status (NRND / obsolete) could not be determined	—	Review
C1, C2, C3, C4, C17, C18 (GCM155R71H104KE02D)	No NRND / obsolete marking on the datasheet obtained 2026-09-28	—
C5, C25, C26, C28 (GCJ188R91H104KA01D)	No NRND / obsolete marking on the datasheet obtained 2026-09-28	—
C7 (EEE-FK1V101P)	No NRND / obsolete marking on the datasheet obtained 2026-08-27	—
C8 (GCJ32EC71H106KA01L)	Active, as of 2026-09-27	—
C9, C10 (GCM155R71C473KA37D)	No NRND / obsolete marking on the datasheet obtained 2026-09-28	—
C12, C13, C14 (EEE-FK1A151P)	No NRND / obsolete marking on the datasheet obtained 2026-08-27	—
C27 (GCM21BR71A106KE22K)	No NRND / obsolete marking on the datasheet obtained 2026-09-28	—
D4 (PESD1IVN24-AX)	Active, as of 2026-09-10	—
D5, D8, D12, D13, D14 (PESD5V0S1BA-115)	No NRND / obsolete marking on the datasheet obtained 2026-07-19	—
D15 (APT2012SURCK)	No NRND / obsolete marking on the datasheet obtained 2026-08-27	—
D16 (APT2012CGCK)	No NRND / obsolete marking on the datasheet obtained 2026-08-27	—
L1, L3 (MLZ1608M100WTD25)	Active, as of 2026-08-27	—
L2 (LQG15HS15NJ02D)	No NRND / obsolete marking on the datasheet obtained 2026-08-15	—
L4 (CDRH103RNP-6R8NC-B)	No NRND / obsolete marking on the datasheet obtained 2026-07-30	—
L5, L6 (MPZ2012S221AT000)	Active, as of 2026-08-27	—
Q1, Q2, Q7 (BSS84-7-F)	Active, as of 2026-08-27	—
Q3, Q4, Q8, Q9, Q10 (2N7002P,215)	No NRND / obsolete marking on the datasheet obtained 2026-07-22	—
Q5 (BSS138K)	No NRND / obsolete marking on the datasheet obtained 2026-07-22	—
U1, U8 (AP22804AW5-7)	No NRND / obsolete marking on the datasheet obtained 2026-07-22	Not determined
U7 (AP64352SP-13)	Active, as of 2026-09-28	—
U11 (TLV271CW5-7)	No NRND / obsolete marking on the datasheet obtained 2026-07-22	Not determined
U12 (MX25R6435FZNIL0)	No NRND / obsolete marking on the datasheet obtained 2026-07-17	Not determined
U13 (FM25L16B-GTR)	Active, as of 2026-09-27	None found on the manufacturer's website, as of 2026-09-27
U14 (MAX98357AETE+T)	No NRND / obsolete marking on the datasheet obtained 2026-07-22	Not determined
U15 (PRTR5V0U2X,215)	No NRND / obsolete marking on the datasheet obtained 2026-09-27	Not determined
X1 (ECS-320-8-37B-CKY-TR)	No NRND / obsolete marking on the datasheet obtained 2026-08-10	—

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

11 unconnected pin(s) found:

11 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
J1_2	2	Passive	CON-1-4	UNC_J1_2_2
J2_2	2	Passive	CON-1-4	UNC_J2_2_2
J7_6	SWO	Passive	TAG-CONNECT-SWD	-	No net
U5_A20	P1.10	Bidirectional	nRF52840-QIAA	P1.10
U5_AC11	P0.16	Bidirectional	nRF52840-QIAA	P0.16
U5_AC15	P0.19	Bidirectional	nRF52840-QIAA	P0.19
U5_AD12	P0.17	Bidirectional	nRF52840-QIAA	P0.17
U5_B15	P1.14	Bidirectional	nRF52840-QIAA	P1.14
U5_B17	P1.12	Bidirectional	nRF52840-QIAA	P1.12
U5_G1	P0.26	Bidirectional	nRF52840-QIAA	P0.26
U5_P2	P1.08	Bidirectional	nRF52840-QIAA	P1.08

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden pins of any electrical type stacked behind visible pins in the symbol.

Implied Net Connections
Component	Type	Pin	Net
U12	MX25R6435FZNIL0	9	GND

3.3 Open-Collector Pull-up Audit

Examined 0 candidate pin(s) on 0 net(s).

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation	Severity
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires that pin 1, the cathode, is on the left with the footprint at zero rotation. Tomachie will call out schematic-symbol problems that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, or a novice may wrongly indict a correct part — keeping consistent is the least-expensive path for everyone who handles the PCB.
D1 BZX84C12-7-F unidirectional · pin_names	Pin 1 (A): NetD1_1 Pin 3 (K): +VIN-PROTECT	Consistent
D2 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NetD2_1 Pin 3 (K): NetD2_3	Consistent
D3 BAS16-7-F unidirectional · pin_names	Pin 1 (A): NetD3_1 Pin 3 (K): NetD3_3	Consistent
D11 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NetD11_1 Pin 3 (K): +VIN-PROTECT	Consistent
D9 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NetD9_1 Pin 3 (K): +VIN-PROTECT	Consistent
D7 BAS16-7-F unidirectional · pin_names	Pin 1 (A): +VBUS Pin 3 (K): NetD6_3	Consistent
D6 BAS16-7-F unidirectional · pin_names	Pin 1 (A): +5v0 Pin 3 (K): NetD6_3	Consistent
D8 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): BTN0-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D5 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): NP0-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D4 PESD1IVN24-AX bidirectional · symbol_graphic	Pin 2 (C): LIN-IO Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D13 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): AUX1-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D12 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): NP1-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D14 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): CHG-LOOP Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information

3.5 Polarized Capacitor Orientation

Capacitor	Connections	Polarity	Severity
Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
C14 EEE-FK1A151P	Pin 1 (+): NetC14_1 Pin 2: GND
C12 EEE-FK1A151P	Pin 1 (+): +5v0 Pin 2: GND
C13 EEE-FK1A151P	Pin 1 (+): +5v0 Pin 2: GND
C7 EEE-FK1V101P	Pin 1 (+): +VIN-PROTECT Pin 2: GND

3.6 Checks Not Performed

Items this report did not check, with the reason. None of these is a finding against the design - an item that was not checked says nothing about it either way.

Note 3: The parameter these checks need is not yet in the datasheet model for the part, so they were not performed. This is a limitation of the analysis data, not a finding on the design.

Checks the AI review could not perform are listed at Review severity in each AI section's Findings table, each naming the input that was missing.

Item	Not checked	Notes
Capacitors and resistors (datasheets and parameter curves)	Datasheets for capacitors and resistors, and the parameter curves they carry (ripple current, derating against temperature, DC bias, a jumper's temperature rise), are obtained on the premium tier only. This standard-tier run reads a datasheet already on file and otherwise states no rating for these parts. The exception is a capacitor on a regulator's input or output rail: this tier obtains its datasheet and curves as well.
U11 (TLV271CW5-7)	Supply range and supply current of U11, whose VCC is fed from U5 P0.03 (supply voltage range and supply current)	See note 3
U5 (NRF52840-QIAA-R)	GPIO P0.03 source capability when supplying U11 VCC (GPIO output current limit)	See note 3
L1 (NRF52840-QIAA-R)	L1 saturation against REG0 peak inductor current (REG0 peak current and switching frequency)	See note 3
C18, C19 (NRF52840-QIAA-R)	DEC2 and DEC3 decoupling values against the reference circuitry (DEC2 and DEC3 reference capacitance)	See note 3
U15 (PRTR5V0U2X,215)	VCC-to-GND diode standoff and breakdown against the 5.5 V Type-C VBUS maximum (VRWM and V_BR(min))	See note 3
Q1 (TJA1021T/20/CM,118)	Q1 drain current including U2 VBAT supply current (VBAT supply current)	See note 3
C12, C13, C14 (EEE-FK1A151P)	Output-capacitor ESR contribution at the 2 MHz switching frequency (ESR at switching frequency)	See note 3
U5 (NRF52840-QIAA-R)	Need for series termination on the USB D+/D- lines (D+/D- driver output impedance)	See note 3
U12 (MX25R6435FZNIL0)	Local VCC bypass capacitance required at U12 (recommended VCC decoupling capacitance)	See note 3
U12 (MX25R6435FZNIL0)	Hardware reset timing on U12 pin RESET#/SIO3 (RESET# pulse width and recovery time)	See note 3
U11 (TLV271CW5-7)	U11 supply range against the 1.8-3.3 V VDD-domain level on P0.03 (supply voltage range (VDD minimum and maximum))	See note 3
U11 (TLV271CW5-7)	Supply current U5 P0.03 must source to power U11 (quiescent supply current)	See note 3
U11 (TLV271CW5-7)	Non-inverting input level of 0.98-1.48 V against the input common-mode range at the programmed VDD (input common-mode voltage range)	See note 3
U5 (NRF52840-QIAA-R)	C18 (0.1µF) on DEC2 and C19 (100pF) on DEC3 against Nordic reference circuitry (reference decoupling capacitance for DEC2 and DEC3)	See note 3
X1, X2 (ECS-320-8-37B-CKY-TR, NX3215SA-32.768K-STD-MUA-9)	Crystal ESR and drive level against the U5 HFXO and LFXO oscillator limits (nRF52840 HFXO/LFXO maximum crystal ESR and drive level)	See note 3
D4, U2 (TJA1021T/20/CM,118)	Compare the D4 42 V clamp level with the U2 LIN pin voltage limit (LIN pin absolute maximum voltage)	See note 3
D14, U5 (NRF52840-QIAA-R)	Compare the D14 14 V clamp level with the U5 P1.13/P1.15 GPIO limit (GPIO absolute maximum voltage)	See note 3
Part lifecycle (NRND / obsolete)	The lifecycle status (NRND / obsolete) for this part is indeterminate from the datasheet - please review

3.7 Summary

Total NO_ERC markers in design	24
Pins needing attention (warnings)	11
Pins for information only	0

4 Power Overview

Power rails	8
Power management sources identified	3

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Values Entered for This Analysis

These values were entered by the designer for this analysis; they are not read from the schematic. Every check in this report that needs one of them uses the figure shown here.

Kind	Entered for	Value entered
Power input	+VIN	12 V nominal, 10.8-16 V operating

4.2 Power Rail Analysis

+VBUS: 5 V assumed by USB convention, because a USB connector power pin is on this net. A design that negotiates a higher USB Power Delivery voltage must state the rail's actual nominal, minimum and maximum voltage — preferably recorded in the design itself, otherwise entered when prompted before the AI review starts. Until it is stated, the assumed 5 V is taken as the intended level.

Power Rails
Rail	Voltage	Source	Consumers
+VIN	12.00V	J5 External	Q6 (ZXMP4A16GTA)
+VIN-PROTECT	12.00V	Q6 ZXMP4A16GTA	U7 (AP64352SP-13)
+5v0	5.00V	U7 AP64352SP-13	U14 (MAX98357AETE+T), U3 (SN74LV1T34DBVR), U8 (AP22804AW5-7), U9 (SN74LV1T34DBVR), U1 (AP22804AW5-7)
+VBUS	5.00V	J8 External	U5 (NRF52840-QIAA-R), U15 (PRTR5V0U2X,215)
NetC14_1	4.98V	U7 AP64352SP-13	-
GND	-	J8 External	-
NetC10_2	1.3V	U5 NRF52840-QIAA-R	-
VDD	1.8-3.3V	U5 NRF52840-QIAA-R	U12 (MX25R6435FZNIL0), U13 (FM25L16B-GTR), U10 (SN74LV1T34DBVR), U4 (SN74LV1T34DBVR)

4.2.1 Rail Voltage Annotation

1 power input(s) into this board were identified - the supplies it takes in at a connector, a terminal or a module socket. Every part on and downstream of each one is judged against what it carries, so the analysis needs its full characterization: whether it is AC or DC, its nominal voltage, the band it operates over, and any level outside normal operation the design must survive.

The preferred way to state a rail's voltage is to record it in the design itself, where it travels with the schematic, survives every re-run, and can be read by anyone who opens the design: attach a Parameter Set directive to the rail carrying VOLTAGE_NOM, VOLTAGE_MIN and VOLTAGE_MAX properties, and VOLTAGE_EXCURSION_MAX for a survivable level outside normal operation.

Where the design does not state the voltage, you will be prompted to enter each rail's nominal, minimum and maximum operating voltage - and, where one exists, the survivable excursion level - before the AI review starts.

1 power input(s) into this board were identified and characterized as follows. These are the levels the analysis uses.

Rail	Required information
+VBUS	USB-C default values will be 5.00 V nominal, 4.75 V minimum, 5.50 V maximum.

Rail	Voltage supplied
+VIN	12.00 V nominal, 10.80-16.00 V operating

4.3 Regulator Enable Pull Resistors

3 regulator enable pin(s) examined for what drives them and which way they are pulled. 0 pulled toward the enabling level while a power output drives the net.

	Finding	Severity
RegulatorU1 [AP22804AW5-7] Enable pinU1_4 (EN) (enabled high) NetNP0-EN Driven byU5_B19 (P1.11) Pull-up- Pull-down-	Driven by the pins listed; no pull resistor is fitted.	Information
RegulatorU8 [AP22804AW5-7] Enable pinU8_4 (EN) (enabled high) NetNP1-EN Driven byU5_J1 (P0.04/AIN2) Pull-up- Pull-down-	Driven by the pins listed; no pull resistor is fitted.	Information
RegulatorU7 [AP64352SP-13] Enable pinU7_3 (EN) (enabled high) Net+VIN-PROTECT Driven by- Pull-up- Pull-down-	The enable is wired to +VIN-PROTECT; the regulator is always enabled.	Information

4.4 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.4.1 Power Tree Overview and Sequencing

AI-Assisted — Power reaches the board by two routes.

The harness input +VIN arrives on wire pads J1_1, J2_1 and J5_1. It is stated as 10.80-16.00 V, 12 V nominal. It passes through the P-channel reverse-polarity FET Q6 (ZXMP4A16GTA) to +VIN-PROTECT, which feeds four things:
- The AP64352 buck U7. Its output NetC14_1 joins +5v0 through the parallel 0Ω jumpers R15 and R16.
- Q1, a high-side switch to the TJA1021 VBAT pin on NetQ1_3.
- Q7, which switches the input-voltage sense network R26/R28 into U11.
- Q2, fed from U2's INH output rather than directly, which switches the LIN commander pull-up (D3, R7).

+5v0 supplies the MAX98357A amplifier U14, the buffers U3 and U9, and the indicator LEDs D15 and D16. It also feeds the two AP22804 load switches U1 and U8, which drive the off-board outputs +5v0-CH0 (J3_1) and +5v0-CH1 (J4_1). J3_6 carries +5v0 off the board directly.

The second route is USB Type-C VBUS on J8, which feeds U5_AD2 (VBUS). The nRF52840 high-voltage input U5_Y2 (VDDH) is diode-ORed through R13 (0Ω) from +5v0 via D6 and from +VBUS via D7. U5's internal regulators then make two rails:
- REG0 (U5_AB2 DCCH through L1 10uH) makes VDD. VDD is register-programmed between 1.8 and 3.3 V and feeds U12, U13, U4 and U10.
- REG1 (U5_B3 DCC through L3 10uH and L2 15nH) makes the 1.3 V node NetC10_2 on U5_B5/U5_E24 (DEC4/DEC6).

Sequence with +VIN applied:
- U7 starts by itself, because U7_3 (EN) is tied to +VIN-PROTECT.
- It soft-starts on C15 in about 2 ms.
- +5v0 powers U5 through D6.
- U5 raises VDD, and firmware then enables U1 (NP0-EN, P1.11), U8 (NP1-EN, P0.04), Q1 via Q4 (LIN-PWR), Q7 via Q8 (P0.03, which also supplies U11_5 VCC) and Q2 via Q3 (P1.06).

The gates of Q4, Q8 and Q3 are held off by 1MΩ pull-downs (R6, R29, R5). NP0-EN and NP1-EN have no pull resistor.

With USB alone, U5 runs from VBUS through D7, and the +5v0 domain and the LIN branches are unpowered. With both inputs present, VDDH is fed by whichever is higher: VBUS (up to 5.5 V) or +5v0 (4.85-5.12 V).

4.4.2 Input Protection and High-Side Switches (Q6, Q1, Q7, Q2)

AI-Assisted — Q6 (ZXMP4A16GTA) has its drain on +VIN and its source on +VIN-PROTECT. Its gate is pulled to GND by R18 (10kΩ), and D9 (BZX84B16) clamps gate to source. The orientation is correct: a reversed input finds the body diode blocking and VGS at zero.

Q6 VDS rating:
- Rating 40 V; derated 30% (mosfet_vds_pct = 70) it permits 28 V.
- 16 V is applied, so the part is correctly sized (Diodes Incorporated ZXMP4A16G datasheet).

Q6 VGS:
- There is no gate-source resistor, so the drive network places the full source voltage across gate-source: 16 V at the top of the band.
- D9 breaks down at 15.7-16.3 V at 5 mA (Diodes Incorporated BZX84B16 datasheet, source: Tomachie), so the applied VGS is 15.7-16 V.
- Q6 is a ±20 V VGS part. Derated 30% (mosfet_vgs_pct = 70) it permits 14 V, which the applied VGS exceeds.
- D9 itself is within Q6's absolute maximum (16.3 V against 20 V). It is simply set too high for the transistor it protects.
- The Q1 stage on this board uses a 12 V clamp (D1) and is the precedent.
- The trade: a BZX84C12 in the D9 position would draw about (16 − 11.4) V / 10kΩ = 0.46 mA through R18 at 16 V, against about 30 µA today.

Q1 (BSS84) stage:
- R1 (100kΩ) runs gate to source and R4 (10kΩ) runs to Q4's drain.
- The network alone would apply 16 × 101/(101 + 9.9) = 14.57 V (1% resistors at the corner that raises the gate-source drop).
- D1 (BZX84C12, 11.4-12.7 V; Diodes Incorporated datasheet) conducts and holds VGS at or below 12.7 V, inside the 14 V derated limit.
- D1 carries about 0.28 mA at 16 V.

Q7 (R24/R25) and Q2 (R2/R3, fed from U2's INH, which is at or below VBAT) use the same 100kΩ/10kΩ ratio:
- They apply 14.57 V gate-source at 16 V.
- Their 16 V clamps D11 and D2 (minimum 15.7 V) never conduct, so the drive network alone sets VGS above the 14 V derated limit of the BSS84 (Diodes Incorporated BSS84 datasheet, source: Tomachie).
- At the 12 V nominal input all three stages sit at 10.9 V. The exceedance exists only in the upper part of the stated band.

R7 (1kΩ, 0.1 W) is the commander pull-up resistor:
- With Q2 on and the LIN bus dominant at the TJA1021's 2.0 V maximum VOL (NXP TJA1021 datasheet, source: Tomachie), R7 carries (16 − 2.0 − 0.855) V / 1010 Ω = 13.0 mA.
- The 0.855 V is D3's BAS16 maximum forward drop at 10 mA; the 1010 Ω adds Q2's 10 Ω maximum on-resistance to R7.
- That dissipates 0.169 W, and more with the bus nearer 0 V.

4.4.3 AP64352 Buck Converter (U7)

AI-Assisted — Output voltage:
- The feedback divider R17 (523kΩ) / R23 (100kΩ) against the 0.8 V reference sets VOUT = 4.969 V.
- With VFB at 792-808 mV and 1% resistors, the output spans 4.85-5.12 V.
- Every +5v0 load is rated to at least 5.5 V.
- Output OVP trips at +10% (Diodes Incorporated AP64352 datasheet, source: Tomachie).

Switching frequency and timing:
- R22 (49.9kΩ) on U7_4 (RT/CLK) gives fSW = 100000/49.9 = 2004 kHz (RT = 100000/fSW, page 14). This is inside the 100 kHz-2.2 MHz valid range, and inside it even at the +6% spread-spectrum excursion (2.12 MHz).
- On-time at 16 V is D/fSW = 0.311/2.004 MHz = 155 ns, above the 100 ns typical minimum on-time.
- C15 (10000pF) gives the 2 ms typical soft-start (page 5). This equals, at nominal, the at-least-10 nF requirement (page 18).
- C5 (0.1µF X8R) matches the 100 nF bootstrap capacitor.
- U7_9 (EP) and U7_7 (GND) are on GND.

Input capacitance:
- C8 (10µF X7S 1210) falls to about 7.8 µF at 16 V and 8.7 µF at 12 V. This is read from Murata's DC bias characteristics graph, page 3 (Datasheet).
- The AP64352 datasheet calls a ceramic above 10 µF sufficient for most applications. That is a note, not a minimum.
- C7 (100µF 35V electrolytic, tan δ 0.12, ESR 0.16 Ω at 100 kHz) serves as bulk hold behind C8, where its higher ESR is acceptable.

Inductor L4 (6.8uH):
- The value is inside the recommended 2.2-10 µH.
- Ripple is 4.969 × (1 − 0.311) / (6.8 µH × 2.004 MHz) = 0.25 A p-p, rising to 0.36 A p-p at the −30% inductance tolerance.
- Its 3.84 A saturation current (Sumida CDRH103R datasheet) is below the high-side current limit of 4.25-5.75 A. The inductor saturates before the limit acts.

Output capacitance:
- U7's own output capacitor is C14 (150µF aluminium).
- Through the R15/R16 wire it is joined by C12 and C13 (150µF aluminium), C27 (10µF X7R) and C26.
- C27, the only ceramic, is about 5.4 µF at 5 V. This is read from Murata's Capacitance-DC Bias Characteristics graph, page 1 (Datasheet).
- The datasheet suggests 22-68 µF of ceramic for most applications and states no ESR limit.
- RMS inductor ripple is 0.36/√12 = 0.104 A, below C14's stated 240 mA even if C14 carried all of it.

Load and dissipation:
- The known +5v0 load is 21.4 mA: U14 3.35 mA, D15 9.15 mA, D16 8.69 mA, U1/U8 0.16 mA, U3/U9 0.02 mA and the divider 8 µA.
- It excludes the off-board loads on J3/J4 and U14's speaker current.
- At that load U7's dissipation is negligible.

4.4.4 +5v0 Distribution and Load Switches (U1, U8)

AI-Assisted — Operating range:
- U1 and U8 run from +5v0 at 4.85-5.12 V, inside the AP22804's 2.7-5.5 V operating range (6.0 V absolute maximum).
- Each limits at 2.7-3.3 A and is rated 2.5 A continuous (Diodes Incorporated AP22804 datasheet).

Coordination with U7:
- The two limits total 5.4-6.6 A, above U7's 3.5 A rating and L4's 3.84 A saturation current.
- A simultaneous heavy load on both channels is therefore limited by U7 and L4, not by the switches.
- The collapse of +5v0 then also removes U5's supply when VBUS is absent.

Enable and fault pins:
- U1_4 and U8_4 (EN) are driven only by U5 GPIOs P1.11 and P0.04.
- The datasheet states EN must not float and advises holding EN low while power is applied or removed.
- U1_3 and U8_3 (FLAG) are designer-NC. Over-current or over-temperature on the external channels is not reported to U5 and cannot be probed.

Output capacitance:
- Neither +5v0-CH0 nor +5v0-CH1 carries a capacitor.
- The datasheet's typical circuit shows 0.1 µF plus at least 10 µF on OUT, and 100 µF for hot-plug (pages 2 and 13).

+5v0 ceramic decoupling:
- C26 (0.1µF) and C27 (10µF) match U14's 0.1 µF plus 10 µF (Maxim MAX98357A datasheet, page 33).
- No ceramic remains for the 1 µF each that the AP22804 typical circuit places at U1 and U8 IN.
- None remains for the 0.1 µF each that the TI SN74LV1T34 datasheet (Datasheet) places at U3 and U9 VCC.

LED indicator path:
- D15 draws (4.969 − 1.95)/330 = 9.15 mA; D16 draws (4.969 − 2.1)/330 = 8.69 mA.
- Against the 30 mA rating, derated 35% (diode_if_pct = 65) to 19.5 mA, both pass.
- At the corner of +5v0 at 5.12 V and Vf 0.1 V below typical, D15 draws 9.9 mA and R34 dissipates 32 mW. R34/R35 are 0.1 W parts, derated 45% (resistor_power_pct = 55) to 55 mW: pass (Kingbright APT2012 datasheets, source: Tomachie).

4.4.5 nRF52840 Supply Inputs and Internal Regulators (U5)

AI-Assisted — VDDH (U5_Y2):
- VDDH sits on NetR13_1, which through R13 (0Ω) reaches NetD6_3.
- Neither net carries a capacitor.
- VDDH is the input of REG0, whose DCCH pin switches L1 and so draws pulsed current.
- The only upstream capacitance, C12/C13/C27 on +5v0, is behind D6. Nothing is behind D7, because +VBUS carries no capacitor at all.
- Nordic's reference circuitry fits 4.7 µF on VDDH in both supply configurations (Nordic nRF52840 datasheet).

VBUS (U5_AD2):
- The datasheet states the USB regulator input and output need to be decoupled for stability (page 87).
- DECUSB has C20 (4.7µF), but VBUS has none.

Voltage ranges:
- VBUS at its 5.5 V Type-C maximum meets U5's 5.5 V recommended maximum (5.8 V absolute).
- VDDH stays between about 4.0 V (+5v0 at 4.85 V less 0.855 V diode drop) and 5.5 V, inside 2.5-5.5 V.
- D6 and D7 see at most 5.5 V reverse against 100 V, derated 30% (diode_vrrm_pct = 70) to 70 V.
- Their forward current is at most REG0's output current: 13.8 mA known, against 215 mA derated 35% (diode_if_pct = 65) to 140 mA.

REG1 and decoupling pins:
- DEC4 and DEC6 are tied as required, with C11 (1µF) matching the 1.0 µF reference, plus C9/C10.
- DEC1 C17 (0.1µF) matches 100 nF.
- DEC5 C16 (1000pF) is near the 820 pF reference, which Nordic marks not required for build codes Fxx and later.

VDD decoupling:
- VDD carries C6 (4.7µF) and six 0.1µF parts.
- The reference fits 4.7 µF plus 1.0 µF plus 100 nF at each of U5's five VDD pins.
- VDD also feeds U12, U13, U4 and U10.

L1 (10uH) current:
- L1 saturates at 90 mA (TDK MLZ1608 datasheet).
- The known VDD load is 13.8 mA: U5 TX 4.8 mA at 0 dBm, U12 program 6 mA max, U13 3 mA max at 20 MHz, U4/U10 20 µA.
- That figure excludes U5 CPU current, TX above 0 dBm, and U11, which is supplied from U5_B13 (P0.03).

4.5 Observations

AI-Assisted — Four themes carry the medium findings.

Gate drive at the top of the input band. At 16 V, Q6, Q7 and Q2 exceed the 14 V derated gate-source limit. On Q6 the D9 clamp sets the level; on Q7 and Q2 the 100kΩ/10kΩ networks do. The board already has the fix in the Q1/D1 stage.

nRF52840 supply inputs. VDDH and VBUS are the nRF52840's supply inputs, and neither has a local capacitor. VDDH feeds a switching regulator through blocking diodes, and VBUS carries a datasheet decoupling requirement.

Buck inductor saturation. L4 saturates below U7's current limit. With two 2.5 A load switches downstream, an overload of +5v0 is foreseeable.

LIN pull-up resistor. R7 is a 0.1 W part dissipating 0.169 W whenever the LIN bus is held dominant at 16 V.

Unstated load currents. The +5v0, +5v0-CH0 and +5v0-CH1 loads leave the board and are not stated. U7 output current, L4 thermal current, Q6 drain current, R15/R16 and C8 ripple are therefore judged only against the 21.4 mA known load.

VDD programming. VDD is register-programmed, and U13 (FM25L16B, 2.7-3.6 V; Cypress datasheet, source: Tomachie) sets its floor at 2.7 V.

Input surge protection. No transient suppressor sits on +VIN or +VIN-PROTECT. The lowest-rated parts at the entry are Q6 (40 V VDS) and U7 (42 V DC, 45 V for 400 ms). A clamp just behind the harness fuse is needed if the installation admits surges beyond them.

C7 endurance. C7 is rated 2000 h at 105 °C (Panasonic EEE-FK datasheet, source: Tomachie). No maximum ambient is stated, so its life on this always-powered node cannot be estimated.

Other items:
- The switched LIN supply NetQ1_3 carries no capacitor.
- U11 is supplied from a GPIO.
- All electrolytic capacitors and power-path diodes are correctly oriented.

4.6 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.6.1	D9 (BZX84B16) gate clamp of Q6	+VIN-PROTECT	Q6 is carried over its derated gate limit at the 16 V band top. R18 (10kΩ) pulls the gate to GND with no gate-source resistor, so D9 sets VGS at 15.7-16 V. Q6 is a ±20 V VGS part, derated 30% (mosfet_vgs_pct = 70) to 14 V. D9 (16.3 V max) is within Q6's absolute maximum but is set too high for Q6. Fit a clamp whose maximum breakdown is at or below 14 V, e.g. BZX84C12 as used for D1 (12.7 V max). It draws about 0.46 mA through R18 at 16 V. Diodes Incorporated ZXMP4A16G and BZX84B16 datasheets.	Medium
4.6.2	Q7 (BSS84)	+VIN-PROTECT	R24 (100kΩ) gate-source and R25 (10kΩ) to Q8 apply 16 × 101/(101 + 9.9) = 14.57 V gate-source at 16 V. BSS84 ±20 V, derated 30% (mosfet_vgs_pct = 70), permits 14 V, so under that derating the part is unsuitable. D11 (minimum 15.7 V) never conducts. Remedy: raise R25 to 18kΩ (13.6 V worst case; 9.1 V at 10.8 V), or use a 12 V clamp as in the D1 precedent. Diodes Incorporated BSS84 datasheet.	Medium
4.6.3	Q2 (BSS84)	NetD2_3 (U2 INH)	R2 (100kΩ) gate-source and R3 (10kΩ) to Q3 apply 14.57 V gate-source with INH at 16 V, against a 14 V derated limit (mosfet_vgs_pct = 70). D2 (minimum 15.7 V) never conducts. Remedy: raise R3 to 18kΩ, or use a 12 V clamp as in the D1 precedent. Diodes Incorporated BSS84 datasheet.	Medium
4.6.4	L4 (6.8uH, CDRH103RNP-6R8NC-B)	NetC5_1 / NetC14_1	Isat is 3.84 A, below U7's high-side current limit of 4.25 A minimum and 5.75 A maximum (maximum end used). In an overload of +5v0 the inductor saturates before the limit acts. Fit a 6.8 µH inductor with Isat at or above 5.75 A. Sumida CDRH103R datasheet; AP64352 datasheet, source: Tomachie.	Medium
4.6.5	U5 VDDH (NRF52840-QIAA-R)	NetR13_1 / NetD6_3	No capacitor on U5_Y2 or its 0Ω far side. VDDH feeds REG0, which switches L1 and draws pulsed current. D6/D7 block the +5v0 bulk from acting as a bypass, and +VBUS has none. Add a local ceramic at U5_Y2; Nordic fits 4.7 µF on VDDH in both reference configurations. Nordic nRF52840 datasheet.	Medium
4.6.6	U5 VBUS (NRF52840-QIAA-R)	+VBUS	No capacitor on +VBUS. The datasheet states the USB regulator input and output need to be decoupled for stability (page 87). The reference fits 4.7 µF on VBUS; add it at U5_AD2. Nordic nRF52840 datasheet.	Medium
4.6.7	R7 (1kΩ 0.1 W)	LIN-IO / NetD3_3	With Q2 on and LIN dominant at 2.0 V max VOL at 16 V, R7 carries (16 − 2.0 − 0.855)/1010 = 13.0 mA and dissipates 0.169 W. R7 is a 0.1 W part, so it is not rated for a held-dominant bus. At 12 V (0.082 W) it exceeds the 0.055 W derated limit (resistor_power_pct = 55). Fit a 1kΩ resistor rated 0.5 W or more. NXP TJA1021 datasheet, source: Tomachie.	Medium
4.6.8	U1, U8 (AP22804AW5-7) current limit	+5v0	Each limits at 2.7-3.3 A, together 5.4-6.6 A. That is above U7's 3.5 A rating and L4's 3.84 A Isat, so U7 and L4, not the switches, limit a simultaneous overload on both channels. Diodes Incorporated AP22804 datasheet.	Low
4.6.9	Q6 (ZXMP4A16GTA)	+VIN-PROTECT	Q6 permits 4.6 A (Note 6), derated 40% (mosfet_id_pct = 60) to 2.76 A. The +VIN-PROTECT load current cannot be calculated. It can be stated with free text on the schematic page, as: "+VIN-PROTECT load current : <value>".	Review
4.6.10	+VIN entry (J1, J2, J5)	+VIN	No transient suppressor at the input. The lowest-rated parts are Q6 (40 V VDS) and U7 (42 V DC, 45 V for 400 ms). If the harness admits surges beyond these, a clamp is needed just downstream of the input fuse. Diodes Incorporated ZXMP4A16G datasheet; AP64352 datasheet, source: Tomachie.	Review
4.6.11	C15 (10000pF, U7 SS)	NetC15_2	Gives 2 ms soft-start (page 5). The datasheet requires at least 10 nF (page 18). The nominal value equals that minimum, and the ±10% tolerance corner is 9 nF. A 12 nF part keeps the minimum across tolerance. AP64352 datasheet, source: Tomachie.	Review
4.6.12	C8 (10µF 50V X7S, GCJ32EC71H106KA01L)	+VIN-PROTECT	About 7.8 µF effective at 16 V and 8.7 µF at 12 V (DC bias characteristics graph, page 3). The AP64352 datasheet calls a ceramic above 10 µF sufficient for most applications. A 22 µF 50 V ceramic restores that margin. Murata datasheet; AP64352 datasheet, source: Tomachie.	Review
4.6.13	C7 (100µF 35V, EEE-FK1V101P)	+VIN-PROTECT	Endurance is 2000 h at 105 °C on an always-powered node. The design states no maximum ambient, so life at the operating temperature cannot be estimated. Panasonic datasheet, source: Tomachie.	Review
4.6.14	C14, C12, C13, C27 (U7 output)	NetC14_1 / +5v0	The output is 450 µF of aluminium electrolytic plus C27, whose 10 µF is about 5.4 µF effective at 5 V. The datasheet suggests 22-68 µF of ceramic for most applications and states no ESR limits. A second 22 µF 10 V-class ceramic at NetC14_1 would meet it. Murata GCM21BR71A106KE22 datasheet; AP64352 datasheet, source: Tomachie.	Review
4.6.15	U7 output current / L4 thermal rating	+5v0	U7 is rated 3.5 A, derated 30% (regulator_output_current_pct = 70) to 2.45 A. L4 has a 3.60 A temperature-rise current. The known load is 21.4 mA, excluding the J3/J4 off-board loads and U14 speaker current. +5v0 load current cannot be calculated. It can be stated with free text on the schematic page, as: "+5v0 load current : <value>".	Review
4.6.16	R15, R16 (0Ω 0805)	NetC14_1 / +5v0	The parallel jumpers carry the whole +5v0 load, up to U7's 3.5 A. The 0805 convention of about 2 A each covers roughly 4 A, but no current rating is stated in the schematic data.	Review
4.6.17	C26 (0.1µF 50V, GCJ188R91H104KA01D)	+5v0	Over-specified: rated 50 V, derated to 40 V (capacitor_voltage_pct = 80), with 5 V applied. A 16 V part serves.	Review
4.6.18	+5v0 decoupling	+5v0	C26 and C27 match U14's 0.1 µF plus 10 µF (Maxim MAX98357A datasheet, page 33). No ceramic remains for the 1 µF each that the AP22804 typical circuit places at U1/U8 IN, or the 0.1 µF each that the TI SN74LV1T34 datasheet places at U3/U9 VCC.	Review
4.6.19	U1, U8 (AP22804AW5-7)	+5v0-CH0 / +5v0-CH1	No capacitor on OUT. The datasheet typical circuit shows 0.1 µF plus at least 10 µF, and 100 µF for hot-plug (pages 2 and 13). Diodes Incorporated AP22804 datasheet.	Review
4.6.20	U1, U8 (AP22804AW5-7) EN	NP0-EN / NP1-EN	EN is driven only by U5 P1.11 and P0.04, with no pull resistor. The datasheet says EN must not float and should be held low while power is applied or removed. Check U5's pin state from power-up until firmware drives these pins. A pull-down to GND on each net holds the switch off until then. Diodes Incorporated AP22804 datasheet.	Review
4.6.21	U1, U8 (AP22804AW5-7) FLAG	+5v0-CH0 / +5v0-CH1	U1_3 and U8_3 (open-drain FLAG) are unconnected. Channel over-current and over-temperature are neither reported nor probeable. Route FLAG to a spare U5 input with a pull-up to VDD, or at minimum to a test point.	Review
4.6.22	U1 (AP22804AW5-7)	+5v0-CH0	Rated 2.5 A, derated 30% (regulator_output_current_pct = 70) to 1.75 A. +5v0-CH0 load current cannot be calculated. It can be stated with free text on the schematic page, as: "+5v0-CH0 load current : <value>".	Review
4.6.23	U8 (AP22804AW5-7)	+5v0-CH1	Rated 2.5 A, derated 30% (regulator_output_current_pct = 70) to 1.75 A. +5v0-CH1 load current cannot be calculated. It can be stated with free text on the schematic page, as: "+5v0-CH1 load current : <value>".	Review
4.6.24	C16 (1000pF, U5 DEC5)	NetC16_2	The reference fits 820 pF, marked not required for build codes Fxx and later. 1000pF is fitted. Nordic nRF52840 datasheet.	Review
4.6.25	VDD decoupling (U5 REG0 output)	VDD	C6 4.7µF plus six 0.1µF parts serve five U5 VDD pins and U4, U10, U12 and U13. The reference fits 4.7 µF plus 1.0 µF plus 100 nF at each VDD pin. The 1.0 µF, and 100 nF for three of the nine supply pins, are absent. Nordic nRF52840 datasheet.	Review
4.6.26	L1 (10uH, MLZ1608M100WTD25)	NetL1_2 / VDD	Isat is 90 mA. The known VDD load is 13.8 mA, excluding U5 CPU current and TX above 0 dBm. Check that REG0's peak inductor current stays below 90 mA. TDK MLZ1608 datasheet.	Review
4.6.27	VDD (U5 REG0) with U13 (FM25L16B)	VDD	VDD is register-set between 1.8 and 3.3 V. U13 requires 2.7-3.6 V, so REG0 must be programmed to at least 2.7 V. U12 (1.65-3.6 V), U4/U10 (1.6-5.5 V) and U5 (1.7-3.6 V) accept the whole range. Cypress FM25L16B datasheet, source: Tomachie.	Review
4.6.28	C1, C2, C3, C4 (0.1µF 50V, GCM155R71H104KE02D)	VDD	Over-specified: rated 50 V, derated to 40 V (capacitor_voltage_pct = 80), with 3.3 V applied. A 16 V part serves.	Review
4.6.29	C25, C28 (0.1µF 50V, GCJ188R91H104KA01D)	VDD	Over-specified: rated 50 V, derated to 40 V (capacitor_voltage_pct = 80), with 3.3 V applied. A 16 V part serves.	Review
4.6.30	NetQ1_3 (Q1 drain, U2 VBAT)	NetQ1_3	The switched LIN supply carries no capacitor. The TJA1021 typical application draws VBAT bypass capacitors without a stated value (page 16). NXP TJA1021 datasheet, source: Tomachie.	Review
4.6.31	Q1 (BSS84) with D1 (BZX84C12)	+VIN-PROTECT	The network would apply 14.57 V. D1 clamps VGS at or below 12.7 V, inside the 14 V derated limit (mosfet_vgs_pct = 70). D1 carries about 0.28 mA at 16 V. Diodes Incorporated BZX84C12 and BSS84 datasheets.	✓
4.6.32	Q6 (ZXMP4A16GTA)	+VIN / +VIN-PROTECT	Reverse-polarity orientation is correct (drain on +VIN, source on the load). VDS rating 40 V, derated 30% (mosfet_vds_pct = 70), permits 28 V; 16 V is applied, so the part is correctly sized. Diodes Incorporated ZXMP4A16G datasheet.	✓
4.6.33	U7 (AP64352SP-13)	+VIN-PROTECT	VIN absolute maximum 42 V, derated 25% (regulator_input_voltage_pct = 75), permits 31.5 V. The recommended range is 3.8-40 V. 16 V is applied. Pass. Diodes Incorporated AP64352 datasheet, source: Tomachie.	✓
4.6.34	U7 feedback R17/R23	NetC14_1 / +5v0	VOUT 4.969 V; 4.85-5.12 V across VFB 792-808 mV and 1% resistors. This is inside the 5.5 V maximum of every +5v0 load. AP64352 datasheet, source: Tomachie.	✓
4.6.35	U7 R22 (49.9kΩ)	NetR22_1	fSW = 100000/49.9 = 2004 kHz (page 14), within 100 kHz-2.2 MHz. On-time at 16 V is 155 ns, above the 100 ns typical minimum. AP64352 datasheet, source: Tomachie.	✓
4.6.36	U7 EN	+VIN-PROTECT	U7_3 is tied to VIN, which the datasheet pin table permits for automatic start-up; EN absolute maximum is 42 V. AP64352 datasheet, source: Tomachie.	✓
4.6.37	C5 (0.1µF, U7 BST)	NetC5_2 / NetC5_1	Matches the 100 nF BST-SW bootstrap capacitor. AP64352 datasheet, source: Tomachie.	✓
4.6.38	U7 GND / EP	GND	U7_7 and U7_9 (EP) are on GND, as the datasheet requires. AP64352 datasheet, source: Tomachie.	✓
4.6.39	C7 (100µF 35V, EEE-FK1V101P)	+VIN-PROTECT	Bulk-hold role behind the ceramic C8, where tan δ 0.12 / ESR 0.16 Ω at 100 kHz is acceptable. Rated 35 V, derated 30% (capacitor_aluminum_voltage_pct = 70), permits 24.5 V; 16 V is applied. Correctly sized. Panasonic datasheet, source: Tomachie.	✓
4.6.40	C14 (150µF 10V, EEE-FK1A151P)	NetC14_1	RMS inductor ripple is at most 0.104 A (0.36 A p-p at −30% L), below the stated 240 mA ripple rating. Rated 10 V, derated 30% (capacitor_aluminum_voltage_pct = 70), permits 7 V; 4.984 V is applied. Pass.	✓
4.6.41	L4 (6.8uH)	NetC5_1 / NetC14_1	6.8 µH is inside the recommended 2.2-10 µH. Ripple is 0.25 A p-p nominal and 0.36 A p-p at −30%. DCR 27 mΩ typical / 35 mΩ maximum, against under 30 mΩ recommended for efficiency. Sumida CDRH103R datasheet.	✓
4.6.42	C12, C13 (150µF 10V, EEE-FK1A151P)	+5v0	Rated 10 V, derated 30% (capacitor_aluminum_voltage_pct = 70), permits 7 V; 5 V is applied. Correctly sized. Polarity: pin 1 on the rail.	✓
4.6.43	C27 (10µF 10V, GCM21BR71A106KE22K)	+5v0	Rated 10 V, derated 20% (capacitor_voltage_pct = 80), permits 8 V; 5 V is applied. Pass.	✓
4.6.44	U1, U8 (AP22804AW5-7) VIN	+5v0	4.85-5.12 V is inside the 2.7-5.5 V operating range (6.0 V absolute maximum). Diodes Incorporated AP22804 datasheet.	✓
4.6.45	D15, D16 with R34, R35	+5v0	D15 draws 9.15 mA and D16 8.69 mA; D15 reaches 9.9 mA at the worst corner. The 30 mA rating derated 35% (diode_if_pct = 65) permits 19.5 mA. R34 dissipates 32 mW against 55 mW (resistor_power_pct = 55). Pass. Kingbright datasheets, source: Tomachie.	✓
4.6.46	U5 VBUS / VDDH range	+VBUS / NetR13_1	VBUS at the 5.5 V Type-C maximum meets the 5.5 V recommended maximum (5.8 V absolute). VDDH at 4.0-5.5 V is inside 2.5-5.5 V. Nordic nRF52840 datasheet; USB Type-C specification.	✓
4.6.47	D6, D7 (BAS16)	NetD6_3	Orientation is consistent for OR-ing. Reverse voltage is at most 5.5 V against 100 V derated to 70 V (diode_vrrm_pct = 70). Forward current is at most 13.8 mA known against 140 mA (diode_if_pct = 65). Nexperia BAS16 datasheet.	✓
4.6.48	U5 DEC4/DEC6, DECUSB, DEC1	NetC10_2 / NetC20_2 / NetC17_2	DEC4 and DEC6 are tied as required, with C11 1µF matching 1.0 µF. C20 4.7µF matches the DECUSB 4.7 µF reference. C17 0.1µF matches the DEC1 100 nF reference. Nordic nRF52840 datasheet.	✓
4.6.49	C6 (4.7µF 16V), C9, C10 (0.047µF 16V), C11 (1µF 16V)	VDD / NetC10_2	Rated 16 V, derated 20% (capacitor_voltage_pct = 80), permits 12.8 V. 3.3 V is applied to C6 and 1.3 V to C9, C10 and C11. Pass.	✓
4.6.50	D3 (BAS16)	NetD3_1 / NetD3_3	Forward current is at most about 15 mA against 140 mA (diode_if_pct = 65). Reverse voltage is at most 16 V against 70 V (diode_vrrm_pct = 70). Orientation is consistent. Nexperia BAS16 datasheet.	✓
4.6.51	C7, C12, C13, C14 polarity	+VIN-PROTECT / +5v0 / NetC14_1	Pin 1 (positive) is on the rail and pin 2 on GND for every aluminium capacitor. Orientation is correct.	✓

4.7 Citations

AI-Assisted —

References
2N7002P (Nexperia) — datasheet, cited pages 2,3 assets.nexperia.com/documents/data-sheet/2N7002P.pdf
AP22804 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/AP22804.pdf
BAS16 (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/BAS16.pdf
BSS138K (onsemi) — datasheet, cited pages 1,2 www.onsemi.com/download/data-sheet/pdf/bss138k-d.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
CDRH103RNP-6R8NC-B (Sumida) — datasheet products.sumida.com/products/pdf/CDRH103R.pdf
GCJ188R91H104KA01D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/24e69d76f59b023f447ab5...
GCJ32EC71H106KA01L (Murata Manufacturing Co., Ltd.) — datasheet datasheets.b-cdn.net/files/GCJ32EC71H106KA01L-Murata-data...
GCM155R71C473KA37 (Murata Manufacturing Co., Ltd.) — datasheet static.chipdip.ru/lib/891/DOC031891133.pdf
GCM155R71H104KE02D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/b385f789d1f9e1d12e8261...
GCM21BR71A106KE22K (Murata) — datasheet ds.murata.co.jp/simserve/characteristics?ModeType=normal&...
LQG15HS15NJ02 (Murata Manufacturing Co., Ltd.) — datasheet, cited pages 1,4,5 pim.murata.com/asset/pim4/inductor/JELF243B-0010_PDF_INDU...
MAX98357A (Maxim Integrated) — datasheet www.mouser.com/datasheet/2/256/MAX98357A-MAX98357B-271244...
MLZ1608M100WTD25 (TDK) — datasheet product.tdk.com/info/en/catalog/datasheets/inductor_autom...
MPZ2012S221AT000 (TDK) — datasheet product.tdk.com/info/en/catalog/datasheets/beads_commerci...
MX25R6435F (Ultra Low Power Mode - Default) (Macronix International Co., Ltd.) — datasheet, cited pages 1 www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R64...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
NX3215SA-32.768K-STD-MUA-9 (NIHON DEMPA KOGYO CO., LTD. (NDK)) — datasheet, cited pages 1 pdf.datasheet.live/datasheets-1/ndk/NX3215SA-32.768K-STD-...
SN74LV1T34 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/sn74lv1t34.pdf
TLV271 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/TLV27x.pdf
ZXMP4A16G (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/ZXMP4A16G.pdf

5 Connector Pinouts

Total connectors

5.1 J1 WIREPAD-18AWG-4X-3.5MM

J1 - WIREPAD-18AWG-4X-3.5MM (WIREPAD-18AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	NC
3	3	LIN-IO
4	4	GND

5.2 J2 WIREPAD-18AWG-4X-3.5MM

J2 - WIREPAD-18AWG-4X-3.5MM (WIREPAD-18AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	NC
3	3	LIN-IO
4	4	GND

5.3 J3 WIREPAD-22AWG-6X-3.5MM

J3 - WIREPAD-22AWG-6X-3.5MM (WIREPAD-22AWG-6X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+5v0-CH0
2	2	NP0-EXT
3	3	GND
4	4	GND
5	5	BTN0-EXT
6	6	+5v0

5.4 J4 WIREPAD-22AWG-4X-3.5MM

J4 - WIREPAD-22AWG-4X-3.5MM (WIREPAD-22AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+5v0-CH1
2	2	NP1-EXT
3	3	AUX1-EXT
4	4	GND

5.5 J5 WIREPAD-22AWG-3X-3.5MM

J5 - WIREPAD-22AWG-3X-3.5MM (WIREPAD-22AWG-3X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	CHG-LOOP
3	3	GND

5.6 J6 WIREPAD-22AWG-2X-3.5MM

J6 - WIREPAD-22AWG-2X-3.5MM (WIREPAD-22AWG-2X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	SP-
2	2	SP+

5.7 J7 TAG-CONNECT-SWD (SWD)

J7 - TAG-CONNECT-SWD (SWD)
Pin	Pin Name	Net	Notes
1	VCC	VDD
2	SWDIO	SWDIO
3	RST	RESET
4	SWDCLK	SWDCLK
5	GND	GND
6	SWO	NC

5.8 J8 USB4145-03-0230-C

J8 - USB4145-03-0230-C
Pin	Pin Name	Net	Notes
A1	GND_A	GND
A4	VBUS_A	+VBUS
A5	CC1	CC1
A6	DP1	USB-DEVICE-D_P
A7	DN1	USB-DEVICE-D_N
A8	SBU1	NC
A9	VBUS_A	+VBUS
A12	GND_A	GND
B1	GND_B	GND
B4	VBUS_B	+VBUS
B5	CC2	CC2
B6	DP2	USB-DEVICE-D_P
B7	DN2	USB-DEVICE-D_N
B8	SBU2	NC
B9	VBUS_B	+VBUS
B12	GND_B	GND
S1	SHIELD	GND
S2	SHIELD	GND
S3	SHIELD	GND
S4	SHIELD	GND

5.9 J9 20021121-00010T4LF

J9 - 20021121-00010T4LF (20021121-00010T4LF)
Pin	Pin Name	Net	Notes
1	VCC	NC
2	SWDIO/TMS	NC
3	GND	NC
4	SWDCLK/TCK	NC
5	GND	NC
6	SWO/TDO	NC
7	KEY	NC
8	TDI	NC
9	GND_DETECT	NC
10	RST	NC

6 Indicator Documentation

2 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D16	LED-GREEN	Green	D16_C, R35_2	cricket-node-hw--top-level_B.SchDoc	LOW = On; R35 (330Ω); A:+5v0 K:D16_C, R35_2
D15	LED-RED	Red	D15_C, R34_2	cricket-node-hw--top-level_B.SchDoc	LOW = On; R34 (330Ω); A:+5v0 K:D15_C, R34_2

6.2 Indicator Testability

0 of 2 indicators have test coverage.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D16	Direct	D16_C, R35_2	Design Warning: Test point needed on D16_C, R35_2. Drive LOW to turn on LED D16.
D15	Direct	D15_C, R34_2	Design Warning: Test point needed on D15_C, R34_2. Drive LOW to turn on LED D15.

7 Switch Documentation

No switches or push buttons found in design.

8 Low-Speed Serial Interfaces (LSSI)

Detected: 2 SWD | 1 partial

8.1 SWD

SWD -> U5
Topology: Access (J7, TP21, TP22) » Targets (U5)
Signal	Net Name	Connector	Test Point	Target Pin
SWCLK	SWDCLK	J7_4	TP22_1	U5_AA24 (SWDCLK)
SWDIO	SWDIO	J7_2	TP21_1	U5_AC24 (SWDIO)
NRST	RESET	J7_3	TP23_1	U5_AC13 (P0.18/RESET)
Target	Industry Type	Description
U5	nRF52840-QIAA	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN

SWD -> U5
Topology: Access (J7, TP21, TP22) » Targets (U5)
Signal	Net Name	Connector	Test Point
SWCLK	SWDCLK	J7	TP22_1
SWDIO	SWDIO	J7	TP21_1
NRST	RESET	J7	TP23_1
Target	Industry Type	Description
U5	nRF52840-QIAA	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN

8.2 Signals That Failed to Trace

These signals appear to be part of LSSI interfaces based on naming patterns, but their endpoints could not be fully traced. The signals were found on test points or connectors but the target IC could not be determined. This may indicate daisy-chained connections (TDO->TDI), signals through resistors, or non-standard naming.

Failed Interface Trace Details
Interface	Target	Found Signals	Trace Path	Missing Signals	Connector	Test Point
JTAG	J9	TCK, TDI, TDO, TMS	-	NOT_ROUTED	J9	(none)

8.3 LSSI DFT Analysis

4 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

Missing Test Points
Signal	Net Name	Connector	Interface
TCK		J9_4	JTAG -> J9
TDI		J9_8	JTAG -> J9
TDO		J9_6	JTAG -> J9
TMS		J9_2	JTAG -> J9

9 High-Speed Serial Interfaces (HSSI)

2 differential pair(s)

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 1 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
USB-DEVICE-D_P/N	USB

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Device Port (U5 to J8)

AI-Assisted — The only differential interface on the board is the nRF52840 (U5) USB 2.0 device port. USB-DEVICE-D_P runs from U5 pin D+ (AD6) to J8_A6 (DP1) and J8_B6 (DP2). USB-DEVICE-D_N runs from U5 pin D- (AD4) to J8_A7 (DN1) and J8_B7 (DN2). J8 is a USB4145-03-0230-C vertical Type-C receptacle. Both D+ contacts and both D- contacts are tied together, which the USB Type-C specification requires so that a USB 2.0 port works with either plug orientation. CC1 and CC2 each carry a 5.1kΩ pull-down to GND (R37, R36). That is the Rd value the Type-C specification assigns to a sink, so a source advertises vSafe5V and the board draws only default USB power.

The pair has no series capacitor. USB 2.0 is DC-coupled and requires none.

The pair has no series resistor or external termination. The U5 driver impedance is not in the datasheet data supplied, so the need for series termination is not assessed.

USB 2.0 specifies a 90 Ω differential impedance. Both nets are grouped as a differential USB pair, but no impedance value is attached to the pair.

TP3 and TP4 add a test pad to each line. At USB 2.0 signalling rates a pad placed directly on the trace is a negligible stub.

The Type-C receptacle is an impedance-controlled connector and suits this interface. The decoupling of U5 VBUS and DECUSB is covered in the power review and is not repeated here.

9.2.2 USB ESD Protection (U15)

AI-Assisted — U15 (PRTR5V0U2X) protects both data lines: U15_2 is on D+, U15_3 on D-, U15_4 (VCC) on +VBUS and U15_1 on GND. Its 5.5 V maximum standoff is adequate for the 5.5 V vSafe5V maximum on a Type-C VBUS (Nexperia datasheet, source: Tomachie; USB Type-C specification). The VCC-pin breakdown is 6-9 V.

The I/O-to-ground capacitance is 1 pF typical and 1.5 pF maximum at 1 MHz and 25 °C. The I/O-to-I/O capacitance is 0.6 pF typical. Both are small loads for USB 2.0 signalling and are symmetric across the pair.

The datasheet notes that the internal VCC diode keeps signal-line protection available when VBUS is absent, so an unpowered cable insertion is still protected. U15 is rated for ±8 kV IEC 61000-4-2 contact discharge. U5 (aQFN73) is rated at 2 kV HBM, Class 2 (Nordic datasheet).

U15 clamps at 17 V typical at 2.5 A (8/20 µs). U5 states no transient rating for D+ and D-. The ordering of protection at J8 belongs to the EMC/ESD review.

9.3 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.3.1	USB (J8, U5)	USB 2.0	USB-DEVICE-D_P and USB-DEVICE-D_N are grouped as a differential pair, but no impedance value is assigned. Assign the 90 Ω differential class the USB 2.0 specification requires.	Review
9.3.2	USB ESD (U15, U5)	USB 2.0	U15 clamps at 17 V typical at 2.5 A, 8/20 µs (Nexperia datasheet, source: Tomachie). Check that U5 D+ and D- are rated for this waveform. The U5 transient rating was not available at report generation time.	Review
9.3.3	Radio (U5 ANT)	2.4 GHz BLE / 802.15.4	No antenna matching network (reference: 4.7 nH series, 0.8 pF and 0.5 pF shunt) and no antenna is shown at U5 pin ANT, so the radio is unusable as built. Nordic nRF52840 datasheet	Review
9.3.4	HFXO (X1)	32 MHz reference	C21 and C22 (8pF) give 4 pF in series, implying 4 pF of stray for the 8 pF crystal. Nordic's reference circuit shows 12 pF per pin, and the reference crystal load is not stated. X1 has no datasheet entry.	Review
9.3.5	LFXO (X2)	32.768 kHz	C23 and C24 (8pF) give 4 pF in series, implying 5 pF of stray for the 9 pF crystal. Nordic's reference circuit shows 12 pF per pin. X2 has no datasheet entry.	Review
9.3.6	USB (J8, U5)	USB 2.0	D+ and D- are each tied to both J8 contact rows (A6/B6, A7/B7), which makes the port orientation-independent as the USB Type-C specification requires.	✓
9.3.7	USB (J8)	USB Type-C	R36 and R37 (5.1kΩ, CC2/CC1 to GND) are the sink Rd value set by the USB Type-C specification.	✓
9.3.8	USB (J8, U5)	USB 2.0	No series capacitor on either line. USB 2.0 is DC-coupled and requires none.	✓
9.3.9	USB (J8)	USB 2.0	The USB4145-03-0230-C Type-C receptacle is an impedance-controlled connector suited to USB 2.0.	✓
9.3.10	USB (TP3, TP4)	USB 2.0	The test pads on D+ and D- are negligible stubs at USB 2.0 rates when placed directly on the trace.	✓
9.3.11	USB ESD (U15)	USB 2.0	A 5.5 V standoff is adequate for a 5.5 V maximum rail (vSafe5V). Nexperia PRTR5V0U2X datasheet, source: Tomachie; USB Type-C specification.	✓
9.3.12	USB ESD (U15)	USB 2.0	I/O capacitance is 1 pF typical and 1.5 pF maximum to GND, with 0.6 pF between the lines, which is acceptable loading for USB 2.0. Nexperia datasheet, source: Tomachie.	✓

9.4 Citations

AI-Assisted —

References
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 U12 QSPI

U12 (MX25R6435FZNIL0) - QSPI [4-bit data]
Signal	Pin Name	Pin #	Net Name	Test Point
CLOCK	SCLK	6	QSPI-SCLK / P0.14	-
DATA_0	SIO0/SI	5	P0.21 / QSPI-D0	-
DATA_1	SIO1/SO	2	QSPI-D1 / P0.22	-
DATA_2	SIO2/WP	3	QSPI-D2 / P0.20	-
DATA_3	SIO3/RESET	7	QSPI-D3 / P0.23	-
SELECT	CS	1	QSPI-CS / P0.24	-
DESIGN_WARNING: Test points would be needed on P0.21, QSPI-CS, QSPI-D1, QSPI-D2, QSPI-D3 and QSPI-SCLK if direct on-board programming is desired over indirect programming via the FPGA/CPU (U5)
U12 is in-system programmable via U5 (nRF52840-QIAA) over SWD. A debug probe on the SWD port loads a programming routine into U5, which then drives the memory bus

10.2 AI-Assisted Analysis

10.2.1 QSPI Flash (U12, MX25R6435F)

AI-Assisted — U12 is a Macronix MX25R6435F 64 Mbit serial NOR flash in its default Ultra Low Power mode. It connects point-to-point to U5 (nRF52840) over a four-bit QSPI bus with no other device on the six nets. The connections are: QSPI-SCLK to U5 P0.14; QSPI-CS to U5 P0.24; P0.21 (QSPI-D0) to U12 pin SIO0/SI; QSPI-D1 to P0.22; QSPI-D2 to P0.20 on U12 pin SIO2/WP#; and QSPI-D3 to P0.23 on U12 pin SIO3/RESET#. None of the six nets has a series resistor, pull-up or test point.

Clock ceilings (Macronix datasheet, page 68): in Ultra Low Power mode, single-I/O READ and FAST_READ run up to 33 MHz, but 2READ/DREAD and 4READ/QREAD are limited to 8 MHz. Quad-read throughput therefore depends on firmware. It can either clock the controller at 8 MHz or below, or switch U12 to its high-performance mode through a status/configuration register write; the datasheet gives that mode switch 20 µs maximum.

At 33 MHz the clock half-period is 15.2 ns. U12 tCLQV is 12 ns maximum at 30 pF, which leaves 3.2 ns for the trace flight time and U5's input setup. At 8 MHz quad the half-period is 62.5 ns and timing is not critical.

Power and ground: U12 VCC is on VDD, which is register-set between 1.8 V and 3.3 V. This is inside U12's 1.65-3.6 V range and below its 4.0 V absolute maximum. U12_4 and U12_9 (exposed pad) are on GND. U12 and U5 share the VDD domain, so no level translation is needed and no pin can exceed U12's VCC+0.5 V or U5's VDD+0.3 V input limits.

Power-up: U12 accepts a VCC ramp of up to 500000 µs/V. U5 requires VDD to rise from 0 V to 1.7 V within 60 ms (Nordic datasheet, page 410), so U5 sets the tighter ramp limit.

Sources: Macronix datasheet; Nordic datasheet

10.3 Observations

AI-Assisted — U12's three control-capable pins (CS#, WP#/SIO2 and RESET#/SIO3) carry no pull resistor. They are defined only while U5 actively drives P0.24, P0.20 and P0.23. Through U5 reset, boot and any low-power state in which the QSPI pins are released, all three float.

A floating RESET# can reset U12 or leave it in an indeterminate state. A floating CS# can select it during power-up. U12 requires 800 µs (tVSL) from VCC reaching its minimum before the device is operational, and its write-inhibit threshold is 1.1-1.5 V. Pull-ups from QSPI-CS and QSPI-D3 to VDD would hold U12 deselected and out of reset whenever U5 is not driving; a pull-up on QSPI-D2 would do the same for WP#. Whether U5's own pin states make these unnecessary is for the designer to check against the firmware's pin configuration.

The lack of series termination is acceptable at the 8 MHz quad ceiling. At 33 MHz single-I/O the 3.2 ns read margin makes trace length a layout concern. Source-series pads on QSPI-SCLK are a low-cost option to keep open during placement.

None of the six QSPI nets carries a test point. In-circuit access to U12 is therefore only through U5, for example over the SWD port on J7. Firmware-driven flash programming and verification over that port is the available structural test path; direct net probing of U12 is not available.

10.4 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.4.1	QSPI flash (U12)	QSPI clock	In default Ultra Low Power mode U12 is limited to 8 MHz for 4READ/QREAD and 33 MHz for single-I/O reads (page 68). Check that U5's QSPI clock is set to 8 MHz or below for quad reads, or that firmware switches U12 to high-performance mode first. The U5 QSPI maximum clock value was not available at report generation time.	Review
10.4.2	QSPI flash (U12)	QSPI read timing	U12 tCLQV is 12 ns maximum at 30 pF (page 68), leaving 3.2 ns of the 15.2 ns half-period at 33 MHz. Check that U5's QSPI input setup time plus trace delay fits within 3.2 ns. The U5 input setup value was not available at report generation time.	Review
10.4.3	QSPI flash (U12)	Logic levels	U12 VIH is 0.8×VCC minimum and VOH is VCC-0.2 V at -100 µA (page 66); both parts are on VDD. Check that U5 GPIO VOH meets 0.8×VDD. The U5 VOH value was not available at report generation time.	Review
10.4.4	QSPI flash (U12)	Power-up sequencing	U12 CS# must not be asserted until 800 µs (tVSL) after VCC reaches its minimum (page 74). Check that U5's first access to U12 occurs at least 800 µs after VDD is valid.	Review
10.4.5	QSPI flash (U12)	CS# pull-up	QSPI-CS has no pull-up to VDD, so U12 CS# floats whenever U5 P0.24 is not driven (reset, boot). Check whether a pull-up from QSPI-CS to VDD is needed to hold U12 deselected.	Review
10.4.6	QSPI flash (U12)	RESET#/SIO3 pull-up	QSPI-D3 has no pull-up, so U12 RESET# floats whenever U5 P0.23 is not driven. Check whether a pull-up from QSPI-D3 to VDD is needed to hold U12 out of reset.	Review
10.4.7	QSPI flash (U12)	WP#/SIO2 pull-up	QSPI-D2 has no pull-up, so U12 WP# floats whenever U5 P0.20 is not driven. Check whether a pull-up from QSPI-D2 to VDD is needed to define WP# outside quad transfers.	Review
10.4.8	QSPI flash (U12)	Series termination	None of the six QSPI nets has a series resistor. This is adequate at the 8 MHz quad ceiling; at 33 MHz single-I/O the trace length set in layout decides the margin.	Review
10.4.9	QSPI flash (U12)	Test access	None of the six QSPI nets carries a test point. U12 is reachable only through U5 firmware, for example via the SWD port on J7.	Review
10.4.10	QSPI flash (U12, MX25R6435FZNIL0)	QSPI to U5	All four data lines (SIO0-SIO3), SCLK and CS# are wired point-to-point to U5 GPIOs, with no shared or conflicting bus members. Macronix datasheet.	✓
10.4.11	QSPI flash (U12)	VCC supply	VDD is register-set between 1.8 V and 3.3 V, inside U12's 1.65-3.6 V range and below its 4.0 V absolute maximum. Macronix datasheet, page 64.	✓
10.4.12	QSPI flash (U12)	Ground	U12_4 GND and U12_9 exposed pad are on GND. Macronix datasheet.	✓
10.4.13	QSPI flash (U12)	Pin absolute maximum	Both devices are supplied from VDD, so no QSPI level exceeds U12's VCC+0.5 V or U5's VDD+0.3 V pin limits. Macronix and Nordic datasheets.	✓
10.4.14	QSPI flash (U12)	VCC ramp	U12 permits up to 500000 µs/V (page 72). U5 requires VDD from 0 V to 1.7 V within 60 ms (Nordic datasheet, page 410), so any ramp that meets U5 also meets U12.	✓
10.4.15	QSPI flash (U12)	Operating temperature	U12 is rated -40 to 85 °C, matching U5's -40 to 85 °C. Macronix and Nordic datasheets.	✓

10.5 Citations

AI-Assisted —

References
MX25R6435F (Ultra Low Power Mode - Default) (Macronix International Co., Ltd.) — datasheet, cited pages 1 www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R64...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...

11 Functional Analysis

11 device(s) to review across 6 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
U2	COMMUNICATION	TJA1021T/20/CM,118	1 Transceiver Full Duplex 1 SOIC-8 LIN Transceivers ROHS	-	-
U11	DEVICE	TLV271CW5-7	Single 1pA 2V/us 1.9MHz SOT-25 Operational Amplifier ROHS	-	-
U13	DEVICE	FM25L16B-GTR	16Kbit 20MHz SPI SOIC-8 FRAM ROHS	-	-
U14	DEVICE	MAX98357AETE+T	Monaural 3.2Wx2@4O TQFN-16-EP(3x3) Audio Amplifiers ROHS	-	-
X1	DEVICE	ECS-320-8-37B-CKY-TR	32MHz 8pF ±10ppm SMD2016-4P	-	-
X2	DEVICE	NX3215SA-32.768K-STD-MUA-9	32.768kHz 9pF ±20ppm SMD3215-2P	-	-
D2	DIODE	BZX84B16-7-F	DIODE ZENER 16V 300MW SOT23	-	-
D3	DIODE	BAS16-7-F	DIODE SWITCHING 75V 200MA SOT23	-	-
U15	Prot.	PRTR5V0U2X,215	6V Unidirectional 5.5V SOT-143 ESD and Surge Protection (TVS/ESD) ROHS	-	-
Q2	Trans.	BSS84-7-F	MOSFET P-CH 50V 130MA SOT23-3	-	-
U5	WIRELESS	NRF52840-QIAA-R	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN	SWD	-

11.1 Reset-Time Strap Configuration

Each device below takes part of its start-up configuration from resistors the board fits on pins it samples at reset. Every setting is resolved against that device's own datasheet tables - the combination this board selects, and whether the datasheet marks that combination reserved or invalid.

RefDes	Configuration	This Board Selects	Read From	Status
U5	NRF52840-QIAA-R	No reset-time straps: probe: the pages show no reset-time configuration		✓

11.2 Functional Analysis

11.2.1 LIN Transceiver U2 with Commander Termination Q2, D2 and D3

AI-Assisted — U2 VBAT (pin 7) is fed from +VIN-PROTECT through the P-channel switch Q1. Q1 is turned on by Q4 from U5 P0.27 (LIN-PWR), so firmware can remove power from the transceiver entirely. The 10.8-16 V band sits inside the TJA1021 static VBAT range of 5.5-27 V and well below its 40 V absolute maximum. The unbypassed VBAT node is already reported in the power review.

WAKE_N (pin 3) is pulled up to the switched VBAT by R8 (100kΩ) and pulled low by Q5 (BSS138K) from U5 P0.28. This matches the datasheet arrangement of a pull-up to VBAT with a local wake switch to GND. RXD (pin 1) is open-drain and has R11 (10kΩ) to VDD. That pull-up draws 0.33 mA, well inside the 1.5 mA minimum IOL at 0.4 V. TXD and SLP_N are driven directly by U5 P0.29 and P0.31, and both have a 2 V minimum VIH.

The commander termination runs from INH (pin 8) through Q2, then D3 (BAS16), then R7 (1kΩ) to LIN-IO. This is the datasheet commander arrangement of a 1 kΩ resistor in series with a diode between INH and LIN. Q2 adds firmware selection of commander or responder through Q3 from U5 P1.06. At a held dominant bus, INH sources about 13 mA.

D2 (BZX84B16) is Q2's gate-source clamp, with its anode on the gate and its cathode on the source. Its maximum breakdown of 16.3 V is below Q2's ±20 V VGS rating. The divider alone keeps VGS below D2's 15.7 V minimum, so D2 carries only leakage. The 14.57 V gate-source stress on Q2 is reported in the power review, as are D3's ratings and R7's dissipation.

The 1MΩ pull-downs R5, R6 and R10 give a defined reset state: U2 unpowered, commander termination off, and no local wake.

11.2.2 Input Voltage Sense Buffer U11

AI-Assisted — U11 (TLV271) is a unity-gain follower. Its output drives U5 P0.02/AIN0 (net V-C) and is tied back to its inverting input. Its non-inverting input takes the R26 (100kΩ) / R28 (10kΩ) divider, which is fed from +VIN-PROTECT through Q7. Q7 is switched by Q8 from U5 P0.03.

U11 VCC (pin 5) is the same net, P0.03, so the GPIO that enables the divider also powers the op-amp. The input therefore never carries voltage while U11 is unpowered. With the divider switched off, NetR26_1 returns to 0 V through R28.

The divider ratio is 0.0909. That gives 0.982 V at 10.8 V and 1.455 V at 16 V. At the 1% tolerance corner (R28 high, R26 low) the level is 1.481 V. This is below the lowest VDD setting of 1.8 V, so the AIN0 level stays inside the U5 pin limit of VDD + 0.3 V. The 9.1 kΩ source impedance into a 1 pA-class input gives negligible error.

No capacitor sits on U11 VCC, and the GPIO supplies the amplifier's quiescent current directly. The output drives AIN0 with no series resistor. The TLV271 datasheet (Datasheet, page 13) requires a series resistor of at least 20 Ω when the capacitive load exceeds 100 pF.

The fitted TLV271CW5-7 is the C grade, specified for 0 to +70 °C. That is the narrowest temperature grade among the devices in this section. U5 is rated -40 to 85 °C. The design states no ambient range.

11.2.3 SPI FRAM U13

AI-Assisted — U13 (FM25L16B) is wired point-to-point to U5. FRAM-CS goes to P1.02, FRAM-CLK to P0.25, FRAM-SDI to P1.04 and FRAM-SDO to P1.03. Both parts run from VDD, so the 0.7 x VDD VIH and the VDD - 0.8 V VOH at 2 mA are referenced to the same rail. The requirement that REG0 be programmed to at least 2.7 V for U13 is carried by the power review.

HOLD (pin 7) is pulled to VDD by R38 (100kΩ), and WP (pin 3) by R14 (100kΩ). This satisfies the datasheet rule that unused HOLD and WP be tied to VDD (Infineon/Cypress FM25L16B datasheet, page 3, source: Tomachie).

With WP held permanently HIGH, the Status Register is never hardware write-protected. Firmware setting WPEN = 1 therefore gains nothing, and the block-protect bits stay writable by any errant write. Spare U5 pins exist to drive WP; P0.26, for example, is unconnected.

FRAM-CS has no pull-up. The FM25L16B datasheet in hand states no internal pull-up on CS. What holds U13 deselected during U5 reset and boot therefore rests on the reset state of U5 P1.02. The datasheet also requires 1 ms (tPU) from VDD reaching its minimum to the first CS LOW.

11.2.4 Class-D Audio Amplifier U14

AI-Assisted — U14 (MAX98357A) VDD pins 7 and 8 are on +5v0. The power review sets that rail at 4.85-5.12 V, inside the 2.5-5.5 V supply range. GND pins 3, 11 and 15 and the exposed pad (pin 17) are on GND. Decoupling by C26 and C27 is already passed in the power review.

BCLK, LRCLK and DIN come directly from U5 P0.07, P1.09 and P0.12. Their VIH is 1.3 V minimum, VIL 0.6 V maximum and absolute maximum 6 V, so a VDD-domain drive at any setting from 1.8 V to 3.3 V meets them.

GAIN_SLOT is tied to GND through R33 (100kΩ). The datasheet states table gives 15 dB (14.4-15.6 dB) for this connection.

SD_MODE is driven directly by U5 P0.05, with no external resistor. Below the B0 trip (0.16 V typical) the part shuts down. The internal 100 kΩ pull-down holds it there while the GPIO is undriven, which gives a click-free default. A push-pull HIGH at VDD is above the B2 trip (1.5 V maximum) and selects the left channel only. Summed (L+R)/2 mono would need a pull-up of RLARGE = 222.2 x 3.3 - 100 = 633 kΩ at a 3.3 V VDD. The right channel alone would need RSMALL = 210 kΩ.

OUTP and OUTN reach the speaker pads J6 through the ferrite beads L6 and L5 (MPZ2012S221AT000). The beads are rated 3 A, 40 mΩ maximum DCR. The amplifier's current limit is 2.8 A typical. The speaker is off-board and its impedance is not stated, so the output current and U14 dissipation against the 1666 mW TQFN rating at 70 °C cannot be computed.

11.2.5 USB ESD Array U15

AI-Assisted — U15 (PRTR5V0U2X) has IO1 (pin 2) on USB-DEVICE-D_P and IO2 (pin 3) on USB-DEVICE-D_N, at the point where both J8 contact rows join. VCC (pin 4) is on +VBUS and GND (pin 1) on GND. The Nexperia datasheet (source: Tomachie) describes the VCC diode as preventing charge-up of the supply, with signal protection that holds even without supply. Tying VCC to +VBUS is therefore the intended connection. Standoff, capacitance and clamping level are reported in the signal-integrity review, and cascade order is left to the EMC/ESD section.

11.2.6 nRF52840 U5 and Crystals X1, X2

AI-Assisted — The DCC output (U5_B3) feeds DEC4/DEC6 through L3 (10uH, MLZ1608M100WTD25) and then L2 (15nH, LQG15HS15NJ02D). L2 is rated 450 mA Irms and its self-resonance is at least 2500 MHz. L3's saturation current is 90 mA. The unconnected ANT pin, the VDD, VDDH and VBUS decoupling, and the DEC capacitors are covered by the power and signal-integrity reviews.

SWD is complete. SWDIO, SWDCLK and P0.18/RESET reach J7 pins 2, 4 and 3, with TP21, TP22 and TP23. J7_1 is on VDD and J7_5 on GND.

The board-ID straps are R21, R20 and R19 (100kΩ each), pulling P0.09, P0.10 and P0.11 to GND, so all three read low. P0.09 and P0.10 are also the NFC1/NFC2 pins, so reading them relies on firmware configuring them as GPIO.

The 2N7002P gates Q3, Q4, Q8, Q9 and Q10 are driven from VDD-domain GPIOs. Their VGS(th) is 1.1-2.4 V at 250 µA (Nexperia, Datasheet).

X1 (ECS-320-8-37B-CKY-TR) on XC1/XC2 is a 32 MHz fundamental unit, inside its 16-50 MHz range. Its maximum ESR is 50 Ω and its maximum drive level 100 µW. It has 8 pF CL and is specified for -30 to +85 °C, which is narrower at the cold end than U5's -40 °C (ECS datasheet, source: Tomachie). Its load capacitors are covered by the signal-integrity review.

X2 (NX3215SA-32.768K-STD-MUA-9) on XL1/XL2 has a 9.0 pF CL, 70 kΩ maximum ESR and 0.5 µW maximum drive level, and is rated -40 to +85 °C. The load seen across X2 through ground is CL = 8 x 8 / (8 + 8) + C_stray = 4 pF + C_stray. That implies 5 pF of stray, against Nordic's 12 pF-per-pin reference.

11.2.7 2.4 GHz Radio and Reference Clocks

AI-Assisted — Nordic's reference circuit feeds U5 pin ANT through a 4.7 nH series inductor with 0.8 pF and 0.5 pF shunt capacitors. No part of those values is fitted on this board, and no antenna or RF connector is shown on U5 pin ANT. As drawn, the Bluetooth / 802.15.4 radio cannot be used. This is taken as a deliberate build option.

U5 must run from its 32 MHz crystal oscillator for USB operation. X1 (ECS-320-8-37B-CKY-TR, 32MHz, 8pF, ±10ppm) sits on XC1/XC2 with C22 and C21 (8pF C0G each), which present 4 pF in series. For the stated 8 pF load, this implies 4 pF of stray capacitance. X2 (NX3215SA, 32.768kHz, 9pF) sits on U5 pins XL1/XL2 with C24 and C23 (8pF), which present 4 pF in series and imply 5 pF of stray.

Nordic's reference circuit fits 12 pF per pin on both oscillators. That is an application-circuit value, and the load of the crystal Nordic drew is not stated, so the reference stray cannot be derived. With no datasheet for X1 or X2, both load choices remain design judgements rather than verified values.

11.3 Findings

AI-Assisted —

#	Device	Finding	Severity
11.3.1	FM25L16B-GTR (U13)	WP is held permanently HIGH by R14 (100kΩ) to VDD, and no controller can lower it. The Status Register block-protect bits can never be hardware write-protected. Drive WP from a spare U5 GPIO (for example P0.26, currently unconnected) so firmware can hold WP LOW with WPEN = 1, protecting the block-protect settings, and raise it only to change them. Infineon/Cypress FM25L16B datasheet, source: Tomachie.	Low
11.3.2	TJA1021T/20/CM,118 (U2)	TXD and SLP_N are driven directly from U5 P0.29 and P0.31 and need a 2 V minimum VIH. VDD is a 1.8-3.3 V programmable range, so it must be programmed above 2 V; the 2.7 V needed by U13 already covers this. Check that U5 VOH at the programmed VDD meets 2 V. NXP TJA1021 datasheet, source: Tomachie.	Review
11.3.3	TJA1021T/20/CM,118 (U2)	TXD has no external pull-up to the controller supply. The datasheet adds one to tell remote wake from local wake in Standby (page 8). Without it, U5 cannot identify the wake source from TXD. NXP TJA1021 datasheet, source: Tomachie.	Review
11.3.4	TJA1021T/20/CM,118 (U2)	LIN-IO carries no bus capacitor to GND. The typical application shows 1 nF for a commander or 220 pF for a responder, normally set by the vehicle maker (page 16). This is an application-circuit figure, not a minimum. NXP TJA1021 datasheet, source: Tomachie.	Review
11.3.5	2N7002P,215 (Q3, Q4, Q8, Q9, Q10)	VGS(th) is 1.1-2.4 V at 250 µA, and the gates are driven from GPIOs in the 1.8-3.3 V VDD range. VDD must be programmed above 2.4 V for these switches to turn on reliably; the 2.7 V needed by U13 covers this. VDS at most 16 V against 60 V derated 30% (mosfet_vds_pct = 70) to 42 V. VGS at most 3.3 V against 20 V derated 30% (mosfet_vgs_pct = 70) to 14 V. Nexperia datasheet.	Review
11.3.6	TLV271CW5-7 (U11)	U11 VCC is powered from U5 P0.03, which also drives the Q8 gate, and carries no bypass capacitor. The GPIO supplies the amplifier's supply current directly. A local capacitor would add load to that GPIO, so the designer should decide whether one is needed.	Review
11.3.7	TLV271CW5-7 (U11)	The output drives AIN0 with no series resistor. The datasheet requires at least 20 Ω when the capacitive load exceeds 100 pF (page 13). Check that the AIN0 input and trace capacitance stay below 100 pF. The U5 AIN input capacitance value was not available at report generation time. Diodes Incorporated datasheet.	Review
11.3.8	TLV271CW5-7 (U11)	The C-grade part is specified for 0 to +70 °C, against -40 to 85 °C for U5, X2 and U13. The design states no ambient range; an I-grade part covers -40 to +125 °C. Diodes Incorporated datasheet.	Review
11.3.9	FM25L16B-GTR (U13)	FRAM-CS has no external pull-up, and no internal pull-up is stated for U13 CS. Check that the reset state of U5 P1.02 holds U13 deselected until firmware configures it. The U5 P1.02 reset-state pull value was not available at report generation time.	Review
11.3.10	FM25L16B-GTR (U13)	U13 CS must not be asserted LOW until 1 ms (tPU) after VDD reaches its minimum. Check that U5's first access to U13 occurs at least 1 ms after VDD is valid. Infineon/Cypress FM25L16B datasheet, page 15, source: Tomachie.	Review
11.3.11	MAX98357AETE+T (U14)	GAIN_SLOT is tied to GND through R33 (100kΩ), which selects 15 dB (14.4-15.6 dB). A direct GND tie would give 12 dB and an open pin 9 dB. Maxim datasheet.	Review
11.3.12	MAX98357AETE+T (U14)	SD_MODE is driven directly by U5 P0.05. LOW, or undriven via the internal 100 kΩ pull-down, is shutdown. A push-pull HIGH (above the 1.5 V B2 trip) selects the left channel only, so audio must be sent in the left slot. (L+R)/2 would need about 633 kΩ RLARGE to 3.3 V. Maxim datasheet.	Review
11.3.13	MAX98357AETE+T (U14)	The SP+ / SP- speaker load on J6 is off-board and its impedance is not stated. The output current through L5/L6 (3 A rating) and U14 dissipation against 1666 mW (TQFN, 70 °C) cannot be calculated. It can be stated with free text on the schematic page, as: "SP+ load impedance : <value>".	Review
11.3.14	MLZ1608M100WTD25 (L3)	L3 (10uH) in the DCC-to-DEC4 path has a 90 mA saturation current. Check that U5 REG1 peak inductor current stays below 90 mA. The REG1 peak inductor current value was not available at report generation time. TDK datasheet.	Review
11.3.15	NRF52840-QIAA-R (U5)	The board-ID straps R21, R20 and R19 (100kΩ) pull P0.09, P0.10 and P0.11 to GND, so all three read low. P0.09 and P0.10 are the NFC1/NFC2 pins, and reading them depends on firmware configuring them as GPIO.	Review
11.3.16	ECS-320-8-37B-CKY-TR (X1)	32 MHz fundamental, inside the 16-50 MHz range. Maximum ESR 50 Ω, maximum drive level 100 µW, stability ±10 ppm. The part is specified for -30 to +85 °C, narrower at the cold end than U5's -40 °C; the design states no ambient range. ECS datasheet, source: Tomachie.	Review
11.3.17	NX3215SA-32.768K-STD-MUA-9 (X2)	C23 and C24 (8pF) present CL = 8 x 8 / (8 + 8) + C_stray = 4 pF + C_stray across X2 through ground. Against the 9.0 pF CL this implies 5 pF of stray, while Nordic's reference fits 12 pF per pin with an unstated reference crystal load. Maximum ESR 70 kΩ, maximum drive level 0.5 µW, -40 to +85 °C. NDK datasheet.	Review
11.3.18	TJA1021T/20/CM,118 (U2)	VBAT is fed from +VIN-PROTECT through Q1. The 10.8-16 V band is inside the 5.5-27 V static range and the 40 V absolute maximum. GND pin 5 is on GND. NXP TJA1021 datasheet, source: Tomachie.	✓
11.3.19	TJA1021T/20/CM,118 (U2)	RXD is open-drain with R11 (10kΩ) to VDD. The 0.33 mA pull-up current is below the 1.5 mA minimum IOL at 0.4 V, and VDD is below the 6 V RXD absolute maximum. NXP TJA1021 datasheet, source: Tomachie.	✓
11.3.20	TJA1021T/20/CM,118 (U2)	WAKE_N has R8 (100kΩ) to the switched VBAT (NetQ1_3) and is pulled low by Q5 from U5 P0.28, matching the datasheet local-wake arrangement. Q5 (BSS138K): 50 V VDS derated 30% (mosfet_vds_pct = 70) permits 35 V against 16 V applied. 12 V VGS derated 30% (mosfet_vgs_pct = 70) permits 8.4 V against at most 3.3 V applied. onsemi datasheet.	✓
11.3.21	TJA1021T/20/CM,118 (U2)	INH sources about 13 mA into the commander termination at a held dominant bus. The -50 mA absolute maximum, derated 30% (ic_output_current_pct = 70), permits 35 mA. Pass. NXP TJA1021 datasheet, source: Tomachie.	✓
11.3.22	TJA1021T/20/CM,118 (U2)	The 1MΩ pull-downs R6 (LIN-PWR), R5 (LIN-CMDR) and R10 (LIN-WAKE) hold Q4, Q3 and Q5 off from reset. U2 stays unpowered, commander termination off and local wake inactive until firmware drives them.	✓
11.3.23	BSS84-7-F (Q2)	Q2 switches the commander termination from INH, selected by Q3 from U5 P1.06. It carries about 13 mA against 130 mA derated 40% (mosfet_id_pct = 60) to 78 mA. VDS is at most 16 V against 50 V derated 30% (mosfet_vds_pct = 70) to 35 V. Diodes Incorporated BSS84 datasheet, source: Tomachie.	✓
11.3.24	BAS16-7-F (D3)	D3 sits in series with R7 (1kΩ) between the Q2 drain and LIN-IO. This is the 1 kΩ plus series diode commander termination the TJA1021 datasheet requires between INH and LIN (pages 1 and 16). Anode is on NetD3_1 and cathode on NetD3_3. NXP TJA1021 datasheet, source: Tomachie; Nexperia BAS16 datasheet.	✓
11.3.25	BZX84B16-7-F (D2)	Gate-source clamp of Q2, with anode on the gate and cathode on the source. Its maximum breakdown of 16.3 V at 5 mA is below Q2's ±20 V VGS rating. The divider keeps VGS below the 15.7 V minimum breakdown, so D2 carries leakage only. Diodes Incorporated BZX84B16 datasheet, source: Tomachie.	✓
11.3.26	TLV271CW5-7 (U11)	Unity-gain follower. The R26 (100kΩ) / R28 (10kΩ) divider gives 0.982-1.455 V at P0.02/AIN0 over 10.8-16 V, and 1.481 V at the 1% corner, below the 1.8 V lowest VDD. The divider source is switched by the same P0.03 net that powers U11, so the input is never driven while U11 is unpowered.	✓
11.3.27	FM25L16B-GTR (U13)	HOLD is tied to VDD through R38 (100kΩ), as the datasheet requires when HOLD is unused (page 3). Infineon/Cypress FM25L16B datasheet, source: Tomachie.	✓
11.3.28	FM25L16B-GTR (U13)	SPI is wired point-to-point: CS to P1.02, SCK to P0.25, SI to P1.04 and SO to P1.03. Both parts run on VDD, so the 0.7 x VDD VIH and the VDD - 0.8 V VOH share a reference. Infineon/Cypress FM25L16B datasheet, source: Tomachie.	✓
11.3.29	MAX98357AETE+T (U14)	VDD pins 7 and 8 are on +5v0 (4.85-5.12 V), inside the 2.5-5.5 V supply range. GND pins 3, 11, 15 and EP pin 17 are on GND. Maxim datasheet.	✓
11.3.30	MAX98357AETE+T (U14)	BCLK, LRCLK and DIN are driven from the VDD domain (1.8-3.3 V), against VIH 1.3 V minimum, VIL 0.6 V maximum and a 6 V absolute maximum. Maxim datasheet.	✓
11.3.31	PRTR5V0U2X,215 (U15)	IO1 is on USB-DEVICE-D_P, IO2 on USB-DEVICE-D_N, VCC on +VBUS and GND on GND. Tying VCC to the supply is the datasheet connection, and signal protection holds without supply. Nexperia PRTR5V0U2X datasheet, source: Tomachie.	✓
11.3.32	NRF52840-QIAA-R (U5)	SWDIO, SWDCLK and P0.18/RESET reach J7 pins 2, 4 and 3, with TP21, TP22 and TP23. J7_1 is on VDD and J7_5 on GND. Nordic nRF52840 datasheet.	✓

11.4 Citations

AI-Assisted —

References
2N7002P (Nexperia) — datasheet, cited pages 2,3 assets.nexperia.com/documents/data-sheet/2N7002P.pdf
AP22804 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/AP22804.pdf
BAS16 (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/BAS16.pdf
BSS138K (onsemi) — datasheet, cited pages 1,2 www.onsemi.com/download/data-sheet/pdf/bss138k-d.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
CDRH103RNP-6R8NC-B (Sumida) — datasheet products.sumida.com/products/pdf/CDRH103R.pdf
GCJ188R91H104KA01D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/24e69d76f59b023f447ab5...
GCJ32EC71H106KA01L (Murata Manufacturing Co., Ltd.) — datasheet datasheets.b-cdn.net/files/GCJ32EC71H106KA01L-Murata-data...
GCM155R71C473KA37 (Murata Manufacturing Co., Ltd.) — datasheet static.chipdip.ru/lib/891/DOC031891133.pdf
GCM155R71H104KE02D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/b385f789d1f9e1d12e8261...
GCM21BR71A106KE22K (Murata) — datasheet ds.murata.co.jp/simserve/characteristics?ModeType=normal&...
LQG15HS15NJ02 (Murata Manufacturing Co., Ltd.) — datasheet, cited pages 1,4,5 pim.murata.com/asset/pim4/inductor/JELF243B-0010_PDF_INDU...
MAX98357A (Maxim Integrated) — datasheet www.mouser.com/datasheet/2/256/MAX98357A-MAX98357B-271244...
MLZ1608M100WTD25 (TDK) — datasheet product.tdk.com/info/en/catalog/datasheets/inductor_autom...
MPZ2012S221AT000 (TDK) — datasheet product.tdk.com/info/en/catalog/datasheets/beads_commerci...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
NX3215SA-32.768K-STD-MUA-9 (NIHON DEMPA KOGYO CO., LTD. (NDK)) — datasheet, cited pages 1 pdf.datasheet.live/datasheets-1/ndk/NX3215SA-32.768K-STD-...
TLV271 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/TLV27x.pdf
ZXMP4A16G (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/ZXMP4A16G.pdf

12 Designer Annotated Nets

No additional annotations are present beyond those already reported in previous sections.

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J8	USB4145-03-0230-C	J8 (USB4145-03-0230-C): Shell pins share the logic GND net, so the shield-bond strategy is not captured as design intent.	USB Type-C R2.5 §3.2.1 requires the receptacle shell to be connected to the PCB ground plane; a shield net bonded to logic GND through R\|\|C satisfies it and does not leave the shell floating. Assign a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD) so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MΩ \|\| 4.7 nF (≥2 kV) from the shield net to logic GND. IEC 61000-4-2.

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed:4 connector-facing signal(s). 0 protected, 4 unprotected, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
USB-DEVICE-D_N	J8	No ESD Protection
CC1	J8	No ESD Protection
USB-DEVICE-D_P	J8	No ESD Protection
CC2	J8	No ESD Protection

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture

AI-Assisted — The board has one ground domain, GND, which is digital. No chassis or earth domain is drawn. The harness return reaches GND directly at J1_4, J2_4, J3_3, J3_4, J4_4 and J5_3. The J8 USB-C shell contacts S1 to S4 also sit directly on GND. As an automotive module, the design is judged against ISO 10605 for ESD, CISPR 25 for radiated and conducted emissions, ISO 11452 for radiated immunity, and ISO 7637-2 for conducted transients.

Every external signal on the wire pads J1 to J5 has a bidirectional TVS to GND at the pad net. Each is followed by a series element to its endpoint: 100Ω on the buffer lines, 100Ω and 100kΩ on the charger loop, and R7 (1kΩ) with D3 on the LIN termination path. These clamps and resistors give first-contact energy one designed return path. The clamps reference the same GND that the protected devices use, which is correct.

Filtering is limited to the ferrite beads L5 and L6 on the speaker outputs. None of the wire-pad signal nets carries a filter capacitor. At CISPR 25 frequencies, the harness wires act as antennas for both emission and immunity.

The +VIN transient suppression at J1, J2 and J5 is already reported in the power review and is not repeated here.

13.3.2 J1, J2 - LIN and Battery Harness

AI-Assisted — J1 and J2 are 18AWG wire pads that carry +VIN (pin 1), LIN-IO (pin 3) and GND (pin 4). This suits a LIN daisy-chain harness entry and exit. Both are external harness entry points.

D4 (PESD1IVN24-AX) sits on LIN-IO directly at the pads, clamping to GND. Its description gives a 24 V working voltage and a 42 V clamp. The 24 V stand-off is above the 16 V top of the +VIN band, so D4 does not conduct in normal operation, even with a held dominant or recessive bus.

The endpoint, U2_6 (LIN), is itself rated ±6 kV contact to IEC 61000-4-2 with a 150 pF / 330 Ω network (NXP TJA1021 datasheet, source: Tomachie). D4 adds margin toward ISO 10605 module-level levels.

The U2 LIN absolute maximum needed to compare against the 42 V clamp is not available, so that comparison is listed under Checks Not Performed.

J1_2 and J2_2 have no connection.

13.3.3 J3, J4 - Peripheral Harness

AI-Assisted — J3 and J4 feed off-board peripherals: switched 5 V, two data outputs and two inputs. Each signal pad has a PESD5V0S1BA bidirectional TVS to GND. Each clamp is followed by a 100Ω series resistor to an SN74LV1T34 buffer. Relative to the pad, the order is clamp first, then resistor, then IC pin.

The data outputs NP0-EXT and NP1-EXT are driven by U3_4 and U9_4, whose VCC is +5v0 at 4.85-5.12 V. At the top of that band the high level exceeds the clamps' 5 V working voltage, which puts the TVS into its leakage region. This is a margin issue, not conduction.

The input buffers U4 and U10 accept 7.0 V absolute on pin A. The outputs U3 and U9 accept VCC + 0.5 V on pin Y, with ±20 mA clamp current (TI SN74LV1T34 datasheet). The 14 V clamp figure is a pulse clamping level, so it cannot be compared directly with these DC limits.

The power pads carry no clamp: J3_1 (+5v0-CH0 from U1_1), J4_1 (+5v0-CH1 from U8_1) and J3_6 (+5v0 direct). U1 and U8 are rated 2000 V HBM (Diodes Incorporated AP22804 datasheet).

13.3.4 J5 - Charger Detect Loop

AI-Assisted — J5 carries +VIN (pin 1), CHG-LOOP (pin 2) and GND (pin 3). D14 (PESD5V0S1BA) clamps CHG-LOOP to GND at the pad. Beyond the clamp, R32 (100Ω) leads to U5 P1.13 and R31 (100kΩ) leads to U5 P1.15.

The U5 aQFN73 package is rated 2 kV HBM and 450 V CDM (Nordic nRF52840 datasheet). The series resistance of R32 limits the current that a residual above the D14 clamp can drive into P1.13.

The GPIO absolute maximum needed to judge the 14 V clamp is not available, so that comparison is listed under Checks Not Performed.

13.3.5 J6 - Speaker Output

AI-Assisted — J6 carries the filterless Class D output of U14 (MAX98357A) through the ferrite beads L5 and L6 (MPZ2012S221AT000, 220@100MHz, 3 A). The datasheet states that the device uses spread-spectrum modulation and needs no output LC filter (Maxim MAX98357A datasheet).

Without shunt capacitors, the beads add series impedance but no low-impedance return. The speaker leads still radiate the switching edges, which is a CISPR 25 radiated-emission risk that depends on lead length. No clamp is fitted on SP+ or SP-. The pads face an off-board speaker that is normally inside the enclosure, so ESD exposure depends on the installation.

The net naming is crossed: SP+ reaches U14_10 (OUTN) through L5, and SP- reaches U14_9 (OUTP) through L6.

13.3.6 J8 - USB Type-C Receptacle

AI-Assisted — J8 (USB4145-03-0230-C, vertical SMT) is a user-accessible USB 2.0 port and must withstand hot-plug discharges.

U15 (PRTR5V0U2X) connects as follows: IO1 to USB-DEVICE-D_P, IO2 to USB-DEVICE-D_N, VCC to +VBUS and GND to logic GND. The data clamps therefore reference the ground of the PHY in U5, which is correct.

CC1 and CC2 terminate only in R37 and R36 (5.1kΩ to GND) and reach no IC pin. A strike on these contacts dissipates in the resistors.

On the J8 VBUS contacts, the only device-level protection is U15's VCC pin. U5_AD2 (VBUS) has a 5.8 V absolute maximum (Nordic nRF52840 datasheet).

The shell contacts sit directly on GND. The report judges them at the professional level, because an automotive module is ESD-tested. Directly stitched shell tabs let a strike pull the GND copper under the connector away from the GND under U5 for the edge duration. In a module with no chassis, the charge still lands on the board. An R||C bond changes where and how it enters, not where it ends up.

13.4 Observations

AI-Assisted — The wire-pad signal entries are consistently clamped at the pad, ahead of a series resistor. For ESD this is the correct order: the clamp fires first and the resistor limits the residual reaching the IC.

The remaining exposures are concentrated at three kinds of entry point:

The unclamped 5 V power pads on J3 and J4.
The USB VBUS contact.
The unfiltered speaker leads.

On the J3 and J4 power pads, the 150µF bulk on +5v0 absorbs ESD energy at J3_6. It does not help at J3_1 or J4_1, which are separated from it by the U1 and U8 switches.

The J8 shell bond is the one medium finding. It is a design-intent gap: a dedicated shield net is needed so layout can place the bond parts.

All fitted TVS parts are bidirectional, so they have no orientation to check. D3 (BAS16) is unidirectional and its orientation is consistent.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J8	Shell contacts share the logic GND net, so the shield-bond strategy is not captured as design intent. Assign a dedicated SHIELD_GND_J8 net so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MOhm \|\| 4.7 nF (>= 2 kV) from SHIELD_GND_J8 to logic GND. USB Type-C R2.5 section 3.2.1; IEC 61000-4-2.	Medium
13.5.2	J3, J4	D5 and D12 (PESD5V0S1BA, 5 V working voltage) on NP0-EXT and NP1-EXT see the U3/U9 output high level of up to 5.12 V at the +5v0 band top. This is above the working voltage and puts the TVS in its leakage region, but it is below conduction. A 5.5 V or 6 V working-voltage bidirectional TVS clears the band.	Low
13.5.3	J8	CC1 and CC2 carry no clamp. They terminate only in R37 and R36 (5.1kΩ to GND) and reach no IC pin, so ESD energy dissipates in the resistors. IEC 61000-4-2.	Review
13.5.4	J8	The J8 VBUS contacts (A4, A9, B4, B9) have only U15's VCC pin on +VBUS, and no dedicated surge clamp. U5_AD2 VBUS is rated 5.8 V absolute maximum. Investigate a VBUS TVS for vehicle-cabin hot-plug. Nordic nRF52840 datasheet; ISO 10605.	Review
13.5.5	J3, J4	NP0-EXT and NP1-EXT: the D5/D12 14 V clamp level passes through R9/R27 (100Ω) to U3_4 and U9_4. Those pins are rated VCC + 0.5 V absolute with ±20 mA IOK. The clamp is a pulse level and the limits are DC ratings, so the two are not directly comparable. TI SN74LV1T34 datasheet.	Review
13.5.6	J3, J4	BTN0-EXT and AUX1-EXT: the D8/D13 14 V clamp level passes through R12/R30 (100Ω) to U4_2 and U10_2. Those pins are rated 7.0 V absolute. The clamp is a pulse level and the limit is a DC rating, so the two are not directly comparable. TI SN74LV1T34 datasheet.	Review
13.5.7	J3	J3_1 (+5v0-CH0) connects directly to U1_1 OUT with no clamp on the pad net. U1 is rated 2000 V HBM. Investigate a clamp for harness-level ESD per ISO 10605. Diodes Incorporated AP22804 datasheet.	Review
13.5.8	J4	J4_1 (+5v0-CH1) connects directly to U8_1 OUT with no clamp on the pad net. U8 is rated 2000 V HBM. Investigate a clamp for harness-level ESD per ISO 10605. Diodes Incorporated AP22804 datasheet.	Review
13.5.9	J3	J3_6 is on +5v0 with no clamp. The C12/C13 150µF bulk on the rail absorbs ESD energy at this pad. ISO 10605.	Review
13.5.10	J6	The filterless Class D outputs leave through L5/L6 (220@100MHz) with no shunt return and no clamp. The speaker leads are a radiated-emission path. Check the lead length and routing against CISPR 25 during pre-compliance testing. Maxim MAX98357A datasheet.	Review
13.5.11	J6	SP+ reaches U14_10 OUTN and SP- reaches U14_9 OUTP, so the net naming is crossed. This is speaker polarity and belongs to the functional review.	Review
13.5.12	All	The ground architecture has a single logic GND with no chassis domain. The harness GND at J1, J2, J3, J4 and J5 is the module's only reference. Every clamp returns to that GND. CISPR 25; ISO 10605.	Review
13.5.13	J8	The U15 data clamps sit on USB-DEVICE-D_P and USB-DEVICE-D_N, and U15 GND is on logic GND. The clamps therefore reference the PHY they protect (U5 D+/D-). IEC 61000-4-2.	✓
13.5.14	J1, J2	D4 (PESD1IVN24-AX, 24 V working voltage) clamps LIN-IO at the pads. The working voltage is above the 16 V top of the +VIN band, so D4 stays off in operation. U2_6 LIN is itself rated ±6 kV contact to IEC 61000-4-2. NXP TJA1021 datasheet, source: Tomachie; ISO 10605.	✓
13.5.15	J5	D14 (PESD5V0S1BA) clamps CHG-LOOP at the pad, ahead of R32 (100Ω) to U5 P1.13 and R31 (100kΩ) to U5 P1.15. The clamp and series-resistance order is correct. IEC 61000-4-2.	✓
13.5.16	All	D4, D5, D8, D12, D13 and D14 are bidirectional, so they have no orientation to check. D3 (BAS16) is unidirectional and its orientation is consistent.	✓

13.6 Citations

AI-Assisted —

References
AP22804 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/AP22804.pdf
MAX98357A (Maxim Integrated) — datasheet www.mouser.com/datasheet/2/256/MAX98357A-MAX98357B-271244...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
SN74LV1T34 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/sn74lv1t34.pdf

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on LSSI buses	Yes	Place test points on every LSSI bus signal (JTAG, SWD, I2C, I3C, MDIO, SPI, QSPI, UART) that has none
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	8
Rails with TPs	7
Rails without TPs	1

1 power rail(s) need test points in the submitted design.

9 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+5v0		TP18	✓
+VBUS		TP1	✓
+VIN		TP27	✓
+VIN-PROTECT		TP5	✓
GND		TP2, TP24, TP25, TP26	✓
NetC10_2		-	NEEDS TP
NetC14_1		TP18 on +5v0, across R15	✓
VDD		TP17	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP28	NetC10_2	cricket-node-hw--top-level_B.SchDoc
TP31	GND	cricket-node-hw--top-level_B.SchDoc
TP32	GND	cricket-node-hw--top-level_B.SchDoc
TP33	GND	cricket-node-hw--top-level_B.SchDoc
TP34	GND	cricket-node-hw--top-level_B.SchDoc
TP35	GND	cricket-node-hw--top-level_B.SchDoc
TP36	GND	cricket-node-hw--top-level_B.SchDoc

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP29	NetD15_C	cricket-node-hw--top-level_B.SchDoc
TP30	NetD16_C	cricket-node-hw--top-level_B.SchDoc

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U7	AP64352SP-13	EN	3	tied to VCC - recommend pull-up resistor and test point

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.5 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
SMT_TP-1MM	SMT Testpoint 1MM	27

14.5.1 By Sheet

Test Point	Net Name	Footprint
cricket-node-hw--top-level_B (27 test points)
TP1	+VBUS	SMT_TP-1MM
TP2	GND	SMT_TP-1MM
TP3	USB-DEVICE-D_P	SMT_TP-1MM
TP4	USB-DEVICE-D_N	SMT_TP-1MM
TP5	+VIN-PROTECT	SMT_TP-1MM
TP6	NP0-EXT	SMT_TP-1MM
TP7	BTN0-EXT	SMT_TP-1MM
TP8	+5v0-CH0	SMT_TP-1MM
TP9	P1.06	SMT_TP-1MM
TP10	NP1-EXT	SMT_TP-1MM
TP11	AUX1-EXT	SMT_TP-1MM
TP12	+5v0-CH1	SMT_TP-1MM
TP13	LIN-IO	SMT_TP-1MM
TP14	SP+	SMT_TP-1MM
TP15	SP-	SMT_TP-1MM
TP16	CHG-LOOP	SMT_TP-1MM
TP17	VDD	SMT_TP-1MM
TP18	+5v0	SMT_TP-1MM
TP19	P0.13	SMT_TP-1MM
TP20	TEST1	SMT_TP-1MM
TP21	SWDIO	SMT_TP-1MM
TP22	SWDCLK	SMT_TP-1MM
TP23	RESET	SMT_TP-1MM
TP24	GND	SMT_TP-1MM
TP25	GND	SMT_TP-1MM
TP26	GND	SMT_TP-1MM
TP27	+VIN	SMT_TP-1MM

14.5.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP1	+VBUS	cricket-node-hw--top-level_B	SMT_TP-1MM
TP2	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP3	USB-DEVICE-D_P	cricket-node-hw--top-level_B	SMT_TP-1MM
TP4	USB-DEVICE-D_N	cricket-node-hw--top-level_B	SMT_TP-1MM
TP5	+VIN-PROTECT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP6	NP0-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP7	BTN0-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP8	+5v0-CH0	cricket-node-hw--top-level_B	SMT_TP-1MM
TP9	P1.06	cricket-node-hw--top-level_B	SMT_TP-1MM
TP10	NP1-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP11	AUX1-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP12	+5v0-CH1	cricket-node-hw--top-level_B	SMT_TP-1MM
TP13	LIN-IO	cricket-node-hw--top-level_B	SMT_TP-1MM
TP14	SP+	cricket-node-hw--top-level_B	SMT_TP-1MM
TP15	SP-	cricket-node-hw--top-level_B	SMT_TP-1MM
TP16	CHG-LOOP	cricket-node-hw--top-level_B	SMT_TP-1MM
TP17	VDD	cricket-node-hw--top-level_B	SMT_TP-1MM
TP18	+5v0	cricket-node-hw--top-level_B	SMT_TP-1MM
TP19	P0.13	cricket-node-hw--top-level_B	SMT_TP-1MM
TP20	TEST1	cricket-node-hw--top-level_B	SMT_TP-1MM
TP21	SWDIO	cricket-node-hw--top-level_B	SMT_TP-1MM
TP22	SWDCLK	cricket-node-hw--top-level_B	SMT_TP-1MM
TP23	RESET	cricket-node-hw--top-level_B	SMT_TP-1MM
TP24	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP25	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP26	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP27	+VIN	cricket-node-hw--top-level_B	SMT_TP-1MM

14.6 Powered-off Testing

24 nets with test points: 23 pins with opens coverage, 4 pins with partial opens, 197 pins with shorts coverage.

Open pin faults may be masked when two or more IC pins share a net (current flow through one internal pin ESD diode may mask the open on another).

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
C12_1	+5v0	Capacitor	-	●
C13_1	+5v0	Capacitor	-	●
C26_2	+5v0	Capacitor	-	●
C27_2	+5v0	Capacitor	-	●
D6_1	+5v0	Passive	-	●
D15_A	+5v0	Passive	-	●
D16_A	+5v0	Passive	-	●
J3_6	+5v0	Connector	-	●
R15_2	+5v0	Passive	-	●
R16_2	+5v0	Passive	-	●
U1_5	+5v0	IC	-	●
U3_5	+5v0	IC	-	●
U8_5	+5v0	IC	-	●
U9_5	+5v0	IC	-	●
U14_7	+5v0	IC	-	●
U14_8	+5v0	IC	-	●
J3_1	+5v0-CH0	Connector	-	●
U1_1	+5v0-CH0	IC	●	●
J4_1	+5v0-CH1	Connector	-	●
U8_1	+5v0-CH1	IC	●	●
D7_1	+VBUS	Passive	-	●
J8_A4	+VBUS	Connector	-	●
J8_A9	+VBUS	Connector	-	●
J8_B4	+VBUS	Connector	-	●
J8_B9	+VBUS	Connector	-	●
U5_AD2	+VBUS	IC	-	●
U15_4	+VBUS	IC	-	●
J1_1	+VIN	Connector	-	●
J2_1	+VIN	Connector	-	●
J5_1	+VIN	Connector	-	●
Q6_2,4	+VIN	Transistor	-	●
C7_1	+VIN-PROTECT	Capacitor	-	●
C8_1	+VIN-PROTECT	Capacitor	-	●
D1_3	+VIN-PROTECT	Passive	-	●
D9_3	+VIN-PROTECT	Passive	-	●
D11_3	+VIN-PROTECT	Passive	-	●
Q1_2	+VIN-PROTECT	Transistor	-	●
Q6_3	+VIN-PROTECT	Transistor	-	●
Q7_2	+VIN-PROTECT	Transistor	-	●
R1_2	+VIN-PROTECT	Passive	-	●
R24_2	+VIN-PROTECT	Passive	-	●
U7_2	+VIN-PROTECT	IC	-	●
U7_3	+VIN-PROTECT	IC	-	●
D13_2	AUX1-EXT	Passive	●	●
J4_3	AUX1-EXT	Connector	-	●
R30_2	AUX1-EXT	Passive	-	●
D8_2	BTN0-EXT	Passive	●	●
J3_5	BTN0-EXT	Connector	-	●
R12_2	BTN0-EXT	Passive	-	●
D14_2	CHG-LOOP	Passive	●	●
J5_2	CHG-LOOP	Connector	-	●
R31_1	CHG-LOOP	Passive	-	●
R32_2	CHG-LOOP	Passive	-	●
C1_1	GND	Capacitor	-	●
C2_1	GND	Capacitor	-	●
C3_1	GND	Capacitor	-	●
C4_1	GND	Capacitor	-	●
C6_1	GND	Capacitor	-	●
C7_2	GND	Capacitor	-	●
C8_2	GND	Capacitor	-	●
C9_1	GND	Capacitor	-	●
C10_1	GND	Capacitor	-	●
C11_1	GND	Capacitor	-	●
C12_2	GND	Capacitor	-	●
C13_2	GND	Capacitor	-	●
C14_2	GND	Capacitor	-	●
C15_1	GND	Capacitor	-	●
C16_1	GND	Capacitor	-	●
C17_1	GND	Capacitor	-	●
C18_1	GND	Capacitor	-	●
C19_1	GND	Capacitor	-	●
C20_1	GND	Capacitor	-	●
C21_2	GND	Capacitor	-	●
C22_2	GND	Capacitor	-	●
C23_1	GND	Capacitor	-	●
C24_1	GND	Capacitor	-	●
C25_1	GND	Capacitor	-	●
C26_1	GND	Capacitor	-	●
C27_1	GND	Capacitor	-	●
C28_1	GND	Capacitor	-	●
D4_1	GND	Passive	●	●
D5_1	GND	Passive	●	●
D8_1	GND	Passive	●	●
D12_1	GND	Passive	●	●
D13_1	GND	Passive	●	●
D14_1	GND	Passive	●	●
J1_4	GND	Connector	-	●
J2_4	GND	Connector	-	●
J3_3	GND	Connector	-	●
J3_4	GND	Connector	-	●
J4_4	GND	Connector	-	●
J5_3	GND	Connector	-	●
J7_5	GND	Connector	-	●
J8_A1	GND	Connector	-	●
J8_A12	GND	Connector	-	●
J8_B1	GND	Connector	-	●
J8_B12	GND	Connector	-	●
J8_S1	GND	Connector	-	●
J8_S2	GND	Connector	-	●
J8_S3	GND	Connector	-	●
J8_S4	GND	Connector	-	●
Q3_2	GND	Transistor	-	●
Q4_2	GND	Transistor	-	●
Q5_2	GND	Transistor	-	●
Q8_2	GND	Transistor	-	●
Q9_2	GND	Transistor	-	●
Q10_2	GND	Transistor	-	●
R5_1	GND	Passive	●	●
R6_1	GND	Passive	-	●
R10_1	GND	Passive	-	●
R18_2	GND	Passive	-	●
R19_1	GND	Passive	-	●
R20_1	GND	Passive	-	●
R21_1	GND	Passive	-	●
R22_2	GND	Passive	-	●
R23_2	GND	Passive	-	●
R28_2	GND	Passive	-	●
R29_1	GND	Passive	-	●
R33_2	GND	Passive	-	●
R36_1	GND	Passive	-	●
R37_1	GND	Passive	-	●
U1_2	GND	IC	-	●
U2_5	GND	IC	-	●
U3_3	GND	IC	-	●
U4_3	GND	IC	-	●
U5_B7	GND	IC	-	●
U5_F23	GND	IC	-	●
U5_74	GND	IC	-	●
U7_7	GND	IC	-	●
U7_9	GND	IC	-	●
U8_2	GND	IC	-	●
U9_3	GND	IC	-	●
U10_3	GND	IC	-	●
U11_2	GND	IC	-	●
U12_4	GND	IC	-	●
U12_9	GND	IC	-	●
U13_4	GND	IC	-	●
U14_3	GND	IC	-	●
U14_11	GND	IC	-	●
U14_15	GND	IC	-	●
U14_17	GND	IC	-	●
U15_1	GND	IC	-	●
D4_2	LIN-IO	Passive	●	●
J1_3	LIN-IO	Connector	-	●
J2_3	LIN-IO	Connector	-	●
R7_2	LIN-IO	Passive	-	●
U2_6	LIN-IO	IC	●	●
D5_2	NP0-EXT	Passive	●	●
J3_2	NP0-EXT	Connector	-	●
R9_2	NP0-EXT	Passive	-	●
D12_2	NP1-EXT	Passive	●	●
J4_2	NP1-EXT	Connector	-	●
R27_2	NP1-EXT	Passive	-	●
U5_AD8	P0.13	IC	●	●
Q3_1	P1.06	Transistor	-	●
R5_2	P1.06	Passive	●	●
U5_R24	P1.06	IC	●	●
J7_3	RESET	Connector	-	●
U5_AC13	RESET	IC	●	●
J6_2	SP+	Connector	-	●
L5_2	SP+	Passive	-	●
J6_1	SP-	Connector	-	●
L6_2	SP-	Passive	-	●
J7_4	SWDCLK	Connector	-	●
U5_AA24	SWDCLK	IC	●	●
J7_2	SWDIO	Connector	-	●
U5_AC24	SWDIO	IC	●	●
U5_AD10	TEST1	IC	●	●
J8_A7	USB-DEVICE-D_N	Connector	-	●
J8_B7	USB-DEVICE-D_N	Connector	-	●
U5_AD4	USB-DEVICE-D_N	IC	◐	●
U15_3	USB-DEVICE-D_N	IC	◐	●
J8_A6	USB-DEVICE-D_P	Connector	-	●
J8_B6	USB-DEVICE-D_P	Connector	-	●
U5_AD6	USB-DEVICE-D_P	IC	◐	●
U15_2	USB-DEVICE-D_P	IC	◐	●
C1_2	VDD	Capacitor	-	●
C2_2	VDD	Capacitor	-	●
C3_2	VDD	Capacitor	-	●
C4_2	VDD	Capacitor	-	●
C6_2	VDD	Capacitor	-	●
C25_2	VDD	Capacitor	-	●
C28_2	VDD	Capacitor	-	●
J7_1	VDD	Connector	-	●
L1_1	VDD	Passive	-	●
R11_1	VDD	Passive	-	●
R14_2	VDD	Passive	-	●
R38_2	VDD	Passive	-	●
U4_5	VDD	IC	-	●
U5_AD14	VDD	IC	-	●
U5_AD23	VDD	IC	-	●
U5_A22	VDD	IC	-	●
U5_B1	VDD	IC	-	●
U5_W1	VDD	IC	-	●
U10_5	VDD	IC	-	●
U12_8	VDD	IC	-	●
U13_8	VDD	IC	-	●

14.7 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

6 power rail nets with test points: 41 source-path pins (opens + shorts), 117 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
C12_1	+5v0	Sink	-	●
C13_1	+5v0	Sink	-	●
C26_2	+5v0	Sink	-	●
C27_2	+5v0	Sink	-	●
D6_1	+5v0	Sink	-	●
D15_A	+5v0	Sink	-	●
D16_A	+5v0	Sink	-	●
J3_6	+5v0	Sink	-	●
R15_2	+5v0	Sink	-	●
R16_2	+5v0	Sink	-	●
TP18_1	+5v0	Sink	-	●
U1_5	+5v0	Sink	-	●
U3_5	+5v0	Sink	-	●
U8_5	+5v0	Sink	-	●
U9_5	+5v0	Sink	-	●
U14_7	+5v0	Sink	-	●
U14_8	+5v0	Sink	-	●
D7_1	+VBUS	Sink	-	●
J8_A4	+VBUS	Sink	-	●
J8_A9	+VBUS	Sink	-	●
J8_B4	+VBUS	Sink	-	●
J8_B9	+VBUS	Sink	-	●
TP1_1	+VBUS	Sink	-	●
U5_AD2	+VBUS	Sink	-	●
U15_4	+VBUS	Sink	-	●
J1_1	+VIN	Sink	-	●
J2_1	+VIN	Sink	-	●
J5_1	+VIN	Sink	-	●
Q6_2,4	+VIN	Sink	-	●
TP27_1	+VIN	Sink	-	●
C7_1	+VIN-PROTECT	Sink	-	●
C8_1	+VIN-PROTECT	Sink	-	●
D1_3	+VIN-PROTECT	Sink	-	●
D9_3	+VIN-PROTECT	Sink	-	●
D11_3	+VIN-PROTECT	Sink	-	●
Q1_2	+VIN-PROTECT	Sink	-	●
Q6_3	+VIN-PROTECT	Sink	-	●
Q7_2	+VIN-PROTECT	Sink	-	●
R1_2	+VIN-PROTECT	Sink	-	●
R24_2	+VIN-PROTECT	Sink	-	●
TP5_1	+VIN-PROTECT	Sink	-	●
U7_2	+VIN-PROTECT	Sink	-	●
U7_3	+VIN-PROTECT	Sink	-	●
C1_1	GND	Sink	-	●
C2_1	GND	Sink	-	●
C3_1	GND	Sink	-	●
C4_1	GND	Sink	-	●
C6_1	GND	Sink	-	●
C7_2	GND	Sink	-	●
C8_2	GND	Sink	-	●
C9_1	GND	Sink	-	●
C10_1	GND	Sink	-	●
C11_1	GND	Sink	-	●
C12_2	GND	Sink	-	●
C13_2	GND	Sink	-	●
C14_2	GND	Sink	-	●
C15_1	GND	Series (U7 → C15)	●	●
C16_1	GND	Series (U5 → C16)	●	●
C17_1	GND	Series (U5 → C17)	●	●
C18_1	GND	Series (U5 → C18)	●	●
C19_1	GND	Series (U5 → C19)	●	●
C20_1	GND	Series (U5 → C20)	●	●
C21_2	GND	Series (U5 → C21)	●	●
C22_2	GND	Series (U5 → C22)	●	●
C23_1	GND	Series (U5 → C23)	●	●
C24_1	GND	Series (U5 → C24)	●	●
C25_1	GND	Sink	-	●
C26_1	GND	Sink	-	●
C27_1	GND	Sink	-	●
C28_1	GND	Sink	-	●
D4_1	GND	Sink	-	●
D5_1	GND	Sink	-	●
D8_1	GND	Sink	-	●
D12_1	GND	Sink	-	●
D13_1	GND	Sink	-	●
D14_1	GND	Sink	-	●
J1_4	GND	Sink	-	●
J2_4	GND	Sink	-	●
J3_3	GND	Sink	-	●
J3_4	GND	Sink	-	●
J4_4	GND	Sink	-	●
J5_3	GND	Sink	-	●
J7_5	GND	Sink	-	●
J8_A1	GND	Sink	-	●
J8_A12	GND	Sink	-	●
J8_B1	GND	Sink	-	●
J8_B12	GND	Sink	-	●
J8_S1	GND	Sink	-	●
J8_S2	GND	Sink	-	●
J8_S3	GND	Sink	-	●
J8_S4	GND	Sink	-	●
Q3_2	GND	Sink	-	●
Q4_2	GND	Sink	-	●
Q5_2	GND	Sink	-	●
Q8_2	GND	Sink	-	●
Q9_2	GND	Sink	-	●
Q10_2	GND	Sink	-	●
R5_1	GND	Series (U5 → R5)	●	●
R6_1	GND	Series (U5 → R6)	●	●
R10_1	GND	Series (U5 → R10)	●	●
R18_2	GND	Sink	-	●
R19_1	GND	Series (U5 → R19)	●	●
R20_1	GND	Series (U5 → R20)	●	●
R21_1	GND	Series (U5 → R21)	●	●
R22_2	GND	Series (U7 → R22)	●	●
R23_2	GND	Series (U7 → R23)	●	●
R28_2	GND	Series (U11 → R28)	●	●
R29_1	GND	Series (U5 → R29)	●	●
R33_2	GND	Series (U14 → R33)	●	●
R36_1	GND	Sink	-	●
R37_1	GND	Sink	-	●
TP2_1	GND	Sink	-	●
TP24_1	GND	Sink	-	●
TP25_1	GND	Sink	-	●
TP26_1	GND	Sink	-	●
U1_2	GND	Sink	-	●
U2_5	GND	Sink	-	●
U3_3	GND	Sink	-	●
U4_3	GND	Sink	-	●
U5_B7	GND	Series path	●	●
U5_F23	GND	Series path	●	●
U5_74	GND	Series path	●	●
U7_7	GND	Series path	●	●
U7_9	GND	Series path	●	●
U8_2	GND	Sink	-	●
U9_3	GND	Sink	-	●
U10_3	GND	Sink	-	●
U11_2	GND	Series path	●	●
U12_4	GND	Sink	-	●
U12_9	GND	Sink	-	●
U13_4	GND	Sink	-	●
U14_3	GND	Series path	●	●
U14_11	GND	Series path	●	●
U14_15	GND	Series path	●	●
U14_17	GND	Series path	●	●
U15_1	GND	Sink	-	●
C1_2	VDD	Sink	-	●
C2_2	VDD	Sink	-	●
C3_2	VDD	Sink	-	●
C4_2	VDD	Sink	-	●
C6_2	VDD	Sink	-	●
C25_2	VDD	Sink	-	●
C28_2	VDD	Sink	-	●
J7_1	VDD	Sink	-	●
L1_1	VDD	Series (U5 → L1)	●	●
R11_1	VDD	Series (U5 → R11)	●	●
R14_2	VDD	Series (U13 → R14)	●	●
R38_2	VDD	Series (U13 → R38)	●	●
TP17_1	VDD	Sink	-	●
U4_5	VDD	Sink	-	●
U5_AD14	VDD	Series path	●	●
U5_AD23	VDD	Series path	●	●
U5_A22	VDD	Series path	●	●
U5_B1	VDD	Series path	●	●
U5_W1	VDD	Series path	●	●
U10_5	VDD	Sink	-	●
U12_8	VDD	Sink	-	●
U13_8	VDD	Series path	●	●

14.8 Boundary Scan Testability

14.8.1 Test Coverage

Net fault coverage classification for boundary scan testing (BSCAN-Only scenario). Signal nets: 110, BSCAN nets: 0, BSCAN pins: 0 (drivers: 0, observers: 0), Connector nets: 19, Test point nets: 18

Fault Coverage Class Definitions

Fault Coverage Class 1: Full opens and shorts fault coverage on the nets listed in this class.

Fault Coverage Class 2: Shorts fault coverage on the nets listed in this class. Opens coverage is provided on the boundary scan portion of each net through series components.

Fault Coverage Class 3: No opens coverage on the nets listed in this class. Shorts will be detected between the nets listed in this class and the nets listed in the following classes:

Fault Coverage Class 1
Fault Coverage Class 2

Fault Coverage Class 4: Opens will be detected on the nets listed in this class only if they cause a boundary scan input or tester pin to float to a logic state that is different from the net's constant state. Shorts will be detected between the nets listed in this class and the nets listed in the following classes:

Fault Coverage Class 1
Fault Coverage Class 2

Fault Coverage Class 5: The nets listed in this class are the Test Access Port signals (TCK, TMS, TRST, TDI, TDO), boundary scan compliance enable pins, level translators and passives that are connected to the TAP.

Fault Coverage Class 6: No fault coverage on the nets listed in this class.

General Notes

The above discussion about opens coverage does not apply to any connector leads that might be on each net. Opens are not covered on any connector leads unless a tester pin is connected to that lead with a mating connector. Connector leads are listed in the net descriptions and are marked with asterisks (*).

Shorts will never be detected between two nets of any class that are connected together with transparent series components.

Nets that are described as "resistively isolated" may not have the shorts detection described for their class above. This is because these nets are tested through transparent series components whose impedance might be high enough to isolate the effect of a short so that it causes no failure.

Differential nets may not have the shorts detection described for their class above. This is because the redundancy inherent in differential signalling can make some shorts undetectable, such as a short to a logic level between 0 and 1.

Opens coverage on pull-ups and pull-downs is described as "possible" because opens on these leads can be detected only if the affected inputs float to the complement of their pulled state.

Fault Coverage Summary (BSCAN-Only)
Class	Description	Nets
Class 1	Full coverage	0 nets
Class 2	Through series / connector	0 nets
Class 3	No opens, shorts to 1-2	0 nets
Class 4	Pulled nets	0 nets
Class 5	TAP signals	0 nets
Class 6	No coverage	110 nets
Total		110 nets

Coverage Percentages
Metric	BSCAN-Only
Opens Coverage	0.0%
Shorts Coverage	0.0%