11-10028cricket-node-hwB Design Analysis

1 Design Summary

out of 100

Depth of review, as a baseline: 328 verified datasheet parameters applied and 298 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

CCA_CODENAME	cricket-node
CCA_DESCRIPTION	cricket-node
CCA_PART_NUMBER	10-10028
CCA_TITLE	cricket-node
ENGINEER	E. Hughes
PCB_CODENAME	cricket-node
PCB_DATE	2025-05-27
PCB_DESCRIPTION	cricket-node
PCB_MIXDOWN	B
PCB_PART_NUMBER	11-10028
SCH_DATE	2025-05-27
STATUS	PROTOTYPE
Active Variant	Base (all components)
Design Type	Flat (1 sheets)
Total Components	153
Total Pins	454
Total Nets	120
Total Test Points	27
Project Variants	1

Improve your score:

Improve fault coverage (opens/shorts) +7
Add test points on indicator signals +1
Improve schematic library models +1
Move component values to VALUE property +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1

Points deducted for open High/Medium AI findings:

0 High, 14 Medium -7

AI findings to review:

Power findings — 6 Medium, 1 Low, 14 Review
HSSI findings — 2 Medium, 2 Review
Memory findings — 3 Medium, 1 Low, 2 Review
Functional findings — 9 Review
EMC/ESD findings — 3 Medium, 6 Low, 3 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 8 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — The board is a single-sheet, wireless sensor/actuator node built around U5, a Nordic nRF52840 (aQFN73) Arm Cortex-M4F with FPU running at 64 MHz, with an integrated 2.4 GHz multiprotocol radio supporting Bluetooth Low Energy and IEEE 802.15.4. Per the Nordic datasheet, the radio delivers -20 dBm to +8 dBm output and -95 dBm sensitivity at 1 Mbps (-103 dBm in 125 kbps long-range mode), with a 12-bit 200 ksps SAADC across eight configurable channels. The antenna port is single-ended from the ANT pin. Timing is provided by X1, a 32 MHz ±10 ppm crystal for the HFXO, and X2, an NX3215SA 32.768 kHz ±20 ppm, 9.0 pF tuning-fork crystal for the LFXO.

Non-volatile storage and memory

Two memory devices sit alongside the MCU's internal flash and RAM: U12, a Macronix MX25R6435F 64 Mbit ultra-low-power serial flash on the nRF52840 QSPI port in 4-bit mode, and U13, a Cypress/Infineon FM25L16B 16 kbit SPI F-RAM rated for 1E14 write cycles and 10-year retention at 85 °C, giving the node a high-endurance journal alongside bulk code/data storage.

Interfaces

External connectivity comprises a LIN transceiver (U2, NXP TJA1021T/20/CM, 20 kBd normal-slope variant) with bus-side transient protection, a USB 2.0 Type-C receptacle (J8) feeding the nRF52840's internal USB device controller and its VBUS/DECUSB regulator, and field wiring through screw-free wire pads J1–J6 (18 AWG and 22 AWG, 3.5 mm pitch). Audio output is provided by U14, a MAX98357A filterless Class D amplifier driven over I2S, capable of 3.2 W into 4 Ω + 33 µH at 10 % THD+N with gain selectable between 3 dB and 15 dB. Level translation between the 3.3 V core domain and 5 V domain uses four SN74LV1T34 single-buffer translators (U3, U4, U9, U10); U11, a TLV271 rail-to-rail op-amp, provides analog conditioning. Debug access is duplicated as a Tag-Connect TC2030 footprint (J7) and a 10-pin 1.27 mm SWD header (J9), both serving the SWD port of U5. Two indicator LEDs (D15 red, D16 green) provide local status.

Power tree

Primary input arrives on +VIN and is passed through series protection to +VIN-PROTECT, which includes a P-channel ZXMP4A16G (Q6, -40 V, -6.4 A) pass element and Zener/TVS clamping. U7, a Diodes AP64352 synchronous buck (3.8 V to 40 V input, 3.5 A, 500 kHz at RT = 200 kΩ), switches from its SW pin through L4 to generate the main step-down rail, forming the +5v0 domain. The nRF52840's own regulators supply the remaining low-voltage rails: VDD is sourced from U5 pin DCCH through L1 (the high-voltage DC/DC path), and a second internal DC/DC output at U5 pin DCC feeds through L3 and L2. USB VBUS is carried on the +VBUS rail. Two Diodes AP22804AW5-7 current-limited load switches (U1, U8) provide 2.5 A distribution with 3.0 A typical current limit, active-high enable, and open-drain fault reporting; the AP22804 is oversized relative to the loads a node of this scale presents, which is benign headroom rather than a defect. Twenty-seven test points are distributed across the rails and signals.

Temperature and ratings

The controller, memories, audio amplifier, LIN transceiver and switching regulator are all rated -40 °C to +85 °C ambient, with the nRF52840 limited to a 90 °C junction temperature and the AP64352 to +125 °C junction. The narrowest device on the board is U11: the TLV271CW5-7 suffix selects the commercial C grade, specified 0 °C to +70 °C in the Diodes datasheet, which sets the assembly's guaranteed operating window unless the I grade is substituted.

1.2 Processed Sheets

#	Sheet Name
1	cricket-node-hw--top-level_B

1.3 Variants

#	Variant	DNP	ALT
0	Base (all components)	-	-
1	B	1	0

1.3.1 B

Status	RefDes	Part Type	Alt Part	Footprint
DNP	J9	CORTEX-DEBUG		FTSH-105-05-F-DV

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
3 of 36 unique footprints are IPC-7351B or IPC-7251	✓
31 SMT footprints do not follow IPC-7351B naming
2 footprints (connectors, specialty) — compliance unknown

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Ferrite beads on inductor designators (L5, L6): the Description indicates a ferrite bead, but the part uses an inductor (L) designator. Use an FB or FL designator. A ferrite value is an impedance at a frequency (e.g. 600R@100MHz), not an inductance.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	28	C26, C27, C15, C8, C5, C14, C6, C11 (+20 more)	✓
Capacitors	The dedicated Voltage property holds the whole value string (e.g. "100uF 35V") instead of only the rating. VALUE itself is clean, which is why the value checks above pass. Tomachie separates the fields, so the analysis and the AI read a clean voltage and are not misled — this is a cleanliness note, not a parsing failure. Downstream BOM/ICT/AOI tools that read the Voltage property literally will not parse it: put only the rating there (e.g. 35V) and leave the magnitude in VALUE. (C14 currently has VALUE="150µF 10V")	4	C14, C12, C13, C7
Resistors	Values in VALUE or Resistance	38	R36, R37, R33, R9, R12, R11, R8, R10 (+30 more)	✓
Inductors	Values in VALUE or Inductance	3	L2, L1, L3	✓
Inductors	VALUE holds both the magnitude and a current rating (e.g. "6.8uH 3.84A"). Tomachie has already separated the two and uses the magnitude as the value, so the analysis and the AI read a clean value — the misinterpretation risk is low. This is a cleanliness note: move the current rating into a named Current property for downstream BOM/ICT/AOI tools and a self-describing schematic. (L4 currently has VALUE="6.8 uH 3.84A")	1	L4
Ferrite Beads	VALUE contains a part number, not an electrical value. Actual value found in another property. Put part numbers in Industry_PN or Manufacturing_PN fields. (e.g. L5 VALUE="MPZ2012S221AT000", actual value: 220@100MHz)	2	L5, L6
Oscillators	Values in VALUE or Frequency	2	X1, X2	✓

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

13 unconnected pin(s) found:

13 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
J1_2	2	Passive	CON-1-4	UNC_J1_2_2
J2_2	2	Passive	CON-1-4	UNC_J2_2_2
J7_6	SWO	Passive	TAG-CONNECT-SWD	-	No net
J9_6	SWO/TDO	Passive	CORTEX-DEBUG	UNC_J9_6_SWO/TDO
J9_8	TDI	Passive	CORTEX-DEBUG	UNC_J9_8_TDI
U5_A20	P1.10	Bidirectional	nRF52840-QIAA	P1.10
U5_AC11	P0.16	Bidirectional	nRF52840-QIAA	P0.16
U5_AC15	P0.19	Bidirectional	nRF52840-QIAA	P0.19
U5_AD12	P0.17	Bidirectional	nRF52840-QIAA	P0.17
U5_B15	P1.14	Bidirectional	nRF52840-QIAA	P1.14
U5_B17	P1.12	Bidirectional	nRF52840-QIAA	P1.12
U5_G1	P0.26	Bidirectional	nRF52840-QIAA	P0.26
U5_P2	P1.08	Bidirectional	nRF52840-QIAA	P1.08

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden power pins stacked behind visible pins in the symbol.

Implied Net Connections
Component	Type	Pin	Net
U12	MX25R6435FZNIL0	9	GND

3.3 Open-Collector Pull-up Audit

Examined 0 candidate pin(s) on 0 net(s).

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation	Severity
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires that pin 1, the cathode, is on the left with the footprint at zero rotation. Tomachie will call out schematic-symbol problems that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, or a novice may wrongly indict a correct part — keeping consistent is the least-expensive path for everyone who handles the PCB.
D1 BZX84C12-7-F unidirectional · pin_names	Pin 1 (A): NOLBL_D1_1_A Pin 3 (K): +VIN-PROTECT	Consistent
D2 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NOLBL_D2_1_A Pin 3 (K): NOLBL_D2_3_K	Consistent
D3 BAS16-7-F unidirectional · pin_names	Pin 1 (A): NOLBL_D3_1_A Pin 3 (K): NOLBL_D3_3_K	Consistent
D11 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NOLBL_D11_1_A Pin 3 (K): +VIN-PROTECT	Consistent
D9 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NOLBL_D9_1_A Pin 3 (K): +VIN-PROTECT	Consistent
D7 BAS16-7-F unidirectional · pin_names	Pin 1 (A): +VBUS Pin 3 (K): NOLBL_D6_3_K	Consistent
D6 BAS16-7-F unidirectional · pin_names	Pin 1 (A): +5v0 Pin 3 (K): NOLBL_D6_3_K	Consistent
D8 PESD5V0S1BA-115 bidirectional · pin_names	Pin 2 (C): BTN0-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D5 PESD5V0S1BA-115 bidirectional · pin_names	Pin 2 (C): NP0-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D4 PESD1IVN24-AX bidirectional · pin_names	Pin 2 (C): LIN-IO Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D13 PESD5V0S1BA-115 bidirectional · pin_names	Pin 2 (C): AUX1-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D12 PESD5V0S1BA-115 bidirectional · pin_names	Pin 2 (C): NP1-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D14 PESD5V0S1BA-115 bidirectional · pin_names	Pin 2 (C): CHG-LOOP Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information

3.5 Polarized Capacitor Orientation

Capacitor	Connections	Polarity	Severity
Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
C14 EEE-FK1A151P	Pin 1 (+): NOLBL_C14_1_1 Pin 2: GND
C12 EEE-FK1A151P	Pin 1 (+): +5v0 Pin 2: GND
C13 EEE-FK1A151P	Pin 1 (+): +5v0 Pin 2: GND
C7 EEE-FK1V101P	Pin 1 (+): +VIN-PROTECT Pin 2: GND

3.6 Summary

Total NO_ERC markers in design	24
Pins needing attention (warnings)	13
Pins for information only	0

4 Power Overview

Power rails	8
Power management sources identified	3

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

+VBUS: 5 V assumed by USB convention, because a USB connector power pin is on this net. A design that negotiates a higher USB Power Delivery voltage must state the rail's actual nominal, minimum and maximum voltage — preferably recorded in the design itself, otherwise entered when prompted before the AI review starts. Until it is stated, the assumed 5 V is taken as the intended level.

Power Rails
Rail	Voltage	Source	Consumers
+VIN	12.00V	J5 External	Q6 (ZXMP4A16GTA)
+VIN-PROTECT	12.00V	Q6 ZXMP4A16GTA	U7 (AP64352SP-13)
+5v0	5.00V	U7 AP64352SP-13	U14 (MAX98357AETE+T), U3 (SN74LV1T34DBVR), U8 (AP22804AW5-7), U9 (SN74LV1T34DBVR), U1 (AP22804AW5-7)
+VBUS	5.00V	J8 External	U5 (NRF52840-QIAA-R), U15 (PRTR5V0U2X,215)
NOLBL_C14_1_1	5.00V	U7 AP64352SP-13	-
GND	-	J8 External	-
NOLBL_C10_2_1	1.3V	U5 NRF52840-QIAA-R	-
VDD	1.8-3.3V	U5 NRF52840-QIAA-R	U12 (MX25R6435FZNIL0), U13 (FM25L16B-GTR), U10 (SN74LV1T34DBVR), U4 (SN74LV1T34DBVR)

4.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.2.1 Power Tree Overview

AI-Assisted — The board runs from two independent sources. A nominal 12 V harness input arrives on J1/J2 (18 AWG wire pads) and J5, labelled +VIN with a stated operating window of 10.80 V to 16.00 V. It passes through P-channel MOSFET Q6 (ZXMP4A16GTA) into +VIN-PROTECT, which is the same DC level less the channel drop and can be switched off by reverse polarity. +VIN-PROTECT feeds only the synchronous buck U7 (AP64352SP-13), whose output node carries C14 and reaches the +5v0 rail through the parallel 0 ohm links R15/R16. +5v0 supplies the Class-D audio amplifier U14, the two 5 V level-shifting buffers U3/U9, and the two current-limited load switches U1/U8 that drive the external channels +5v0-CH0 (J3) and +5v0-CH1 (J4).

The second source is USB VBUS from J8, resolved at 5.00 V, which reaches the nRF52840 (U5) VBUS pin for the USB peripheral and, through BAS16 diode D7, the VDDH node. The +5v0 rail reaches the same VDDH node through BAS16 diode D6, so VDDH is a diode-OR of the two 5 V sources at roughly 4.3 V after the forward drop, inside the 2.5 V to 5.5 V VDDH window of the Nordic nRF52840 datasheet (https://datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d588639838e545.pdf).

From VDDH the MCU's internal high-voltage DC/DC drives DCCH through L1 (10uH) to the VDD rail, stated as 1.8 V to 3.3 V because the level is set by the REGOUT0 register rather than by any external divider. VDD powers the QSPI flash U12, the FRAM U13, buffers U4/U10, and the VCC pins of both debug connectors J7 and J9. A second internal converter drives DCC through L3 (10uH) and L2 (15nH) into the 1.3 V DEC4/DEC6 node.

4.2.2 12 V Input Protection and Front End

AI-Assisted — Q6 is wired as the classic reverse-polarity pass element: source on +VIN-PROTECT, drain on +VIN, gate held at ground through R18 (10 kOhm) with zener D9 (BZX84B16, 15.7 V to 16.3 V at 5 mA per the Diodes Incorporated datasheet, source: Tomachie) cathode on the source rail. Forward connection biases Vgs negative and turns the channel on; the zener caps Vgs at roughly 16 V, safely inside the +/-20 V VGSS limit of the ZXMP4A16G datasheet (https://www.diodes.com/assets/Datasheets/ZXMP4A16G.pdf). Reverse connection leaves the channel off. Note that D9 limits gate stress only; it does not clamp the rail.

Q6's -40 V VDSS and -6.4 A continuous drain current at 25 C are far above the 16 V maximum input and the roughly 1.5 A the buck will draw at full 5 V load, so the device is comfortably oversized. This is benign margin in a SOT223 package that also gives the thermal headroom for a 60 mOhm Rds(on) at Vgs = -10 V.

The input bulk is C7 (100uF, 35 V aluminium) plus C8 (10uF, 50 V X7S, 1210). The AP64352 datasheet (Diodes Incorporated, source: Tomachie) asks for a ceramic greater than 10uF from VIN to GND; C8 is exactly 10uF before DC-bias derating at 12 V, with C7 carrying the low-frequency bulk. Polarity of C7 is correct, positive terminal on +VIN-PROTECT.

No fuse, PTC, or transient suppressor is fitted anywhere between the harness pads and the converter. The lowest withstand element on the protected node is C7 at 35 V, and the AP64352 VIN absolute maximum is 42 V DC (45 V for 400 ms). A harness-borne surge above 35 V therefore reaches C7 unattenuated.

4.2.3 AP64352SP-13 Buck Converter (U7) — 5 V Rail

AI-Assisted — Configuration is complete and consistent with the Diodes Incorporated AP64352 datasheet (source: Tomachie). VIN sits on +VIN-PROTECT, GND (pin 7) and the exposed pad (pin 9) are both on GND, and BST is closed to SW by C5 (0.1uF), matching the specified 100 nF boot capacitor.

EN is tied directly to +VIN-PROTECT, which the datasheet lists as the automatic-startup configuration: the converter releases as the input rises past the internal VIN UVLO of 3.5 V typical (3.7 V maximum, 400 mV hysteresis). VEN absolute maximum is 42 V, well clear of the 16 V input ceiling. Soft start is set by C15 (10000pF) on SS; the datasheet table gives 2 ms typical at Css = 10 nF, which is also the stated minimum, so start-up ramp is at the specified floor. The formula Css = 3.7 x tss would imply 2.7 ms — the tabulated 2 ms is the value used here.

Switching frequency is set by R22 (49.9 kOhm) on RT/CLK: RT[kOhm] = 100000/fSW[kHz] gives fSW = 100000/49.9 = 2004 kHz, inside the 100 kHz to 2200 kHz range. At 12 V in and 4.97 V out the duty is 0.417, so on-time is 208 ns against the 100 ns minimum; at 16 V in it falls to 156 ns, still legal.

Output voltage is set by R17 (523 kOhm) and R23 (100 kOhm) against the verified 0.800 V FB reference, giving 4.969 V. The 623 kOhm total divider draws about 8 uA and presents a high-impedance FB node; no feed-forward capacitor is fitted across R17, which the datasheet offers as an optional 10 pF to 220 pF transient aid.

Ripple current in L4 is (12 - 4.97) x 0.417 / (6.8uH x 2.004 MHz) = 0.214 A peak-to-peak, negligible against the 3.84 A saturation and 3.60 A temperature-rise ratings of the Sumida CDRH103R datasheet (https://products.sumida.com/products/pdf/CDRH103R.pdf). Its maximum DCR of 35 mOhm sits just above the datasheet's 30 mOhm guidance.

4.2.4 5 V Output Capacitance and Loop Stability

AI-Assisted — Counting both sides of the 0 ohm links: the converter-side node carries C14 (150uF aluminium, 10 V) and the load-side +5v0 rail carries C12 and C13 (150uF aluminium, 10 V each), C27 (10uF X7R, 10 V) and C26 (0.1uF), for 460.1uF total. All three aluminium parts have their positive terminal on the output node, correct per manufacturer convention.

The AP64352 datasheet calls for an output ceramic capacitor of 22uF to 68uF. Only 10uF of ceramic is fitted, and an 0805 X7R rated 10 V loses a substantial fraction of its capacitance at 5 V bias, so the effective high-frequency ceramic content is below the stated range. At the 2.0 MHz switching frequency the aluminium bulk contributes little: its impedance is ESR-dominated well before that frequency, so the ripple attenuation and the loop's high-frequency behaviour rest on C27 alone. The remedy is straightforward — add ceramic on +5v0 near U7 to bring the ceramic content into the datasheet range — but the datasheet phrases this as a recommendation rather than a minimum, so it is raised as a review item.

Ripple current loading of the electrolytics is not a concern: 0.214 A peak-to-peak triangular ripple is roughly 62 mA RMS shared across three EEE-FK1A151P parts each rated 240 mA.

The 10 V rating of C12, C13, C14 and C27 against the computed 4.969 V output gives a factor of two on ceramic and on aluminium alike. That is acceptable for the ceramics; for aluminium electrolytics on a permanently powered rail it is the minimum most process guidance accepts, with no headroom for the start-up overshoot of a 460uF output at a 2 ms soft start.

4.2.5 nRF52840 Supply Domains and Decoupling

AI-Assisted — VDDH is reached only through R13 (0 ohm) from the diode-OR node fed by D6 and D7. Neither the VDDH pin's own net nor the far side of that 0 ohm link carries any capacitor, so the pin has no local bypass — the only things on the node are two BAS16 cathodes and the link. Nordic's reference circuitry fits 4.7uF on VDDH (C19 in that figure). A rectifier cannot bypass a supply pin, and with the internal high-voltage DC/DC drawing pulsed current from VDDH through L1, the absence of that capacitor is a genuine gap.

The VBUS pin has the same problem from the other direction: the +VBUS rail carries no capacitance at all between the J8 receptacle and U5. The Nordic datasheet states, for the USB physical interface, that the input and output of the USB regulator need to be decoupled with a suitable capacitor, and the reference circuitry shows 4.7uF on VBUS. The output side is correctly served — C20 (4.7uF) sits on DECUSB, matching the reference — but the input side is bare.

The remaining decoupling matches the reference. DEC4 and DEC6 are tied together as the datasheet explicitly requires and share 1.094uF (C11 plus C9/C10) against the reference 1.0uF. DEC1 carries 0.1uF, matching the reference 100 nF. DEC5 carries C16 (1000pF) where the reference shows 820 pF, and that pin is marked not connected for build codes Fxx and later. The VDD rail carries 5.3uF total (C6 4.7uF plus six 0.1uF) across five VDD pins, consistent with the reference bulk-plus-per-pin arrangement.

L1 (MLZ1608M100WTD25) has a saturation rating of 90 mA and an Irms of 250 mA per the TDK datasheet (source: Tomachie). The peak inductor current of the nRF52840 high-voltage DC/DC is not stated in the verified parameters, so that saturation comparison cannot be closed here.

4.2.6 VDD Rail Programming Constraint

AI-Assisted — VDD is not set by any component on the schematic; its level comes from the MCU's REGOUT0 register, hence the 1.8 V to 3.3 V range. Three classes of load sit on it. The QSPI flash U12 and the two SN74LV1T34 buffers operate across the whole window. The FRAM U13 (FM25L16B-GTR) does not: its datasheet specifies VDD of 2.7 V minimum, 3.6 V maximum (source: Tomachie). A valid setting exists — anything from 2.7 V to 3.3 V — so this is a programming constraint rather than a defect, but the firmware must set REGOUT0 to at least 2.7 V or the FRAM operates out of specification, and its 1 ms power-up delay to first chip-select applies from that level.

The same rail drives the gates of the 2N7002P devices Q9 and Q10 (LED sinks) and Q3, Q4, Q8. The Nexperia 2N7002P datasheet gives a gate threshold of 1.1 V minimum to 2.4 V maximum and specifies Rds(on) only at Vgs of 5 V and 10 V (https://assets.nexperia.com/documents/data-sheet/2N7002P.pdf). A 1.8 V gate drive would sit below the worst-case threshold. Programming VDD to 2.7 V or above, as the FRAM already demands, keeps these gates above the maximum threshold, although Rds(on) at that drive remains outside the characterised range. Where a genuinely logic-level device was needed, the designer used a BSS138K (Q5, 0.6 V to 1.2 V threshold), so the distinction was made deliberately elsewhere.

VDD also feeds the VCC pins of debug connectors J7 and J9, and the pull-ups R14 and R38 (100 kOhm each) that hold the FRAM WP and HOLD pins to VDD as its datasheet requires for unused function pins.

4.2.7 5 V Distribution, Load Switches and Amplifier

AI-Assisted — U1 and U8 (AP22804AW5-7) take +5v0 on IN and deliver the two external channels. The A suffix is the active-high enable variant, driven from GPIO P1.11 and P0.04 respectively; VIH minimum is 1.5 V, so even a VDD of 1.8 V satisfies the input. Two issues attach to these switches.

First, the datasheet (https://www.diodes.com/datasheet/download/AP22804.pdf) states the EN pin should not be left floating and that it is advisable to hold EN low while power is applied or removed. Neither NP0-EN nor NP1-EN carries a pull-down; both are high-impedance until the MCU boots and configures its GPIOs, which is precisely the interval during which +5v0 is rising.

Second, neither switch output carries any capacitance. The datasheet asks for a 0.1uF bypass plus a high-value capacitor close to the IC on OUT, and a minimum 100uF low-ESR part (or 10uF MLCC) for hot-plug applications. Both outputs run straight to wire-pad connectors J3 and J4 with only a test point on the way, which is exactly the hot-plug case.

Current coordination is the more significant point. Each AP22804 has a fixed current limit of 2.7 A to 3.3 A (3.0 A typical) and a maximum continuous output of 2.5 A, and U14 (MAX98357A) is rated for 1.6 A continuous on VDD/GND/OUT with a 2.8 A internal current limit. The AP64352 delivers 3.5 A typical. A single channel faulting into its 3.0 A limit, or two channels loaded simultaneously, exceeds what the buck can source, and the converter's own 4.25 A to 5.75 A high-side peak limit will fold the whole 5 V rail — browning out the amplifier, the buffers and, through D6, the MCU's VDDH.

U14's supply pins are correctly served by C27 (10uF) and C26 (0.1uF) on +5v0, matching its datasheet bypass requirement, and its exposed pad and three GND pins are on GND.

4.2.8 LIN Domain Supply and Input Monitoring

AI-Assisted — The LIN transceiver U2 (TJA1021T/20/CM) is powered through a switched high-side leg rather than directly from +VIN-PROTECT: BSS84 P-FET Q1 has its source on +VIN-PROTECT and its drain on U2's VBAT pin, gate biased through R1 (100 kOhm) to the rail and pulled down through R4 (10 kOhm) by 2N7002P Q4, whose gate is GPIO P0.27 with R6 (1 MOhm) to GND. Zener D1 (BZX84C12, 11.4 V to 12.7 V) caps Q1's Vgs, well inside the BSS84's +/-20 V limit. The 1 MOhm gate pull-down on Q4 holds the leg off until firmware asserts it, so the LIN transceiver draws nothing at power-on.

U2's INH output drives a second BSS84 (Q2) through R2, clamped by D2 (BZX84B16). Q2's drain feeds D3 (BAS16) and R7 (1 kOhm) onto the LIN bus — the series resistor plus diode from INH to LIN that the NXP TJA1021 datasheet specifies for a commander node, with the 1 kOhm value matching its typical application.

Input voltage sensing uses a gated divider. Q7 (BSS84, gate clamped by D11 and biased by R24) is switched by Q8 from GPIO P0.03, connecting +VIN-PROTECT through R26 (100 kOhm) to R28 (10 kOhm), a ratio of 0.0909. At 12 V that presents 1.09 V and at the 16 V ceiling 1.45 V to the non-inverting input of U11 (TLV271), wired as a unity-gain follower into AIN0 on P0.02. When P0.03 is low the divider is disconnected and R28 holds the node at ground, so no input is applied to an unpowered amplifier.

U11's own VCC pin, however, is tied to that same GPIO P0.03 — the op-amp is powered from an MCU output. The TLV271 supply current is not among the verified parameters, so the draw cannot be weighed against the nRF52840's GPIO drive capability from the data available.

4.3 Observations

AI-Assisted — Three items dominate. The missing VDDH and VBUS decoupling at U5 is the clearest departure from a vendor reference and is cheap to close. The uncoordinated 5 V current limits mean a single external channel fault takes down the whole 5 V domain including the MCU's VDDH feed. The floating enables on U1 and U8 during power-up leave the external channels in an undefined state until firmware runs.

On temperature grade, U11 is specified as TLV271CW5-7 — the C grade, rated 0 C to +70 C per the Diodes Incorporated datasheet (https://www.diodes.com/assets/Datasheets/TLV27x.pdf). Every other active device on the board is rated -40 C to +85 C, including the MCU, the buck, the load switches, the amplifier and the FRAM. For a LIN-connected node this single part sets the assembly's operating range unless the I grade is substituted.

On transient protection of the LIN line, D4 (PESD1IVN24-AX) has a 24 V standoff against the 16 V maximum rail, correct for the working voltage, and clamps at 42 V maximum for a 3.5 A 8/20 us pulse. The TJA1021 LIN pin carries ISO 7637 transient ratings of -100 V (pulse 1), +75 V (pulse 2a), -150 V (3a) and +100 V (3b), so the clamp sits inside the correct transient class — not against the +/-40 V DC limiting value, which is a different quantity.

Both ESD arrays, PESD5V0S1BA (D5, D8, D12, D13, D14) and PRTR5V0U2X (U15 on the USB data pair), changed to non-automotive qualification in their latest Nexperia revisions. If this node is destined for a vehicle harness — the LIN interface suggests as much — automotive-qualified equivalents apply.

Electrolytic and tantalum polarity was checked across C7, C12, C13 and C14: all four have the positive terminal on the powered node and no polarity error is present.

4.4 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.4.1	U5 (NRF52840-QIAA-R)	VDDH	The VDDH pin's net and the far side of the 0 ohm link R13 carry no capacitor; the node is fed only by BAS16 diodes D6 and D7. Nordic's reference circuitry fits 4.7uF on VDDH. A diode cannot bypass a supply pin. Add local bulk at VDDH. Nordic nRF52840 datasheet, https://datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d588639838e545.pdf	Medium
4.4.2	U5 (NRF52840-QIAA-R)	+VBUS	No capacitance anywhere on +VBUS between the J8 receptacle and the VBUS pin. The datasheet states the input and output of the USB regulator need to be decoupled; the reference shows 4.7uF on VBUS. The output side (DECUSB, C20 4.7uF) is correct. Nordic nRF52840 datasheet	Medium
4.4.3	U1, U8 (AP22804AW5-7)	+5v0 / +5v0-CH0, +5v0-CH1	Fixed current limit 2.7-3.3 A each (2.5 A max continuous output) against the AP64352's 3.5 A typical output. Concurrent channel loading or a single channel fault exceeds the converter's capability and collapses +5v0, browning out U14 and the MCU VDDH feed. Diodes Incorporated AP22804 datasheet, https://www.diodes.com/datasheet/download/AP22804.pdf	Medium
4.4.4	U1, U8 (AP22804AW5-7)	NP0-EN, NP1-EN	No pull-down on either enable net; both are high-impedance until MCU GPIOs P1.11 and P0.04 are configured. The datasheet states the EN pin should not be left floating and advises holding it low while power is applied or removed. Diodes Incorporated AP22804 datasheet	Medium
4.4.5	U1, U8 (AP22804AW5-7)	+5v0-CH0, +5v0-CH1	No output capacitance on either switch output; both run straight to wire-pad connectors J3/J4 via a test point. The datasheet calls for 0.1uF plus a high-value capacitor close to the IC, and a minimum 100uF low-ESR part for hot-plug applications, which these external channels are. Diodes Incorporated AP22804 datasheet	Medium
4.4.6	U11 (TLV271CW5-7)	P0.03 (gated supply)	The C temperature grade is rated 0 C to +70 C; every other active device on the board is rated -40 C to +85 C. This part alone sets the assembly's operating window. Diodes Incorporated TLV27x datasheet, https://www.diodes.com/assets/Datasheets/TLV27x.pdf	Medium
4.4.7	+VIN input (J1, J2, J5)	+VIN	No fuse, PTC or transient suppressor between the harness pads and Q6. The lowest withstand element on the protected node is C7 at 35 V; the AP64352 VIN absolute maximum is 42 V DC. A harness surge above 35 V reaches C7 unattenuated. Diodes Incorporated AP64352 datasheet	Low
4.4.8	U7 (AP64352SP-13)	+5v0	Ceramic output content is 10uF (C27, 0805 X7R 10 V, before DC-bias derating at 5 V) against the datasheet's recommended 22uF to 68uF ceramic. The 450uF of aluminium bulk contributes little at the 2.0 MHz switching frequency. Recommendation wording, not a minimum. Diodes Incorporated AP64352 datasheet (source: Tomachie)	Review
4.4.9	U7 (AP64352SP-13)	NOLBL_R17_1_1 (FB)	Output set by R17 523 kOhm / R23 100 kOhm against the verified 0.800 V FB reference, giving 4.969 V. Divider current is about 8 uA and the FB node is high impedance; no optional feed-forward capacitor (10-220 pF) is fitted across R17. Diodes Incorporated AP64352 datasheet	Review
4.4.10	L4 (CDRH103RNP-6R8NC-B)	+5v0	Computed ripple 0.214 A peak-to-peak at 12 V in / 4.969 V out / 2004 kHz, far below the 3.84 A saturation and 3.60 A temperature-rise ratings — benign margin. Maximum DCR 35 mOhm (27 mOhm typical) is marginally above the datasheet's 30 mOhm guidance for the inductor selection. Sumida CDRH103R datasheet, https://products.sumida.com/products/pdf/CDRH103R.pdf	Review
4.4.11	C12, C13, C14 (EEE-FK1A151P)	+5v0	Ripple loading about 62 mA RMS shared across three parts each rated 240 mA. Voltage rating 10 V against the computed 4.969 V output is a factor of two, the minimum normally accepted for aluminium electrolytics on an always-on rail. Panasonic FK series rating as stated on the schematic	Review
4.4.12	C8 (10uF 50V X7S 1210)	+VIN-PROTECT	The AP64352 datasheet asks for greater than 10uF ceramic from VIN to GND; C8 is exactly 10uF nominal before DC-bias derating at 12 V, backed by C7 100uF aluminium for the low-frequency bulk. Diodes Incorporated AP64352 datasheet	Review
4.4.13	U13 (FM25L16B-GTR)	VDD (1.8-3.3 V, register set)	The FRAM requires VDD of 2.7 V minimum. VDD is programmable over 1.8-3.3 V, so a valid setting exists — REGOUT0 must be programmed to at least 2.7 V for U13. Infineon/Cypress FM25L16B datasheet (source: Tomachie)	Review
4.4.14	Q9, Q10 (2N7002P)	VDD (1.8-3.3 V)	Gate threshold is 1.1 V minimum to 2.4 V maximum and Rds(on) is characterised only at Vgs of 5 V and 10 V. A 1.8 V gate drive sits below the worst-case threshold; programming VDD to at least 2.7 V, as U13 already demands, resolves it. Nexperia 2N7002P datasheet, https://assets.nexperia.com/documents/data-sheet/2N7002P.pdf	Review
4.4.15	L1 (MLZ1608M100WTD25)	VDDH -> VDD	Saturation rating 90 mA, Irms 250 mA. The peak inductor current of the nRF52840 high-voltage DC/DC is not stated in the verified parameters, so the saturation comparison cannot be closed from the data available. TDK MLZ1608 datasheet (source: Tomachie)	Review
4.4.16	U5 (NRF52840-QIAA-R)	NOLBL_C16_2_1 (DEC5)	C16 is 1000pF where the reference circuitry shows 820 pF; the datasheet notes DEC5 is not connected for build codes Fxx and later. Nordic nRF52840 datasheet	Review
4.4.17	X1, X2	VDD domain	Both crystals use 8pF pairs, presenting 4.00 pF in series at each oscillator. Nordic's reference circuitry fits 12 pF per terminal (6 pF series) for both HFXO and LFXO. The stray capacitance the reference implies is not stated, so the resulting pull cannot be quantified. Nordic nRF52840 datasheet	Review
4.4.18	U11 (TLV271CW5-7)	P0.03	The op-amp VCC pin is fed from MCU GPIO P0.03, the same signal that gates the divider through Q8/Q7 — a deliberate power-gated sense chain, and the input is held at ground by R28 when the supply is off. The TLV271 supply current is not among the verified parameters, so the load on the GPIO cannot be weighed. Diodes Incorporated TLV27x datasheet	Review
4.4.19	D5, D8, D12-D14, U15	External I/O, USB data	PESD5V0S1BA and PRTR5V0U2X both changed to non-automotive qualification in their latest revisions. The LIN interface suggests a vehicle harness application, where automotive-qualified equivalents apply. Nexperia datasheets (source: Tomachie)	Review
4.4.20	U1, U8 (AP22804AW5-7)	FLAG (pin 3)	The open-drain over-current and over-temperature flag on both load switches is unconnected in the schematic, so channel fault status is not observable by the MCU or by a bench probe. Functionally optional, but a pull-up to VDD and a GPIO or test point would make the 6 ms fault deglitch visible. Diodes Incorporated AP22804 datasheet	Review
4.4.21	Q6 (ZXMP4A16GTA)	+VIN-PROTECT	The datasheet is marked Advance Information, indicating preliminary status with parameters subject to change; it also directs automotive users to contact the manufacturer rather than stating AEC-Q101 qualification as standard. Diodes Incorporated ZXMP4A16G datasheet	Review
4.4.22	U7 (AP64352SP-13)	+VIN-PROTECT	EN tied directly to the input rail — the datasheet's automatic-startup configuration; VEN absolute maximum 42 V against a 16 V rail ceiling. Internal VIN UVLO releases at 3.5 V typical. Configuration reviewed and valid. Diodes Incorporated AP64352 datasheet	✓
4.4.23	Q6 (ZXMP4A16GTA), D9, R18	+VIN -> +VIN-PROTECT	Reverse-polarity pass FET with gate zener D9 (BZX84B16) to the source rail and R18 10 kOhm gate pull-down reviewed: a valid auto-enable arrangement that limits Vgs within the +/-20 V VGSS limit. The zener does not clamp the rail. Diodes Incorporated ZXMP4A16G datasheet, https://www.diodes.com/assets/Datasheets/ZXMP4A16G.pdf	✓
4.4.24	U7 (AP64352SP-13)	RT/CLK	R22 49.9 kOhm gives fSW = 100000/49.9 = 2004 kHz, within the 100-2200 kHz range; the pin is not floating. Minimum on-time 208 ns at 12 V input and 156 ns at 16 V, both above the 100 ns limit. Diodes Incorporated AP64352 datasheet	✓
4.4.25	U7 (AP64352SP-13)	SS	C15 10000pF sets the tabulated 2 ms soft start, equal to the datasheet minimum Css of 10 nF and minimum tss of 2 ms. The stated table value is used in preference to the 3.7 x tss formula, which would give 2.7 ms. Diodes Incorporated AP64352 datasheet	✓
4.4.26	U7 (AP64352SP-13)	BST / SW	C5 0.1uF connected BST to SW, matching the specified 100 nF boot capacitor. Diodes Incorporated AP64352 datasheet	✓
4.4.27	U7 (AP64352SP-13)	+VIN-PROTECT / GND	VIN (pin 2) on +VIN-PROTECT; GND (pin 7) and the exposed pad (pin 9) both on GND, as the datasheet requires for the die heat path. All supply and return pins have a genuine DC path. Diodes Incorporated AP64352 datasheet	✓
4.4.28	C7, C12, C13, C14	+VIN-PROTECT, +5v0	All aluminium electrolytics have their positive terminal on the powered node and the negative terminal on GND. No polarity error present.	✓
4.4.29	U5 (NRF52840-QIAA-R)	NOLBL_C10_2_1 (DEC4/DEC6)	DEC4 and DEC6 are tied together as the datasheet explicitly requires, and the shared node carries 1.094uF against the reference figure of 1.0uF. DEC1 carries 0.1uF, matching the reference 100 nF. Nordic nRF52840 datasheet	✓
4.4.30	U5 (NRF52840-QIAA-R)	DECUSB	C20 4.7uF on DECUSB matches the reference circuitry value for the USB regulator output. Nordic nRF52840 datasheet	✓
4.4.31	U5 (NRF52840-QIAA-R)	VDD	Five VDD pins served by 5.3uF total (C6 4.7uF plus six 0.1uF), consistent with the reference bulk-plus-per-pin arrangement. Nordic nRF52840 datasheet	✓
4.4.32	D6, D7 (BAS16-7-F)	+5v0 / +VBUS -> VDDH	Diode-OR of the two 5 V sources onto VDDH; cathodes are correctly common on the VDDH node. Resulting level is about 4.3 V after forward drop, inside the 2.5-5.5 V VDDH window. VRRM 100 V and 215 mA average forward current are ample. Nexperia BAS16 datasheet, https://assets.nexperia.com/documents/data-sheet/BAS16.pdf	✓
4.4.33	D1 (BZX84C12), D2, D11 (BZX84B16)	+VIN-PROTECT gate networks	Gate-referenced zeners on the BSS84 high-side switches Q1, Q2 and Q7 limit Vgs to 11.4-12.7 V and 15.7-16.3 V respectively, inside the BSS84 +/-20 V VGSS limit. Orientation is consistent, cathode on the source rail. Diodes Incorporated BZX84 datasheets (source: Tomachie)	✓
4.4.34	U11 / R26, R28	+VIN-PROTECT sense	Divider 100 kOhm / 10 kOhm presents 1.09 V at 12 V input and 1.45 V at the 16 V ceiling to AIN0 on P0.02 through a unity-gain follower — within the VDD-referenced analogue input range for any legal REGOUT0 setting. Nordic nRF52840 datasheet	✓
4.4.35	U2 (TJA1021T/20/CM)	Q1 drain (switched 12 V)	VBAT supplied through P-FET Q1, held off at power-on by the 1 MOhm gate pull-down on Q4, so the transceiver draws nothing until firmware enables it. GND on GND. R7 1 kOhm plus D3 from the INH-driven leg to LIN matches the series resistor and diode the datasheet specifies for a commander node. NXP TJA1021 datasheet	✓
4.4.36	D4 (PESD1IVN24-AX)	LIN-IO	24 V standoff covers the 16 V rail ceiling; clamping 42 V maximum at 3.5 A 8/20 us sits inside the TJA1021 LIN pin's ISO 7637 transient levels (+75 V pulse 2a, +100 V pulse 3b). Bidirectional part, no orientation to check. Nexperia PESD1IVN24-A datasheet (source: Tomachie)	✓
4.4.37	U14 (MAX98357AETE+T)	+5v0	Both VDD pins served by C27 10uF and C26 0.1uF, matching the datasheet's 0.1uF plus 10uF bypass requirement. Exposed pad and all three GND pins on GND. Supply 4.969 V is inside the 2.5-5.5 V range and above the 2.3 V maximum UVLO. Maxim MAX98357A datasheet, https://www.mouser.com/datasheet/2/256/MAX98357A-MAX98357B-271244.pdf	✓
4.4.38	D15, D16 (APT2012SURCK / CGCK)	+5v0	Anodes on +5v0 with cathodes returned through R34/R35 330 Ohm to 2N7002P sinks: (5 - 1.95)/330 = 9.2 mA red and (5 - 2.1)/330 = 8.8 mA green, both well inside the 30 mA DC forward limit. Kingbright datasheets, https://www.kingbrightusa.com/images/catalog/spec/apt2012surck.pdf	✓
4.4.39	J9 (debug header)	VDD	Design variant B would depopulate J9, leaving the Tag-Connect pads J7 as the sole debug access. Both carry VCC from VDD as drawn in the base design; this is an intentional build option, not a defect.	✓

4.5 Citations

AI-Assisted —

References
2N7002P (Nexperia) — datasheet, cited pages 2,3 assets.nexperia.com/documents/data-sheet/2N7002P.pdf
AP22804 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/AP22804.pdf
AP64352 (Diodes Incorporated) — datasheet AP64352SP-13.pdf
APT2012CGCK (Kingbright) — datasheet APT2012CGCK.pdf
APT2012SURCK (Kingbright) — datasheet, cited pages 1,2 www.kingbrightusa.com/images/catalog/spec/apt2012surck.pdf
BAS16 (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/BAS16.pdf
BSS138K (onsemi) — datasheet, cited pages 1,2 www.onsemi.com/download/data-sheet/pdf/bss138k-d.pdf
BSS84 (Diodes Incorporated) — datasheet, cited pages 1 BSS84-7-F.pdf
BZX84B16 (Diodes Incorporated) — datasheet diodes.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
CDRH103RNP-6R8NC-B (Sumida) — datasheet products.sumida.com/products/pdf/CDRH103R.pdf
FM25L16B (Cypress (Infineon Technologies)) — datasheet, cited pages 1,2,4,8,13 via web_fetch
LQG15HS15NJ02D (Murata Mfg Co., Ltd) — datasheet, cited pages 1,5 no.mouser.com/datasheet/2/281/1/JELF243B_0010-1699614.pdf
MAX98357A (Maxim Integrated) — datasheet www.mouser.com/datasheet/2/256/MAX98357A-MAX98357B-271244...
MLZ1608M100WTD25 (TDK) — datasheet, cited pages 1,5,6 MLZ1608M100WTD25.pdf
MPZ2012S221AT000 (TDK) — datasheet product.tdk.com/info/en/catalog/datasheets/beads_commerci...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
NX3215SA-32.768K-STD-MUA-9 (NIHON DEMPA KOGYO CO., LTD. (NDK)) — datasheet, cited pages 1 pdf.datasheet.live/datasheets-1/ndk/NX3215SA-32.768K-STD-...
PESD1IVN24-A (Nexperia) — datasheet PESD1IVN24-AX.pdf
PESD5V0S1BA (Nexperia) — datasheet PESD5V0S1BA.pdf
PRTR5V0U2X (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf
TLV271 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/TLV27x.pdf
ZXMP4A16G (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/ZXMP4A16G.pdf

5 Connector Pinouts

Total connectors

5.1 J1 WIREPAD-18AWG-4X-3.5MM

J1 - WIREPAD-18AWG-4X-3.5MM (WIREPAD-18AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	NC
3	3	LIN-IO
4	4	GND

5.2 J2 WIREPAD-18AWG-4X-3.5MM

J2 - WIREPAD-18AWG-4X-3.5MM (WIREPAD-18AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	NC
3	3	LIN-IO
4	4	GND

5.3 J3 WIREPAD-22AWG-6X-3.5MM

J3 - WIREPAD-22AWG-6X-3.5MM (WIREPAD-22AWG-6X-3.5MM) [WIREPAD-22AWG-6X-3.5MM]
Pin	Pin Name	Net	Notes
1	1	+5v0-CH0
2	2	NP0-EXT
3	3	GND
4	4	GND
5	5	BTN0-EXT
6	6	+5v0

5.4 J4 WIREPAD-22AWG-4X-3.5MM

J4 - WIREPAD-22AWG-4X-3.5MM (WIREPAD-22AWG-4X-3.5MM) [WIREPAD-22AWG-4X-3.5MM]
Pin	Pin Name	Net	Notes
1	1	+5v0-CH1
2	2	NP1-EXT
3	3	AUX1-EXT
4	4	GND

5.5 J5 WIREPAD-22AWG-3X-3.5MM

J5 - WIREPAD-22AWG-3X-3.5MM (WIREPAD-22AWG-3X-3.5MM) [WIREPAD-22AWG-3X-3.5MM]
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	CHG-LOOP
3	3	GND

5.6 J6 WIREPAD-22AWG-2X-3.5MM

J6 - WIREPAD-22AWG-2X-3.5MM (WIREPAD-22AWG-2X-3.5MM) [WIREPAD-22AWG-2X-3.5MM]
Pin	Pin Name	Net	Notes
1	1	SP-
2	2	SP+

5.7 J7 TAG-CONNECT-SWD (SWD)

J7 - TAG-CONNECT-SWD (SWD)
Pin	Pin Name	Net	Notes
1	VCC	VDD
2	SWDIO	SWDIO
3	RST	RESET
4	SWDCLK	SWDCLK
5	GND	GND
6	SWO	NC

5.8 J8 USB4145-03-0230-C

J8 - USB4145-03-0230-C
Pin	Pin Name	Net	Notes
A1	GND_A	GND
A4	VBUS_A	+VBUS
A5	CC1	CC1
A6	DP1	USB-DEVICE-D_P
A7	DN1	USB-DEVICE-D_N
A8	SBU1	NC
A9	VBUS_A	+VBUS
A12	GND_A	GND
B1	GND_B	GND
B4	VBUS_B	+VBUS
B5	CC2	CC2
B6	DP2	USB-DEVICE-D_P
B7	DN2	USB-DEVICE-D_N
B8	SBU2	NC
B9	VBUS_B	+VBUS
B12	GND_B	GND
S1	SHIELD	GND
S2	SHIELD	GND
S3	SHIELD	GND
S4	SHIELD	GND

5.9 J9 20021121-00010T4LF (SWD)

J9 - 20021121-00010T4LF (SWD) (20021121-00010T4LF) [20021121-00010T4LF]
Pin	Pin Name	Net	Notes
1	VCC	VDD
2	SWDIO/TMS	SWDIO
3	GND	GND
4	SWDCLK/TCK	SWDCLK
5	GND	GND
6	SWO/TDO	NC
7	KEY	NC
8	TDI	NC
9	GND_DETECT	GND
10	RST	RESET

6 Indicator Documentation

2 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D16	LED-GREEN	Green	D16_C, R35_2	cricket-node-hw--top-level_B.SchDoc	LOW = On; R35 (330Ω); A:+5v0 K:D16_C, R35_2
D15	LED-RED	Red	D15_C, R34_2	cricket-node-hw--top-level_B.SchDoc	LOW = On; R34 (330Ω); A:+5v0 K:D15_C, R34_2

6.2 Indicator Testability

0 of 2 indicators have test coverage.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D16	Direct	D16_C, R35_2	Design Warning: Test point needed on D16_C, R35_2. Drive HIGH to turn on LED D16.
D15	Direct	D15_C, R34_2	Design Warning: Test point needed on D15_C, R34_2. Drive HIGH to turn on LED D15.

7 Switch Documentation

No switches or push buttons found in design.

8 Low-Speed Serial Interfaces (LSSI)

Detected: 2 SWD

8.1 SWD

SWD -> U5
Topology: Access (J7, J9, TP21, TP22) » Targets (U5)
Signal	Net Name	Connector	Test Point	Target Pin
SWCLK	SWDCLK	J7_4, J9_4	TP22_1	U5_AA24 (SWDCLK)
SWDIO	SWDIO	J7_2, J9_2	TP21_1	U5_AC24 (SWDIO)
NRST	RESET	J7_3, J9_10	TP23_1	U5_AC13 (P0.18/RESET)
Target	Industry Type	Description
U5	NRF52840-QIAA-R	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN

SWD -> U5
Topology: Access (J7, J9, TP21, TP22) » Targets (U5)
Signal	Net Name	Connector	Test Point
SWCLK	SWDCLK	J7, J9	TP22_1
SWDIO	SWDIO	J7, J9	TP21_1
NRST	RESET	J7, J9	TP23_1
Target	Industry Type	Description
U5	NRF52840-QIAA-R	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN

8.2 LSSI DFT Analysis

All serial interface signals have test point coverage.

9 High-Speed Serial Interfaces (HSSI)

2 differential pair(s)

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 1 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
USB-DEVICE-D_P/N	USB

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Full-Speed Device Port (J8)

AI-Assisted — The only differential interface in the design is the USB 2.0 device port on the Type-C receptacle J8 (USB4145-03-0230-C). USB-DEVICE-D_P runs from J8 pins A6 and B6 to U5 pin AD6 (D+), and USB-DEVICE-D_N from J8 pins A7 and B7 to U5 pin AD4 (D-), with U15 (PRTR5V0U2X) IO1/IO2 on the pair and test points TP3/TP4. No series components sit in either leg, which is correct: USB 2.0 (USB 2.0 specification, chapter 7) is DC-coupled and requires no AC coupling capacitors; termination is on-die in the nRF52840 USB PHY, so no external resistors are expected. The pair requires 90 ohm differential controlled impedance; the two nets are grouped as a differential pair but carry no impedance class assignment, which must be set as a net class in the schematic tool so layout inherits it. U15 adds about 1 pF per line to ground (Nexperia PRTR5V0U2X datasheet, https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf), acceptable for 12 Mbit/s full speed. Its standoff of 5.5 V max and clamp of 17 V typical at 2.5 A (8/20 us) sit above the D+/D- absolute maximum of VDD+0.3 V; the nRF52840 states no matching transient rating, so this comparison cannot be closed and is reported as a note. Both CC lines are terminated with 5.1k resistors R37 (CC1) and R36 (CC2) to GND, the correct sink-only Rd configuration. VBUS reaches U5 pin AD2 and U15 VCC directly; DECUSB carries C20, 4.7 uF, matching the Nordic nRF52840 reference circuitry.

9.3 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.3.1	J8 D+/D- to U5	USB 2.0 full speed	No 90 ohm differential impedance class assigned to USB-DEVICE-D_P / USB-DEVICE-D_N; set it as a net class before layout	Medium
9.3.2	+VBUS	USB PHY supply	No bulk capacitor on +VBUS; Nordic reference circuitry fits 4.7 uF at the USB regulator input for stability	Medium
9.3.3	U15 clamp vs U5 D+/D-	ESD protection	Clamp 17 V typ at 2.5 A (8/20 us) versus a DC absolute maximum of VDD+0.3 V on D+/D-; nRF52840 states no comparable transient rating, so the margin cannot be closed	Review
9.3.4	X1 32 MHz HFXO	USB bit clock	C22/C21, 8pF each, give 4.00 pF series against a 12 pF-per-pin reference; stray assumption not stated, pulling unverifiable	Review
9.3.5	J8 D+/D- to U5	USB 2.0 full speed	DC-coupled pair with no series capacitors — correct, USB 2.0 requires no AC coupling (USB 2.0 specification ch. 7)	✓
9.3.6	J8 D+/D- to U5	USB 2.0 full speed	Termination is on-die in the nRF52840 USB PHY; no external termination expected or fitted (Nordic nRF52840 datasheet)	✓
9.3.7	U15 on D+/D-	ESD protection	Line capacitance 1 pF typ, 1.5 pF max per channel — negligible at 12 Mbit/s (Nexperia PRTR5V0U2X datasheet)	✓
9.3.8	J8 CC1/CC2	USB Type-C	R37 and R36, 5.1k to GND, correct Rd sink configuration	✓
9.3.9	J8 connector	USB 2.0	Type-C receptacle is an impedance-controlled connector suited to the signal rate	✓
9.3.10	DECUSB	USB regulator output	C20, 4.7uF, matches the Nordic nRF52840 reference circuitry value	✓
9.3.11	VDD / DEC nodes	PHY supply filtering	VDD 5.3 uF total behind L1, 10uH; DEC4 and DEC6 tied together with 1.094 uF as required (Nordic nRF52840 datasheet)	✓

9.4 Citations

AI-Assisted —

References
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
PRTR5V0U2X (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 U12 QSPI

U12 (MX25R6435FZNIL0) - QSPI [4-bit data]
Signal	Pin Name	Pin #	Net Name	Test Point
CLOCK	SCLK	6	QSPI-SCLK / P0.14	-
DATA_0	SIO0/SI	5	P0.21 / QSPI-D0	-
DATA_1	SIO1/SO	2	QSPI-D1 / P0.22	-
DATA_2	SIO2/WP	3	QSPI-D2 / P0.20	-
DATA_3	SIO3/RESET	7	QSPI-D3 / P0.23	-
SELECT	CS	1	QSPI-CS / P0.24	-
DESIGN_WARNING: Test points needed on P0.21, QSPI-CS, QSPI-D1, QSPI-D2, QSPI-D3 and QSPI-SCLK for direct on-board programming
U12 is in-system programmable via U5 (nRF52840-QIAA) over SWD. A debug probe on the SWD port loads a programming routine into U5, which then drives the memory bus

10.2 AI-Assisted Analysis

10.2.1 QSPI Flash U12 (MX25R6435FZNIL0)

AI-Assisted — U12 is a 64 Mbit ultra-low-power serial flash wired point-to-point to the nRF52840 (U5) QSPI peripheral: SCLK on QSPI-SCLK (P0.14), CS# on QSPI-CS (P0.24), and the four data lines SIO0..SIO3 on P0.21, P0.22, P0.20 and P0.23. All six bus signals are single-load nets with no series damping resistors and no stubs, which is the correct topology for this interface. VCC (pin 8) sits on VDD and both GND pins (4 and 9) are on the board ground, so the device has proper DC supply and return paths. Decoupling on VDD totals 5.3 uF across seven capacitors (1x4.7uF plus six 0.1uF), shared with U5, U13, U4 and U10; the 0.1uF X7R parts provide local high-frequency bypass for the flash. Per the Macronix datasheet (https://www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R6435F,%20Wide%20Range,%2064Mb,%20v1.6.pdf), quad read (4READ/QREAD) is limited to 8 MHz in the default Ultra Low Power Mode, and 33 MHz applies to single-lane FAST_READ and 4PP. The nRF52840 QSPI defaults to 32 MHz, so firmware must set the divider accordingly or enable High Performance Mode. CS# has no pull-up to VDD; with SIO3 doubling as RESET# and no pull-up either, both lines float while U5 is in reset or under SWD control, leaving the flash exposed to spurious selection and reset assertion. VDD is stated as 1.8-3.3V, inside the 1.65-3.6 V supply window of the part.

10.2.2 SPI FRAM U13 (FM25L16B-GTR)

AI-Assisted — U13 is a 16 Kbit SPI FRAM on a separate, dedicated bus from the QSPI flash: FRAM-CS (P1.02), FRAM-CLK (P0.25), FRAM-SDI (P1.04, driven by U5) and FRAM-SDO (P1.03, driven by U13). Directions are consistent — one slave input and one slave output on separate wires — so there is no bus contention. HOLD# is pulled to VDD through R38 (pin 1 on the HOLD# net, pin 2 on VDD) and WP# is pulled to VDD through R14 (pin 1 on the WP# net, pin 2 on VDD); both are the correct passive de-assertions and permit write access under firmware control. VCC (pin 8) is on VDD and VSS (pin 4) is on ground. There is no dedicated local bypass capacitor uniquely assigned to U13; it shares the VDD bulk and 0.1uF network. Chip select FRAM-CS has no pull-up, so the device can see a floating select during MCU reset — for a non-volatile store this is the higher-consequence case of the two, since an inadvertent write cycle is destructive rather than merely disruptive. The 20 MHz interface rating comfortably exceeds anything the nRF52840 SPIM will present on this bus.

10.3 Observations

AI-Assisted — Both memory devices sit on VDD, whose stated operating window is 1.8-3.3V. The flash is specified 1.65-3.6 V and functions across the whole window; the FRAM's minimum supply is 2.0 V, so a valid operating point exists inside the stated range but the low end of the window is not usable for U13 — the rail must be set at or above 2.0 V. Neither memory has series termination on clock or data; with point-to-point routing and the modest clock rates involved this is appropriate, but keep the QSPI group length-matched and short at layout. No test point is provided on any memory bus signal, so in-system fault isolation on the flash and FRAM buses depends entirely on the SWD access at J7/J9.

10.4 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.4.1	U12 MX25R6435FZNIL0	QSPI Flash	No pull-up on CS#; line floats while U5 is held in reset, allowing spurious selection — add a 10k pull-up to VDD (Macronix datasheet)	Medium
10.4.2	U12 MX25R6435FZNIL0	QSPI Flash	SIO3/RESET# has no pull-up; in quad mode the pin is a data line, but during reset it is undriven and can assert RESET# — add a pull-up to VDD (Macronix datasheet)	Medium
10.4.3	U13 FM25L16B-GTR	SPI FRAM	No pull-up on FRAM-CS; floating select during MCU reset risks an unintended write to non-volatile storage — add a pull-up to VDD (Infineon datasheet, source: Tomachie)	Medium
10.4.4	U12 MX25R6435FZNIL0	QSPI Flash	Quad read limited to 8 MHz in default Ultra Low Power Mode; nRF52840 QSPI default clock exceeds this, requires divider or High Performance Mode (Macronix datasheet)	Low
10.4.5	U13 FM25L16B-GTR	SPI FRAM	VDD stated as 1.8-3.3V; device minimum supply is 2.0 V, so the rail must be set at or above 2.0 V (Infineon datasheet, source: Tomachie)	Review
10.4.6	U12 / U13	Test access	No test points on any memory bus signal; fault isolation depends on SWD at J7/J9 (design review observation)	Review
10.4.7	U12 MX25R6435FZNIL0	QSPI Flash	Point-to-point 4-lane topology, no stubs; all six signals single-load to U5 — correct (Macronix datasheet)	✓
10.4.8	U12 MX25R6435FZNIL0	QSPI Flash	VCC on VDD, both GND pins on ground; DC paths correct (Macronix datasheet)	✓
10.4.9	U12 MX25R6435FZNIL0	QSPI Flash	No series damping on SCLK/data; acceptable for point-to-point at 8-33 MHz (Macronix AC characteristics)	✓
10.4.10	U12 MX25R6435FZNIL0	QSPI Flash	VDD 1.8-3.3V within the 1.65-3.6 V supply range; industrial -40 to 85 C grade (Macronix datasheet)	✓
10.4.11	U13 FM25L16B-GTR	SPI FRAM	Dedicated SPI bus, SDI/SDO on separate nets with consistent directions — no multi-slave direction conflict (Infineon datasheet, source: Tomachie)	✓
10.4.12	U13 FM25L16B-GTR	SPI FRAM	HOLD# pulled to VDD via R38 and WP# pulled to VDD via R14 — correct de-assertion (Infineon datasheet, source: Tomachie)	✓
10.4.13	U13 FM25L16B-GTR	SPI FRAM	VCC on VDD, VSS on ground; DC paths correct (Infineon datasheet, source: Tomachie)	✓
10.4.14	U12 / U13	Shared VDD	Decoupling on VDD totals 5.3 uF (1x4.7uF + 6x0.1uF) shared across U5, U12, U13, U4, U10; local 0.1uF bypass present (Macronix / Infineon datasheets)	✓

10.5 Citations

AI-Assisted —

References
MX25R6435F (Ultra Low Power Mode - Default) (Macronix International Co., Ltd.) — datasheet, cited pages 1 www.macronix.com/Lists/Datasheet/Attachments/8868/MX25R64...

11 Functional Analysis

11 device(s) to review across 6 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
U2	COMMUNICATION	TJA1021T/20/CM,118	1 Transceiver Full Duplex 1 SOIC-8 LIN Transceivers ROHS	-	-
U11	DEVICE	TLV271CW5-7	Single 1pA 2V/us 1.9MHz SOT-25 Operational Amplifier ROHS	-	-
U13	DEVICE	FM25L16B-GTR	16Kbit 20MHz SPI SOIC-8 FRAM ROHS	-	-
U14	DEVICE	MAX98357AETE+T	Monaural 3.2Wx2@4O TQFN-16-EP(3x3) Audio Amplifiers ROHS	-	-
X1	DEVICE	ECS-320-8-37B-CKY-TR	32MHz 8pF ±10ppm SMD2016-4P	-	-
X2	DEVICE	NX3215SA-32.768K-STD-MUA-9	32.768kHz 9pF ±20ppm SMD3215-2P	-	-
D2	DIODE	BZX84B16-7-F	DIODE ZENER 16V 300MW SOT23	-	-
D3	DIODE	BAS16-7-F	DIODE SWITCHING 75V 200MA SOT23	-	-
U15	Prot.	PRTR5V0U2X,215	6V Unidirectional 5.5V SOT-143 ESD and Surge Protection (TVS/ESD) ROHS	-	-
Q2	Trans.	BSS84-7-F	MOSFET P-CH 50V 130MA SOT23-3	-	-
U5	WIRELESS	NRF52840-QIAA-R	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN	SWD	-

11.1 Functional Analysis

11.1.1 LIN transceiver U2 (TJA1021T/20/CM)

AI-Assisted — U2 is supplied on VBAT through the P-channel switch Q1 from +VIN-PROTECT, so the transceiver can be powered down under MCU control (P0.27 driving Q4); GND is on the board ground and the VBAT limiting value of 40 V comfortably covers the stated 10.8–16.0 V input window. RXD is an open-drain output and is correctly pulled up by R11 10kΩ from VDD to LIN-RX-OUT, which also feeds P0.30. SLP_N is driven directly from P0.31; the internal pull-down means the device falls back to Sleep mode if the MCU rail is absent, which is the intended fail-safe behaviour per the NXP TJA1021 datasheet. WAKE_N is biased to the switched VBAT node through R8 100kΩ and pulled low by Q5, giving the negative-edge local wake-up the datasheet describes, so the pin is used rather than left to float. TXD from P0.29 has no external pull-up: the NXP datasheet states an external pull-up from TXD to the microcontroller supply is needed so that the wake-up source (local versus remote, signalled by a weak or strong internal pull-down) can be read during Standby mode; as wired only the strong local pull-down state is distinguishable unless the internal pull-up of the nRF52840 GPIO is enabled in firmware. The bus pin LIN reaches J1/J2 and carries the PESD1IVN24-AX bidirectional protector, whose 24 V standoff sits above the LIN recessive level at the top of the input window and whose 30.5 V typical breakdown stays inside the 40 V LIN limiting value.

11.1.2 LIN commander termination network (Q2, D2, D3)

AI-Assisted — The commander pull-up required by the NXP datasheet — a series resistor plus diode between INH or VBAT and the LIN line — is implemented switchably: R7 1kΩ in series with the BAS16 D3 from the INH node through the BSS84 Q2, enabled when P1.06 turns on Q3 and pulls the Q2 gate down through R3 10kΩ. R2 100kΩ from gate to source holds Q2 off by default, and with R3 in series the gate–source voltage settles at about 0.91 times VBAT, i.e. roughly 10.9 V at 12 V input and 14.5 V at the 16 V top of the window — past the −2.0 V maximum threshold with wide margin and inside the ±20 V gate rating of the Diodes Incorporated BSS84. D2 (BZX84B16, 15.7–16.3 V) sits anode-on-gate, cathode-on-source and acts purely as a gate–source backstop; it is correctly oriented and, at the computed 14.5 V worst case, does not conduct in normal operation. Q2 drain current in the dominant state is about 11 mA through R7, far below the −130 mA continuous rating, and drain–source stress when off is one battery voltage against the −50 V rating. D3 carries the same ~11 mA against its 215 mA average rating and blocks the bus with 100 V of reverse capability. As a general preference for series blocking elements of this kind — and wherever a MOSFET is deliberately held off to act as a clamp — a Schottky diode is the better choice: the BAS16 drops up to 0.855 V at 10 mA per the Nexperia datasheet, which is subtracted directly from the commander pull-up headroom.

11.1.3 Sense buffer U11 (TLV271)

AI-Assisted — U11 is wired as a unity-gain follower: output and inverting input are tied together on P0.02/AIN0 and the non-inverting input takes the tap of the R26 100kΩ / R28 10kΩ divider, which is gated to +VIN-PROTECT by Q7. The divider ratio of 0.0909 puts the buffer input at 1.09 V at the nominal 12 V input and 1.45 V at the 16 V top of the stated input window, so the buffered value stays inside the ADC range even if VDD is programmed to the 1.8 V bottom of its range. R28 also holds the input at ground whenever Q7 is off, so the buffer input is never floating. The output drives the MCU analogue input directly with no capacitive load fitted; the Diodes Incorporated TLV271 datasheet only calls for a series RNULL of at least 20 Ω when driving more than 100 pF, so the direct connection is acceptable as drawn, though a small series resistor would also serve as the anti-alias element for the sampling input. Ground is on the board ground net and the supply comes from P0.03, the same signal that gates the divider.

11.1.4 FRAM U13 (FM25L16B-GTR)

AI-Assisted — U13 sits on its own SPI channel — FRAM-CS from P1.02, FRAM-CLK from P0.25, D (SDI) from P1.04 and Q (SDO) to P1.03 — entirely separate from the QSPI flash bus, so there is no shared data line and no direction conflict between the two memories. HOLD is held at VDD through R38 100kΩ and WP through R14 100kΩ; the Infineon/Cypress FM25L16B datasheet requires both to be tied to VDD when unused, and with ±1 µA maximum input leakage the 100 kΩ pull-ups hold the pins within 0.1 V of the rail, well above the 0.7×VDD input-high threshold. Note that with WP held high the status-register write protection is not asserted, so write protection depends entirely on the WEL bit in firmware. Chip select has no pull-up to VDD: while the MCU GPIOs are high-impedance during reset and for the 1 ms power-up delay the datasheet specifies before the first CS low, the select line is undriven, and a pull-up would guarantee the device stays deselected across those windows. The 20 MHz maximum clock frequency bounds the SPI bit rate that may be configured for this channel.

11.1.5 Class-D amplifier U14 (MAX98357A)

AI-Assisted — U14 runs from +5v0, inside the 2.5–5.5 V supply range, and the 0.1 µF and 10 µF ceramics called for by the Maxim datasheet are both present on that rail (C26 0.1µF and C27 10µF). All three ground pins and the exposed pad are on the board ground net, satisfying the thermal and reference path for the TQFN package. GAIN_SLOT is returned to ground through R33 100kΩ, which per the datasheet gain table selects the 15 dB setting (14.4–15.6 dB) — the highest of the five options; at 5 V into a 4 Ω load this is the configuration that reaches the 3.2 W figure, and the input drive level from the I2S source must be scaled accordingly. SD_MODE is driven directly from P0.05: the datasheet places the B2 comparator trip at 1.5 V maximum, so a logic high selects the left channel of the stereo stream. Because VDD for the MCU is programmable over 1.8–3.3 V, the worst-case high level is 1.8 V, only 0.3 V above that 1.5 V trip point — a valid setting exists, but the rail should be programmed toward the upper end for a comfortable channel-select margin. The same consideration applies to DIN, BCLK and LRCLK, whose 1.3 V minimum input-high leaves 0.5 V of margin at a 1.8 V rail; those pins tolerate up to 6 V, so 3.3 V drive into the 5 V-powered amplifier is safe. The bridge outputs reach J6 through the ferrite beads L5/L6 (220 Ω at 100 MHz, 3 A, 40 mΩ) — no output LC filter is required by the filterless modulator, and the ~0.9 A RMS at full output is well inside the bead rating.

11.1.6 Crystals X1 and X2

AI-Assisted — X1 (32 MHz, ±10 ppm) is wired across XC1 and XC2 and X2 (32.768 kHz, ±20 ppm) across P0.00/XL1 and P0.01/XL2 — the correct oscillator terminals in both cases. Frequency accuracy is appropriate for the radio: ±10 ppm on the high-frequency reference is inside the tolerance Bluetooth low energy operation demands, and ±20 ppm on the low-frequency crystal is far tighter than any sleep-clock requirement. The NDK NX3215SA part carries a 9.0 pF load capacitance, a 70 kΩ maximum ESR and a 0.5 µW maximum drive level; both oscillator networks use 8pF shunt capacitors per terminal, which the power review has already assessed against Nordic's 12 pF reference figure, and the stray contribution cannot be resolved from the schematic. No series drive-limiting resistor is fitted on the low-frequency loop, which is normal for the nRF52840 LFXO but leaves the 0.5 µW drive-level limit to be governed by the oscillator's internal drive setting.

11.1.7 USB ESD protection U15 (PRTR5V0U2X)

AI-Assisted — U15 is correctly placed as a rail-referenced array: IO1 and IO2 sit on the D+ and D− pairs between the Type-C receptacle and the MCU, GND on board ground, and VCC on +VBUS. The 5.5 V maximum standoff is at or above the 5 V USB bus level, so the device does not conduct in normal operation, and the 1 pF typical line capacitance per the Nexperia datasheet is negligible for USB 2.0 full-speed signalling. The device works by diverting positive transients into the VCC rail; because +VBUS carries no local capacitance, that diverted charge has no reservoir to sink into, which raises the effective let-through at the protected pins — a functional consequence of the missing VBUS bulk capacitor already raised in the power review. The 17 V typical clamping figure is specified at 2.5 A with an 8/20 µs waveform; the nRF52840 data provides no transient rating for the D+/D− pins under that waveform, so the coordination between clamp and protected input cannot be closed from the available specifications and is reported as an open item rather than a violation.

11.1.8 Host MCU U5 (nRF52840-QIAA-R)

AI-Assisted — The high-voltage supply path is coherent: VDDH takes the diode-OR of +5v0 and +VBUS through D6/D7 and the 0 Ω link R13, giving roughly 4.1–4.7 V at the pin after the BAS16 forward drop — inside the 2.5–5.5 V VDDH range and well below the 5.8 V absolute maximum even with a 5.5 V USB bus. The DCCH output feeds VDD through L1, and the low-voltage DC/DC on DCC uses the L3 10 µH plus L2 15 nH ladder into the DEC4/DEC6 node, where DEC4 and DEC6 are joined on the same net exactly as the Nordic datasheet requires; DEC1, DEC2, DEC3 and DECUSB all carry the values shown in Nordic's reference circuitry (C17 0.1µF, C18 0.1µF, C19 100pF and C20 4.7µF respectively). The ANT pin is left unconnected and no matching network or antenna feed is fitted anywhere on the board, so the radio is unusable in this build — an omission this visible reads as a deliberate build option rather than an error, but it should be dispositioned explicitly. SWO is not available for trace: the debug footprint J7 has its SWO pad unconnected, and P1.00, the trace output pin, is committed to the green LED driver. SWDIO, SWDCLK and RESET are common to J7 and J9 with test points on each, giving two mechanically distinct debug attachment options. P0.09/NFC1 and P0.10/NFC2 are used as board-identification inputs alongside P0.11, each pulled to ground through 100 kΩ; the NFC pair carries a dual antenna function in the Nordic pin list and must be released to GPIO use in the device configuration registers, and as populated all three straps read low, so only identifier zero is encoded by the fitted parts. The Type-C configuration channels present 5.1 kΩ to ground on both CC pins, the correct sink-role termination for the USB device port on P0.02-independent hardware.

11.1.9 Clocks and PHY Supply Filtering

AI-Assisted — The USB PHY derives its bit clock from the 32 MHz HFXO X1 (ECS-320-8-37B-CKY-TR) on XC1/XC2 with C22 and C21, 8 pF each, presenting 4.00 pF in series against the 12 pF-per-pin figure in the Nordic reference circuitry; the stray assumed by that reference is not stated, so the resulting pulling cannot be quantified and the pair is reported as unverifiable rather than wrong. X2 (32.768 kHz) with C24/C23, 8 pF each, serves the LFXO only and is not in the USB clock path. VDD is filtered through L1, 10uH, from the DCCH regulator output and carries 5.3 uF total including four 0.1uF parts and C6, 4.7uF, matching the reference bulk plus per-pin decoupling. The 1.3 V regulator node feeding DEC4 and DEC6 is tied together as the datasheet requires, with 1.094 uF total, close to the 1.0 uF reference value; DEC1 has C17, 0.1uF, per the reference. VBUS is unfiltered and unbypassed apart from the PHY's internal path — no capacitor sits on +VBUS, while the Nordic reference fits 4.7 uF there for USB regulator input stability.

11.2 Findings

AI-Assisted —

#	Device	Finding	Severity
11.2.1	U2 (TJA1021T/20/CM)	TXD (P0.29) has no external pull-up. The datasheet states a pull-up to the microcontroller supply is needed to read the wake-up source (local versus remote) during Standby mode; the nRF52840 internal GPIO pull-up can serve this function if enabled. NXP TJA1021 datasheet.	Review
11.2.2	D3 (BAS16-7-F)	Silicon switching diode drops up to 0.855 V at 10 mA, subtracted directly from the commander pull-up headroom; a Schottky is the preferable element in this series position, and likewise wherever a MOSFET is held intentionally off to act as a clamp. Nexperia BAS16 datasheet.	Review
11.2.3	U13 (FM25L16B-GTR)	No pull-up on FRAM-CS: the select line is undriven while the MCU GPIOs are high-impedance during reset and across the specified 1 ms power-up delay before the first CS low. A pull-up to VDD would guarantee the device stays deselected. Infineon/Cypress FM25L16B datasheet.	Review
11.2.4	U14 (MAX98357A)	SD_MODE driven from P0.05 selects the left channel above the 1.5 V maximum B2 trip; with VDD programmable down to 1.8 V the worst-case high sits only 0.3 V above that trip and DIN/BCLK/LRCLK have 0.5 V over the 1.3 V input-high minimum. A valid setting exists — program VDD toward the upper end. Maxim MAX98357A datasheet.	Review
11.2.5	X2 (NX3215SA-32.768K)	9.0 pF load capacitance, 70 kΩ maximum ESR and 0.5 µW maximum drive level; no series drive-limiting resistor is fitted, so drive level depends on the internal oscillator setting. NDK NX3215SA datasheet.	Review
11.2.6	U15 (PRTR5V0U2X)	The 17 V typical clamping figure is specified at 2.5 A, 8/20 µs; no transient rating is given for the nRF52840 D+/D− pins under that waveform, so the clamp-to-protected-pin coordination cannot be closed. Diverted charge also has no local reservoir on +VBUS, raising effective let-through. Nexperia PRTR5V0U2X and Nordic nRF52840 datasheets.	Review
11.2.7	U5 (NRF52840-QIAA-R)	The ANT pin is unconnected and no matching network or antenna feed is fitted on the board — the radio is unusable as built. Almost certainly a deliberate build option; disposition explicitly. Nordic nRF52840 datasheet.	Review
11.2.8	U5 (NRF52840-QIAA-R)	No SWO trace output available: the SWO pad on the debug footprint J7 is unconnected and P1.00, the trace pin, drives the green LED. SWDIO, SWDCLK and RESET are common to J7 and J9 with test points. Nordic nRF52840 datasheet.	Review
11.2.9	U5 (NRF52840-QIAA-R)	P0.09/NFC1 and P0.10/NFC2 are used as board-ID inputs with 100 kΩ pull-downs alongside P0.11; the NFC pair carries a dual antenna function and must be released to GPIO use in the device configuration registers, and as populated all three straps read low so only identifier zero is encoded. Nordic nRF52840 datasheet.	Review
11.2.10	U2 (TJA1021T/20/CM)	VBAT supplied from +VIN-PROTECT through the Q1 P-channel switch; 40 V VBAT limiting value covers the 10.8–16.0 V input window. GND on board ground. NXP TJA1021 datasheet.	✓
11.2.11	U2 (TJA1021T/20/CM)	RXD open-drain output pulled up by R11 10kΩ from VDD to LIN-RX-OUT; required external pull-up present. NXP TJA1021 datasheet.	✓
11.2.12	U2 (TJA1021T/20/CM)	SLP_N driven from P0.31; internal pull-down gives the fail-safe Sleep default when the pin is unsupplied. WAKE_N biased to VBAT through R8 100kΩ and pulled low by Q5 for the negative-edge local wake-up. NXP TJA1021 datasheet.	✓
11.2.13	U2 (TJA1021T/20/CM)	Commander termination implemented as required: R7 1kΩ in series with D3 from the INH node to LIN, switched by Q2. NXP TJA1021 datasheet.	✓
11.2.14	Q2 (BSS84-7-F)	Gate–source voltage set by R2 100kΩ / R3 10kΩ at about 0.91×VBAT, giving 10.9 V at 12 V and 14.5 V at 16 V — past the −2.0 V maximum threshold and inside the ±20 V gate rating; drain current about 11 mA against the −130 mA continuous rating, Vds stress one battery voltage against −50 V. Diodes Incorporated BSS84 datasheet.	✓
11.2.15	D2 (BZX84B16-7-F)	Anode on the Q2 gate, cathode on the source: gate–source clamp at 15.7–16.3 V, correctly oriented and non-conducting at the computed 14.5 V worst-case drive. Diodes Incorporated BZX84B16 datasheet.	✓
11.2.16	D3 (BAS16-7-F)	Series blocking diode in the commander pull-up: about 11 mA against the 215 mA average rating and 100 V reverse capability against the 40 V LIN limiting value. Nexperia BAS16 datasheet.	✓
11.2.17	U11 (TLV271CW5-7)	Unity-gain follower with output tied to the inverting input; R26 100kΩ / R28 10kΩ tap gives 1.09 V at 12 V input and 1.45 V at 16 V, inside the ADC range even at the 1.8 V bottom of the programmable VDD. R28 holds the input at ground when Q7 is off. Diodes Incorporated TLV271 datasheet.	✓
11.2.18	U11 (TLV271CW5-7)	Output drives P0.02 directly with no capacitive load fitted; the datasheet requires a series RNULL of at least 20 Ω only above 100 pF, so the direct connection is acceptable. Diodes Incorporated TLV271 datasheet.	✓
11.2.19	U13 (FM25L16B-GTR)	HOLD tied to VDD through R38 100kΩ and WP through R14 100kΩ, satisfying the requirement that both be tied to VDD when unused; ±1 µA leakage keeps both within 0.1 V of the rail, above the 0.7×VDD input-high threshold. Infineon/Cypress FM25L16B datasheet.	✓
11.2.20	U13 (FM25L16B-GTR)	Dedicated SPI channel (P1.02/P0.25/P1.04/P1.03), separate from the QSPI flash bus — no shared data line, no direction conflict. Maximum clock 20 MHz bounds the configurable bit rate. Infineon/Cypress FM25L16B datasheet.	✓
11.2.21	U14 (MAX98357A)	Supplied from +5v0 within the 2.5–5.5 V range with the specified 0.1 µF (C26) and 10 µF (C27) ceramics on the rail; all three ground pins and the exposed pad on board ground. Maxim MAX98357A datasheet.	✓
11.2.22	U14 (MAX98357A)	GAIN_SLOT returned to ground through R33 100kΩ selects the 15 dB gain setting (14.4–15.6 dB) — the highest of the five options; source drive level must be scaled for this gain. Maxim MAX98357A datasheet.	✓
11.2.23	U14 (MAX98357A)	Bridge outputs reach J6 through ferrites L5/L6 (220 Ω at 100 MHz, 3 A, 40 mΩ); no output LC filter is required by the filterless modulator and the ~0.9 A RMS at full output is inside the bead rating. Maxim MAX98357A and TDK MPZ2012S221 datasheets.	✓
11.2.24	X1, X2	X1 across XC1/XC2 and X2 across XL1/XL2 — correct oscillator terminals. ±10 ppm at 32 MHz suits Bluetooth low energy operation and ±20 ppm at 32.768 kHz is far tighter than any sleep-clock requirement. Nordic nRF52840, ECS and NDK datasheets.	✓
11.2.25	U15 (PRTR5V0U2X)	Correctly placed rail-referenced array on D+/D− with GND on board ground and VCC on +VBUS; 5.5 V standoff at or above the 5 V bus level and 1 pF typical line capacitance suits USB 2.0 full-speed. Nexperia PRTR5V0U2X datasheet.	✓
11.2.26	U5 (NRF52840-QIAA-R)	VDDH takes the D6/D7 diode-OR of +5v0 and +VBUS through the 0 Ω link R13, giving about 4.1–4.7 V after the forward drop — inside the 2.5–5.5 V range and below the 5.8 V absolute maximum. Nordic nRF52840 datasheet.	✓
11.2.27	U5 (NRF52840-QIAA-R)	DEC4 and DEC6 are joined on the same node as explicitly required; DEC1 (C17 0.1µF), DEC2 (C18 0.1µF), DEC3 (C19 100pF) and DECUSB (C20 4.7µF) match the reference circuitry, and the DCC path uses the L3 10 µH plus L2 15 nH ladder. Nordic nRF52840 datasheet.	✓

11.3 Citations

AI-Assisted —

References
2N7002P (Nexperia) — datasheet, cited pages 2,3 assets.nexperia.com/documents/data-sheet/2N7002P.pdf
AP22804 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/AP22804.pdf
AP64352 (Diodes Incorporated) — datasheet AP64352SP-13.pdf
APT2012CGCK (Kingbright) — datasheet APT2012CGCK.pdf
APT2012SURCK (Kingbright) — datasheet, cited pages 1,2 www.kingbrightusa.com/images/catalog/spec/apt2012surck.pdf
BAS16 (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/BAS16.pdf
BSS138K (onsemi) — datasheet, cited pages 1,2 www.onsemi.com/download/data-sheet/pdf/bss138k-d.pdf
BSS84 (Diodes Incorporated) — datasheet, cited pages 1 BSS84-7-F.pdf
BZX84B16 (Diodes Incorporated) — datasheet diodes.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
CDRH103RNP-6R8NC-B (Sumida) — datasheet products.sumida.com/products/pdf/CDRH103R.pdf
FM25L16B (Cypress (Infineon Technologies)) — datasheet, cited pages 1,2,4,8,13 via web_fetch
LQG15HS15NJ02D (Murata Mfg Co., Ltd) — datasheet, cited pages 1,5 no.mouser.com/datasheet/2/281/1/JELF243B_0010-1699614.pdf
MAX98357A (Maxim Integrated) — datasheet www.mouser.com/datasheet/2/256/MAX98357A-MAX98357B-271244...
MLZ1608M100WTD25 (TDK) — datasheet, cited pages 1,5,6 MLZ1608M100WTD25.pdf
MPZ2012S221AT000 (TDK) — datasheet product.tdk.com/info/en/catalog/datasheets/beads_commerci...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
NX3215SA-32.768K-STD-MUA-9 (NIHON DEMPA KOGYO CO., LTD. (NDK)) — datasheet, cited pages 1 pdf.datasheet.live/datasheets-1/ndk/NX3215SA-32.768K-STD-...
PESD1IVN24-A (Nexperia) — datasheet PESD1IVN24-AX.pdf
PESD5V0S1BA (Nexperia) — datasheet PESD5V0S1BA.pdf
PRTR5V0U2X (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf
TLV271 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/TLV27x.pdf
ZXMP4A16G (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/ZXMP4A16G.pdf

12 Designer Annotated Nets

No additional annotations are present beyond those already reported in previous sections.

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J8	USB4145-03-0230-C	J8 (USB4145-03-0230-C) [USB4145-03-0230-C]: Shell pins connected directly to logic GND which masks design intent for layout.	Per USB Type-C Specification R2.5, Section 3.2.1: the receptacle shell shall be connected to the PCB ground plane — this is a directive to prevent a floating shell, not a directive to ignore IEC 61000-4-2 ESD requirements and mandate a direct short. Place shell/shield tabs on a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD). This net represents the copper pour under the shielded connector. For plastic enclosed products with no earth ground, add a schematic note for dense via stitching of the shield copper pours to the ground plane with no isolation network. For earth ground connected products, review if the product requires R\|\|C isolation of shields from logic GND to meet ESD compliance (IEC 61000-4-2).

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed:4 connector-facing signal(s). 0 protected, 4 unprotected, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
USB-DEVICE-D_N	J8	No ESD Protection
CC1	J8	No ESD Protection
USB-DEVICE-D_P	J8	No ESD Protection
CC2	J8	No ESD Protection

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture — Grounding, Filtering and Shielding

AI-Assisted — The board uses a single digital ground domain, GND, shared by the USB-C receptacle J8 (shell pins S1-S4 and all GND contacts), the wire-pad field connectors J1-J6, the debug headers and every IC return. There is no separate chassis or shield domain, and no single-point bond element is drawn. For an industrial product under IEC 61000-6-2, the entry-point filtering is uneven: the low-speed field lines BTN0-EXT, NP0-EXT, NP1-EXT and AUX1-EXT each carry a 100Ω series resistor plus a bidirectional TVS to GND, which forms a usable RC/clamp entry filter with the receiving buffer input capacitance; CHG-LOOP carries 100Ω plus a clamp. By contrast the +VIN 12,00V feed at J1, J2 and J5, the +5v0 feed at J3 pin 6, the switched outputs +5v0-CH0 and +5v0-CH1 at J3/J4, and the speaker pair at J6 enter or leave the board with no clamp and no common-mode element. The speaker outputs carry only ferrite beads L5/L6 (220Ω@100MHz) between the MAX98357A filterless Class D outputs and the J6 wire pads; with no shunt capacitance to complete an LC low-pass, the ~300 kHz switching edges leave on unshielded speaker wire, which is a credible radiated-emissions risk against CISPR 32/EN 55032 and conducted coupling back into the +5v0 rail.

13.3.2 J8 — USB 2.0 Type-C Receptacle

AI-Assisted — J8 is a vertical SMT Type-C receptacle and is the primary consumer-facing port. D+/D- (USB-DEVICE-D_P, USB-DEVICE-D_N) are protected by U15, a PRTR5V0U2X,215 dual rail-to-rail array (5,5V working, 6V clamp reference, Nexperia datasheet), wired with GND on pin 1, VCC on +VBUS, and IO1/IO2 on the two data lines directly at the connector ahead of the nRF52840 D+/D- pins — correct topology and correct orientation for a symmetric array. CC1 and CC2 each carry a 5,1kΩ resistor to GND, which is the correct Rd sink advertisement per USB Type-C R2.5, but neither CC contact nor any of the four VBUS contacts (A4, A9, B4, B9) has a transient clamp; VBUS at J8 arrives unfiltered on the +VBUS rail that also feeds U15 pin 4 and the nRF52840 VBUS input. IEC 61000-4-2 ±8 kV contact is the normal acceptance level for a hot-plugged port. U15 pin 4 on +VBUS has no local decoupling shown. Shield handling: S1-S4 share the logic GND net, so the bond strategy is not captured as design intent for layout. In a plastic enclosure, the logic ground plane is the only ESD sink and a direct, densely stitched shield pour bond is appropriate; in an earthed metal chassis, a 1 MΩ || 4,7 nF (≥2 kV) bridge from an isolated shield pour to logic GND with a mechanical bond to earth should be evaluated. A dedicated SHIELD_GND_TYPE_C net makes either choice explicit.

13.3.3 J1, J2 — LIN Bus and +VIN Wire Pads

AI-Assisted — J1 and J2 are 18 AWG wire-pad field connectors carrying the 12,00V (10,80-16,00V) input rail, GND, and the LIN-IO bus, with pin 2 left unconnected on both. LIN-IO is clamped by D4, a PESD1IVN24-AX bidirectional device (24V working, 42V clamping voltage, Nexperia datasheet), sized above the 16,00V maximum rail so it does not conduct at normal bus recessive levels, and terminated through R7 (1kΩ) and D3 (BAS16-7-F, 75V) to the TJA1021T/20 LIN transceiver, whose bus pin carries the transceiver's own ±8 kV IEC 61000-4-2 rating (NXP datasheet). That is a coherent LIN entry stage for a cabled industrial bus. The +VIN contacts on J1, J2 and J5 have no transient clamp of any kind at the entry point: a long unshielded 12 V harness in an industrial installation is exposed to IEC 61000-4-5 surge and IEC 61000-4-4 fast transients, and the first semiconductor seen is the ZXMP4A16GTA reverse/ideal-diode PMOS. A bidirectional clamp rated above 16,00V at the +VIN pads, coordinated with the PMOS VDS rating, is worth investigating.

13.3.4 J3, J4 — Sensor, Button and Addressable-LED Wire Pads

AI-Assisted — J3 (6-way) and J4 (4-way) are external field harnesses. The four signal lines each have a 100Ω series resistor and a PESD5V0S1BA-115 bidirectional clamp (5V working, 14V clamping voltage, Nexperia datasheet) placed on the connector side of the series resistor — correct ordering, since the clamp takes the strike and the resistor limits residual current into the SN74LV1T34 buffers. The buffers run from +5v0, so a 5V working-voltage clamp is a correct match to the driven signal levels. The 14 V clamping voltage exceeds the 5,5 V absolute maximum of the SN74LV1T34 inputs/outputs, but that comparison cannot be closed from the supplied figures: the clamping voltage is quoted at the device's 8/20 µs peak-current condition, and the 100Ω series element sits between the clamp and the buffer, so the actual residual at the buffer pin is not determined by these two numbers alone. The +5v0-CH0 and +5v0-CH1 switched outputs from U1 and U8 leave the board on J3 pin 1 and J4 pin 1 with no clamp; both AP22804AW5-7 switches are rated 2,7V-5,5V, so any inductive kick or ESD returning on those wires reaches the switch output pin directly.

13.3.5 J5 — Charge/Loop Detect

AI-Assisted — J5 combines +VIN, GND and CHG-LOOP on 22 AWG wire pads. CHG-LOOP is pulled by R31 (100kΩ) to P1.15 and sensed through R32 (100Ω) at P1.13 of the nRF52840, with D14 (PESD5V0S1BA-115, 5V working) clamping to GND at the pad. The clamp working voltage is 5V while the adjacent contact on the same connector carries 10,80-16,00V; a wiring or chafe fault that shorts the loop wire to +VIN drives D14 into hard conduction with only the harness resistance in series, so the clamp becomes the fault current path rather than the protection. That is a fault-tolerance observation for a mixed-voltage connector, not a normal-operation defect.

13.3.6 J6 — Speaker Output

AI-Assisted — J6 is a two-pin wire pad carrying SP+/SP- from the MAX98357A Class D amplifier through ferrite beads L5/L6 (MPZ2012S221AT000, 220Ω@100MHz, 3A, 40mΩ). No shunt capacitance to GND is fitted after the beads and no clamp is present, so the beads act as a series impedance rather than a completed low-pass filter. Analog Devices' MAX98357A datasheet notes the filterless modulation scheme relies on the speaker inductance for a short cable; with a field harness on wire pads, an LC or ferrite-plus-capacitor network on both outputs is the standard countermeasure for CISPR 32 radiated emissions. Speaker leads are also an ESD entry path back into the amplifier output stage; the MAX98357A carries no stated connector-level ESD rating in the supplied data.

13.4 Observations

AI-Assisted — The design's field-signal protection philosophy is consistent and well executed on the low-speed I/O and on the LIN bus, where series resistance, clamp selection and clamp placement all follow the intended order. The gaps are concentrated on the power contacts and the audio pair: every DC power entry or exit pad (+VIN at J1/J2/J5, +5v0 at J3, and the two switched channel outputs) reaches a semiconductor with no transient element at the entry point, and the speaker pair leaves the enclosure with an incomplete filter. For an industrial classification, IEC 61000-6-2 immunity (referencing IEC 61000-4-2, -4-4, -4-5) and IEC 61000-6-4 / CISPR 32 emissions are the governing generic standards; the harness-mounted power and audio pads are the interfaces where those tests will concentrate energy. Separately, the shield bond of J8 is not expressed at schematic level, which leaves the layout engineer without net-level guidance on pour separation and bond components. Variant B depopulates J9, so field units expose only the Tag-Connect pads for SWD; RESET, SWDIO and SWDCLK reach the nRF52840 with no series element, which is acceptable for pads that are not cable-accessible in normal use.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J8	VBUS contacts A4/A9/B4/B9 have no transient clamp at the entry point; +VBUS reaches U15 pin 4 and the nRF52840 VBUS input unfiltered. Hot-plug port normally assessed at IEC 61000-4-2 ±8 kV contact.	Medium
13.5.2	J1, J2, J5	+VIN wire pads (10,80-16,00V) have no transient clamp at the entry point; first semiconductor is the ZXMP4A16GTA input PMOS. IEC 61000-4-5 / -4-4 exposure on a long industrial harness.	Medium
13.5.3	J6	Speaker outputs use ferrite beads L5/L6 (220Ω@100MHz) with no shunt capacitance, so no LC low-pass is formed on the filterless Class D output before an external harness — radiated-emissions risk against CISPR 32/EN 55032. Source: Analog Devices MAX98357A datasheet.	Medium
13.5.4	J8	Shell pins S1-S4 share the logic GND net, so the shield bond strategy is not captured as design intent. Recommend a dedicated SHIELD_GND_TYPE_C net; plastic-enclosure and earthed-chassis bonding options both apply per IEC 61000-4-2 return-path practice.	Low
13.5.5	J8	U15 supply pin on +VBUS has no local decoupling capacitor shown. Source: Nexperia PRTR5V0U2X datasheet.	Low
13.5.6	J3, J4	Switched outputs +5v0-CH0 and +5v0-CH1 leave the board on wire pads with no clamp; AP22804AW5-7 output pins rated 2,7V-5,5V. Source: Diodes Inc. datasheet.	Low
13.5.7	J5	CHG-LOOP clamped by D14 (PESD5V0S1BA-115, 5V working) on a connector that also carries the 10,80-16,00V +VIN contact; a wire-to-wire fault would drive the clamp into hard conduction as the fault path.	Low
13.5.8	J6	SP+/SP- have no ESD clamp; external speaker leads couple directly to the amplifier output stage.	Low
13.5.9	All	Single GND domain with no separate chassis/shield net and no single-point bond element drawn; acceptable for a plastic-enclosure product, needs an explicit bond scheme for an earthed metal chassis per IEC 61000-6-2.	Low
13.5.10	J8	CC1/CC2 terminated with 5,1kΩ to GND — correct Rd sink advertisement per USB Type-C R2.5; no clamp on the CC contacts.	Review
13.5.11	J1, J2	Pin 2 of both connectors is unconnected on the schematic.	Review
13.5.12	J3, J4	PESD5V0S1BA-115 clamping voltage of 14V is above the 5,5V absolute maximum of the SN74LV1T34 buffers, but the two figures use different conditions (clamping quoted at peak pulse current) and the 100Ω series element sits between clamp and buffer; residual at the buffer pin not determined.	Review
13.5.13	J8	D+/D- protected by U15 (PRTR5V0U2X,215, 5,5V working) placed at the connector ahead of the nRF52840 USB pins; correct topology and symmetric-array orientation. Source: Nexperia datasheet.	✓
13.5.14	J1, J2	LIN-IO clamped by D4 (PESD1IVN24-AX, 24V working / 42V clamping) above the 16,00V rail maximum, with R7 1kΩ and D3 BAS16-7-F 75V into the TJA1021T/20 (±8 kV IEC 61000-4-2 bus rating). Coherent LIN entry stage. Source: Nexperia and NXP datasheets.	✓
13.5.15	J3, J4	BTN0-EXT, AUX1-EXT, NP0-EXT, NP1-EXT each use 100Ω series plus PESD5V0S1BA-115 bidirectional clamp on the connector side of the resistor — correct placement and 5V working voltage matched to the +5v0 signalling. Source: Nexperia datasheet.	✓
13.5.16	All bidirectional TVS	D4, D5, D8, D12, D13, D14 are symmetric bidirectional devices — no orientation to check; D3 (BAS16-7-F) anode/cathode wiring is consistent with its steering role.	✓

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	8
Rails with TPs	6
Rails without TPs	2

2 power rail(s) need test points in the submitted design.

8 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+5v0		TP18	✓
+VBUS		TP1	✓
+VIN		TP27	✓
+VIN-PROTECT		TP5	✓
GND		TP2, TP24, TP25, TP26	✓
NOLBL_C10_2_1		-	NEEDS TP
NOLBL_C14_1_1		-	NEEDS TP
VDD		TP17	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP28	NOLBL_C10_2_1	cricket-node-hw--top-level_B.SchDoc
TP29	NOLBL_C14_1_1	cricket-node-hw--top-level_B.SchDoc
TP30	GND	cricket-node-hw--top-level_B.SchDoc
TP31	GND	cricket-node-hw--top-level_B.SchDoc
TP32	GND	cricket-node-hw--top-level_B.SchDoc
TP33	GND	cricket-node-hw--top-level_B.SchDoc
TP34	GND	cricket-node-hw--top-level_B.SchDoc
TP35	GND	cricket-node-hw--top-level_B.SchDoc

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U7	AP64352SP-13	EN	3	tied to VCC - recommend pull-up resistor and test point

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.5 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
SMT_TP-1MM	SMT Testpoint 1MM	27

14.5.1 By Sheet

Test Point	Net Name	Footprint
cricket-node-hw--top-level_B (27 test points)
TP1	+VBUS	SMT_TP-1MM
TP2	GND	SMT_TP-1MM
TP3	USB-DEVICE-D_P	SMT_TP-1MM
TP4	USB-DEVICE-D_N	SMT_TP-1MM
TP5	+VIN-PROTECT	SMT_TP-1MM
TP6	NP0-EXT	SMT_TP-1MM
TP7	BTN0-EXT	SMT_TP-1MM
TP8	+5v0-CH0	SMT_TP-1MM
TP9	P1.06	SMT_TP-1MM
TP10	NP1-EXT	SMT_TP-1MM
TP11	AUX1-EXT	SMT_TP-1MM
TP12	+5v0-CH1	SMT_TP-1MM
TP13	LIN-IO	SMT_TP-1MM
TP14	SP+	SMT_TP-1MM
TP15	SP-	SMT_TP-1MM
TP16	CHG-LOOP	SMT_TP-1MM
TP17	VDD	SMT_TP-1MM
TP18	+5v0	SMT_TP-1MM
TP19	P0.13	SMT_TP-1MM
TP20	TEST1	SMT_TP-1MM
TP21	SWDIO	SMT_TP-1MM
TP22	SWDCLK	SMT_TP-1MM
TP23	RESET	SMT_TP-1MM
TP24	GND	SMT_TP-1MM
TP25	GND	SMT_TP-1MM
TP26	GND	SMT_TP-1MM
TP27	+VIN	SMT_TP-1MM

14.5.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP1	+VBUS	cricket-node-hw--top-level_B	SMT_TP-1MM
TP2	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP3	USB-DEVICE-D_P	cricket-node-hw--top-level_B	SMT_TP-1MM
TP4	USB-DEVICE-D_N	cricket-node-hw--top-level_B	SMT_TP-1MM
TP5	+VIN-PROTECT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP6	NP0-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP7	BTN0-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP8	+5v0-CH0	cricket-node-hw--top-level_B	SMT_TP-1MM
TP9	P1.06	cricket-node-hw--top-level_B	SMT_TP-1MM
TP10	NP1-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP11	AUX1-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP12	+5v0-CH1	cricket-node-hw--top-level_B	SMT_TP-1MM
TP13	LIN-IO	cricket-node-hw--top-level_B	SMT_TP-1MM
TP14	SP+	cricket-node-hw--top-level_B	SMT_TP-1MM
TP15	SP-	cricket-node-hw--top-level_B	SMT_TP-1MM
TP16	CHG-LOOP	cricket-node-hw--top-level_B	SMT_TP-1MM
TP17	VDD	cricket-node-hw--top-level_B	SMT_TP-1MM
TP18	+5v0	cricket-node-hw--top-level_B	SMT_TP-1MM
TP19	P0.13	cricket-node-hw--top-level_B	SMT_TP-1MM
TP20	TEST1	cricket-node-hw--top-level_B	SMT_TP-1MM
TP21	SWDIO	cricket-node-hw--top-level_B	SMT_TP-1MM
TP22	SWDCLK	cricket-node-hw--top-level_B	SMT_TP-1MM
TP23	RESET	cricket-node-hw--top-level_B	SMT_TP-1MM
TP24	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP25	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP26	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP27	+VIN	cricket-node-hw--top-level_B	SMT_TP-1MM

14.6 Powered-off Testing

24 nets with test points: 23 pins with opens coverage, 4 pins with partial opens, 204 pins with shorts coverage.

Open pin faults may be masked when two or more IC pins share a net (current flow through one internal pin ESD diode may mask the open on another).

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
C12_1	+5v0	Capacitor	-	●
C13_1	+5v0	Capacitor	-	●
C26_2	+5v0	Capacitor	-	●
C27_2	+5v0	Capacitor	-	●
D6_1	+5v0	Passive	-	●
D15_A	+5v0	Passive	-	●
D16_A	+5v0	Passive	-	●
J3_6	+5v0	Connector	-	●
R15_2	+5v0	Passive	-	●
R16_2	+5v0	Passive	-	●
U1_5	+5v0	IC	-	●
U3_5	+5v0	IC	-	●
U8_5	+5v0	IC	-	●
U9_5	+5v0	IC	-	●
U14_7	+5v0	IC	-	●
U14_8	+5v0	IC	-	●
J3_1	+5v0-CH0	Connector	-	●
U1_1	+5v0-CH0	IC	●	●
J4_1	+5v0-CH1	Connector	-	●
U8_1	+5v0-CH1	IC	●	●
D7_1	+VBUS	Passive	-	●
J8_A4	+VBUS	Connector	-	●
J8_A9	+VBUS	Connector	-	●
J8_B4	+VBUS	Connector	-	●
J8_B9	+VBUS	Connector	-	●
U5_AD2	+VBUS	IC	-	●
U15_4	+VBUS	IC	-	●
J1_1	+VIN	Connector	-	●
J2_1	+VIN	Connector	-	●
J5_1	+VIN	Connector	-	●
Q6_2,4	+VIN	Transistor	-	●
C7_1	+VIN-PROTECT	Capacitor	-	●
C8_1	+VIN-PROTECT	Capacitor	-	●
D1_3	+VIN-PROTECT	Passive	-	●
D9_3	+VIN-PROTECT	Passive	-	●
D11_3	+VIN-PROTECT	Passive	-	●
Q1_2	+VIN-PROTECT	Transistor	-	●
Q6_3	+VIN-PROTECT	Transistor	-	●
Q7_2	+VIN-PROTECT	Transistor	-	●
R1_2	+VIN-PROTECT	Passive	-	●
R24_2	+VIN-PROTECT	Passive	-	●
U7_2	+VIN-PROTECT	IC	-	●
U7_3	+VIN-PROTECT	IC	-	●
D13_2	AUX1-EXT	Passive	●	●
J4_3	AUX1-EXT	Connector	-	●
R30_2	AUX1-EXT	Passive	-	●
D8_2	BTN0-EXT	Passive	●	●
J3_5	BTN0-EXT	Connector	-	●
R12_2	BTN0-EXT	Passive	-	●
D14_2	CHG-LOOP	Passive	●	●
J5_2	CHG-LOOP	Connector	-	●
R31_1	CHG-LOOP	Passive	-	●
R32_2	CHG-LOOP	Passive	-	●
C1_1	GND	Capacitor	-	●
C2_1	GND	Capacitor	-	●
C3_1	GND	Capacitor	-	●
C4_1	GND	Capacitor	-	●
C6_1	GND	Capacitor	-	●
C7_2	GND	Capacitor	-	●
C8_2	GND	Capacitor	-	●
C9_1	GND	Capacitor	-	●
C10_1	GND	Capacitor	-	●
C11_1	GND	Capacitor	-	●
C12_2	GND	Capacitor	-	●
C13_2	GND	Capacitor	-	●
C14_2	GND	Capacitor	-	●
C15_1	GND	Capacitor	-	●
C16_1	GND	Capacitor	-	●
C17_1	GND	Capacitor	-	●
C18_1	GND	Capacitor	-	●
C19_1	GND	Capacitor	-	●
C20_1	GND	Capacitor	-	●
C21_2	GND	Capacitor	-	●
C22_2	GND	Capacitor	-	●
C23_1	GND	Capacitor	-	●
C24_1	GND	Capacitor	-	●
C25_1	GND	Capacitor	-	●
C26_1	GND	Capacitor	-	●
C27_1	GND	Capacitor	-	●
C28_1	GND	Capacitor	-	●
D4_1	GND	Passive	●	●
D5_1	GND	Passive	●	●
D8_1	GND	Passive	●	●
D12_1	GND	Passive	●	●
D13_1	GND	Passive	●	●
D14_1	GND	Passive	●	●
J1_4	GND	Connector	-	●
J2_4	GND	Connector	-	●
J3_3	GND	Connector	-	●
J3_4	GND	Connector	-	●
J4_4	GND	Connector	-	●
J5_3	GND	Connector	-	●
J7_5	GND	Connector	-	●
J8_A1	GND	Connector	-	●
J8_A12	GND	Connector	-	●
J8_B1	GND	Connector	-	●
J8_B12	GND	Connector	-	●
J8_S1	GND	Connector	-	●
J8_S2	GND	Connector	-	●
J8_S3	GND	Connector	-	●
J8_S4	GND	Connector	-	●
J9_3	GND	Connector	-	●
J9_5	GND	Connector	-	●
J9_9	GND	Connector	-	●
Q3_2	GND	Transistor	-	●
Q4_2	GND	Transistor	-	●
Q5_2	GND	Transistor	-	●
Q8_2	GND	Transistor	-	●
Q9_2	GND	Transistor	-	●
Q10_2	GND	Transistor	-	●
R5_1	GND	Passive	●	●
R6_1	GND	Passive	-	●
R10_1	GND	Passive	-	●
R18_2	GND	Passive	-	●
R19_1	GND	Passive	-	●
R20_1	GND	Passive	-	●
R21_1	GND	Passive	-	●
R22_2	GND	Passive	-	●
R23_2	GND	Passive	-	●
R28_2	GND	Passive	-	●
R29_1	GND	Passive	-	●
R33_2	GND	Passive	-	●
R36_1	GND	Passive	-	●
R37_1	GND	Passive	-	●
U1_2	GND	IC	-	●
U2_5	GND	IC	-	●
U3_3	GND	IC	-	●
U4_3	GND	IC	-	●
U5_B7	GND	IC	-	●
U5_F23	GND	IC	-	●
U5_74	GND	IC	-	●
U7_7	GND	IC	-	●
U7_9	GND	IC	-	●
U8_2	GND	IC	-	●
U9_3	GND	IC	-	●
U10_3	GND	IC	-	●
U11_2	GND	IC	-	●
U12_4	GND	IC	-	●
U12_9	GND	IC	-	●
U13_4	GND	IC	-	●
U14_3	GND	IC	-	●
U14_11	GND	IC	-	●
U14_15	GND	IC	-	●
U14_17	GND	IC	-	●
U15_1	GND	IC	-	●
D4_2	LIN-IO	Passive	●	●
J1_3	LIN-IO	Connector	-	●
J2_3	LIN-IO	Connector	-	●
R7_2	LIN-IO	Passive	-	●
U2_6	LIN-IO	IC	●	●
D5_2	NP0-EXT	Passive	●	●
J3_2	NP0-EXT	Connector	-	●
R9_2	NP0-EXT	Passive	-	●
D12_2	NP1-EXT	Passive	●	●
J4_2	NP1-EXT	Connector	-	●
R27_2	NP1-EXT	Passive	-	●
U5_AD8	P0.13	IC	●	●
Q3_1	P1.06	Transistor	-	●
R5_2	P1.06	Passive	●	●
U5_R24	P1.06	IC	●	●
J7_3	RESET	Connector	-	●
J9_10	RESET	Connector	-	●
U5_AC13	RESET	IC	●	●
J6_2	SP+	Connector	-	●
L5_2	SP+	Passive	-	●
J6_1	SP-	Connector	-	●
L6_2	SP-	Passive	-	●
J7_4	SWDCLK	Connector	-	●
J9_4	SWDCLK	Connector	-	●
U5_AA24	SWDCLK	IC	●	●
J7_2	SWDIO	Connector	-	●
J9_2	SWDIO	Connector	-	●
U5_AC24	SWDIO	IC	●	●
U5_AD10	TEST1	IC	●	●
J8_A7	USB-DEVICE-D_N	Connector	-	●
J8_B7	USB-DEVICE-D_N	Connector	-	●
U5_AD4	USB-DEVICE-D_N	IC	◐	●
U15_3	USB-DEVICE-D_N	IC	◐	●
J8_A6	USB-DEVICE-D_P	Connector	-	●
J8_B6	USB-DEVICE-D_P	Connector	-	●
U5_AD6	USB-DEVICE-D_P	IC	◐	●
U15_2	USB-DEVICE-D_P	IC	◐	●
C1_2	VDD	Capacitor	-	●
C2_2	VDD	Capacitor	-	●
C3_2	VDD	Capacitor	-	●
C4_2	VDD	Capacitor	-	●
C6_2	VDD	Capacitor	-	●
C25_2	VDD	Capacitor	-	●
C28_2	VDD	Capacitor	-	●
J7_1	VDD	Connector	-	●
J9_1	VDD	Connector	-	●
L1_1	VDD	Passive	-	●
R11_1	VDD	Passive	-	●
R14_2	VDD	Passive	-	●
R38_2	VDD	Passive	-	●
U4_5	VDD	IC	-	●
U5_AD14	VDD	IC	-	●
U5_AD23	VDD	IC	-	●
U5_A22	VDD	IC	-	●
U5_B1	VDD	IC	-	●
U5_W1	VDD	IC	-	●
U10_5	VDD	IC	-	●
U12_8	VDD	IC	-	●
U13_8	VDD	IC	-	●

14.7 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

6 power rail nets with test points: 47 source-path pins (opens + shorts), 115 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
C12_1	+5v0	Sink	-	●
C13_1	+5v0	Sink	-	●
C26_2	+5v0	Sink	-	●
C27_2	+5v0	Sink	-	●
D6_1	+5v0	Sink	-	●
D15_A	+5v0	Sink	-	●
D16_A	+5v0	Sink	-	●
J3_6	+5v0	Sink	-	●
R15_2	+5v0	Series (U7 → R15)	●	●
R16_2	+5v0	Series (U7 → R16)	●	●
TP18_1	+5v0	Sink	-	●
U1_5	+5v0	Sink	-	●
U3_5	+5v0	Sink	-	●
U8_5	+5v0	Sink	-	●
U9_5	+5v0	Sink	-	●
U14_7	+5v0	Sink	-	●
U14_8	+5v0	Sink	-	●
D7_1	+VBUS	Sink	-	●
J8_A4	+VBUS	Sink	-	●
J8_A9	+VBUS	Sink	-	●
J8_B4	+VBUS	Sink	-	●
J8_B9	+VBUS	Sink	-	●
TP1_1	+VBUS	Sink	-	●
U5_AD2	+VBUS	Sink	-	●
U15_4	+VBUS	Sink	-	●
J1_1	+VIN	Sink	-	●
J2_1	+VIN	Sink	-	●
J5_1	+VIN	Sink	-	●
Q6_2,4	+VIN	Sink	-	●
TP27_1	+VIN	Sink	-	●
C7_1	+VIN-PROTECT	Sink	-	●
C8_1	+VIN-PROTECT	Sink	-	●
D1_3	+VIN-PROTECT	Sink	-	●
D9_3	+VIN-PROTECT	Sink	-	●
D11_3	+VIN-PROTECT	Sink	-	●
Q1_2	+VIN-PROTECT	Sink	-	●
Q6_3	+VIN-PROTECT	Sink	-	●
Q7_2	+VIN-PROTECT	Sink	-	●
R1_2	+VIN-PROTECT	Sink	-	●
R24_2	+VIN-PROTECT	Sink	-	●
TP5_1	+VIN-PROTECT	Sink	-	●
U7_2	+VIN-PROTECT	Sink	-	●
U7_3	+VIN-PROTECT	Sink	-	●
C1_1	GND	Sink	-	●
C2_1	GND	Sink	-	●
C3_1	GND	Sink	-	●
C4_1	GND	Sink	-	●
C6_1	GND	Sink	-	●
C7_2	GND	Sink	-	●
C8_2	GND	Sink	-	●
C9_1	GND	Series (U5 → C9)	●	●
C10_1	GND	Series (U5 → C10)	●	●
C11_1	GND	Series (U5 → C11)	●	●
C12_2	GND	Sink	-	●
C13_2	GND	Sink	-	●
C14_2	GND	Series (U7 → C14)	●	●
C15_1	GND	Series (U7 → C15)	●	●
C16_1	GND	Series (U5 → C16)	●	●
C17_1	GND	Series (U5 → C17)	●	●
C18_1	GND	Series (U5 → C18)	●	●
C19_1	GND	Series (U5 → C19)	●	●
C20_1	GND	Series (U5 → C20)	●	●
C21_2	GND	Series (U5 → C21)	●	●
C22_2	GND	Series (U5 → C22)	●	●
C23_1	GND	Series (U5 → C23)	●	●
C24_1	GND	Series (U5 → C24)	●	●
C25_1	GND	Sink	-	●
C26_1	GND	Sink	-	●
C27_1	GND	Sink	-	●
C28_1	GND	Sink	-	●
D4_1	GND	Sink	-	●
D5_1	GND	Sink	-	●
D8_1	GND	Sink	-	●
D12_1	GND	Sink	-	●
D13_1	GND	Sink	-	●
D14_1	GND	Sink	-	●
J1_4	GND	Sink	-	●
J2_4	GND	Sink	-	●
J3_3	GND	Sink	-	●
J3_4	GND	Sink	-	●
J4_4	GND	Sink	-	●
J5_3	GND	Sink	-	●
J7_5	GND	Sink	-	●
J8_A1	GND	Sink	-	●
J8_A12	GND	Sink	-	●
J8_B1	GND	Sink	-	●
J8_B12	GND	Sink	-	●
J8_S1	GND	Sink	-	●
J8_S2	GND	Sink	-	●
J8_S3	GND	Sink	-	●
J8_S4	GND	Sink	-	●
J9_3	GND	Sink	-	●
J9_5	GND	Sink	-	●
J9_9	GND	Sink	-	●
Q3_2	GND	Sink	-	●
Q4_2	GND	Sink	-	●
Q5_2	GND	Sink	-	●
Q8_2	GND	Sink	-	●
Q9_2	GND	Sink	-	●
Q10_2	GND	Sink	-	●
R5_1	GND	Series (U5 → R5)	●	●
R6_1	GND	Series (U5 → R6)	●	●
R10_1	GND	Series (U5 → R10)	●	●
R18_2	GND	Sink	-	●
R19_1	GND	Series (U5 → R19)	●	●
R20_1	GND	Series (U5 → R20)	●	●
R21_1	GND	Series (U5 → R21)	●	●
R22_2	GND	Series (U7 → R22)	●	●
R23_2	GND	Series (U7 → R23)	●	●
R28_2	GND	Series (U11 → R28)	●	●
R29_1	GND	Series (U5 → R29)	●	●
R33_2	GND	Series (U14 → R33)	●	●
R36_1	GND	Sink	-	●
R37_1	GND	Sink	-	●
TP2_1	GND	Sink	-	●
TP24_1	GND	Sink	-	●
TP25_1	GND	Sink	-	●
TP26_1	GND	Sink	-	●
U1_2	GND	Sink	-	●
U2_5	GND	Sink	-	●
U3_3	GND	Sink	-	●
U4_3	GND	Sink	-	●
U5_B7	GND	Series path	●	●
U5_F23	GND	Series path	●	●
U5_74	GND	Series path	●	●
U7_7	GND	Series path	●	●
U7_9	GND	Series path	●	●
U8_2	GND	Sink	-	●
U9_3	GND	Sink	-	●
U10_3	GND	Sink	-	●
U11_2	GND	Series path	●	●
U12_4	GND	Sink	-	●
U12_9	GND	Sink	-	●
U13_4	GND	Sink	-	●
U14_3	GND	Series path	●	●
U14_11	GND	Series path	●	●
U14_15	GND	Series path	●	●
U14_17	GND	Series path	●	●
U15_1	GND	Sink	-	●
C1_2	VDD	Sink	-	●
C2_2	VDD	Sink	-	●
C3_2	VDD	Sink	-	●
C4_2	VDD	Sink	-	●
C6_2	VDD	Sink	-	●
C25_2	VDD	Sink	-	●
C28_2	VDD	Sink	-	●
J7_1	VDD	Sink	-	●
J9_1	VDD	Sink	-	●
L1_1	VDD	Series (U5 → L1)	●	●
R11_1	VDD	Series (U5 → R11)	●	●
R14_2	VDD	Series (U13 → R14)	●	●
R38_2	VDD	Series (U13 → R38)	●	●
TP17_1	VDD	Sink	-	●
U4_5	VDD	Sink	-	●
U5_AD14	VDD	Series path	●	●
U5_AD23	VDD	Series path	●	●
U5_A22	VDD	Series path	●	●
U5_B1	VDD	Series path	●	●
U5_W1	VDD	Series path	●	●
U10_5	VDD	Sink	-	●
U12_8	VDD	Sink	-	●
U13_8	VDD	Series path	●	●

14.8 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.9 Inspection

Total: 115 components, 394 of 394 pins with inspection coverage.

14.9.1 AOI

IPC Compliant Footprints
Visible-joint components with IPC compliant footprints. Package type structurally verified from footprint name.
Footprint	Size (mm)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens only (leads visible, shorts unreliable)
SOIC127P600X175-8N			SOIC/SOP	IPC-7351B	1	8	U2
Subtotal: 1 components, 8 pins

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mm)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
D_SOT-23-3
D_SOT-23-3_P			SOT (Small Outline Transistor)	Footprint	4	8	D1, D11, D2, D9
D_SOT-23-3_P			SOT (Small Outline Transistor)	Footprint	3	6	D3, D6, D7
SOT-23			SOT (Small Outline Transistor)	Footprint	9	27	Q1, Q10, Q2, Q3, Q4, Q5, Q7, Q8 ...+1 more
SOT223
SOT223			SOT (Small Outline Transistor)	Footprint	1	3	Q6
SOT23-5			SOT (Small Outline Transistor)	Footprint	6	26	U1, U10, U3, U4, U8, U9
sot23-5			SOT (Small Outline Transistor)	Footprint	1	5	U11
C0402_0.55MM_HD			Chip Passive	Designator	14	28	C1, C10, C16, C17, C18, C19, C2, C21 ...+6 more
C0402_0.55MM_MD
C0402_0.55MM_MD			Chip Passive	Designator	1	2	L2
C0603_0.90MM_HD			Chip Passive	Designator	1	2	C11
C0603_0.90MM_MD			Chip Passive	Designator	5	10	C15, C25, C26, C28, C5
C0603_0.90MM_MD
C0603_0.90MM_MD			Chip Passive	Designator	2	4	L1, L3
C0805_1.40MM_HD			Chip Passive	Designator	2	4	C20, C6
C0805_1.40MM_MD			Chip Passive	Designator	1	2	C27
C1210_2.80MM_MD			Chip Passive	Designator	1	2	C8
C_ALU_D			Chip Passive	Designator	3	6	C12, C13, C14
C_ALU_F
C_ALU_F			Chip Passive	Designator	1	2	C7
L_0805
L0805_1.45MM_MD			Chip Passive	Designator	2	4	L5, L6
L_MSS1038			Chip Passive	Designator	1	2	L4
R0603_0.55MM_HD			Chip Passive	Designator	26	52	R1, R10, R11, R14, R17, R18, R19, R2 ...+18 more
R0603_0.55MM_HD
R0603_0.55MM_HD			Chip Passive	Designator	2	4	R34, R35
R0603_0.55MM_MD			Chip Passive	Designator	7	14	R12, R23, R27, R30, R32, R33, R9
R0805_0.70MM_HD
R0805_0.70MM_HD			Chip Passive	Designator	3	6	R13, R15, R16
D_SOD-323_P			SOD (Diode Package)	Footprint	6	12	D12, D13, D14, D4, D5, D8
LED-0805-GREEN
LED-0805-GREEN			SOD (Diode Package)	Designator	1	2	D16
LED-0805-RED
LED-0805-RED			SOD (Diode Package)	Designator	1	2	D15
XTAL_2016
XTAL_2016			Oscillator / Crystal	Designator	1	2	X1
XTAL_3215
XTAL_3215			Oscillator / Crystal	Designator	1	2	X2
Subtotal: 106 components, 239 pins
Opens only (leads visible, shorts unreliable)
SO8-EP
SO8-EP			SOIC/SOP	Footprint	1	9	U7
SOIC 8
SOIC 8			SOIC/SOP	Footprint	1	8	U13
SOT143B			SOIC/SOP	Designator	1	4	U15
Subtotal: 3 components, 21 pins
Presence check (manual verification)
FTSH-105-05-F-DV			Connector	Designator	1	10	J9
USB4145-03-0230-C
USB4145-03-0230-C			Connector	Designator	1	20	J8
Subtotal: 2 components, 30 pins

14.9.2 AXI

IPC Compliant Footprints (Hidden Joints)
Components with IPC compliant footprints and solder joints hidden under the package body.
Footprint	Size (mm)	Pkg Type	Classification	Method	Count	Pins	Refdes
QFN50P300X300X80_HS-17N-2			QFN/DFN (No-Lead)	IPC-7351B	1	13	U14
SON127P600X80_HS-9N			QFN/DFN (No-Lead)	IPC-7351B	1	9	U12
Subtotal: 2 components, 22 pins

Assumed Classification (Non-IPC Footprints)
Hidden-joint classification inferred from Pkg Type property or designator prefix. Footprint names are not IPC-7351B or IPC-7251.
Footprint	Size (mm)	Pkg Type	Classification	Method	Count	Pins	Refdes
AQFN50P700X700X85_HS-74N			QFN/DFN (No-Lead)	Footprint	1	74	U5
Subtotal: 1 components, 74 pins

14.10 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.10.1 Fault Coverage Summary

Fault Coverage Summary (423 pins)
Test Method	Opens	Shorts
X-ray (AXI)	22 (5.2%)	22 (5.2%)
Optical (AOI)	8 (1.9%)	0 (0.0%)
Electrical
Powered-off Testing	77 (18.2%)	204 (48.2%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	9 (2.1%)	9 (2.1%)
Total	77 (18.2%)	204 (48.2%)
Total Fault Coverage	102 (24.1%)	217 (51.3%)
No coverage	321 (75.9%)	206 (48.7%)

14.10.2 Uncovered Pins (200)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
J8_A5	CC1
J8_A8
J8_B5	CC2
J8_B8
R36_2	CC2
R37_2	CC1
J1_2	UNC_J1_2_2
J2_2	UNC_J2_2_2
R33_1	NOLBL_R33_1_1
L5_1	NOLBL_L5_1_1
L6_1	NOLBL_L6_1_1
U3_2	NP0
U3_4	NOLBL_R9_1_1
R9_1	NOLBL_R9_1_1
R12_1	NOLBL_R12_1_1
R11_2	LIN-RX-OUT
R8_2	NOLBL_Q5_3_D
R8_1	NOLBL_Q1_3_D
R10_2	LIN-WAKE
Q5_3	NOLBL_Q5_3_D
Q5_1	LIN-WAKE
D1_1	NOLBL_D1_1_A
R1_1	NOLBL_D1_1_A
R4_2	NOLBL_Q4_3_D
R4_1	NOLBL_D1_1_A
Q4_3	NOLBL_Q4_3_D
Q4_1	LIN-PWR
Q1_3	NOLBL_Q1_3_D
Q1_1	NOLBL_D1_1_A
R6_2	LIN-PWR
D2_1	NOLBL_D2_1_A
D2_3	NOLBL_D2_3_K
R2_2	NOLBL_D2_3_K
R2_1	NOLBL_D2_1_A
R3_2	NOLBL_Q3_3_D
R3_1	NOLBL_D2_1_A
Q3_3	NOLBL_Q3_3_D
Q2_3	NOLBL_D3_1_A
Q2_1	NOLBL_D2_1_A
Q2_2	NOLBL_D2_3_K
D3_1	NOLBL_D3_1_A
D3_3	NOLBL_D3_3_K
R7_1	NOLBL_D3_3_K
R26_2	NOLBL_Q7_3_D
R26_1	NOLBL_R26_1_1
R28_1	NOLBL_R26_1_1
D11_1	NOLBL_D11_1_A
R24_1	NOLBL_D11_1_A
R25_2	NOLBL_Q8_3_D
R25_1	NOLBL_D11_1_A
U11_3	NOLBL_R26_1_1
U11_4	P0.02
U11_5	P0.03
U11_1	P0.02
Q8_3	NOLBL_Q8_3_D
Q8_1	P0.03
Q7_3	NOLBL_Q7_3_D
Q7_1	NOLBL_D11_1_A
R29_2	P0.03
C15_2	NOLBL_C15_2_1
R23_1	NOLBL_R17_1_1
R17_2	NOLBL_C14_1_1
R17_1	NOLBL_R17_1_1
L4_1	NOLBL_C5_1_1
L4_2	NOLBL_C14_1_1
C5_1	NOLBL_C5_1_1
C5_2	NOLBL_C5_2_1
R22_1	NOLBL_R22_1_1
C14_1	NOLBL_C14_1_1
J9_6	UNC_J9_6_SWO/TDO
J9_7
J9_8	UNC_J9_8_TDI
J7_6
U13_7	NOLBL_R38_1_1
U13_1	FRAM-CS
U13_6	FRAM-CLK
U13_2	FRAM-SDO
U13_3	NOLBL_R14_1_1
U13_5	P1.04
C11_2	NOLBL_C10_2_1
C10_2	NOLBL_C10_2_1
U5_C1	NOLBL_C17_2_1
U5_E24	NOLBL_C10_2_1
U5_AD22	GREEN-LED
U5_H23
U5_N1	AUX1
U5_D23	NOLBL_C19_2_1
U5_A23	NOLBL_C21_1_1
U5_Y23	P1.01
U5_B24	NOLBL_C22_1_1
U5_M2	SP-BCK
U5_A20	P1.10
U5_U1	SP-DIN
U5_D2	P0.00
U5_F2	P0.01
U5_B11	LIN-WAKE
U5_B5	NOLBL_C10_2_1
U5_U24	P1.04
U5_B3	NOLBL_L3_2_2
U5_B15	P1.14
U5_J24	P0.10
U5_T2	P0.11
U5_AC15	P0.19
U5_Y2	NOLBL_R13_1_1
U5_K2	P0.05
U5_AB2	NOLBL_L1_2_2
U5_AC5	NOLBL_C20_2_1
U5_AD20	QSPI-CS
U5_P2	P1.08
U5_AC19	QSPI-D3
U5_AD16	QSPI-D2
U5_AD18	QSPI-D1
U5_AC17	P0.21
U5_N24	NOLBL_C16_2_1
U5_L24	P0.09
U5_R1	SP-LRCLK
U5_AC21	FRAM-CLK
U5_J1	NP1-EN
U5_G1	P0.26
U5_A10	LIN-TX-IN
U5_H2	LIN-PWR
U5_L1	P0.06
U5_AC9	QSPI-SCLK
U5_A12	P0.02
U5_AC11	P0.16
U5_AD12	P0.17
U5_B13	P0.03
U5_B9	LIN-RX-OUT
U5_P23	NP0
U5_A8	LIN-SLP-N
U5_W24	FRAM-CS
U5_V23	FRAM-SDO
U5_T23	BTN0
U5_B19	NP0-EN
U5_B17	P1.12
U5_A16	CHG-DET
U5_A14	P1.15
U5_A18	NOLBL_C18_2_1
C18_2	NOLBL_C18_2_1
C20_2	NOLBL_C20_2_1
C21_1	NOLBL_C21_1_1
C22_1	NOLBL_C22_1_1
C17_2	NOLBL_C17_2_1
C19_2	NOLBL_C19_2_1
C9_2	NOLBL_C10_2_1
C16_2	NOLBL_C16_2_1
C23_2	P0.00
C24_2	P0.01
R13_2	NOLBL_D6_3_K
R13_1	NOLBL_R13_1_1
U10_2	NOLBL_R30_1_1
U10_4	AUX1
U9_2	P0.06
U9_4	NOLBL_R27_1_1
R27_1	NOLBL_R27_1_1
R30_1	NOLBL_R30_1_1
X1_1	NOLBL_C22_1_1
X1_3	NOLBL_C21_1_1
X2_1	P0.01
X2_2	P0.00
Q6_1	NOLBL_D9_1_A
R18_1	NOLBL_D9_1_A
D9_1	NOLBL_D9_1_A
R16_1	NOLBL_C14_1_1
R15_1	NOLBL_C14_1_1
L2_1	NOLBL_C10_2_1
L2_2	NOLBL_L2_2_2
L1_2	NOLBL_L1_2_2
L3_1	NOLBL_L2_2_2
L3_2	NOLBL_L3_2_2
R32_1	CHG-DET
R31_2	P1.15
D16_C	NOLBL_D16_C_C
R35_2	NOLBL_D16_C_C
R35_1	NOLBL_Q10_3_D
R34_2	NOLBL_D15_C_C
R34_1	NOLBL_Q9_3_D
D15_C	NOLBL_D15_C_C
R21_2	P0.09
R20_2	P0.10
R19_2	P0.11
U1_3
U1_4	NP0-EN
U4_2	NOLBL_R12_1_1
U4_4	BTN0
U8_3
U8_4	NP1-EN
Q9_3	NOLBL_Q9_3_D
Q9_1	P1.01
Q10_3	NOLBL_Q10_3_D
Q10_1	GREEN-LED
D7_3	NOLBL_D6_3_K
D6_3	NOLBL_D6_3_K
R38_1	NOLBL_R38_1_1
R14_1	NOLBL_R14_1_1
U7_1	NOLBL_C5_2_1
U7_4	NOLBL_R22_1_1
U7_5	NOLBL_R17_1_1
U7_6	NOLBL_C15_2_1
U7_8	NOLBL_C5_1_1

14.10.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
J8_A4	+VBUS	-	●	-	-	-	-
J8_A12	GND	-	●	-	-	-	-
J8_A1	GND	-	●	-	-	-	-
J8_A9	+VBUS	-	●	-	-	-	-
J8_A5	CC1	-	-	-	-	-	-
J8_A6	USB-DEVICE-D_P	-	●	-	-	-	-
J8_A7	USB-DEVICE-D_N	-	●	-	-	-	-
J8_A8		-	-	-	-	-	-
J8_B6	USB-DEVICE-D_P	-	●	-	-	-	-
J8_S1	GND	-	●	-	-	-	-
J8_B5	CC2	-	-	-	-	-	-
J8_S2	GND	-	●	-	-	-	-
J8_B4	+VBUS	-	●	-	-	-	-
J8_S3	GND	-	●	-	-	-	-
J8_S4	GND	-	●	-	-	-	-
J8_B9	+VBUS	-	●	-	-	-	-
J8_B8		-	-	-	-	-	-
J8_B7	USB-DEVICE-D_N	-	●	-	-	-	-
J8_B1	GND	-	●	-	-	-	-
J8_B12	GND	-	●	-	-	-	-
R36_2	CC2	-	-	-	-	-	-
R36_1	GND	-	●	-	-	-	-
R37_2	CC1	-	-	-	-	-	-
R37_1	GND	-	●	-	-	-	-
U15_1	GND	●	●	-	-	-	-
U15_4	+VBUS	●	●	-	-	-	-
U15_2	USB-DEVICE-D_P	-	●	-	-	-	-
U15_3	USB-DEVICE-D_N	-	●	-	-	-	-
J1_1	+VIN	-	●	-	-	-	-
J1_2	UNC_J1_2_2	-	-	-	-	-	-
J1_3	LIN-IO	-	●	-	-	-	-
J1_4	GND	-	●	-	-	-	-
J2_1	+VIN	-	●	-	-	-	-
J2_2	UNC_J2_2_2	-	-	-	-	-	-
J2_3	LIN-IO	-	●	-	-	-	-
J2_4	GND	-	●	-	-	-	-
C26_1	GND	-	●	-	-	-	-
C26_2	+5v0	-	●	-	-	-	-
C27_1	GND	-	●	-	-	-	-
C27_2	+5v0	-	●	-	-	-	-
R33_2	GND	●	●	-	-	-	-
R33_1	NOLBL_R33_1_1	-	-	-	-	-	-
U14_7	+5v0	-	●	-	-	●	◐
U14_16	SP-BCK	-	-	-	-	●	◐
U14_10	NOLBL_L5_1_1	-	-	-	-	●	◐
U14_1	SP-DIN	-	-	-	-	●	◐
U14_2	NOLBL_R33_1_1	-	-	-	-	●	◐
U14_14	SP-LRCLK	-	-	-	-	●	◐
U14_4	P0.05	-	-	-	-	●	◐
U14_8	+5v0	-	●	-	-	●	◐
U14_9	NOLBL_L6_1_1	-	-	-	-	●	◐
U14_17	GND	●	●	-	-	●	◐
U14_3	GND	●	●	-	-	●	◐
U14_11	GND	●	●	-	-	●	◐
U14_15	GND	●	●	-	-	●	◐
L5_1	NOLBL_L5_1_1	-	-	-	-	-	-
L5_2	SP+	-	●	-	-	-	-
L6_1	NOLBL_L6_1_1	-	-	-	-	-	-
L6_2	SP-	-	●	-	-	-	-
U3_2	NP0	-	-	-	-	-	-
U3_3	GND	-	●	-	-	-	-
U3_4	NOLBL_R9_1_1	-	-	-	-	-	-
U3_5	+5v0	-	●	-	-	-	-
D8_2	BTN0-EXT	●	●	-	-	-	-
D8_1	GND	●	●	-	-	-	-
D5_2	NP0-EXT	●	●	-	-	-	-
D5_1	GND	●	●	-	-	-	-
R9_2	NP0-EXT	-	●	-	-	-	-
R9_1	NOLBL_R9_1_1	-	-	-	-	-	-
R12_2	BTN0-EXT	-	●	-	-	-	-
R12_1	NOLBL_R12_1_1	-	-	-	-	-	-
U2_1	LIN-RX-OUT	-	-	●	-	-	-
U2_2	LIN-SLP-N	-	-	●	-	-	-
U2_3	NOLBL_Q5_3_D	-	-	●	-	-	-
U2_4	LIN-TX-IN	-	-	●	-	-	-
U2_5	GND	-	●	●	-	-	-
U2_6	LIN-IO	●	●	●	-	-	-
U2_7	NOLBL_Q1_3_D	-	-	●	-	-	-
U2_8	NOLBL_D2_3_K	-	-	●	-	-	-
R11_2	LIN-RX-OUT	-	-	-	-	-	-
R11_1	VDD	●	●	-	-	-	-
R8_2	NOLBL_Q5_3_D	-	-	-	-	-	-
R8_1	NOLBL_Q1_3_D	-	-	-	-	-	-
R10_2	LIN-WAKE	-	-	-	-	-	-
R10_1	GND	●	●	-	-	-	-
D4_2	LIN-IO	●	●	-	-	-	-
D4_1	GND	●	●	-	-	-	-
Q5_3	NOLBL_Q5_3_D	-	-	-	-	-	-
Q5_1	LIN-WAKE	-	-	-	-	-	-
Q5_2	GND	-	●	-	-	-	-
D1_1	NOLBL_D1_1_A	-	-	-	-	-	-
D1_3	+VIN-PROTECT	-	●	-	-	-	-
R1_2	+VIN-PROTECT	-	●	-	-	-	-
R1_1	NOLBL_D1_1_A	-	-	-	-	-	-
R4_2	NOLBL_Q4_3_D	-	-	-	-	-	-
R4_1	NOLBL_D1_1_A	-	-	-	-	-	-
Q4_3	NOLBL_Q4_3_D	-	-	-	-	-	-
Q4_1	LIN-PWR	-	-	-	-	-	-
Q4_2	GND	-	●	-	-	-	-
Q1_3	NOLBL_Q1_3_D	-	-	-	-	-	-
Q1_1	NOLBL_D1_1_A	-	-	-	-	-	-
Q1_2	+VIN-PROTECT	-	●	-	-	-	-
R6_2	LIN-PWR	-	-	-	-	-	-
R6_1	GND	●	●	-	-	-	-
D2_1	NOLBL_D2_1_A	-	-	-	-	-	-
D2_3	NOLBL_D2_3_K	-	-	-	-	-	-
R2_2	NOLBL_D2_3_K	-	-	-	-	-	-
R2_1	NOLBL_D2_1_A	-	-	-	-	-	-
R3_2	NOLBL_Q3_3_D	-	-	-	-	-	-
R3_1	NOLBL_D2_1_A	-	-	-	-	-	-
Q3_3	NOLBL_Q3_3_D	-	-	-	-	-	-
Q3_1	P1.06	-	●	-	-	-	-
Q3_2	GND	-	●	-	-	-	-
Q2_3	NOLBL_D3_1_A	-	-	-	-	-	-
Q2_1	NOLBL_D2_1_A	-	-	-	-	-	-
Q2_2	NOLBL_D2_3_K	-	-	-	-	-	-
R5_2	P1.06	●	●	-	-	-	-
R5_1	GND	●	●	-	-	-	-
D3_1	NOLBL_D3_1_A	-	-	-	-	-	-
D3_3	NOLBL_D3_3_K	-	-	-	-	-	-
R7_2	LIN-IO	-	●	-	-	-	-
R7_1	NOLBL_D3_3_K	-	-	-	-	-	-
R26_2	NOLBL_Q7_3_D	-	-	-	-	-	-
R26_1	NOLBL_R26_1_1	-	-	-	-	-	-
R28_2	GND	●	●	-	-	-	-
R28_1	NOLBL_R26_1_1	-	-	-	-	-	-
D11_1	NOLBL_D11_1_A	-	-	-	-	-	-
D11_3	+VIN-PROTECT	-	●	-	-	-	-
R24_2	+VIN-PROTECT	-	●	-	-	-	-
R24_1	NOLBL_D11_1_A	-	-	-	-	-	-
R25_2	NOLBL_Q8_3_D	-	-	-	-	-	-
R25_1	NOLBL_D11_1_A	-	-	-	-	-	-
U11_3	NOLBL_R26_1_1	-	-	-	-	-	-
U11_4	P0.02	-	-	-	-	-	-
U11_2	GND	●	●	-	-	-	-
U11_5	P0.03	-	-	-	-	-	-
U11_1	P0.02	-	-	-	-	-	-
Q8_3	NOLBL_Q8_3_D	-	-	-	-	-	-
Q8_1	P0.03	-	-	-	-	-	-
Q8_2	GND	-	●	-	-	-	-
Q7_3	NOLBL_Q7_3_D	-	-	-	-	-	-
Q7_1	NOLBL_D11_1_A	-	-	-	-	-	-
Q7_2	+VIN-PROTECT	-	●	-	-	-	-
R29_2	P0.03	-	-	-	-	-	-
R29_1	GND	●	●	-	-	-	-
C15_1	GND	●	●	-	-	-	-
C15_2	NOLBL_C15_2_1	-	-	-	-	-	-
R23_2	GND	●	●	-	-	-	-
R23_1	NOLBL_R17_1_1	-	-	-	-	-	-
R17_2	NOLBL_C14_1_1	-	-	-	-	-	-
R17_1	NOLBL_R17_1_1	-	-	-	-	-	-
L4_1	NOLBL_C5_1_1	-	-	-	-	-	-
L4_2	NOLBL_C14_1_1	-	-	-	-	-	-
C8_1	+VIN-PROTECT	-	●	-	-	-	-
C8_2	GND	-	●	-	-	-	-
C5_1	NOLBL_C5_1_1	-	-	-	-	-	-
C5_2	NOLBL_C5_2_1	-	-	-	-	-	-
R22_2	GND	●	●	-	-	-	-
R22_1	NOLBL_R22_1_1	-	-	-	-	-	-
C14_1	NOLBL_C14_1_1	-	-	-	-	-	-
C14_2	GND	●	●	-	-	-	-
J9_1	VDD	-	●	-	-	-	-
J9_2	SWDIO	●	●	-	-	-	-
J9_3	GND	-	●	-	-	-	-
J9_4	SWDCLK	●	●	-	-	-	-
J9_5	GND	-	●	-	-	-	-
J9_6	UNC_J9_6_SWO/TDO	-	-	-	-	-	-
J9_7		-	-	-	-	-	-
J9_8	UNC_J9_8_TDI	-	-	-	-	-	-
J9_9	GND	-	●	-	-	-	-
J9_10	RESET	●	●	-	-	-	-
J7_1	VDD	-	●	-	-	-	-
J7_2	SWDIO	●	●	-	-	-	-
J7_3	RESET	●	●	-	-	-	-
J7_4	SWDCLK	●	●	-	-	-	-
J7_5	GND	-	●	-	-	-	-
J7_6		-	-	-	-	-	-
U12_1	QSPI-CS	-	-	-	-	●	◐
U12_9	GND	-	●	-	-	●	◐
U12_4	GND	-	●	-	-	●	◐
U12_8	VDD	-	●	-	-	●	◐
U12_5	P0.21	-	-	-	-	●	◐
U12_3	QSPI-D2	-	-	-	-	●	◐
U12_6	QSPI-SCLK	-	-	-	-	●	◐
U12_7	QSPI-D3	-	-	-	-	●	◐
U12_2	QSPI-D1	-	-	-	-	●	◐
U13_7	NOLBL_R38_1_1	-	-	-	-	-	-
U13_8	VDD	●	●	-	-	-	-
U13_1	FRAM-CS	-	-	-	-	-	-
U13_6	FRAM-CLK	-	-	-	-	-	-
U13_2	FRAM-SDO	-	-	-	-	-	-
U13_3	NOLBL_R14_1_1	-	-	-	-	-	-
U13_5	P1.04	-	-	-	-	-	-
U13_4	GND	-	●	-	-	-	-
C6_1	GND	-	●	-	-	-	-
C6_2	VDD	-	●	-	-	-	-
C11_1	GND	●	●	-	-	-	-
C11_2	NOLBL_C10_2_1	-	-	-	-	-	-
C10_1	GND	●	●	-	-	-	-
C10_2	NOLBL_C10_2_1	-	-	-	-	-	-
U5_C1	NOLBL_C17_2_1	-	-	-	-	-	-
U5_W1	VDD	●	●	-	-	-	-
U5_E24	NOLBL_C10_2_1	-	-	-	-	-	-
U5_F23	GND	●	●	-	-	-	-
U5_AD22	GREEN-LED	-	-	-	-	-	-
U5_AD4	USB-DEVICE-D_N	-	●	-	-	-	-
U5_H23		-	-	-	-	-	-
U5_N1	AUX1	-	-	-	-	-	-
U5_D23	NOLBL_C19_2_1	-	-	-	-	-	-
U5_A23	NOLBL_C21_1_1	-	-	-	-	-	-
U5_Y23	P1.01	-	-	-	-	-	-
U5_B24	NOLBL_C22_1_1	-	-	-	-	-	-
U5_A22	VDD	●	●	-	-	-	-
U5_M2	SP-BCK	-	-	-	-	-	-
U5_AD2	+VBUS	-	●	-	-	-	-
U5_A20	P1.10	-	-	-	-	-	-
U5_U1	SP-DIN	-	-	-	-	-	-
U5_D2	P0.00	-	-	-	-	-	-
U5_AA24	SWDCLK	●	●	-	-	-	-
U5_F2	P0.01	-	-	-	-	-	-
U5_B11	LIN-WAKE	-	-	-	-	-	-
U5_B5	NOLBL_C10_2_1	-	-	-	-	-	-
U5_U24	P1.04	-	-	-	-	-	-
U5_B7	GND	●	●	-	-	-	-
U5_B1	VDD	●	●	-	-	-	-
U5_B3	NOLBL_L3_2_2	-	-	-	-	-	-
U5_B15	P1.14	-	-	-	-	-	-
U5_J24	P0.10	-	-	-	-	-	-
U5_AC24	SWDIO	●	●	-	-	-	-
U5_T2	P0.11	-	-	-	-	-	-
U5_AC15	P0.19	-	-	-	-	-	-
U5_Y2	NOLBL_R13_1_1	-	-	-	-	-	-
U5_K2	P0.05	-	-	-	-	-	-
U5_AB2	NOLBL_L1_2_2	-	-	-	-	-	-
U5_AC5	NOLBL_C20_2_1	-	-	-	-	-	-
U5_AD20	QSPI-CS	-	-	-	-	-	-
U5_AD6	USB-DEVICE-D_P	-	●	-	-	-	-
U5_P2	P1.08	-	-	-	-	-	-
U5_AC19	QSPI-D3	-	-	-	-	-	-
U5_AD16	QSPI-D2	-	-	-	-	-	-
U5_AD18	QSPI-D1	-	-	-	-	-	-
U5_AC17	P0.21	-	-	-	-	-	-
U5_N24	NOLBL_C16_2_1	-	-	-	-	-	-
U5_AD23	VDD	●	●	-	-	-	-
U5_L24	P0.09	-	-	-	-	-	-
U5_R1	SP-LRCLK	-	-	-	-	-	-
U5_AC21	FRAM-CLK	-	-	-	-	-	-
U5_J1	NP1-EN	-	-	-	-	-	-
U5_G1	P0.26	-	-	-	-	-	-
U5_A10	LIN-TX-IN	-	-	-	-	-	-
U5_AC13	RESET	●	●	-	-	-	-
U5_H2	LIN-PWR	-	-	-	-	-	-
U5_L1	P0.06	-	-	-	-	-	-
U5_AD8	P0.13	●	●	-	-	-	-
U5_AC9	QSPI-SCLK	-	-	-	-	-	-
U5_AD10	TEST1	●	●	-	-	-	-
U5_A12	P0.02	-	-	-	-	-	-
U5_AC11	P0.16	-	-	-	-	-	-
U5_AD12	P0.17	-	-	-	-	-	-
U5_B13	P0.03	-	-	-	-	-	-
U5_B9	LIN-RX-OUT	-	-	-	-	-	-
U5_P23	NP0	-	-	-	-	-	-
U5_A8	LIN-SLP-N	-	-	-	-	-	-
U5_AD14	VDD	●	●	-	-	-	-
U5_W24	FRAM-CS	-	-	-	-	-	-
U5_V23	FRAM-SDO	-	-	-	-	-	-
U5_T23	BTN0	-	-	-	-	-	-
U5_R24	P1.06	●	●	-	-	-	-
U5_B19	NP0-EN	-	-	-	-	-	-
U5_B17	P1.12	-	-	-	-	-	-
U5_A16	CHG-DET	-	-	-	-	-	-
U5_A14	P1.15	-	-	-	-	-	-
U5_A18	NOLBL_C18_2_1	-	-	-	-	-	-
U5_74	GND	●	●	-	-	-	-
C18_1	GND	●	●	-	-	-	-
C18_2	NOLBL_C18_2_1	-	-	-	-	-	-
C20_1	GND	●	●	-	-	-	-
C20_2	NOLBL_C20_2_1	-	-	-	-	-	-
C4_1	GND	-	●	-	-	-	-
C4_2	VDD	-	●	-	-	-	-
C3_1	GND	-	●	-	-	-	-
C3_2	VDD	-	●	-	-	-	-
C2_1	GND	-	●	-	-	-	-
C2_2	VDD	-	●	-	-	-	-
C1_1	GND	-	●	-	-	-	-
C1_2	VDD	-	●	-	-	-	-
C21_1	NOLBL_C21_1_1	-	-	-	-	-	-
C21_2	GND	●	●	-	-	-	-
C22_1	NOLBL_C22_1_1	-	-	-	-	-	-
C22_2	GND	●	●	-	-	-	-
C17_1	GND	●	●	-	-	-	-
C17_2	NOLBL_C17_2_1	-	-	-	-	-	-
C19_1	GND	●	●	-	-	-	-
C19_2	NOLBL_C19_2_1	-	-	-	-	-	-
C9_1	GND	●	●	-	-	-	-
C9_2	NOLBL_C10_2_1	-	-	-	-	-	-
C16_1	GND	●	●	-	-	-	-
C16_2	NOLBL_C16_2_1	-	-	-	-	-	-
C23_1	GND	●	●	-	-	-	-
C23_2	P0.00	-	-	-	-	-	-
C24_1	GND	●	●	-	-	-	-
C24_2	P0.01	-	-	-	-	-	-
R13_2	NOLBL_D6_3_K	-	-	-	-	-	-
R13_1	NOLBL_R13_1_1	-	-	-	-	-	-
C28_1	GND	-	●	-	-	-	-
C28_2	VDD	-	●	-	-	-	-
C25_1	GND	-	●	-	-	-	-
C25_2	VDD	-	●	-	-	-	-
U10_2	NOLBL_R30_1_1	-	-	-	-	-	-
U10_3	GND	-	●	-	-	-	-
U10_4	AUX1	-	-	-	-	-	-
U10_5	VDD	-	●	-	-	-	-
U9_2	P0.06	-	-	-	-	-	-
U9_3	GND	-	●	-	-	-	-
U9_4	NOLBL_R27_1_1	-	-	-	-	-	-
U9_5	+5v0	-	●	-	-	-	-
D13_2	AUX1-EXT	●	●	-	-	-	-
D13_1	GND	●	●	-	-	-	-
D12_2	NP1-EXT	●	●	-	-	-	-
D12_1	GND	●	●	-	-	-	-
R27_2	NP1-EXT	-	●	-	-	-	-
R27_1	NOLBL_R27_1_1	-	-	-	-	-	-
R30_2	AUX1-EXT	-	●	-	-	-	-
R30_1	NOLBL_R30_1_1	-	-	-	-	-	-
X1_1	NOLBL_C22_1_1	-	-	-	-	-	-
X1_3	NOLBL_C21_1_1	-	-	-	-	-	-
X2_1	P0.01	-	-	-	-	-	-
X2_2	P0.00	-	-	-	-	-	-
Q6_2,4	+VIN	-	●	-	-	-	-
Q6_1	NOLBL_D9_1_A	-	-	-	-	-	-
Q6_3	+VIN-PROTECT	-	●	-	-	-	-
R18_2	GND	-	●	-	-	-	-
R18_1	NOLBL_D9_1_A	-	-	-	-	-	-
D9_1	NOLBL_D9_1_A	-	-	-	-	-	-
D9_3	+VIN-PROTECT	-	●	-	-	-	-
R16_2	+5v0	●	●	-	-	-	-
R16_1	NOLBL_C14_1_1	-	-	-	-	-	-
R15_2	+5v0	●	●	-	-	-	-
R15_1	NOLBL_C14_1_1	-	-	-	-	-	-
C12_1	+5v0	-	●	-	-	-	-
C12_2	GND	-	●	-	-	-	-
C13_1	+5v0	-	●	-	-	-	-
C13_2	GND	-	●	-	-	-	-
L2_1	NOLBL_C10_2_1	-	-	-	-	-	-
L2_2	NOLBL_L2_2_2	-	-	-	-	-	-
L1_1	VDD	●	●	-	-	-	-
L1_2	NOLBL_L1_2_2	-	-	-	-	-	-
L3_1	NOLBL_L2_2_2	-	-	-	-	-	-
L3_2	NOLBL_L3_2_2	-	-	-	-	-	-
J6_1	SP-	-	●	-	-	-	-
J6_2	SP+	-	●	-	-	-	-
J5_1	+VIN	-	●	-	-	-	-
J5_2	CHG-LOOP	-	●	-	-	-	-
J5_3	GND	-	●	-	-	-	-
D14_2	CHG-LOOP	●	●	-	-	-	-
D14_1	GND	●	●	-	-	-	-
R32_2	CHG-LOOP	-	●	-	-	-	-
R32_1	CHG-DET	-	-	-	-	-	-
R31_2	P1.15	-	-	-	-	-	-
R31_1	CHG-LOOP	-	●	-	-	-	-
J3_1	+5v0-CH0	-	●	-	-	-	-
J3_2	NP0-EXT	-	●	-	-	-	-
J3_3	GND	-	●	-	-	-	-
J3_4	GND	-	●	-	-	-	-
J3_5	BTN0-EXT	-	●	-	-	-	-
J3_6	+5v0	-	●	-	-	-	-
C7_1	+VIN-PROTECT	-	●	-	-	-	-
C7_2	GND	-	●	-	-	-	-
D16_A	+5v0	-	●	-	-	-	-
D16_C	NOLBL_D16_C_C	-	-	-	-	-	-
R35_2	NOLBL_D16_C_C	-	-	-	-	-	-
R35_1	NOLBL_Q10_3_D	-	-	-	-	-	-
R34_2	NOLBL_D15_C_C	-	-	-	-	-	-
R34_1	NOLBL_Q9_3_D	-	-	-	-	-	-
D15_C	NOLBL_D15_C_C	-	-	-	-	-	-
D15_A	+5v0	-	●	-	-	-	-
R21_2	P0.09	-	-	-	-	-	-
R21_1	GND	●	●	-	-	-	-
R20_2	P0.10	-	-	-	-	-	-
R20_1	GND	●	●	-	-	-	-
R19_2	P0.11	-	-	-	-	-	-
R19_1	GND	●	●	-	-	-	-
J4_1	+5v0-CH1	-	●	-	-	-	-
J4_2	NP1-EXT	-	●	-	-	-	-
J4_3	AUX1-EXT	-	●	-	-	-	-
J4_4	GND	-	●	-	-	-	-
U1_1	+5v0-CH0	●	●	-	-	-	-
U1_2	GND	-	●	-	-	-	-
U1_3		-	-	-	-	-	-
U1_4	NP0-EN	-	-	-	-	-	-
U1_5	+5v0	-	●	-	-	-	-
U4_2	NOLBL_R12_1_1	-	-	-	-	-	-
U4_3	GND	-	●	-	-	-	-
U4_4	BTN0	-	-	-	-	-	-
U4_5	VDD	-	●	-	-	-	-
U8_1	+5v0-CH1	●	●	-	-	-	-
U8_2	GND	-	●	-	-	-	-
U8_3		-	-	-	-	-	-
U8_4	NP1-EN	-	-	-	-	-	-
U8_5	+5v0	-	●	-	-	-	-
Q9_3	NOLBL_Q9_3_D	-	-	-	-	-	-
Q9_1	P1.01	-	-	-	-	-	-
Q9_2	GND	-	●	-	-	-	-
Q10_3	NOLBL_Q10_3_D	-	-	-	-	-	-
Q10_1	GREEN-LED	-	-	-	-	-	-
Q10_2	GND	-	●	-	-	-	-
D7_1	+VBUS	-	●	-	-	-	-
D7_3	NOLBL_D6_3_K	-	-	-	-	-	-
D6_1	+5v0	-	●	-	-	-	-
D6_3	NOLBL_D6_3_K	-	-	-	-	-	-
R38_2	VDD	●	●	-	-	-	-
R38_1	NOLBL_R38_1_1	-	-	-	-	-	-
R14_2	VDD	●	●	-	-	-	-
R14_1	NOLBL_R14_1_1	-	-	-	-	-	-
U7_3	+VIN-PROTECT	-	●	-	-	-	-
U7_1	NOLBL_C5_2_1	-	-	-	-	-	-
U7_2	+VIN-PROTECT	-	●	-	-	-	-
U7_4	NOLBL_R22_1_1	-	-	-	-	-	-
U7_5	NOLBL_R17_1_1	-	-	-	-	-	-
U7_6	NOLBL_C15_2_1	-	-	-	-	-	-
U7_7	GND	●	●	-	-	-	-
U7_8	NOLBL_C5_1_1	-	-	-	-	-	-
U7_9	GND	●	●	-	-	-	-

14.11 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.11.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	47.8%	12.2%	0.0%	1.2%	0.0%	22.6%	18.8%	0.0%
Optical Inspection (AOI)	2.6%	2.6%	2.6%	0.0%	0.4%	0.0%	1.0%	1.0%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	0.9%	2.8%	2.8%	2.8%
Combined	49.1%	14.8%	2.6%	1.2%	1.3%	24.2%	22.0%	3.8%

14.11.2 PCB Device/Pin Count

Devices (PCOLA): 115
Pins (SOQ): 394

14.11.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	13809 / 100,000	13.8%
SOQ	16667 / 100,000	16.7%
Combined	15238 / 100,000	15.2%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	12244 / 100,000	13790 / 100,000
Optical/X-ray Inspection	1826 / 100,000	3469 / 100,000
Combined (max)	13809 / 100,000	16667 / 100,000

14.11.4 PCOLA (115 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
70%	U14	MAX98357AETE+T / QFN50P300X300X80_HS-17N-2	IC	●	●	●	○	◐	AOI, AXI, Powered_Off
70%	U12	MX25R6435FZNIL0 / SON127P600X80_HS-9N	IC	●	●	●	○	◐	AOI, AXI, Powered_Off
70%	U2	TJA1021T / SOIC127P600X175-8N	IC	●	●	●	○	◐	AOI, Powered_Off
40%	R5	R_2P / R0603_0.55MM_HD *	Resistor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C28	C_2P_NP / C0603_0.90MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C8	C_2P_NP / C1210_2.80MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C1	C_2P_NP / C0402_0.55MM_HD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C26	C_2P_NP / C0603_0.90MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C27	C_2P_NP / C0805_1.40MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C6	C_2P_NP / C0805_1.40MM_HD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C2	C_2P_NP / C0402_0.55MM_HD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C3	C_2P_NP / C0402_0.55MM_HD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C7	C_2P_P / C_ALU_F *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C13	C_2P_P / C_ALU_D *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C12	C_2P_P / C_ALU_D *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C4	C_2P_NP / C0402_0.55MM_HD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C25	C_2P_NP / C0603_0.90MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
20%	U5	nRF52840-QIAA / AQFN50P700X700X85_HS-74N *	IC	◐	○	○	◐	○	LSSI, Powered_Off
10%	J8	USB4145-03-0230-C / USB4145-03-0230-C *	Connector	◐	○	○	—	○	Powered_Off
10%	R36	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R37	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	U15	PRTR5V0U2X,215 / SOT143B *	IC	◐	○	○	○	○	Powered_Off
10%	R33	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	L5	L_2P / L0805_1.45MM_MD *	Inductor	◐	○	○	—	○	Powered_Off
10%	L6	L_2P / L0805_1.45MM_MD *	Inductor	◐	○	○	—	○	Powered_Off
10%	U3	SN74LV1T34DBVR / SOT23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	D8	PESD5V0S1BA-115 / D_SOD-323_P *	Diode	◐	○	○	○	○	Powered_Off
10%	D5	PESD5V0S1BA-115 / D_SOD-323_P *	Diode	◐	○	○	○	○	Powered_Off
10%	R9	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R12	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R11	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R38	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R10	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	D4	PESD1IVN24-AX / D_SOD-323_P *	Diode	◐	○	○	○	○	Powered_Off
10%	Q5	MOSFET-N-CH-SOT23-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	D1	DZ_1A_3C / D_SOT-23-3_P *	Diode	◐	○	○	○	○	Powered_Off
10%	R1	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R14	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	Q4	MOSFET-N-CH-SOT23-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	Q1	MOSFET-P-CH-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	R6	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	Q3	MOSFET-N-CH-SOT23-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	R7	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R28	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	D11	DZ_1A_3C / D_SOT-23-3_P *	Diode	◐	○	○	○	○	Powered_Off
10%	R24	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	U11	opamp-sot23-5 / sot23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	Q8	MOSFET-N-CH-SOT23-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	Q7	MOSFET-P-CH-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	R29	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	C15	C_2P_NP / C0603_0.90MM_MD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R23	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R22	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	C14	C_2P_P / C_ALU_D *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J9	CORTEX-DEBUG / FTSH-105-05-F-DV *	Connector	◐	○	○	—	○	Powered_Off
10%	U13	FM25-FRAM / SOIC 8 *	IC	◐	○	○	○	○	Powered_Off
10%	C11	C_2P_NP / C0603_0.90MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C10	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C18	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C20	C_2P_NP / C0805_1.40MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C21	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C22	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C17	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C19	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C9	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C16	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C23	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C24	C_2P_NP / C0402_0.55MM_HD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U10	SN74LV1T34DBVR / SOT23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	U9	SN74LV1T34DBVR / SOT23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	D13	PESD5V0S1BA-115 / D_SOD-323_P *	Diode	◐	○	○	○	○	Powered_Off
10%	D12	PESD5V0S1BA-115 / D_SOD-323_P *	Diode	◐	○	○	○	○	Powered_Off
10%	R27	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R30	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	Q6	MOSFET-P-CH-1G2D4D3S / SOT223 *	Transistor	◐	○	○	○	○	Powered_Off
10%	R18	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	D9	DZ_1A_3C / D_SOT-23-3_P *	Diode	◐	○	○	○	○	Powered_Off
10%	R16	R_2P / R0805_0.70MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R15	R_2P / R0805_0.70MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	L1	Inductor / C0603_0.90MM_MD *	Inductor	◐	○	○	—	○	Powered_Off
10%	D14	PESD5V0S1BA-115 / D_SOD-323_P *	Diode	◐	○	○	○	○	Powered_Off
10%	R32	R_2P / R0603_0.55MM_MD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R31	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	D16	LED-GREEN / LED-0805-GREEN *	Diode	◐	○	○	○	○	Powered_Off
10%	U7	AP64352SP-13 / SO8-EP *	IC	◐	○	○	○	○	Powered_Off
10%	D15	LED-RED / LED-0805-RED *	Diode	◐	○	○	○	○	Powered_Off
10%	R21	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R20	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R19	R_2P / R0603_0.55MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	U1	AP22804AW5-7 / SOT23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	U4	SN74LV1T34DBVR / SOT23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	U8	AP22804AW5-7 / SOT23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	Q9	MOSFET-N-CH-SOT23-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	Q10	MOSFET-N-CH-SOT23-1G2S3D / SOT-23 *	Transistor	◐	○	○	○	○	Powered_Off
10%	D7	DP_1A_3C / D_SOT-23-3_P *	Diode	◐	○	○	○	○	Powered_Off
10%	D6	DP_1A_3C / D_SOT-23-3_P *	Diode	◐	○	○	○	○	Powered_Off
0%	R8	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	R4	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	X2	CRYSTAL-2P--1-2 / XTAL_3215 *	Oscillator	○	○	○	○	○
0%	R35	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	D3	DP_1A_3C / D_SOT-23-3_P *	Diode	○	○	○	○	○
0%	Q2	MOSFET-P-CH-1G2S3D / SOT-23 *	Transistor	○	○	○	○	○
0%	R25	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	R26	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	C5	C_2P_NP / C0603_0.90MM_MD *	Capacitor	○	○	○	—	○
0%	R3	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	R2	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	L2	Inductor / C0402_0.55MM_MD *	Inductor	○	○	○	—	○
0%	L4	L_2P / L_MSS1038 *	Inductor	○	○	○	—	○
0%	L3	Inductor / C0603_0.90MM_MD *	Inductor	○	○	○	—	○
0%	R17	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○
0%	R13	R_2P / R0805_0.70MM_HD *	Resistor	○	○	○	—	○
0%	X1	CRYSTAL-4P--1-3 / XTAL_2016 *	Oscillator	○	○	○	○	○
0%	D2	DZ_1A_3C / D_SOT-23-3_P *	Diode	○	○	○	○	○
0%	R34	R_2P / R0603_0.55MM_HD *	Resistor	○	○	○	—	○

14.11.5 SOQ (394 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
67%	U14_11	GND	◐	●	◐
67%	U14_15	GND	◐	●	◐
67%	U2_6	LIN-IO	◐	●	◐
67%	U14_17	GND	◐	●	◐
67%	U14_3	GND	◐	●	◐
50%	U15_1	GND	◐	●	○
50%	R14_2	VDD	◐	●	○
50%	U12_3	QSPI-D2	◐	◐	◐
50%	R6_1	GND	◐	●	○
50%	R23_2	GND	◐	●	○
50%	U12_6	QSPI-SCLK	◐	◐	◐
50%	U7_7	GND	◐	●	○
50%	U12_2	QSPI-D1	◐	◐	◐
50%	U13_8	VDD	◐	●	○
50%	C11_1	GND	◐	●	○
50%	C14_2	GND	◐	●	○
50%	U5_W1	VDD	◐	●	○
50%	R5_2	P1.06	◐	●	○
50%	R5_1	GND	◐	●	○
50%	R22_2	GND	◐	●	○
50%	C10_1	GND	◐	●	○
50%	U5_A22	VDD	◐	●	○
50%	U5_AA24	SWDCLK	◐	●	○
50%	U5_B7	GND	◐	●	○
50%	U5_B1	VDD	◐	●	○
50%	R28_2	GND	◐	●	○
50%	U5_AC24	SWDIO	◐	●	○
50%	J9_2	SWDIO	◐	●	○
50%	U5_AD23	VDD	◐	●	○
50%	U12_7	QSPI-D3	◐	◐	◐
50%	U15_4	+VBUS	◐	●	○
50%	U5_AC13	RESET	◐	●	○
50%	U5_AD8	P0.13	◐	●	○
50%	U5_AD10	TEST1	◐	●	○
50%	U5_AD14	VDD	◐	●	○
50%	U5_R24	P1.06	◐	●	○
50%	U5_74	GND	◐	●	○
50%	R33_2	GND	◐	●	○
50%	C18_1	GND	◐	●	○
50%	U14_7	+5v0	◐	◐	◐
50%	U14_16	SP-BCK	◐	◐	◐
50%	U14_10	NOLBL_L5_1_1	◐	◐	◐
50%	U14_1	SP-DIN	◐	◐	◐
50%	U14_2	NOLBL_R33_1_1	◐	◐	◐
50%	U14_14	SP-LRCLK	◐	◐	◐
50%	U14_4	P0.05	◐	◐	◐
50%	U14_8	+5v0	◐	◐	◐
50%	U14_9	NOLBL_L6_1_1	◐	◐	◐
50%	C20_1	GND	◐	●	○
50%	C21_2	GND	◐	●	○
50%	C22_2	GND	◐	●	○
50%	C17_1	GND	◐	●	○
50%	C19_1	GND	◐	●	○
50%	C9_1	GND	◐	●	○
50%	J9_4	SWDCLK	◐	●	○
50%	C16_1	GND	◐	●	○
50%	D8_2	BTN0-EXT	◐	●	○
50%	D8_1	GND	◐	●	○
50%	D5_2	NP0-EXT	◐	●	○
50%	D5_1	GND	◐	●	○
50%	C23_1	GND	◐	●	○
50%	C24_1	GND	◐	●	○
50%	U7_9	GND	◐	●	○
50%	U5_F23	GND	◐	●	○
50%	D13_2	AUX1-EXT	◐	●	○
50%	D13_1	GND	◐	●	○
50%	D12_2	NP1-EXT	◐	●	○
50%	D12_1	GND	◐	●	○
50%	U2_5	GND	◐	◐	◐
50%	R16_2	+5v0	◐	●	○
50%	R15_2	+5v0	◐	●	○
50%	L1_1	VDD	◐	●	○
50%	R11_1	VDD	◐	●	○
50%	D14_2	CHG-LOOP	◐	●	○
50%	U11_2	GND	◐	●	○
50%	D14_1	GND	◐	●	○
50%	R10_1	GND	◐	●	○
50%	D4_2	LIN-IO	◐	●	○
50%	D4_1	GND	◐	●	○
50%	J9_10	RESET	◐	●	○
50%	U12_1	QSPI-CS	◐	◐	◐
50%	R21_1	GND	◐	●	○
50%	U12_9	GND	◐	◐	◐
50%	R20_1	GND	◐	●	○
50%	R19_1	GND	◐	●	○
50%	U1_1	+5v0-CH0	◐	●	○
50%	U12_4	GND	◐	◐	◐
50%	U12_8	VDD	◐	◐	◐
50%	U8_1	+5v0-CH1	◐	●	○
50%	U12_5	P0.21	◐	◐	◐
50%	R38_2	VDD	◐	●	○
50%	R29_1	GND	◐	●	○
50%	C15_1	GND	◐	●	○
33%	U2_8	NOLBL_D2_3_K	○	◐	◐
33%	U2_1	LIN-RX-OUT	○	◐	◐
33%	U2_2	LIN-SLP-N	○	◐	◐
33%	U2_3	NOLBL_Q5_3_D	○	◐	◐
33%	U2_4	LIN-TX-IN	○	◐	◐
33%	U2_7	NOLBL_Q1_3_D	○	◐	◐
17%	J8_A12	GND	◐	○	○
17%	J8_A1	GND	◐	○	○
17%	J8_A9	+VBUS	◐	○	○
17%	R7_2	LIN-IO	◐	○	○
17%	J8_A6	USB-DEVICE-D_P	◐	○	○
17%	J8_A7	USB-DEVICE-D_N	◐	○	○
17%	U5_AD4	USB-DEVICE-D_N	◐	○	○
17%	J8_B6	USB-DEVICE-D_P	◐	○	○
17%	J8_S1	GND	◐	○	○
17%	J8_S2	GND	◐	○	○
17%	J8_B4	+VBUS	◐	○	○
17%	J8_S3	GND	◐	○	○
17%	J8_S4	GND	◐	○	○
17%	J8_B9	+VBUS	◐	○	○
17%	J9_1	VDD	◐	○	○
17%	J8_B7	USB-DEVICE-D_N	◐	○	○
17%	J8_B1	GND	◐	○	○
17%	J8_B12	GND	◐	○	○
17%	R36_1	GND	◐	○	○
17%	R37_1	GND	◐	○	○
17%	U15_2	USB-DEVICE-D_P	◐	○	○
17%	U15_3	USB-DEVICE-D_N	◐	○	○
17%	C26_1	GND	◐	○	○
17%	C26_2	+5v0	◐	○	○
17%	C27_1	GND	◐	○	○
17%	C27_2	+5v0	◐	○	○
17%	J9_3	GND	◐	○	○
17%	D11_3	+VIN-PROTECT	◐	○	○
17%	L5_2	SP+	◐	○	○
17%	U10_3	GND	◐	○	○
17%	L6_2	SP-	◐	○	○
17%	R24_2	+VIN-PROTECT	◐	○	○
17%	U3_3	GND	◐	○	○
17%	U3_5	+5v0	◐	○	○
17%	R9_2	NP0-EXT	◐	○	○
17%	J9_5	GND	◐	○	○
17%	R12_2	BTN0-EXT	◐	○	○
17%	U13_4	GND	◐	○	○
17%	C6_1	GND	◐	○	○
17%	J9_9	GND	◐	○	○
17%	Q5_2	GND	◐	○	○
17%	D1_3	+VIN-PROTECT	◐	○	○
17%	R1_2	+VIN-PROTECT	◐	○	○
17%	Q8_2	GND	◐	○	○
17%	Q7_2	+VIN-PROTECT	◐	○	○
17%	Q4_2	GND	◐	○	○
17%	Q1_2	+VIN-PROTECT	◐	○	○
17%	C25_1	GND	◐	○	○
17%	C25_2	VDD	◐	○	○
17%	C4_2	VDD	◐	○	○
17%	U10_5	VDD	◐	○	○
17%	U9_3	GND	◐	○	○
17%	U9_5	+5v0	◐	○	○
17%	C3_1	GND	◐	○	○
17%	C3_2	VDD	◐	○	○
17%	C2_1	GND	◐	○	○
17%	C2_2	VDD	◐	○	○
17%	R27_2	NP1-EXT	◐	○	○
17%	R30_2	AUX1-EXT	◐	○	○
17%	Q6_2,4	+VIN	◐	○	○
17%	Q6_3	+VIN-PROTECT	◐	○	○
17%	R18_2	GND	◐	○	○
17%	D9_3	+VIN-PROTECT	◐	○	○
17%	C1_1	GND	◐	○	○
17%	C1_2	VDD	◐	○	○
17%	C12_1	+5v0	◐	○	○
17%	C12_2	GND	◐	○	○
17%	C13_1	+5v0	◐	○	○
17%	C13_2	GND	◐	○	○
17%	Q3_1	P1.06	◐	○	○
17%	Q3_2	GND	◐	○	○
17%	C8_2	GND	◐	○	○
17%	R32_2	CHG-LOOP	◐	○	○
17%	J8_A4	+VBUS	◐	○	○
17%	C7_1	+VIN-PROTECT	◐	○	○
17%	C7_2	GND	◐	○	○
17%	D16_A	+5v0	◐	○	○
17%	D15_A	+5v0	◐	○	○
17%	C6_2	VDD	◐	○	○
17%	U5_AD6	USB-DEVICE-D_P	◐	○	○
17%	C8_1	+VIN-PROTECT	◐	○	○
17%	U5_AD2	+VBUS	◐	○	○
17%	U1_2	GND	◐	○	○
17%	U1_5	+5v0	◐	○	○
17%	U4_3	GND	◐	○	○
17%	U4_5	VDD	◐	○	○
17%	C4_1	GND	◐	○	○
17%	U8_2	GND	◐	○	○
17%	U8_5	+5v0	◐	○	○
17%	Q9_2	GND	◐	○	○
17%	Q10_2	GND	◐	○	○
17%	D7_1	+VBUS	◐	○	○
17%	D6_1	+5v0	◐	○	○
17%	C28_1	GND	◐	○	○
17%	C28_2	VDD	◐	○	○
17%	U7_3	+VIN-PROTECT	◐	○	○
17%	U7_2	+VIN-PROTECT	◐	○	○
17%	R31_1	CHG-LOOP	◐	○	○
0%	L6_1	NOLBL_L6_1_1	○	○	○
0%	J8_A5	CC1	○	○	○
0%	U5_M2	SP-BCK	○	○	○
0%	J8_A8		○	○	○
0%	U5_A20	P1.10	○	○	○
0%	U5_U1	SP-DIN	○	○	○
0%	U5_D2	P0.00	○	○	○
0%	J8_B5	CC2	○	○	○
0%	U5_F2	P0.01	○	○	○
0%	U5_B11	LIN-WAKE	○	○	○
0%	U5_B5	NOLBL_C10_2_1	○	○	○
0%	U5_U24	P1.04	○	○	○
0%	J8_B8		○	○	○
0%	R36_2	CC2	○	○	○
0%	U5_B3	NOLBL_L3_2_2	○	○	○
0%	U5_B15	P1.14	○	○	○
0%	U5_J24	P0.10	○	○	○
0%	R37_2	CC1	○	○	○
0%	U5_T2	P0.11	○	○	○
0%	U5_AC15	P0.19	○	○	○
0%	U5_Y2	NOLBL_R13_1_1	○	○	○
0%	U5_K2	P0.05	○	○	○
0%	U5_AB2	NOLBL_L1_2_2	○	○	○
0%	U5_AC5	NOLBL_C20_2_1	○	○	○
0%	U5_AD20	QSPI-CS	○	○	○
0%	R33_1	NOLBL_R33_1_1	○	○	○
0%	U5_P2	P1.08	○	○	○
0%	U5_AC19	QSPI-D3	○	○	○
0%	U5_AD16	QSPI-D2	○	○	○
0%	U5_AD18	QSPI-D1	○	○	○
0%	U5_AC17	P0.21	○	○	○
0%	U5_N24	NOLBL_C16_2_1	○	○	○
0%	L5_1	NOLBL_L5_1_1	○	○	○
0%	U5_L24	P0.09	○	○	○
0%	U5_R1	SP-LRCLK	○	○	○
0%	U5_AC21	FRAM-CLK	○	○	○
0%	U5_J1	NP1-EN	○	○	○
0%	U5_G1	P0.26	○	○	○
0%	U5_A10	LIN-TX-IN	○	○	○
0%	U3_2	NP0	○	○	○
0%	U5_H2	LIN-PWR	○	○	○
0%	U5_L1	P0.06	○	○	○
0%	U3_4	NOLBL_R9_1_1	○	○	○
0%	U5_AC9	QSPI-SCLK	○	○	○
0%	R9_1	NOLBL_R9_1_1	○	○	○
0%	U5_A12	P0.02	○	○	○
0%	U5_AC11	P0.16	○	○	○
0%	U5_AD12	P0.17	○	○	○
0%	U5_B13	P0.03	○	○	○
0%	U5_B9	LIN-RX-OUT	○	○	○
0%	U5_P23	NP0	○	○	○
0%	U5_A8	LIN-SLP-N	○	○	○
0%	R12_1	NOLBL_R12_1_1	○	○	○
0%	U5_W24	FRAM-CS	○	○	○
0%	U5_V23	FRAM-SDO	○	○	○
0%	U5_T23	BTN0	○	○	○
0%	R11_2	LIN-RX-OUT	○	○	○
0%	U5_B19	NP0-EN	○	○	○
0%	U5_B17	P1.12	○	○	○
0%	U5_A16	CHG-DET	○	○	○
0%	U5_A14	P1.15	○	○	○
0%	U5_A18	NOLBL_C18_2_1	○	○	○
0%	R8_2	NOLBL_Q5_3_D	○	○	○
0%	R8_1	NOLBL_Q1_3_D	○	○	○
0%	C18_2	NOLBL_C18_2_1	○	○	○
0%	R10_2	LIN-WAKE	○	○	○
0%	C20_2	NOLBL_C20_2_1	○	○	○
0%	Q5_3	NOLBL_Q5_3_D	○	○	○
0%	Q5_1	LIN-WAKE	○	○	○
0%	D1_1	NOLBL_D1_1_A	○	○	○
0%	R1_1	NOLBL_D1_1_A	○	○	○
0%	R4_2	NOLBL_Q4_3_D	○	○	○
0%	R4_1	NOLBL_D1_1_A	○	○	○
0%	Q4_3	NOLBL_Q4_3_D	○	○	○
0%	Q4_1	LIN-PWR	○	○	○
0%	C21_1	NOLBL_C21_1_1	○	○	○
0%	Q1_3	NOLBL_Q1_3_D	○	○	○
0%	C22_1	NOLBL_C22_1_1	○	○	○
0%	Q1_1	NOLBL_D1_1_A	○	○	○
0%	R6_2	LIN-PWR	○	○	○
0%	C17_2	NOLBL_C17_2_1	○	○	○
0%	D2_1	NOLBL_D2_1_A	○	○	○
0%	C19_2	NOLBL_C19_2_1	○	○	○
0%	D2_3	NOLBL_D2_3_K	○	○	○
0%	C9_2	NOLBL_C10_2_1	○	○	○
0%	R2_2	NOLBL_D2_3_K	○	○	○
0%	C16_2	NOLBL_C16_2_1	○	○	○
0%	R2_1	NOLBL_D2_1_A	○	○	○
0%	C23_2	P0.00	○	○	○
0%	R3_2	NOLBL_Q3_3_D	○	○	○
0%	C24_2	P0.01	○	○	○
0%	R13_2	NOLBL_D6_3_K	○	○	○
0%	R13_1	NOLBL_R13_1_1	○	○	○
0%	R3_1	NOLBL_D2_1_A	○	○	○
0%	Q3_3	NOLBL_Q3_3_D	○	○	○
0%	Q2_3	NOLBL_D3_1_A	○	○	○
0%	Q2_1	NOLBL_D2_1_A	○	○	○
0%	U10_2	NOLBL_R30_1_1	○	○	○
0%	Q2_2	NOLBL_D2_3_K	○	○	○
0%	U10_4	AUX1	○	○	○
0%	D3_1	NOLBL_D3_1_A	○	○	○
0%	U9_2	P0.06	○	○	○
0%	D3_3	NOLBL_D3_3_K	○	○	○
0%	U9_4	NOLBL_R27_1_1	○	○	○
0%	R7_1	NOLBL_D3_3_K	○	○	○
0%	R26_2	NOLBL_Q7_3_D	○	○	○
0%	R26_1	NOLBL_R26_1_1	○	○	○
0%	R28_1	NOLBL_R26_1_1	○	○	○
0%	D11_1	NOLBL_D11_1_A	○	○	○
0%	R24_1	NOLBL_D11_1_A	○	○	○
0%	R27_1	NOLBL_R27_1_1	○	○	○
0%	R25_2	NOLBL_Q8_3_D	○	○	○
0%	R30_1	NOLBL_R30_1_1	○	○	○
0%	X1_1	NOLBL_C22_1_1	○	○	○
0%	X1_3	NOLBL_C21_1_1	○	○	○
0%	X2_1	P0.01	○	○	○
0%	X2_2	P0.00	○	○	○
0%	R25_1	NOLBL_D11_1_A	○	○	○
0%	Q6_1	NOLBL_D9_1_A	○	○	○
0%	U11_3	NOLBL_R26_1_1	○	○	○
0%	U11_4	P0.02	○	○	○
0%	R18_1	NOLBL_D9_1_A	○	○	○
0%	D9_1	NOLBL_D9_1_A	○	○	○
0%	U11_5	P0.03	○	○	○
0%	U11_1	P0.02	○	○	○
0%	R16_1	NOLBL_C14_1_1	○	○	○
0%	Q8_3	NOLBL_Q8_3_D	○	○	○
0%	R15_1	NOLBL_C14_1_1	○	○	○
0%	Q8_1	P0.03	○	○	○
0%	Q7_3	NOLBL_Q7_3_D	○	○	○
0%	Q7_1	NOLBL_D11_1_A	○	○	○
0%	R29_2	P0.03	○	○	○
0%	L2_1	NOLBL_C10_2_1	○	○	○
0%	L2_2	NOLBL_L2_2_2	○	○	○
0%	C15_2	NOLBL_C15_2_1	○	○	○
0%	L1_2	NOLBL_L1_2_2	○	○	○
0%	L3_1	NOLBL_L2_2_2	○	○	○
0%	L3_2	NOLBL_L3_2_2	○	○	○
0%	R23_1	NOLBL_R17_1_1	○	○	○
0%	R17_2	NOLBL_C14_1_1	○	○	○
0%	R17_1	NOLBL_R17_1_1	○	○	○
0%	R32_1	CHG-DET	○	○	○
0%	R31_2	P1.15	○	○	○
0%	L4_1	NOLBL_C5_1_1	○	○	○
0%	L4_2	NOLBL_C14_1_1	○	○	○
0%	C5_1	NOLBL_C5_1_1	○	○	○
0%	C5_2	NOLBL_C5_2_1	○	○	○
0%	U5_B24	NOLBL_C22_1_1	○	○	○
0%	R35_2	NOLBL_D16_C_C	○	○	○
0%	R35_1	NOLBL_Q10_3_D	○	○	○
0%	R34_2	NOLBL_D15_C_C	○	○	○
0%	R34_1	NOLBL_Q9_3_D	○	○	○
0%	D15_C	NOLBL_D15_C_C	○	○	○
0%	R22_1	NOLBL_R22_1_1	○	○	○
0%	R21_2	P0.09	○	○	○
0%	C14_1	NOLBL_C14_1_1	○	○	○
0%	R20_2	P0.10	○	○	○
0%	J9_6	UNC_J9_6_SWO/TDO	○	○	○
0%	R19_2	P0.11	○	○	○
0%	J9_7		○	○	○
0%	J9_8	UNC_J9_8_TDI	○	○	○
0%	U13_7	NOLBL_R38_1_1	○	○	○
0%	U1_3		○	○	○
0%	U1_4	NP0-EN	○	○	○
0%	U13_1	FRAM-CS	○	○	○
0%	U4_2	NOLBL_R12_1_1	○	○	○
0%	U13_6	FRAM-CLK	○	○	○
0%	U4_4	BTN0	○	○	○
0%	U13_2	FRAM-SDO	○	○	○
0%	U13_3	NOLBL_R14_1_1	○	○	○
0%	U13_5	P1.04	○	○	○
0%	U8_3		○	○	○
0%	U8_4	NP1-EN	○	○	○
0%	C11_2	NOLBL_C10_2_1	○	○	○
0%	Q9_3	NOLBL_Q9_3_D	○	○	○
0%	Q9_1	P1.01	○	○	○
0%	C10_2	NOLBL_C10_2_1	○	○	○
0%	Q10_3	NOLBL_Q10_3_D	○	○	○
0%	Q10_1	GREEN-LED	○	○	○
0%	U5_C1	NOLBL_C17_2_1	○	○	○
0%	U5_E24	NOLBL_C10_2_1	○	○	○
0%	D7_3	NOLBL_D6_3_K	○	○	○
0%	U5_AD22	GREEN-LED	○	○	○
0%	D6_3	NOLBL_D6_3_K	○	○	○
0%	U5_H23		○	○	○
0%	R38_1	NOLBL_R38_1_1	○	○	○
0%	U5_N1	AUX1	○	○	○
0%	R14_1	NOLBL_R14_1_1	○	○	○
0%	U5_D23	NOLBL_C19_2_1	○	○	○
0%	U7_1	NOLBL_C5_2_1	○	○	○
0%	U5_A23	NOLBL_C21_1_1	○	○	○
0%	U7_4	NOLBL_R22_1_1	○	○	○
0%	U7_5	NOLBL_R17_1_1	○	○	○
0%	U7_6	NOLBL_C15_2_1	○	○	○
0%	U5_Y23	P1.01	○	○	○
0%	U7_8	NOLBL_C5_1_1	○	○	○
0%	D16_C	NOLBL_D16_C_C	○	○	○

14.11.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Component Properties

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Model Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U1	F	5	0	0	0	0	0	0	0	5	AP22804AW5-7
U10	F	4	0	0	0	0	0	0	0	4	SN74LV1T34DBVR
U11	F	5	0	0	0	0	0	0	0	5	opamp-sot23-5
U12	F	9	0	0	0	0	0	0	0	9	MX25R6435FZNIL0
U13	F	8	0	0	0	0	0	0	0	8	FM25-FRAM
U15	F	4	0	0	0	0	0	0	0	4	PRTR5V0U2X,215
U2	F	8	0	0	0	0	0	0	0	8	TJA1021T
U3	F	4	0	0	0	0	0	0	0	4	SN74LV1T34DBVR
U4	F	4	0	0	0	0	0	0	0	4	SN74LV1T34DBVR
U7	F	9	0	0	0	0	0	0	0	9	AP64352SP-13
U8	F	5	0	0	0	0	0	0	0	5	AP22804AW5-7
U9	F	4	0	0	0	0	0	0	0	4	SN74LV1T34DBVR
U14	B	13	6	0	2	0	0	0	0	5	MAX98357AETE+T
U5	B	74	18	0	2	52	0	0	0	2	nRF52840-QIAA

15.1.1 Library Quality Summary

Total ICs evaluated	14
Grade A (excellent)	0 (0.0%)
Grade B (good)	2 (14.3%)
Grade C (fair)	0 (0.0%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	12 (85.7%)
OVERALL LIBRARY QUALITY	F (0.49/4.00)

15.2 Component Library Validation

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (9 models)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
AP22804AW5-7	AP22804AW5-7	AP22804AW5-7	U1, U8	5	P:5	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [OUT=Passive, GND=Passive, IN=Passive]
AP64352SP-13	AP64352SP-13	AP64352SP-13	U7	9	P:9	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [BST=Passive, VIN=Passive, GND=Passive, SW=Passive]
FM25-FRAM	FM25L16B-GTR	-	U13	8	P:8	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [VCC=Passive, VSS=Passive]
MX25R6435FZNIL0	MX25R6435FZNIL0	MX25R6435FZNIL0	U12	9	P:9	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, GND=Passive, VCC=Passive]
PRTR5V0U2X,215	PRTR5V0U2X,215	PRTR5V0U2X,215	U15	4	P:4	All pins marked as Passive - likely generic library model; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, VCC=Passive]
SN74LV1T34DBVR	SN74LV1T34DBVR	-	U3, U4, U9, U10	4	P:4	All pins marked as Passive - likely generic library model; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, VCC=Passive]
TJA1021T	TJA1021T/20/CM,118	TJA1021T/20/CM,118	U2	8	P:8	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, VBAT=Passive]
nRF52840-QIAA	NRF52840-QIAA-R	NRF52840-QIAA-R	U5	74	P:2 Pwr:18 Bi:52 O:2	Power-named pins not typed as Power - library pin types incomplete [DCC=Output]
opamp-sot23-5	TLV271CW5-7	TLV271CW5-7	U11	5	P:5	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, VCC=Passive, OUT=Passive]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Shielded Connector Model Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.4 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
J1	WIREPAD-18AWG-4X-3.5MM	4	Footprint	WIREPAD-18AWG-4X-3.5MM
J2	WIREPAD-18AWG-4X-3.5MM	4	Footprint	WIREPAD-18AWG-4X-3.5MM
J3	WIREPAD-22AWG-6X-3.5MM	6	Footprint	WIREPAD-22AWG-6X-3.5MM
J4	WIREPAD-22AWG-4X-3.5MM	4	Footprint	WIREPAD-22AWG-4X-3.5MM
J5	WIREPAD-22AWG-3X-3.5MM	3	Footprint	WIREPAD-22AWG-3X-3.5MM
J7	TAG-CONNECT-SWD	6	Footprint	TC2030
J8	USB4145-03-0230-C	20	Footprint	USB4145-03-0230-C:USB4145-03-0230-C
J9	20021121-00010T4LF	10	Footprint	FTSH-105-05-F-DV
Q1	BSS84-7-F	3	Footprint	SOT-23
Q2	BSS84-7-F	3	Footprint	SOT-23
Q3	2N7002P,215	3	Footprint	SOT-23
Q4	2N7002P,215	3	Footprint	SOT-23
Q5	BSS138K	3	Footprint	SOT-23
Q6	ZXMP4A16GTA	3	Footprint	SOT223:SOT223
Q7	BSS84-7-F	3	Footprint	SOT-23
Q8	2N7002P,215	3	Footprint	SOT-23
Q9	2N7002P,215	3	Footprint	SOT-23
Q10	2N7002P,215	3	Footprint	SOT-23
TP1	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP2	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP3	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP4	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP5	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP6	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP7	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP8	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP9	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP10	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP11	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP12	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP13	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP14	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP15	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP16	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP17	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP18	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP19	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP20	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP21	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP22	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP23	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP24	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP25	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP26	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
TP27	SMT_TP-1MM	1	Footprint	SMT_TP-1MM:SMT_TP-1MM
U1	AP22804AW5-7	5	Footprint	SOT23-5
U2	TJA1021T/20/CM,118	8	Footprint	SOIC127P600X175-8N
			(IPC-7351B)	Small Outline IC, 127 pins, 6.00mm pitch
U3	SN74LV1T34DBVR	4	Footprint	SOT23-5
U4	SN74LV1T34DBVR	4	Footprint	SOT23-5
U5	NRF52840-QIAA-R	74	Footprint	AQFN50P700X700X85_HS-74N
U7	AP64352SP-13	9	Footprint	SO8-EP:SO8-EP
U8	AP22804AW5-7	5	Footprint	SOT23-5
U9	SN74LV1T34DBVR	4	Footprint	SOT23-5
U10	SN74LV1T34DBVR	4	Footprint	SOT23-5
U11	TLV271CW5-7	5	Footprint	sot23-5
U12	MX25R6435FZNIL0	9	Footprint	SON127P600X80_HS-9N
			(IPC-7351B)	Small Outline No-lead, 127 pins, 6.00mm pitch
U13	FM25L16B-GTR	8	Footprint	SOIC 8:SOIC 8
U14	MAX98357AETE+T	13	Footprint	QFN50P300X300X80_HS-17N-2
			(IPC-7351B)	Quad Flat No-lead, 50 pins, 3.00mm pitch
U15	PRTR5V0U2X,215	4	Footprint	SOT143B

15.5 IC Pin Electrical Properties

Unique IC models	10
Total IC instances	14

IC Library Models
Industry Name	Library Name	RefDes	Notes
AP22804AW5-7	AP22804AW5-7	U1, U8
AP64352SP-13	AP64352SP-13	U7
FM25L16B-GTR	FM25-FRAM	U13
MAX98357AETE+T	MAX98357AETE+T	U14
MX25R6435FZNIL0	MX25R6435FZNIL0	U12
PRTR5V0U2X,215	PRTR5V0U2X,215	U15
SN74LV1T34DBVR	SN74LV1T34DBVR	U3, U4, U9, U10
TJA1021T/20/CM,118	TJA1021T	U2
NRF52840-QIAA-R	nRF52840-QIAA	U5
TLV271CW5-7	opamp-sot23-5	U11

15.5.1 AP22804AW5-7 (AP22804AW5-7)

Pin	Pin Name	Electrical
1	OUT	Passive
2	GND	Passive
3	FLAG	Passive
4	EN	Passive
5	IN	Passive

15.5.2 AP64352SP-13 (AP64352SP-13)

Pin	Pin Name	Electrical
1	BST	Passive
2	VIN	Passive
3	EN	Passive
4	RT/CLK	Passive
5	FB	Passive
6	SS	Passive
7	GND	Passive
8	SW	Passive
9	EP(GND)	Passive

15.5.3 FM25-FRAM (FM25L16B-GTR)

Pin	Pin Name	Electrical
1	S (CS)	Passive
2	Q (SDO)	Passive
3	WP	Passive
4	VSS	Passive
5	D (SDI)	Passive
6	C (SCLK)	Passive
7	HOLD	Passive
8	VCC	Passive

15.5.4 MAX98357AETE+T (MAX98357AETE+T)

Pin	Pin Name	Electrical
1	DIN	Passive
2	GAIN_SLOT	Passive
3	GND	Power
4	SD_MODE	Passive
7	VDD	Power
8	VDD	Power
9	OUTP	Output
10	OUTN	Output
11	GND	Power
14	LRCLK	Passive
15	GND	Power
16	BCLK	Passive
17	EP	Power

15.5.5 MX25R6435FZNIL0 (MX25R6435FZNIL0)

Pin	Pin Name	Electrical
1	CS	Passive
2	SIO1/SO	Passive
3	SIO2/WP	Passive
4	GND	Passive
5	SIO0/SI	Passive
6	SCLK	Passive
7	SIO3/RESET	Passive
8	VCC	Passive
9	GND	Passive

15.5.6 PRTR5V0U2X,215 (PRTR5V0U2X,215)

Pin	Pin Name	Electrical
1	GND	Passive
2	IO1	Passive
3	IO2	Passive
4	VCC	Passive

15.5.7 SN74LV1T34DBVR (SN74LV1T34DBVR)

Pin	Pin Name	Electrical
2	A	Passive
3	GND	Passive
4	Y	Passive
5	VCC	Passive

15.5.8 TJA1021T (TJA1021T/20/CM,118)

Pin	Pin Name	Electrical
1	RXD	Passive
2	SLP_N	Passive
3	WAKE_N	Passive
4	TXD	Passive
5	GND	Passive
6	LIN	Passive
7	VBAT	Passive
8	INH	Passive

15.5.9 nRF52840-QIAA (NRF52840-QIAA-R)

Pin	Pin Name	Electrical
74	GND	Power
A8	P0.31/AIN7	Bidirectional
A10	P0.29/AIN5	Bidirectional
A12	P0.02/AIN0	Bidirectional
A14	P1.15	Bidirectional
A16	P1.13	Bidirectional
A18	DEC2	Power
A20	P1.10	Bidirectional
A22	VDD	Power
A23	XC2	Output
AA24	SWDCLK	Passive
AB2	DCCH	Power
AC5	DECUSB	Power
AC9	P0.14	Bidirectional
AC11	P0.16	Bidirectional
AC13	P0.18/RESET	Bidirectional
AC15	P0.19	Bidirectional
AC17	P0.21	Bidirectional
AC19	P0.23	Bidirectional
AC21	P0.25	Bidirectional
AC24	SWDIO	Bidirectional
AD2	VBUS	Power
AD4	D-	Bidirectional
AD6	D+	Bidirectional
AD8	P0.13	Bidirectional
AD10	P0.15	Bidirectional
AD12	P0.17	Bidirectional
AD14	VDD	Power
AD16	P0.20	Bidirectional
AD18	P0.22	Bidirectional
AD20	P0.24	Bidirectional
AD22	P1.00	Bidirectional
AD23	VDD	Power
B1	VDD	Power
B3	DCC	Output
B5	DEC4	Power
B7	VSS	Power
B9	P0.30/AIN6	Bidirectional
B11	P0.28/AIN4	Bidirectional
B13	P0.03/AIN1	Bidirectional
B15	P1.14	Bidirectional
B17	P1.12	Bidirectional
B19	P1.11	Bidirectional
B24	XC1	Passive
C1	DEC1	Power
D2	P0.00/XL1	Bidirectional
D23	DEC3	Power
E24	DEC6	Power
F2	P0.01/XL2	Bidirectional
F23	VSS_PA	Power
G1	P0.26	Bidirectional
H2	P0.27	Bidirectional
H23	ANT	Bidirectional
J1	P0.04/AIN2	Bidirectional
J24	P0.10/NFC2	Bidirectional
K2	P0.05/AIN3	Bidirectional
L1	P0.06	Bidirectional
L24	P0.09/NFC1	Bidirectional
M2	P0.07	Bidirectional
N1	P0.08	Bidirectional
N24	DEC5	Power
P2	P1.08	Bidirectional
P23	P1.07	Bidirectional
R1	P1.09	Bidirectional
R24	P1.06	Bidirectional
T2	P0.11	Bidirectional
T23	P1.05	Bidirectional
U1	P0.12	Bidirectional
U24	P1.04	Bidirectional
V23	P1.03	Bidirectional
W1	VDD	Power
W24	P1.02	Bidirectional
Y2	VDDH	Power
Y23	P1.01	Bidirectional

15.5.10 opamp-sot23-5 (TLV271CW5-7)

Pin	Pin Name	Electrical
1	OUT	Passive
2	GND	Passive
3	+	Passive
4	-	Passive
5	VCC	Passive

11-10028__cricket-node-hw__B Design Analysis

1 Design Summary

1.1 Design Overview

1.2 Processed Sheets

1.3 Variants

1.3.1 B

1.4 Footprint Compliance

2 Component Value Properties

3 Pin Connectivity Report

3.1 Unconnected Pins

3.2 Implied/Hidden Net Connections

3.3 Open-Collector Pull-up Audit

3.4 Diode Polarity / Orientation

3.5 Polarized Capacitor Orientation

3.6 Summary

4 Power Overview

4.1 Power Rail Analysis

4.2 AI-Assisted Analysis

4.2.1 Power Tree Overview

4.2.2 12 V Input Protection and Front End

4.2.3 AP64352SP-13 Buck Converter (U7) — 5 V Rail

4.2.4 5 V Output Capacitance and Loop Stability

4.2.5 nRF52840 Supply Domains and Decoupling

4.2.6 VDD Rail Programming Constraint

4.2.7 5 V Distribution, Load Switches and Amplifier

4.2.8 LIN Domain Supply and Input Monitoring

4.3 Observations

4.4 Findings

4.5 Citations

5 Connector Pinouts

5.1 J1 WIREPAD-18AWG-4X-3.5MM

5.2 J2 WIREPAD-18AWG-4X-3.5MM

5.3 J3 WIREPAD-22AWG-6X-3.5MM

5.4 J4 WIREPAD-22AWG-4X-3.5MM

5.5 J5 WIREPAD-22AWG-3X-3.5MM

5.6 J6 WIREPAD-22AWG-2X-3.5MM

5.7 J7 TAG-CONNECT-SWD (SWD)

5.8 J8 USB4145-03-0230-C

5.9 J9 20021121-00010T4LF (SWD)

6 Indicator Documentation

6.1 Indicator Assignments

6.2 Indicator Testability

7 Switch Documentation

8 Low-Speed Serial Interfaces (LSSI)

8.1 SWD

8.2 LSSI DFT Analysis

9 High-Speed Serial Interfaces (HSSI)

9.1 Differential Pairs

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Full-Speed Device Port (J8)

9.3 Findings

9.4 Citations

10 Memory Interface Analysis

10.1 U12 QSPI

10.2 AI-Assisted Analysis

10.2.1 QSPI Flash U12 (MX25R6435FZNIL0)

10.2.2 SPI FRAM U13 (FM25L16B-GTR)

10.3 Observations

10.4 Findings

10.5 Citations

11 Functional Analysis

11.1 Functional Analysis

11.1.1 LIN transceiver U2 (TJA1021T/20/CM)

11.1.2 LIN commander termination network (Q2, D2, D3)

11.1.3 Sense buffer U11 (TLV271)

11.1.4 FRAM U13 (FM25L16B-GTR)

11.1.5 Class-D amplifier U14 (MAX98357A)

11.1.6 Crystals X1 and X2

11.1.7 USB ESD protection U15 (PRTR5V0U2X)

11.1.8 Host MCU U5 (nRF52840-QIAA-R)

11.1.9 Clocks and PHY Supply Filtering

11.2 Findings

11.3 Citations

12 Designer Annotated Nets

13 EMC & ESD Protection Checks

13.1 Connector Shell Grounding

13.2 ESD/TVS Protection Audit

13.2.1 Unprotected Signal Nets

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture — Grounding, Filtering and Shielding

11-10028cricket-node-hwB Design Analysis