11-10028cricket-node-hwB Design Analysis

Job 5a57b27e

1 Design Summary

out of 100

Depth of review, as a baseline: 554 verified datasheet parameters applied and 298 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

CCA_CODENAME	cricket-node
CCA_DESCRIPTION	cricket-node
CCA_PART_NUMBER	10-10028
CCA_TITLE	cricket-node
ENGINEER	E. Hughes
PCB_CODENAME	cricket-node
PCB_DATE	2025-05-27
PCB_DESCRIPTION	cricket-node
PCB_MIXDOWN	B
PCB_PART_NUMBER	11-10028
SCH_DATE	2025-05-27
STATUS	PROTOTYPE
Active Variant	B (variant 1)
Design Type	Flat (1 sheets)
Total Components	153
Total Pins	454
Total Nets	118
Total Test Points	27
Project Variants	1
Analyzed variant	B

Improve your score:

Improve fault coverage (opens/shorts) +4
One life-cycle error +1
Add test points on indicator signals +1
Improve schematic library symbols +1
Move component values to VALUE property +1
Reconcile part numbers with the values on the schematic +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1

Points deducted for open High/Medium AI findings:

1 High, 8 Medium -6

AI findings to review:

Power findings — 6 Medium, 3 Low, 20 Review
HSSI findings — 4 Review
Memory findings — 10 Review
Functional findings — 1 High, 1 Medium, 3 Low, 15 Review
EMC/ESD findings — 1 Medium, 12 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 10 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — The cricket-node board is a single-sheet design built around a Nordic nRF52840 wireless microcontroller (U5). Around it sit external code and data storage, a digital-input class-D audio amplifier, a LIN bus transceiver, and logic-level translation. Power comes from a wide-input synchronous buck converter and two current-limited load switches. Supply, speaker and field wiring connect through solder wire pads J1 to J6. The board also has a vertical USB Type-C receptacle and a Tag-Connect SWD programming footprint. Red and green status LEDs (D15, D16) are fitted.

Processing and Wireless

U5 is an Arm Cortex-M4 with FPU running at 64 MHz. It integrates a 2.4 GHz radio for Bluetooth 5 and IEEE 802.15.4, configurable from −20 dBm to +8 dBm transmit power. Receive sensitivity is −95 dBm at 1 Mbps and −103 dBm in long-range mode. The device also has a 12-bit 200 ksps ADC and native full-speed USB (Nordic Semiconductor nRF52840 datasheet).

Two crystals clock the device. X1 is a 32 MHz, 8 pF part with ±10 ppm tolerance and ±10 ppm stability. X2 is a 32.768 kHz, 9 pF part with ±20 ppm tolerance for the low-frequency clock. Firmware loading and debug use SWD through the TC2030 Tag-Connect footprint J7.

Memory

U12 is a Macronix MX25R6435F 64 Mbit serial flash on the nRF52840's 4-bit QSPI interface. It operates from 1.65 V to 3.6 V and clocks up to 80 MHz in high-performance mode. Its rated endurance is 100,000 erase/program cycles.

U13 is a Cypress FM25L16B 16 kbit SPI F-RAM. It runs at up to 20 MHz from 2.7 V to 3.6 V, with 10^14 read/write cycles and 10-year retention at 85 °C (Cypress FM25L16B datasheet, source: Tomachie).

Audio and Analog

U14 is a MAX98357A mono class-D amplifier that accepts I²S, left-justified or TDM audio at sample rates from 8 kHz to 96 kHz. From a 2.5 V to 5.5 V supply it delivers 3.2 W into 4 Ω at 5 V and 10% THD+N, with 92% typical efficiency (Maxim MAX98357A datasheet, source: Tomachie).

U11 is a TLV271 single operational amplifier rated from 2.7 V to 16 V, with 1.9 MHz unity-gain bandwidth at 5 V.

Interfaces

U2, a TJA1021T/20 LIN transceiver, provides a vehicle-network link at up to 20 kBd. It tolerates 40 V on its battery and bus pins and is rated for ±6 kV IEC 61000-4-2 on the bus-facing pins (NXP TJA1021 datasheet, source: Tomachie).

J8 is a USB 2.0 Type-C receptacle carrying both orientation pairs. U15, a PRTR5V0U2X low-capacitance array, protects its data lines.

Four SN74LV1T34 single buffers (U3, U4, U9, U10) translate logic levels. Each operates from 1.65 V to 5.5 V and has 5 V-tolerant reduced-threshold inputs (Texas Instruments SN74LV1T34 datasheet).

Discrete small-signal switching uses 2N7002P N-channel MOSFETs (Q3, Q4, Q8 to Q10), BSS84 P-channel MOSFETs (Q1, Q2, Q7) and a BSS138K (Q5).

Power Tree

The schematic distinguishes a +VIN rail from a +VIN-PROTECT rail. A ZXMP4A16G P-channel MOSFET (Q6, −40 V, −6.4 A) is fitted as the board's power-path device.

U7 is an AP64352 synchronous buck converter accepting 3.8 V to 40 V and delivering up to 3.5 A, with a 0.8 V ±1% reference. It switches through L4 onto NetC14_1. L4 is a Sumida CDRH103RNP rated 6.8 µH, 3.60 A temperature-rise current and 3.84 A saturation current.

The rails present are:

- +VIN (raw input)
- +VIN-PROTECT (protected input)
- NetC14_1 (buck output)
- +5v0
- +VBUS (from the USB receptacle)
- VDD
- NetC10_2

U1 and U8 are AP22804A load switches rated 2.7 V to 5.5 V and 2.5 A continuous, with a 3.0 A typical current limit and reverse-voltage blocking (Diodes Incorporated AP22804 datasheet, source: Tomachie).

The nRF52840's integrated high-voltage DC/DC stage produces VDD through L1, a 10 µH multilayer inductor. Its second stage feeds NetC10_2 through L3 (10 µH) and L2 (15 nH).

Bulk storage uses Panasonic FK-series aluminium electrolytics (C7, C12 to C14). L5 and L6 are 220 Ω at 100 MHz ferrite beads rated 3 A.

Protection

Transient protection uses a PESD1IVN24 24 V-standoff TVS (D4) rated for ISO 7637-3 pulses, and five PESD5V0S1BA 5 V-standoff bidirectional TVS diodes. BZX84 zeners (D1 at 12 V; D2, D9 and D11 at 16 V) and BAS16 switching diodes complete the clamp and steering functions. These are analysed in the ESD section.

Operating Temperature

The nRF52840, both memories, the load switches, the buck converter, the audio amplifier and X2 are rated −40 °C to +85 °C. X1 is rated −30 °C to +85 °C. U11 is the TLV271CW5 C-grade part, specified 0 °C to +70 °C, which bounds the assembled board's rated ambient range at 0 °C to +70 °C. The fitted ceramics are −55 °C to +125 °C or wider.

1.2 Processed Sheets

#	Sheet Name
1	cricket-node-hw--top-level_B

1.3 Variants

#	Variant	DNP	ALT
0	Base (all components)	-	-
1	B (analyzed)	1	0

1.3.1 B

Status	RefDes	Part Type	Alt Part	Footprint
DNP	J9	CORTEX-DEBUG		FTSH-105-05-F-DV

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
3 of 33 unique footprints are IPC-7351B or IPC-7251	✓
29 SMT footprints do not follow IPC-7351B naming
1 footprints (connectors, specialty) — compliance unknown

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Ferrite beads on inductor designators (L5, L6): the Description indicates a ferrite bead, but the part uses an inductor (L) designator. Use an FB or FL designator. A ferrite value is an impedance at a frequency (e.g. 600R@100MHz), not an inductance.

No .bomdoc was supplied with this design. Highly recommended when a .bomdoc exists that it be included with the upload.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	28	C26, C27, C15, C8, C5, C14, C6, C11 (+20 more)	✓
Resistors	Values in VALUE or Resistance	38	R36, R37, R33, R9, R12, R11, R8, R10 (+30 more)	✓
Inductors	Values in VALUE or Inductance	3	L2, L1, L3	✓
Inductors	VALUE holds both the magnitude and a current rating (e.g. "6.8uH 3.84A"). Tomachie has already separated the two and uses the magnitude as the value, so the analysis and the AI read a clean value — the misinterpretation risk is low. This is a cleanliness note: move the current rating into a named Current property for downstream BOM/ICT/AOI tools and a self-describing schematic. (L4 currently has VALUE="6.8 uH 3.84A")	1	L4
Ferrite Beads	VALUE holds a part number, not an impedance. When the value is expressed as impedance@frequency (e.g. 600R@100MHz) and a separate MPN field carries the part number, the analysis is more deterministic. (L5 currently has VALUE="MPZ2012S221AT000")	2	L5, L6
Oscillators	Values in VALUE or Frequency	2	X1, X2	✓

2.1 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the MANUFACTURER part number. This check decodes the manufacturer part number and compares the two. A distributor catalogue number is a different thing and cannot be used here - an LCSC C-number or a Digi-Key -ND number identifies a stock item, it encodes no capacitance, voltage or tolerance, so there is nothing in it to check against. Where the two readings disagree both are shown and neither is assumed correct: if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose numbering scheme is not recognized are reported as not checked rather than passed.

Part Number	Decoded from Part Number	Stated on Schematic	What Differs	Count	Components	Status
CDRH103RNP-6R8NC-B Manufacturer Part Number / Sumida CDRH103RNP	6.8uH +/-30%	6.8 uH 20%: L4	Tolerance: part number +/-30%, schematic 20%	1	L4	Mismatch
ERJ-3EKF1003V Manufacturer Part Number / Panasonic ERJ-3EK	100k +/-1% 0603	100kΩ ±1%: R1, R2, R8, R14, R19, R20, R21, R23 (+5 more)	Nothing - all stated values agree	13	R1, R2, R8, R14, R19, R20, R21, R23 (+5 more)	✓ Match
ERJ-3EKF1002V Manufacturer Part Number / Panasonic ERJ-3EK	10k +/-1% 0603	10kΩ ±1%: R3, R4, R11, R18, R25, R28	Nothing - all stated values agree	6	R3, R4, R11, R18, R25, R28	✓ Match
GCM155R71H104KE02D Manufacturer Part Number / Murata	100nF 50V +/-10% 0402	0.1µF 50V ±10%: C1, C2, C3, C4, C17, C18	Nothing - all stated values agree	6	C1, C2, C3, C4, C17, C18	✓ Match
ERJ-3EKF1000V Manufacturer Part Number / Panasonic ERJ-3EK	100R +/-1% 0603	100Ω ±1%: R9, R12, R27, R30, R32	Nothing - all stated values agree	5	R9, R12, R27, R30, R32	✓ Match
ERJ-3EKF1004V Manufacturer Part Number / Panasonic ERJ-3EK	1M +/-1% 0603	1MΩ ±1%: R5, R6, R10, R29	Nothing - all stated values agree	4	R5, R6, R10, R29	✓ Match
GCJ188R91H104KA01D Manufacturer Part Number / Murata	100nF 50V +/-10% 0603	0.1µF 50V ±10%: C5, C25, C26, C28	Nothing - all stated values agree	4	C5, C25, C26, C28	✓ Match
GCM1555C1H8R0DA16D Manufacturer Part Number / Murata	8pF 50V +/-0.5pF (+/-6.25%) 0402	8pF 50V ±0.5pF: C21, C22, C23, C24	Nothing - all stated values agree	4	C21, C22, C23, C24	✓ Match
EEE-FK1A151P Manufacturer Part Number / Panasonic	150uF 10V	150µF 10V ±20%: C12, C13, C14	Nothing - all stated values agree	3	C12, C13, C14	✓ Match
ERJ-6GEY0R00V Manufacturer Part Number / Panasonic ERJ-6GEY	0R 0805	0Ω Jumper: R13, R15, R16	Nothing - all stated values agree	3	R13, R15, R16	✓ Match
ERJ-3EKF3300V Manufacturer Part Number / Panasonic ERJ-3EK	330R +/-1% 0603	330Ω ±1%: R34, R35	Nothing - all stated values agree	2	R34, R35	✓ Match
ERJ-3EKF5101V Manufacturer Part Number / Panasonic ERJ-3EK	5.1k +/-1% 0603	5.1kΩ ±1%: R36, R37	Nothing - all stated values agree	2	R36, R37	✓ Match
GCM155R71C473KA37D Manufacturer Part Number / Murata	47nF 16V +/-10% 0402	0.047µF 16V ±10%: C9, C10	Nothing - all stated values agree	2	C9, C10	✓ Match
GCM21BR71C475KA73K Manufacturer Part Number / Murata	4.7uF 16V +/-10% 0805	4.7µF 16V ±10%: C6, C20	Nothing - all stated values agree	2	C6, C20	✓ Match
MLZ1608M100WTD25 Manufacturer Part Number / TDK MLZ1608M	10uH	10uH: L1, L3	Nothing - all stated values agree	2	L1, L3	✓ Match
EEE-FK1V101P Manufacturer Part Number / Panasonic	100uF 35V	100µF 35V ±20%: C7	Nothing - all stated values agree	1	C7	✓ Match
ERJ-3EKF1001V Manufacturer Part Number / Panasonic ERJ-3EK	1k +/-1% 0603	1kΩ ±1%: R7	Nothing - all stated values agree	1	R7	✓ Match
ERJ-3EKF4992V Manufacturer Part Number / Panasonic ERJ-3EK	49.9k +/-1% 0603	49.9kΩ ±1%: R22	Nothing - all stated values agree	1	R22	✓ Match
ERJ-3EKF5233V Manufacturer Part Number / Panasonic ERJ-3EK	523k +/-1% 0603	523kΩ ±1%: R17	Nothing - all stated values agree	1	R17	✓ Match
GCJ32EC71H106KA01L Manufacturer Part Number / Murata	10uF 50V +/-10% 1210	10µF 50V ±10%: C8	Nothing - all stated values agree	1	C8	✓ Match
GCM1555C1H101FA16D Manufacturer Part Number / Murata	100pF 50V +/-1% 0402	100pF 50V ±1%: C19	Nothing - all stated values agree	1	C19	✓ Match
GCM1555C1H102FA16D Manufacturer Part Number / Murata	1nF 50V +/-1% 0402	1000pF 50V ±1%: C16	Nothing - all stated values agree	1	C16	✓ Match
GCM188R71C105KA64J Manufacturer Part Number / Murata	1uF 16V +/-10% 0603	1µF 16V ±10%: C11	Nothing - all stated values agree	1	C11	✓ Match
GCM188R72A103KA37J Manufacturer Part Number / Murata	10nF 100V +/-10% 0603	10000pF 100V ±10%: C15	Nothing - all stated values agree	1	C15	✓ Match
GCM21BR71A106KE22K Manufacturer Part Number / Murata	10uF 10V +/-10% 0805	10µF 10V ±10%: C27	Nothing - all stated values agree	1	C27	✓ Match
LQG15HS15NJ02D Manufacturer Part Number / Murata LQG15HS	15nH +/-5%	15nH: L2	Nothing - all stated values agree	1	L2	✓ Match

2.2 Capacitor Derating Check

Derating profile	industrial
Maximum ambient	not stated - temperature margins not evaluable
Checks performed	17
Over-specified	7
Excursion checks	2

A capacitor is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Every other derating check - for capacitors and for every other part class - is applied by the AI analysis within its report sections.

Derating applied: 30% (capacitor_aluminum_voltage_pct = 70), 20% (capacitor_voltage_pct = 80)

Status key: ↓ = Over-specified ✓ = Adequately rated

Derating is how much is taken off a part's catalogue rating. What remains is the most of that rating the part may be worked at - a 16 V capacitor derated 15% has a maximum permitted value of 13.6 V - and the part is correctly sized when the voltage its position applies stays within it, taken at the worst case of the rail's stated range. This judges DC working voltage only; ripple and switching transients are not included in the compared value.

An excursion is a sustained abnormal level the rail can reach outside normal operation - a charging overvoltage, a jump-start. The design must survive it but need not function at it, so each part's catalogue rating is compared against the excursion with no derating applied; a derating percentage governs normal operation only.

Review: 7 part(s) carry a voltage rating far higher than needed. A lower-cost part can be used, down to the voltage indicated.

Part Voltage Rating vs Design Voltage
RefDes	Net Name	Rated Voltage	Max Permitted	Design Voltage	% of Rating	Sufficient Rating	Status
C26	+5v0	50.00 V	40.00 V	5.00 V	10.0%	16.00 V	↓
C4	VDD	50.00 V	40.00 V	2.70 V	5.4%	16.00 V	↓
C3	VDD	50.00 V	40.00 V	2.70 V	5.4%	16.00 V	↓
C2	VDD	50.00 V	40.00 V	2.70 V	5.4%	16.00 V	↓
C1	VDD	50.00 V	40.00 V	2.70 V	5.4%	16.00 V	↓
C28	VDD	50.00 V	40.00 V	2.70 V	5.4%	16.00 V	↓
C25	VDD	50.00 V	40.00 V	2.70 V	5.4%	16.00 V	↓
C27	+5v0	10.00 V	8.00 V	5.00 V	50.0%		✓
C14	NetC14_1	10.00 V	7.00 V	5.00 V	50.0%		✓
C12	+5v0	10.00 V	7.00 V	5.00 V	50.0%		✓
C13	+5v0	10.00 V	7.00 V	5.00 V	50.0%		✓
C7	+VIN-PROTECT	35.00 V	24.50 V	16.00 V (worst case of +VIN)	45.7%		✓
C8	+VIN-PROTECT	50.00 V	40.00 V	16.00 V (worst case of +VIN)	32.0%		✓
C6	VDD	16.00 V	12.80 V	2.70 V	16.9%		✓
C11	NetC10_2	16.00 V	12.80 V	1.30 V	8.1%		✓
C10	NetC10_2	16.00 V	12.80 V	1.30 V	8.1%		✓
C9	NetC10_2	16.00 V	12.80 V	1.30 V	8.1%		✓

Excursion Withstand (absolute maximum, not derated)
RefDes	Net Name	Rated Voltage	Excursion Voltage	% of Rating	Status
C7	+VIN-PROTECT	35.00 V	18.00 V (worst case of +VIN)	51.4%	✓
C8	+VIN-PROTECT	50.00 V	18.00 V (worst case of +VIN)	36.0%	✓

Derating Settings Used in This Analysis
Parameter	Value	Source	Applied
capacitor_voltage_pct	20% (80)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Checked in the table above (13 part(s))
capacitor_aluminum_voltage_pct	30% (70)	SD-18	Checked in the table above (4 part(s))
capacitor_tantalum_mno2_voltage_pct	60% (40)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	30% (70)	ECSS	Applied by the AI analysis where the rating is in evidence
capacitor_temperature_margin_c	20 °C	ECSS, EEE-INST-002, SD-18	Not evaluable - no maximum ambient is stated
capacitor_aluminum_temperature_margin_c	25 °C	SD-18	Not evaluable - no maximum ambient is stated
resistor_power_pct	45% (55)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	25% (75)	ECSS, EEE-INST-002	Applied by the AI analysis where the rating is in evidence
resistor_temperature_margin_c	25 °C	ECSS, EEE-INST-002, SD-18	Not evaluable - no maximum ambient is stated
inductor_temperature_margin_c	25 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
diode_reverse_voltage_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_average_forward_current_pct	35% (65)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_power_dissipation_pct	50% (50)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
zener_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18	Applied by the AI analysis where the rating is in evidence
zener_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
mosfet_vds_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_vgs_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_continuous_current_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
mosfet_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
bjt_vce_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_continuous_current_pct	40% (60)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_power_dissipation_pct	55% (45)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
bjt_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
regulator_input_voltage_pct	25% (75)	ECSS, EEE-INST-002	Applied by the AI analysis where the rating is in evidence
regulator_output_current_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_power_dissipation_pct	50% (50)	EEE-INST-002, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
ic_output_current_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_power_dissipation_pct	50% (50)	EEE-INST-002, MIL-STD-1547B, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated
connector_current_per_contact_pct	40% (60)	ECSS, EEE-INST-002, MIL-STD-1547B	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	30% (70)	ECSS, EEE-INST-002, SD-18, MIL-STD-975M	Applied by the AI analysis where the rating is in evidence
connector_temperature_margin_c	20 °C	ECSS, EEE-INST-002, MIL-STD-1547B	Not evaluable - no maximum ambient is stated
tvs_junction_temperature_margin_c	30 °C	ECSS, EEE-INST-002, SD-18, MIL-STD-1547B, MIL-STD-975M	Not evaluable - no maximum ambient is stated

2.3 Part Lifecycle and Silicon Errata

Status as found on the manufacturer's website by the AI enrichment run, on the date shown; the page read is linked. Silicon errata: whether the manufacturer publishes an errata sheet for the part - its presence only. No errata document is read or analysed, and no action is implied by its existence.

Item	Lifecycle	Silicon errata	Status
U5 (NRF52840-QIAA-R)	Not recommended for new designs, as of 2026-09-28 No replacement named; the manufacturer's current ordering codes in the same package (QI aQFN™ 7 x 7 73 0.5): nRF52840-QIAA-F-R, nRF52840-QIAA-F-T, nRF52840-QIAA-F-R7. Confirm any silicon or build differences before switching.	Not determined	High
C1, C2, C3, C4, C17, C18 (GCM155R71H104KE02D), C6, C20 (GCM21BR71C475KA73K), C8 (GCJ32EC71H106KA01L), C9, C10 (GCM155R71C473KA37D), C11 (GCM188R71C105KA64J), D3, D6, D7 (BAS16-7-F), D5, D8, D12, D13, D14 (PESD5V0S1BA-115), J8 (USB4145-03-0230-C), L1, L3 (MLZ1608M100WTD25), L2 (LQG15HS15NJ02D), L5, L6 (MPZ2012S221AT000), Q1, Q2, Q7 (BSS84-7-F), ...	The life-cycle status for this part is indeterminate from the datasheet - please review	Not determined	Review
D1 (BZX84C12-7-F), D2, D9, D11 (BZX84B16-7-F)	Life-cycle status could not be determined	—	Review
C5, C25, C26, C28 (GCJ188R91H104KA01D)	There is a In Production marking on the datasheet obtained 2026-10-12	—
C7 (EEE-FK1V101P)	Active, as of 2026-10-12	—
C12, C13, C14 (EEE-FK1A151P)	There isn't a life-cycle marking on the datasheet obtained 2026-10-12	—
C27 (GCM21BR71A106KE22K)	There isn't a life-cycle marking on the datasheet obtained 2026-10-12	—
D4 (PESD1IVN24-AX)	Active, as of 2026-10-12	—
D15 (APT2012SURCK)	There isn't a life-cycle marking on the datasheet obtained 2026-10-12	—
D16 (APT2012CGCK)	There isn't a life-cycle marking on the datasheet obtained 2026-10-12	—
L4 (CDRH103RNP-6R8NC-B)	There isn't a life-cycle marking on the datasheet obtained 2026-10-12	—
Q5 (BSS138K)	Active, as of 2026-10-12	—
U7 (AP64352SP-13)	Active, as of 2026-09-25	None found on the manufacturer's website, as of 2026-09-25
U12 (MX25R6435FZNIL0)	There isn't a life-cycle marking on the datasheet obtained 2026-10-12	Not determined

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

11 unconnected pin(s) found:

11 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
J1_2	2	Passive	CON-1-4	UNC_J1_2_2
J2_2	2	Passive	CON-1-4	UNC_J2_2_2
J7_6	SWO	Passive	TAG-CONNECT-SWD	-	No net
U5_A20	P1.10	Bidirectional	nRF52840-QIAA	P1.10
U5_AC11	P0.16	Bidirectional	nRF52840-QIAA	P0.16
U5_AC15	P0.19	Bidirectional	nRF52840-QIAA	P0.19
U5_AD12	P0.17	Bidirectional	nRF52840-QIAA	P0.17
U5_B15	P1.14	Bidirectional	nRF52840-QIAA	P1.14
U5_B17	P1.12	Bidirectional	nRF52840-QIAA	P1.12
U5_G1	P0.26	Bidirectional	nRF52840-QIAA	P0.26
U5_P2	P1.08	Bidirectional	nRF52840-QIAA	P1.08

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden pins of any electrical type stacked behind visible pins in the symbol.

Implied Net Connections
Component	Type	Pin	Net
U12	MX25R6435FZNIL0	9	GND

3.3 Open-Collector Pull-up Audit

Examined 0 candidate pin(s) on 0 net(s).

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation	Severity
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires pin 1, the cathode, on the left with the footprint at zero rotation. Tomachie calls out symbols that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, initial ATE test generation from a netlist of only pins 1 and 2 will fail, or a novice may wrongly indict a correct part — consistency is the least-expensive path for everyone who handles the PCB.
D1 BZX84C12-7-F unidirectional · pin_names	Pin 1 (A): NetD1_1 Pin 3 (K): +VIN-PROTECT	Consistent
D2 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NetD2_1 Pin 3 (K): NetD2_3	Consistent
D3 BAS16-7-F unidirectional · pin_names	Pin 1 (A): NetD3_1 Pin 3 (K): NetD3_3	Consistent
D11 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NetD11_1 Pin 3 (K): +VIN-PROTECT	Consistent
D9 BZX84B16-7-F unidirectional · pin_names	Pin 1 (A): NetD9_1 Pin 3 (K): +VIN-PROTECT	Consistent
D7 BAS16-7-F unidirectional · pin_names	Pin 1 (A): +VBUS Pin 3 (K): NetD6_3	Consistent
D6 BAS16-7-F unidirectional · pin_names	Pin 1 (A): +5v0 Pin 3 (K): NetD6_3	Consistent
D8 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): BTN0-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D5 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): NP0-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D4 PESD1IVN24-AX bidirectional · symbol_graphic	Pin 2 (C): LIN-IO Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D13 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): AUX1-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D12 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): NP1-EXT Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information
D14 PESD5V0S1BA-115 bidirectional · symbol_graphic	Pin 2 (C): CHG-LOOP Pin 1 (C): GND	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information

3.5 Polarized Capacitor Orientation

Capacitor	Connections	Polarity	Severity
Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
C14 EEE-FK1A151P	Pin 1 (+): NetC14_1 Pin 2: GND
C12 EEE-FK1A151P	Pin 1 (+): +5v0 Pin 2: GND
C13 EEE-FK1A151P	Pin 1 (+): +5v0 Pin 2: GND
C7 EEE-FK1V101P	Pin 1 (+): +VIN-PROTECT Pin 2: GND

3.6 Checks Not Performed

Items this report did not check, with the reason. None of these is a finding against the design - an item that was not checked says nothing about it either way.

Note 3: The figure these checks need was not taken from the part's datasheet, so they were not performed. This is a limitation of the analysis, not a finding on the design.

Checks the AI review could not perform are listed at Review severity in each AI section's Findings table, each naming the input that was missing.

Item	Not checked	Notes
Capacitors and resistors (datasheets and parameter curves)	Datasheets for capacitors and resistors, and the parameter curves they carry (ripple current, derating against temperature, DC bias, a jumper's temperature rise), are obtained on the premium tier only. This standard-tier run reads a datasheet already on file and otherwise states no rating for these parts. The exception is a capacitor on a regulator's input or output rail: this tier obtains its datasheet and curves as well.
C12, C13, C14 (EEE-FK1A151P)	Output capacitor ESR at the 2 MHz switching frequency and load-life endurance (impedance at 100 kHz and endurance hours at 105 °C)	See note 3
C8 (GCJ32EC71H106KA01L)	Effective input capacitance at 12-16 V (capacitance change versus DC bias)	See note 3
C6 (GCM21BR71C475KA73K)	Effective VDD bulk capacitance at 2.7 V (capacitance change versus DC bias)	See note 3
U7 (AP64352SP-13)	Efficiency and package dissipation at the operating point (efficiency versus load at 12 V input and 5 V output)	See note 3
J1, J2, J5 (WIREPAD-18AWG-4X-3.5MM, WIREPAD-22AWG-3X-3.5MM)	Current rating of the +VIN and GND wire pads (rated current per pad)	See note 3
U5 (NRF52840-QIAA-R)	On-die USB D+/D- termination and pull-up, and whether external series resistors are needed on USB-DEVICE-D_P and USB-DEVICE-D_N (USB transceiver termination and series resistance requirement)	See note 3
U5 (NRF52840-QIAA-R)	USB speed class implemented by the U5 USB device controller, which governs edge rates and the routing constraints on the pair (USB data rate (full speed or high speed))	See note 3
U5 (NRF52840-QIAA-R)	Required 32 MHz HFXO frequency tolerance for USB operation, compared with X1 (HFXO frequency tolerance required for USB)	See note 3
U5, X1 (NRF52840-QIAA-R)	Compatibility of X1's ESR (50 Ω max) and drive level (100 µW max) with the 32 MHz oscillator (HFXO maximum crystal ESR and drive level)	See note 3
U5, L3 (NRF52840-QIAA-R)	REG1 DC/DC inductor current against the L3 saturation current (REG1 (DCC) output load current)	See note 3
U2 (TJA1021T/20/CM,118)	Ambient operating range against the design (operating ambient temperature range)	See note 3
U14 (MAX98357AETE+T)	ESD withstand of the OUTP and OUTN speaker outputs on J6 with no external clamp (Component-level ESD rating (HBM) of OUTP/OUTN)	See note 3
U5 (NRF52840-QIAA-R)	Pulse current into the P1.13 internal clamp diodes through R32 (100Ω) behind D14 (Maximum I/O injection or clamp current)	See note 3
Part life-cycle	The life-cycle status for this part is indeterminate from the datasheet - please review

3.7 Summary

Total NO_ERC markers in design	24
Pins needing attention (warnings)	11
Pins for information only	0

4 Power Overview

Power rails	8
Power management sources identified	3

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Values Entered for This Analysis

These values were entered by the designer for this analysis; they are not read from the schematic. Every check in this report that needs one of them uses the figure shown here.

Kind	Entered for	Value entered
Power input	+VIN	12 V nominal, 9-16 V operating, 18 V survivable excursion
Power input	VDD	2.7 V nominal

4.2 Power Rail Analysis

+VBUS: 5 V assumed by USB convention, because a USB connector power pin is on this net. A design that negotiates a higher USB Power Delivery voltage must state the rail's actual nominal, minimum and maximum voltage — preferably recorded in the design itself, otherwise entered when prompted before the AI review starts. Until it is stated, the assumed 5 V is taken as the intended level.

Power Rails
Rail	Voltage	Source	Consumers
+VIN	12.00V	J5 External	Q6 (ZXMP4A16GTA)
+VIN-PROTECT	12.00V	Q6 ZXMP4A16GTA	U7 (AP64352SP-13)
+5v0	5.00V	U7 AP64352SP-13	U14 (MAX98357AETE+T), U3 (SN74LV1T34DBVR), U8 (AP22804AW5-7), U9 (SN74LV1T34DBVR), U1 (AP22804AW5-7)
+VBUS	5.00V	J8 External	U5 (NRF52840-QIAA-R), U15 (PRTR5V0U2X,215)
NetC14_1	5.00V	U7 AP64352SP-13	-
VDD	2.70V	U5 NRF52840-QIAA-R	U12 (MX25R6435FZNIL0), U13 (FM25L16B-GTR), U10 (SN74LV1T34DBVR), U4 (SN74LV1T34DBVR)
GND	-	J8 External	-
NetC10_2	1.3V	U5 NRF52840-QIAA-R	-

4.2.1 Rail Voltage Annotation

1 power input(s) into this board were identified - the supplies it takes in at a connector, a terminal or a module socket. Every part on and downstream of each one is judged against what it carries, so the analysis needs its full characterization: whether it is AC or DC, its nominal voltage, the band it operates over, and any level outside normal operation the design must survive.

The preferred way to state a rail's voltage is to record it in the design itself, where it travels with the schematic, survives every re-run, and can be read by anyone who opens the design: attach a Parameter Set directive to the rail carrying VOLTAGE_NOM, VOLTAGE_MIN and VOLTAGE_MAX properties, and VOLTAGE_EXCURSION_MAX for a survivable level outside normal operation.

You will be prompted to enter each input's nominal, minimum and maximum operating voltage - and, where one exists, the survivable excursion level - before the AI review starts.

2 power input(s) into this board were identified and characterized as follows. These are the levels the analysis uses.

Rail	Required information
+VBUS	USB-C default values will be 5.00 V nominal, 4.75 V minimum, 5.50 V maximum.

Rail	Voltage supplied
+VIN	12.00 V nominal, 9.00-16.00 V operating, 18.00 V survivable excursion
VDD	2.70 V nominal

4.3 Regulator Enable Pull Resistors

3 regulator enable pin(s) examined for what drives them and which way they are pulled. 0 pulled toward the enabling level while a power output drives the net.

	Finding	Severity
RegulatorU1 [AP22804AW5-7] Enable pinU1_4 (EN) (enabled high) NetNP0-EN Driven byU5_B19 (P1.11) Pull-up- Pull-down-	Driven by the pins listed; no pull resistor is fitted.	Information
RegulatorU8 [AP22804AW5-7] Enable pinU8_4 (EN) (enabled high) NetNP1-EN Driven byU5_J1 (P0.04/AIN2) Pull-up- Pull-down-	Driven by the pins listed; no pull resistor is fitted.	Information
RegulatorU7 [AP64352SP-13] Enable pinU7_3 (EN) (enabled high) Net+VIN-PROTECT Driven by- Pull-up- Pull-down-	The enable is wired to +VIN-PROTECT; the regulator is always enabled.	Information

4.4 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.4.1 Power Tree Overview

AI-Assisted — Power enters on the +VIN wire pads J1_1, J2_1 and J5_1. The schematic states +VIN at 12.00V, with a normal band of 9.00-16.00V and an 18.00V excursion.

Q6 (ZXMP4A16GTA, P-channel) is a reverse-polarity pass FET. Its drain is on +VIN and its source forms +VIN-PROTECT. R18 (10kΩ) pulls the gate to GND, and D9 (BZX84B16) clamps gate to source.

+VIN-PROTECT feeds two loads:
- U7 (AP64352SP-13), whose EN is tied directly to its VIN.
- The LIN supply switch Q1.

U7 produces NetC14_1 at 4.984 V. This follows from its 0.8 V reference and the R17 523kΩ / R23 100kΩ divider: 0.8 V × (1 + 523/100). The parallel 0Ω links R15 and R16 make NetC14_1 and +5v0 one conductor.

+5v0 supplies U14, U3, U9, the LEDs D15 and D16, and the unswitched off-board pad J3_6. It also feeds the load switches U1 and U8, which drive J3_1 and J4_1. Through D6, +5v0 reaches the VDDH pin of U5 (nRF52840).

USB +VBUS from J8 reaches U5 VBUS directly and VDDH through D7, so U5 runs from either source. U5 generates two internal rails:
- VDD at 2.70V, from its DCCH stage through L1. VDD supplies U12, U13, U4, U10 and U5 itself.
- The 1.3 V DEC4/DEC6 node NetC10_2, from its DCC stage through L3 and L2.

The GPIO net P0.03 doubles as the supply of U11 and the enable of the input-sense switch Q7. No power-good output is used: U1_3 and U8_3 FLAG are left unconnected by design.

Power-up order with +VIN applied:
+VIN rises; Q6 conducts through its body diode, then through its channel once VGS exceeds its threshold.
U7 starts above its 3.5 V typical (3.7 V maximum) rising UVLO and ramps +5v0 over the 2 ms soft-start set by C15.
+5v0 reaches U5 VDDH through D6; U5 brings up VDD and the DEC rails.
Firmware drives six control nets: NP0-EN and NP1-EN (U1, U8), LIN-PWR (LIN supply), LIN-CMDR (commander pull-up), V-C--ENABLE (input sense) and SP-SD (U14).

On USB power alone, VBUS powers U5 through D7. +5v0 and its loads stay unpowered, because D6 blocks reverse flow.

4.4.2 Input Protection and High-Side Switch Gate Networks

AI-Assisted — Q6 is the only element between the +VIN pads and U7.

Its gate network has no gate-source resistor. R18 returns the gate to GND, so VGS equals the source voltage until D9 conducts:
- At 9 V input, VGS is 9 V. This falls between the -4.5 V and -10 V RDS(on) rows (100 mΩ and 60 mΩ maximum; Diodes Incorporated ZXMP4A16G datasheet p.2, source: Tomachie).
- At the 16 V band top, VGS is about 16 V, held at or below D9's 16.32 V maximum.

On a reverse connection the body diode blocks, and the channel stays off because the gate cannot fall below the source. The resulting 16-18 V drain-source is a fault, judged against the 40 V absolute maximum. D9 conducts only near the band top. Its dissipation cannot exceed the ceiling of 16 V × 1.6 mA = 26 mW set by R18.

Q1, Q2 and Q7 are BSS84 high-side switches built the same way. Each has:
- a 100kΩ gate-source resistor (R1, R2, R24);
- a 10kΩ resistor (R4, R3, R25) to a 2N7002P sink (Q4, Q3, Q8);
- a sink gate that carries a 1MΩ pull-down (R6, R5, R29) and a U5 GPIO.

The divider places 0.909 × the source voltage across gate-source. That is 14.57 V at 16 V with worst-case 1% tolerances. The clamps behave differently:
- On Q1, the 12 V clamp D1 conducts and holds VGS at 11.4-12.7 V, drawing about 0.28 mA.
- On Q2 and Q7, the 16 V clamps D2 and D11 never conduct in the normal band, so the full divider voltage reaches the gate.

The three switches serve different functions:
- Q1 switches U2 VBAT.
- Q2 switches the LIN commander pull-up from U2 INH.
- Q7 switches the R26/R28 input-sense divider. This divider presents +VIN-PROTECT × 10/110 (1.45 V at 16 V) to U11, which buffers it to U5 P0.02/AIN0.

There is no fuse on the +VIN pads. A series fuse belongs in the harness or upstream supply, and it has to exist there. There is also no transient suppressor on +VIN or +VIN-PROTECT. On that node the lowest withstand ratings are C7 at 35 V, Q6 at 40 V, and U7 at 42 V DC (45 V for 400 ms).

4.4.3 AP64352 Synchronous Buck (U7)

AI-Assisted — U7 runs from +VIN-PROTECT. Its input capacitors are C7 (100µF, 35 V aluminium) and C8 (10µF, 50 V X7S, 1210). EN is tied to VIN, so the converter runs whenever VIN exceeds the 3.5 V typical rising UVLO and drops out at 3.1 V.

Switching frequency: R22 (49.9kΩ) sets fsw = 100000/49.9 = 2004 kHz by the datasheet's RT formula. This is inside the 100-2200 kHz range. On-time is 155 ns at 16 V and 138 ns at the 18 V excursion, both above the 100 ns maximum minimum on-time.

Soft-start: C15 (10000pF) sets it. The datasheet table gives 2 ms for 10 nF, while the formula Css = 3.7 × tss gives 2.7 ms; the table value is used. Charging roughly 455 µF of effective output capacitance in 2 ms draws about 1.1 A. That is well inside the 4.25 A minimum peak current limit.

Bootstrap: C5 (0.1µF) is the bootstrap capacitor.

Output capacitance: C14 (150µF aluminium) sits directly on the output node. Through R15/R16 the output also carries:
- C12 and C13 (150µF each);
- C27 (10µF X7R), about 5.4 µF at 5 V on its DC-bias curve;
- C26 (0.1µF).

That is far more capacitance, and far higher ESR, than the 22-68 µF low-ESR ceramic the datasheet recommends. The recommendation is not a minimum, but the data does not characterise loop behaviour with this mix.

Inductor: L4 (CDRH103RNP-6R8NC-B, 6.8 µH) is inside the 2.2-10 µH range. Ripple is 0.25 A peak-to-peak at 16 V, or 0.38 A with the -30% inductance tolerance. Its 3.84 A saturation current lies below the high-side current-limit band of 4.25-5.75 A. An overload therefore drives L4 into saturation before U7 limits. On the manufacturer's curve, inductance falls to:
- 4.18 µH at 4.79 A at 20 °C;
- 1.59 µH at 4.79 A at 105 °C.

The data does not cover efficiency or package dissipation. Both also need the +5v0 load beyond the known 21 mA (Diodes Incorporated AP64352 datasheet pp.1-5, source: Tomachie; Sumida CDRH103R datasheet pp.2-3, source: Tomachie).

4.4.4 5 V Distribution, Load Switches and Audio Amplifier

AI-Assisted — The known +5v0 load is about 21 mA:
- U14 idles at up to 3.35 mA (Maxim MAX98357A datasheet p.4, source: Tomachie).
- D15 draws (4.98 V - 1.95 V)/330Ω = 9.2 mA.
- D16 draws (4.98 V - 2.1 V)/330Ω = 8.7 mA.
- U3 and U9 draw 10 µA each.
- U1 and U8 draw 80 µA quiescent each.

That figure excludes four loads:
- U14's speaker drive.
- The switched outputs of U1 and U8. Each is rated to 2.5 A, with a current limit of 2.7-3.3 A (Diodes Incorporated AP22804 datasheet pp.3-4, source: Tomachie).
- The direct pad J3_6.
- U5's VDDH draw through D6.

Together the two switches permit 5 A, more than U7's 3.5 A rating. U7's own current limit is therefore the only protection against a combined overload on J3 and J4. J3_6 bypasses the switches entirely.

U1 and U8 have four connection points:
- EN is driven straight from U5 GPIOs, with no pull resistor.
- FLAG is unused.
- Neither output has a capacitor.
- Both inputs share the rail ceramics C27 (10µF) and C26 (0.1µF).

Those two ceramics match the 10 µF and 0.1 µF that U14's datasheet calls for at its VDD pins, so they belong to U14. U3 and U9 likewise have no 0.1 µF of their own.

U14's speaker outputs pass through L5 and L6 (MPZ2012S221A, 3 A rated to 85 °C), which covers U14's 1.6 A continuous output limit.

LED path dissipation is about 18 mW per LED and 28 mW per series resistor (R34, R35). The LED derating curve falls to the 9 mA operating current at about 77 °C ambient. The design states no maximum ambient.

4.4.5 nRF52840 Supplies (U5)

AI-Assisted — U5 takes VBUS directly on AD2. It takes VDDH on Y2 through R13 (0Ω) from the D6/D7 OR-ing node.

BAS16 forward drop is 0.715 V at 1 mA and 0.855 V at 10 mA (Nexperia BAS16 datasheet). From +5v0, VDDH therefore sits at about 4.1-4.3 V; from a 5.5 V VBUS it stays below 4.8 V. Both are inside the 2.5-5.5 V VDDH range. VBUS stays inside its 4.35-5.5 V range at the Type-C maximum (nRF52840 datasheet p.410, Datasheet).

Neither +VBUS nor the VDDH node carries a capacitor. Bulk behind D6 cannot bypass VDDH.

VDD (2.70V) is generated on DCCH through L1 (10uH, 90 mA saturation, 1.05 Ω DCR). The known VDD load besides U5 is about 13 mA:
- U12: up to 10 mA while programming.
- U13: up to 3 mA at 20 MHz.
- U4 and U10: 10 µA each.
- R11: 0.27 mA with LIN-RX-OUT low.

VDD carries C6 (4.7µF) and six 0.1 µF capacitors (C1-C4, C25, C28). These are shared by U5's five VDD pins, U12, U13, U4 and U10. Nordic's reference adds 1.0 µF and a 100 nF at each VDD pin.

VDD at 2.7 V is within these supply ranges:
- U5: 1.7-3.6 V.
- U12: 1.65-3.6 V.
- The buffers: 1.6-5.5 V.

It is exactly at U13's 2.7 V minimum.

The core stage DCC feeds the tied DEC4/DEC6 node through L3 and L2. That node carries C11 (1µF), plus C9 and C10 (0.047µF). DEC1, DEC2, DEC3, DEC5 and DECUSB each have their own capacitor to GND (C17, C18, C19, C16 and C20 respectively). P0.03 is used as the supply of U11 and as the enable of the Q8/Q7 sense switch.

4.4.6 LIN Transceiver Supply

AI-Assisted — U2 VBAT is NetQ1_3. Q1 switches it from +VIN-PROTECT under LIN-PWR (P0.27).

When LIN-CMDR (P1.06) turns on Q2, U2's INH output feeds the commander pull-up, D3 and R7 (1kΩ), onto LIN-IO. This is the arrangement the TJA1021 datasheet prescribes for a commander: 1 kΩ in series with a diode from INH or VBAT (p.16, source: Tomachie). NetQ1_3 carries no capacitor.

The branch draws two currents:
- Up to 4 mA for U2 in Normal mode with the bus dominant (p.11).
- The R7 current, (16 V - 0.7 V)/1 kΩ = 15.3 mA while LIN-IO is held low.

Q1, Q2 and D3 carry this with wide margin:
- Q1 and Q2 are rated 130 mA continuous, or 78 mA under the industrial derating.
- D3 is rated 215 mA, or 140 mA under the industrial derating.
- INH's 50 mA output limit is not approached.

R7 is the part the arithmetic reaches. It is an 0603, 1/10 W resistor dissipating 0.234 W while the bus is held low at 16 V. It also exceeds its derated limit in normal dominant traffic at the top of the band.

Q5 (BSS138K) pulls WAKE_N low for a local wake; R8 otherwise holds WAKE_N at VBAT. Q5's 50 V rating covers the 16-18 V it blocks. D4 (PESD1IVN24, 24 V standoff) clamps LIN-IO at the J1/J2 pads.

4.5 Observations

AI-Assisted — The highest-impact items are these:
- No bypass capacitor on U5's VBUS and VDDH pins.
- No bypass capacitor on the U1 and U8 outputs.
- L4's saturation current sits below U7's current-limit band, while J3_6 places +5v0 on an unswitched off-board pad.
- R7 dissipates more than its rating while the LIN bus is held low.
- The 16 V gate clamp leaves Q6, the main power-path FET, above its derated VGS limit.

The gate clamps are inconsistent across identical stages. The same 100kΩ/10kΩ drive network is clamped at 12 V on Q1 and at 16 V on Q2 and Q7. Q6's 16 V clamp is the only VGS limit on the input path. A 12 V clamp, as fitted for D1, brings every gate inside the derated 14 V. The cost is a standing current of a fraction of a milliampere at the 16 V band top, and essentially none at 12 V.

Most load-dependent checks stop at the same missing design facts:
- The currents drawn from J3_1, J4_1 and J3_6.
- The speaker impedance at U14.
- The maximum ambient temperature.

With those stated as free text on the schematic page (for example, +5v0 load current : <value>), the following checks can be closed:
- U7 output current and dissipation.
- U7 input ripple.
- Q6 drain current.
- L4 temperature rise.
- LED and aluminium-capacitor temperature derating.

On VDD at 2.70V, U13 sits exactly at its 2.7 V minimum. U11 is supplied from a GPIO that cannot exceed that level. Neither has any margin.

Several 0.1 µF bypass capacitors are 50 V parts on 2.7 V and 5 V rails. This is benign margin; a 16 V part would serve.

C7's 2000 h endurance at 105 °C needs a stated ambient before its service life on this always-on input can be judged.

4.6 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.6.1	D9 (BZX84B16-7-F), gate clamp of Q6	+VIN-PROTECT	Q6 has no gate-source resistor. R18 (10kΩ) returns its gate to GND, so VGS equals the source voltage until D9 conducts. At the 16 V top of the +VIN band, Q6 sees about 16 V gate-source, held at or below D9's 16.32 V maximum (15.68-16.32 V at 5 mA). Q6 meets its ±20 V VGS rating. The industrial derating selected for this schematic analysis takes 30% off that rating (mosfet_vgs_pct = 70), permitting 14 V, so under that derating Q6 is carried over its limit. D9 sets the applied VGS: the clamp is set too high for the transistor it protects. Remedy: a 12 V clamp, as already fitted for Q1 (D1, BZX84C12, 11.4-12.7 V). It holds VGS below 14 V and conducts about 0.4 mA through R18 at 16 V and about 60 µA at 12 V. Sources: Diodes Incorporated ZXMP4A16G datasheet p.2 (source: Tomachie); Vishay BZX84B16 datasheet p.3 (source: Tomachie).	Medium
4.6.2	L4 (CDRH103RNP-6R8NC-B)	NetC5_1 to NetC14_1	L4's saturation current is 3.84 A (inductance at 65% of nominal). U7's high-side peak current limit is 4.25-5.75 A, compared at its 5.75 A worst end. An overload, such as a short on the unswitched pad J3_6, therefore drives L4 beyond saturation before U7 limits. On the Saturation Current and Temperature Rise graph (p.3), inductance at 4.79 A is 4.18 µH at 20 °C and 1.59 µH at 105 °C. Remedy: a 2.2-10 µH inductor whose saturation current exceeds 5.75 A. This needs a larger body than CDRH103R offers at 6.8 µH, so the footprint must be decided before layout begins. Sources: Diodes Incorporated AP64352 datasheet p.5 (source: Tomachie); Sumida CDRH103R datasheet pp.2-3 (source: Tomachie).	Medium
4.6.3	U1, U8 (AP22804AW5-7)	+5v0-CH0, +5v0-CH1	The output nets carry only a wire pad and a test point: J3_1 with TP8, and J4_1 with TP12. There is no capacitor. The datasheet makes a 0.1 µF ceramic from OUT to GND, close to the IC, mandatory (pin table p.2), and states the output must be bypassed to improve short-circuit transient immunity (p.13). Remedy: a 0.1 µF X7R 16 V capacitor on each output. Where J3/J4 are hot-plugged, add the 100 µF low-ESR electrolytic or 10 µF MLCC the datasheet gives for hot-plug outputs. Source: Diodes Incorporated AP22804 datasheet pp.2, 13 (source: Tomachie).	Medium
4.6.4	U5 (NRF52840-QIAA-R)	+VBUS	+VBUS carries no capacitor. Its members are J8 A4/A9/B4/B9, U5_AD2, U15_4, D7 and TP1. The nRF52840 datasheet states that the input and output of the USB regulator need to be decoupled for stability (page 87). Its reference circuitry places 4.7 µF on VBUS. Remedy: a 4.7 µF X7R 16 V ceramic from +VBUS to GND at U5_AD2. Source: nRF52840 datasheet.	Medium
4.6.5	U5 (NRF52840-QIAA-R) VDDH	NetR13_1, NetD6_3	U5_Y2 VDDH has no capacitor. Its node holds only R13 and the cathodes of D6 and D7. Those diodes supply the pin but cannot bypass it, and the +5v0 bulk behind D6 is not local to the pin. VDDH feeds the DCCH switching stage that generates VDD. Nordic's reference circuitry places 4.7 µF on VDDH. Remedy: a 4.7 µF X7R 16 V ceramic from NetR13_1 to GND at U5_Y2. Source: nRF52840 datasheet.	Medium
4.6.6	R7 (ERJ-3EKF1001V, 1kΩ 0603)	NetD3_3 to LIN-IO	R7 is the LIN commander pull-up, fed from U2 INH through Q2 and D3. It is rated 0.1 W. While LIN-IO is held low, whether by a bus short to ground or a stuck node, R7 dissipates: - (16 V - 0.7 V)² / 1 kΩ = 0.234 W at the band top. - 0.128 W at 12 V. Both exceed its 0.1 W rating. In normal traffic, with the bus dominant at 1.4 V for half the time, R7 averages about 0.097 W at 16 V. That meets its rating but not the industrial derating selected for this schematic analysis (resistor_power_pct = 55, permitting 55 mW). Remedy: a 1kΩ resistor rated at least 0.5 W (0.234 W / 0.55 = 0.43 W). That needs a larger body than 0603, so the footprint must be decided before layout begins. Source: NXP TJA1021 datasheet pp.13, 16 (source: Tomachie).	Medium
4.6.7	Q2, Q7 (BSS84-7-F)	NetD2_3 (U2 INH), +VIN-PROTECT	Each gate is set by a 100kΩ gate-source resistor (R2, R24) and a 10kΩ pull-down (R3, R25) switched by Q3 or Q8. VGS = 16 V × 101 kΩ / (101 kΩ + 9.9 kΩ) = 14.57 V at the band top, with the 1% resistors at their worst corners. D2 and D11 (15.68-16.32 V) do not conduct at 14.57 V, so the drive network alone sets VGS. The part meets its ±20 V rating. Derated 30% (mosfet_vgs_pct = 70) it permits 14 V, so under that derating it is 4.1% over. The identical Q1 stage uses a 12 V clamp (D1) that holds VGS at 12.7 V maximum. Fitting the same BZX84C12 for D2 and D11 brings Q2 and Q7 inside 14 V. Source: Diodes Incorporated BSS84 datasheet p.2 (source: Tomachie).	Low
4.6.8	U7, C15 (10000pF, ±10%)	NetC15_2	The datasheet asks for Css of at least 10 nF. C15 meets this nominally, but at its -10% tolerance corner it is 9 nF. Soft-start is 2 ms from the datasheet table at 10 nF. The formula Css = 3.7 × tss gives 2.7 ms; the two conflict and the table value is used. A 15000pF capacitor keeps the worst case above 10 nF and lengthens soft-start to about 3 ms. Source: Diodes Incorporated AP64352 datasheet p.5 (source: Tomachie).	Low
4.6.9	U1, U8 (AP22804AW5-7)	+5v0	The datasheet needs a 1 µF X7R or X5R ceramic from IN to GND, close to each device (p.13). The only ceramics on +5v0 are C27 and C26, which are U14's bypass. Remedy: a 1 µF X7R 16 V capacitor at each IN pin. Source: Diodes Incorporated AP22804 datasheet pp.2, 13 (source: Tomachie).	Low
4.6.10	Q6 (ZXMP4A16GTA)	+VIN-PROTECT	Q6 is rated -4.6 A continuous at 25 °C on 25 mm × 25 mm copper. Derated 40% (mosfet_id_pct = 60) it permits 2.76 A. The known +VIN-PROTECT load is: - U7's input current for the known 21 mA on +5v0. - About 19 mA on the LIN branch (U2 up to 4 mA, R7 up to 15.3 mA). That figure does not include the J3/J4 loads, U14's speaker drive or U5. Check that the total stays below 2.76 A. Source: Diodes Incorporated ZXMP4A16G datasheet p.2 (source: Tomachie).	Review
4.6.11	Input transient suppression	+VIN, +VIN-PROTECT	No transient suppressor is fitted on +VIN or +VIN-PROTECT. On that node the lowest withstand ratings are: - C7: 35 V. - Q6: VDS 40 V. - U7: VIN 42 V DC, 45 V for 400 ms. If the input can see load dump or a comparable surge, add a TVS at the point of entry, downstream of the input's series fuse. Its maximum clamping level must sit below 35 V at the expected surge current. Sources: Diodes Incorporated AP64352 datasheet p.4 (source: Tomachie); Panasonic EEE-FK datasheet.	Review
4.6.12	U7 output capacitance	NetC14_1, +5v0	U7's own output capacitance is: - C14 (150µF aluminium) directly on the output. - Through R15/R16: C12 and C13 (150µF aluminium), C27 (10µF X7R, about 5.4 µF at 5 V) and C26 (0.1µF). The datasheet recommends 22-68 µF of low-ESR ceramic for ripple, stability and transient response. Here the ceramic share is about 5.4 µF effective, and about 450 µF of higher-ESR aluminium dominates. The recommendation is not a minimum, but loop behaviour with this mix is not characterised. Values are nominal except C27. Source: Diodes Incorporated AP64352 datasheet (source: Tomachie).	Review
4.6.13	U7 output current	+5v0	U7 permits 2.45 A, which is 3.5 A derated 30% (regulator_output_current_pct = 70). The known +5v0 load is about 21 mA: - U14: 3.35 mA idle. - D15: 9.2 mA. - D16: 8.7 mA. - U3 and U9: 20 µA. - U1 and U8: 0.16 mA quiescent. This does not include the J3_1 and J4_1 switched loads (U1 and U8 each permit 2.5 A), J3_6, U14's speaker drive or U5's draw through D6. Check that the total stays below 2.45 A. Sources: Diodes Incorporated AP64352 datasheet p.1 (source: Tomachie); Diodes Incorporated AP22804 datasheet p.3 (source: Tomachie).	Review
4.6.14	C7 (EEE-FK1V101P), C8	+VIN-PROTECT	Input RMS ripple current is IOUT × √(D(1−D)). That is 0.49 × IOUT at 12 V and 0.5 × IOUT at about 10 V input. C7 is stated at 600 mA, and C8 carries most of the 2 MHz component. Check that the output current keeps C7's share within 600 mA.	Review
4.6.15	C7 (EEE-FK1V101P)	+VIN-PROTECT	The FK series endurance is 2000 h at 105 °C, roughly doubling for each 10 °C lower. C7 sits on an always-on input, but the design states no maximum ambient. Source: Panasonic EEE-FK datasheet p.1, Datasheet.	Review
4.6.16	C27 (GCM21BR71A106KE22K)	+5v0	The Capacitance-DC Bias Characteristics graph (p.1) shows -46.4% at 5 V, so the 10 µF part presents about 5.4 µF. U14's datasheet reference circuits show 10 µF and 0.1 µF at VDD, and C27/C26 supply them nominally. The rail also carries 300 µF of aluminium. Sources: Murata GCM21BR71A106KE22 datasheet; Maxim MAX98357A datasheet p.14 (source: Tomachie).	Review
4.6.17	U3, U9 (SN74LV1T34DBVR)	+5v0	+5v0 carries one 0.1 µF ceramic (C26), and it matches U14's own stated bypass. U3 and U9 each ask for a 0.1 µF bypass close to VCC, but have none of their own. Source: Texas Instruments SN74LV1T34 datasheet p.13, Datasheet.	Review
4.6.18	U1, U8 EN	NP0-EN, NP1-EN	U5 P1.11 and P0.04 drive U1_4 and U8_4 directly, with no pull resistor. The datasheet says EN must not be left floating and advises holding it low while power is applied or removed (p.13). Check that P1.11 and P0.04 hold a defined low from the moment +5v0 rises. A 100kΩ pull-down from each EN net to GND would hold U1 and U8 off until firmware drives them, as R5, R6, R10 and R29 already do for the MOSFET gates. The U5 GPIO reset state was not available at report generation time. Source: Diodes Incorporated AP22804 datasheet p.13 (source: Tomachie).	Review
4.6.19	J3_6	+5v0	J3_6 places +5v0 directly on an off-board wire pad, with no load switch. Its load is unknown. An external short there is limited only by U7's 4.25-5.75 A peak current limit, through R15/R16 and L4.	Review
4.6.20	D15 (APT2012SURCK), D16 (APT2012CGCK), R34, R35	+5v0	Operating points: - D15: 9.2 mA, 18 mW. - D16: 8.7 mA, 18 mW. - R34 and R35: 28 mW each, against 0.1 W derated 45% (resistor_power_pct = 55) = 55 mW. Both LEDs are inside their 30 mA and 75 mW ratings at 25 °C. Their forward-current derating curves (-0.4 mA/°C from 30 mA at 25 °C) reach 9.2 mA at about 77 °C ambient. The design states no maximum ambient. Sources: Kingbright APT2012SURCK and APT2012CGCK datasheets pp.2-3 (source: Tomachie).	Review
4.6.21	R15, R16 (ERJ-6GEY0R00V, 0Ω 0805)	NetC14_1 to +5v0	The two links in parallel carry the whole +5v0 load. The schematic data states no current rating for them. The conventional 0805 jumper rating is 2 A each. Sharing equally, each carries about 1.75 A at U7's 3.5 A rating and about 2.9 A at its 5.75 A maximum current limit. That is within the band where the case size alone cannot decide. State the rating in a named Current property.	Review
4.6.22	U5, U12, U13, U4, U10	VDD	VDD carries C6 (4.7µF) and six 0.1 µF capacitors (C1-C4, C25, C28), shared by U5's five VDD pins, U12, U13, U4 and U10. Nordic's reference circuitry adds 1.0 µF, and shows 100 nF at each VDD pin. U12, U4 and U10 each ask for about 0.1 µF of their own. The 1.0 µF is absent, and the 0.1 µF count is below the combined reference demand. These figures come from reference circuits, not stated minimums. Sources: nRF52840 datasheet; Texas Instruments SN74LV1T34 datasheet p.13, Datasheet; Macronix MX25R6435F datasheet p.63 (source: Tomachie).	Review
4.6.23	L1 (MLZ1608M100WTD25)	NetL1_2 to VDD	On the INDUCTANCE VS. DC BIAS graph (p.3, M100W), inductance is about 10.8 µH at the 13 mA known VDD load. That load comprises U12, U13, U4, U10 and R11, and excludes U5. Saturation current is 90 mA (50% drop) and Itemp is 250 mA. Check that U5's DCCH peak inductor current stays below 90 mA. The DCCH peak current value was not available at report generation time. Source: TDK MLZ1608 datasheet pp.1, 3 (source: Tomachie).	Review
4.6.24	U13 (FM25L16B-GTR)	VDD	VDD is 2.70V. U13 is specified for 2.7-3.6 V, so the rail sits exactly at its minimum with no margin. Check that U5's VDD setting and regulation keep the rail at or above 2.7 V under load and temperature. The VDD regulation tolerance was not available at report generation time. Source: Infineon FM25L16B datasheet p.12 (source: Tomachie).	Review
4.6.25	P0.03 used as U11 supply	P0.03 (V-C--ENABLE)	U11 (TLV271) takes its supply from U5 P0.03. It draws up to 560 µA at 2.7 V (p.5) and is specified for a 2.7-16 V supply (p.3). P0.03 cannot rise above VDD = 2.7 V, and sourcing current lowers it further. The Supply Current vs. Supply Voltage graph (p.8) shows about 250 µA at 2.7 V and 183 µA at 2.5 V at 25 °C, a region the datasheet marks as turn-on behaviour. Check that P0.03's output high level at 560 µA keeps U11 at or above 2.7 V. The U5 VOH value was not available at report generation time. Source: Diodes Incorporated TLV271 datasheet pp.3, 5, 8 (source: Tomachie).	Review
4.6.26	U2 VBAT	NetQ1_3	NetQ1_3 (the Q1 drain, U2 VBAT) carries no capacitor. The TJA1021 datasheet shows 100 nF on VBAT in its timing test circuit (p.15). That is a test circuit, not a stated minimum. Source: NXP TJA1021 datasheet p.15 (source: Tomachie).	Review
4.6.27	Q3, Q4, Q8, Q9, Q10 (2N7002P,215)	LIN-CMDR, LIN-PWR, P0.03, GREEN-LED, RED-LED	The gates are driven by U5 GPIOs, whose high level cannot exceed VDD = 2.7 V. Vth is 1.1-2.4 V at 250 µA, and RDS(on) is specified only at VGS of 5 V and 10 V (Nexperia 2N7002P datasheet p.6, source: Tomachie). Q3, Q4 and Q8 sink under 1 mA into their 10kΩ gate networks. Q9 and Q10, however, must sink the 9.2 mA and 8.7 mA LED currents with as little as 0.3 V of overdrive at the worst-case threshold. Q5 (BSS138K) is already on the board and is characterised at this drive: threshold 0.6-1.2 V, RDS(on) 2.0 Ω maximum at 2.5 V (onsemi BSS138K datasheet p.2, source: Tomachie).	Review
4.6.28	C1, C2, C3, C4 (GCM155R71H104KE02D)	VDD	These are 50 V parts. Derated 20% (capacitor_voltage_pct = 80) they permit 40 V, and 2.7 V is applied. That is benign over-specification; a 16 V part would serve. Source: Murata GCM155R71H104KE02 datasheet p.2, Datasheet.	Review
4.6.29	C25, C26, C28 (GCJ188R91H104KA01D)	VDD, +5v0	These are 50 V parts. Derated 20% (capacitor_voltage_pct = 80) they permit 40 V, against 2.7 V on C25 and C28 and 5 V on C26. That is benign over-specification; a 16 V part would serve. Source: Murata GCJ188R91H104KA01 datasheet p.2, Datasheet.	Review
4.6.30	Q1 (BSS84-7-F), D1 (BZX84C12-7-F)	+VIN-PROTECT	The R1/R4 network would apply 14.57 V. D1 conducts and holds VGS at 11.4-12.7 V, which is below the 14 V derated limit (mosfet_vgs_pct = 70) and the ±20 V rating. D1 carries about 0.28 mA (3.4 mW) at 16 V and 0.48 mA (5.8 mW) at the 18 V excursion. Its rating is 300 mW per the part description, or 135 mW derated 55% (zener_power_pct = 45). Sources: Diodes Incorporated BZX84C12 datasheet; Diodes Incorporated BSS84 datasheet p.2 (source: Tomachie).	✓
4.6.31	Q6 (ZXMP4A16GTA), D9	+VIN, +VIN-PROTECT	On a reverse connection the body diode blocks and the gate cannot fall below the source, so the channel stays off. The 16-18 V then across drain-source is a fault, judged against the 40 V absolute maximum un-derated. In normal operation VDS is only the channel drop. D9's dissipation is bounded by 16 V × 1.6 mA = 26 mW even at the R18 ceiling, against 300 mW (135 mW derated, zener_power_pct = 45). Sources: Diodes Incorporated ZXMP4A16G datasheet p.2 (source: Tomachie); Vishay BZX84B16 datasheet p.2 (source: Tomachie).	✓
4.6.32	U7 (AP64352SP-13)	+VIN-PROTECT	VIN absolute maximum is 42 V. Derated 25% (regulator_input_voltage_pct = 75) it permits 31.5 V, against 16 V applied at the band top. The 9-16 V band is inside the 3.8-40 V recommended range. The 18 V excursion is inside the 42 V absolute maximum. Correctly sized. Source: Diodes Incorporated AP64352 datasheet p.4 (source: Tomachie).	✓
4.6.33	U7, R17/R23 feedback divider	NetC14_1, +5v0	VOUT = 0.8 V × (1 + 523kΩ/100kΩ) = 4.984 V. With the 792-808 mV reference band this gives 4.934-5.034 V, before the 1% resistor tolerance. Source: Diodes Incorporated AP64352 datasheet p.5 (source: Tomachie).	✓
4.6.34	U7, R22 (49.9kΩ)	NetR22_1	RT/CLK is not floating. fsw = 100000/49.9 = 2004 kHz, inside the 100-2200 kHz range. On-time is 155 ns at 16 V and 138 ns at 18 V. Even at +10% frequency it is 126 ns at 18 V, above the 100 ns maximum minimum on-time. Source: Diodes Incorporated AP64352 datasheet p.5 (source: Tomachie).	✓
4.6.35	U7, C5 (0.1µF)	NetC5_1/NetC5_2	A 100 nF ceramic bootstrap capacitor sits from BST to SW, as the datasheet requires. Source: Diodes Incorporated AP64352 datasheet (source: Tomachie).	✓
4.6.36	U7 EN	+VIN-PROTECT	EN is tied directly to VIN. The converter enables above the 3.5 V typical (3.7 V maximum) rising UVLO and disables below 3.1 V. EN's 42 V absolute maximum covers the 18 V excursion. Source: Diodes Incorporated AP64352 datasheet pp.4-5 (source: Tomachie).	✓
4.6.37	L4 (CDRH103RNP-6R8NC-B)	NetC5_1 to NetC14_1	6.8 µH is inside the recommended 2.2-10 µH range. DCR is 27 mΩ typical and 35 mΩ maximum, against the datasheet's under 30 mΩ for best efficiency. This is an efficiency note only, not a minimum. Sources: Diodes Incorporated AP64352 datasheet (source: Tomachie); Sumida CDRH103R datasheet p.2 (source: Tomachie).	✓
4.6.38	L4 (CDRH103RNP-6R8NC-B)	NetC14_1	Read from the Saturation Current and Temperature Rise graph (p.3, 6R8 curve): - At 2.45 A, U7's derated output limit (regulator_output_current_pct = 70): rise is about 15 °C, and inductance is 6.29 µH at 20 °C and 6.39 µH at 105 °C. - At 3.5 A: rise is about 29 °C. Ripple is 0.25 A peak-to-peak at 16 V, and 0.38 A with the -30% inductance tolerance. The coil's 100 °C maximum includes self-heating. Source: Sumida CDRH103R datasheet pp.1-3 (source: Tomachie).	✓
4.6.39	C12, C13, C14 (EEE-FK1A151P)	+5v0, NetC14_1	The designer states a 240 mA ripple-current rating. Worst-case inductor ripple is 0.38 A peak-to-peak (18 V input, -30% inductance), which is 0.11 A RMS. This stays below 240 mA even if C14 carried all of it.	✓
4.6.40	C7, C8	+VIN-PROTECT	C7 is a 35 V part. Derated 30% (capacitor_aluminum_voltage_pct = 70) it permits 24.5 V. C8 is a 50 V part. Derated 20% (capacitor_voltage_pct = 80) it permits 40 V. 16 V is applied at the band top, so both are correctly sized. Both are also inside their ratings at the 18 V excursion.	✓
4.6.41	C12, C13, C14, C27	+5v0, NetC14_1	C12, C13 and C14 are 10 V aluminium parts. Derated 30% (capacitor_aluminum_voltage_pct = 70) they permit 7 V. C27 is a 10 V ceramic. Derated 20% (capacitor_voltage_pct = 80) it permits 8 V. 5 V is applied, so all are correctly sized.	✓
4.6.42	C6, C9, C10, C11	VDD, NetC10_2	All four are 16 V parts. Derated 20% (capacitor_voltage_pct = 80) they permit 12.8 V. 2.7 V is applied on VDD and 1.3 V on NetC10_2, so all are correctly sized.	✓
4.6.43	U7 soft-start inrush, U5 VDDH ramp	+5v0	Charging about 455 µF of effective output capacitance to 4.98 V in 2 ms draws about 1.1 A, inside the 4.25 A minimum peak current limit. VDDH therefore rises in a few milliseconds, well inside the nRF52840's 100 ms maximum rise time. Sources: Diodes Incorporated AP64352 datasheet p.5 (source: Tomachie); nRF52840 datasheet p.410, Datasheet.	✓
4.6.44	U1, U8 FLAG	-	U1_3 and U8_3 are open-drain fault outputs, left unconnected by design. An unused FLAG needs no pull-up. Source: Diodes Incorporated AP22804 datasheet p.2 (source: Tomachie).	✓
4.6.45	L5, L6 (MPZ2012S221AT000)	SP+, SP-	The ferrites are rated 3 A from -55 to +85 °C. That is above U14's 1.6 A continuous output-current absolute maximum and its 2.8 A typical current limit. Sources: TDK MPZ2012S221A datasheet p.1 (source: Tomachie); Maxim MAX98357A datasheet pp.4-5 (source: Tomachie).	✓
4.6.46	D6, D7 (BAS16-7-F)	+5v0, +VBUS to NetD6_3	VDDH is about 4.1-4.3 V from +5v0 and below 4.8 V from a 5.5 V VBUS, inside the 2.5-5.5 V VDDH range. VR is 100 V, against 5.5 V. IF is 215 mA; derated 35% (diode_if_pct = 65) it permits 140 mA. The known VDD-side load is about 13 mA plus U5's own draw. Source: Nexperia BAS16 datasheet pp.2-3, Datasheet.	✓
4.6.47	J8, R36, R37, U15	+VBUS	CC1 and CC2 each carry a 5.1kΩ Rd to GND (R37, R36). For U15's VCC, a 5.5 V standoff is adequate for the 5.5 V maximum Type-C VBUS. U5's VBUS range of 4.35-5.5 V (5.8 V absolute maximum) covers the same maximum. Sources: Nexperia PRTR5V0U2X datasheet p.3 (source: Tomachie); nRF52840 datasheet pp.410-411, Datasheet; USB Type-C specification.	✓
4.6.48	U5 DECUSB	NetC20_2	C20 (4.7µF) decouples DECUSB, matching the 4.7 µF in the reference circuitry, which the datasheet requires for USB regulator stability (page 87). Source: nRF52840 datasheet.	✓
4.6.49	U5 DEC4, DEC6	NetC10_2	DEC4 (B5) and DEC6 (E24) are tied together, as the datasheet requires. The shared node carries C11 (1µF), matching the 1.0 µF reference, plus C9 and C10 (0.047µF). It is fed from DCC through L3 (10uH) and L2 (15nH). Source: nRF52840 datasheet.	✓
4.6.50	C9, C10 (GCM155R71C473KA37D)	NetC10_2	The DC bias characteristics graph (p.3) shows about +1.1% at 1.3 V, so the parts present their full 0.047 µF. Source: Murata GCM155R71C473KA37 datasheet.	✓
4.6.51	U5 DEC1, DEC2, DEC3, DEC5	NetC17_2, NetC18_2, NetC19_2, NetC16_2	Each decoupling pin has its own capacitor to GND: - DEC1: C17 (0.1µF), matching the 100 nF reference. - DEC2: C18 (0.1µF). - DEC3: C19 (100pF). - DEC5: C16 (1000pF), against the 820 pF reference, which is marked not required for Fxx and later. Source: nRF52840 datasheet.	✓
4.6.52	D3 (BAS16-7-F)	NetD3_1 to NetD3_3	D3 carries 15.3 mA with LIN-IO held low at 16 V. IF is 215 mA; derated 35% (diode_if_pct = 65) it permits 140 mA. Reverse voltage is at most 16-18 V, against 100 V (70 V derated, diode_vrrm_pct = 70). Correctly sized. Source: Nexperia BAS16 datasheet p.2, Datasheet.	✓
4.6.53	D4 (PESD1IVN24-AX)	LIN-IO	A 24 V standoff is adequate for the 16 V maximum normal level on the LIN line. V_BR(min) is 25.5 V at 10 mA, above the 18 V excursion. Source: Nexperia PESD1IVN24 datasheet p.4 (source: Tomachie).	✓
4.6.54	R1, R4, R18, R24, R25	+VIN-PROTECT gate networks	Dissipation at 16 V: - R1: 1.4 mW. - R4: 1.6 mW. - R24: 2.1 mW. - R25: 0.2 mW. - R18: under 0.6 mW, even at the 18 V excursion, since it conducts only when D9 does. All are far inside 0.1 W derated 45% (resistor_power_pct = 55), which permits 55 mW.	✓

4.7 Citations

AI-Assisted —

References
BAS16 (Nexperia) — datasheet www.diodes.com/datasheets/ds12003.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
EEEFK1V (Panasonic Industry) — datasheet, cited pages 1,5 industrial.panasonic.com/cdbs/www-data/pdf/RDE0000/ABA000...
GCJ188R91H104KA01D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/24e69d76f59b023f447ab5...
GCJ32EC71H106KA01 (Murata) — datasheet www.mouser.com/datasheet/2/281/GCJ32EC71H106KA01_01-19641...
GCM155R71C473KA37 (Murata Manufacturing Co., Ltd.) — datasheet static.chipdip.ru/lib/891/DOC031891133.pdf
GCM155R71H104KE02 (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/b385f789d1f9e1d12e8261...
GCM188R71C105KA64 (Murata) — datasheet www.mouser.com/datasheet/2/281/GCM188R71C105KA64_01-19672...
GCM21BR71A106KE22K (Murata) — datasheet ds.murata.co.jp/simserve/characteristics?ModeType=normal&...
GCM21BR71C475KA73 (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/5a59cb646dab411de77815...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
SN74LV1T34 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/sn74lv1t34.pdf

5 Connector Pinouts

Total connectors

5.1 J1 WIREPAD-18AWG-4X-3.5MM

J1 - WIREPAD-18AWG-4X-3.5MM (WIREPAD-18AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	NC
3	3	LIN-IO
4	4	GND

5.2 J2 WIREPAD-18AWG-4X-3.5MM

J2 - WIREPAD-18AWG-4X-3.5MM (WIREPAD-18AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	NC
3	3	LIN-IO
4	4	GND

5.3 J3 WIREPAD-22AWG-6X-3.5MM

J3 - WIREPAD-22AWG-6X-3.5MM (WIREPAD-22AWG-6X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+5v0-CH0
2	2	NP0-EXT
3	3	GND
4	4	GND
5	5	BTN0-EXT
6	6	+5v0

5.4 J4 WIREPAD-22AWG-4X-3.5MM

J4 - WIREPAD-22AWG-4X-3.5MM (WIREPAD-22AWG-4X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+5v0-CH1
2	2	NP1-EXT
3	3	AUX1-EXT
4	4	GND

5.5 J5 WIREPAD-22AWG-3X-3.5MM

J5 - WIREPAD-22AWG-3X-3.5MM (WIREPAD-22AWG-3X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	+VIN
2	2	CHG-LOOP
3	3	GND

5.6 J6 WIREPAD-22AWG-2X-3.5MM

J6 - WIREPAD-22AWG-2X-3.5MM (WIREPAD-22AWG-2X-3.5MM)
Pin	Pin Name	Net	Notes
1	1	SP-
2	2	SP+

5.7 J7 TAG-CONNECT-SWD (SWD)

J7 - TAG-CONNECT-SWD (SWD)
Pin	Pin Name	Net	Notes
1	VCC	VDD
2	SWDIO	SWDIO
3	RST	RESET
4	SWDCLK	SWDCLK
5	GND	GND
6	SWO	NC

5.8 J8 USB4145-03-0230-C

J8 - USB4145-03-0230-C
Pin	Pin Name	Net	Notes
A1	GND_A	GND
A4	VBUS_A	+VBUS
A5	CC1	CC1
A6	DP1	USB-DEVICE-D_P
A7	DN1	USB-DEVICE-D_N
A8	SBU1	NC
A9	VBUS_A	+VBUS
A12	GND_A	GND
B1	GND_B	GND
B4	VBUS_B	+VBUS
B5	CC2	CC2
B6	DP2	USB-DEVICE-D_P
B7	DN2	USB-DEVICE-D_N
B8	SBU2	NC
B9	VBUS_B	+VBUS
B12	GND_B	GND
S1	SHIELD	GND
S2	SHIELD	GND
S3	SHIELD	GND
S4	SHIELD	GND

5.9 J9 20021121-00010T4LF

J9 - 20021121-00010T4LF (20021121-00010T4LF)
Pin	Pin Name	Net	Notes
1	VCC	NC
2	SWDIO/TMS	NC
3	GND	NC
4	SWDCLK/TCK	NC
5	GND	NC
6	SWO/TDO	NC
7	KEY	NC
8	TDI	NC
9	GND_DETECT	NC
10	RST	NC

6 Indicator Documentation

2 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D16	LED-GREEN	Green	D16_C, R35_2	cricket-node-hw--top-level_B.SchDoc	LOW = On; R35 (330Ω); A:+5v0 K:D16_C, R35_2
D15	LED-RED	Red	D15_C, R34_2	cricket-node-hw--top-level_B.SchDoc	LOW = On; R34 (330Ω); A:+5v0 K:D15_C, R34_2

6.2 Indicator Testability

0 of 2 indicators have test coverage.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D16	Direct	D16_C, R35_2	Design Warning: Test point needed on D16_C, R35_2. Drive LOW to turn on LED D16.
D15	Direct	D15_C, R34_2	Design Warning: Test point needed on D15_C, R34_2. Drive LOW to turn on LED D15.

7 Switch Documentation

No switches or push buttons found in design.

8 Low-Speed Serial Interfaces (LSSI)

Detected: 2 SWD | 1 partial

8.1 SWD

SWD -> U5
Topology: Access (J7, TP21, TP22) » Targets (U5)
Signal	Net Name	Connector	Test Point	Target Pin
SWCLK	SWDCLK	J7_4	TP22_1	U5_AA24 (SWDCLK)
SWDIO	SWDIO	J7_2	TP21_1	U5_AC24 (SWDIO)
NRST	RESET	J7_3	TP23_1	U5_AC13 (P0.18/RESET)
Target	Industry Type	Description
U5	nRF52840-QIAA	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN

SWD -> U5
Topology: Access (J7, TP21, TP22) » Targets (U5)
Signal	Net Name	Connector	Test Point
SWCLK	SWDCLK	J7	TP22_1
SWDIO	SWDIO	J7	TP21_1
NRST	RESET	J7	TP23_1
Target	Industry Type	Description
U5	nRF52840-QIAA	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN

8.2 Signals That Failed to Trace

These signals appear to be part of LSSI interfaces based on naming patterns, but their endpoints could not be fully traced. The signals were found on test points or connectors but the target IC could not be determined. This may indicate daisy-chained connections (TDO->TDI), signals through resistors, or non-standard naming.

Failed Interface Trace Details
Interface	Target	Found Signals	Trace Path	Missing Signals	Connector	Test Point
JTAG	J9	TCK, TDI, TDO, TMS	-	NOT_ROUTED	J9	(none)

8.3 LSSI DFT Analysis

All serial interface signals have test point coverage.

9 High-Speed Serial Interfaces (HSSI)

2 differential pair(s)

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 1 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
USB-DEVICE-D_P/N	USB

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Device Port (J8 Type-C to U5)

AI-Assisted — The only differential interface on the schematic is a USB 2.0 device port. It runs from the J8 Type-C receptacle (GCT USB4145-03-0230-C, a vertical SMT USB 2.0 Type-C receptacle) to U5 (nRF52840). Net USB-DEVICE-D_P joins J8_A6 DP1 and J8_B6 DP2 to U5_AD6 D+. Net USB-DEVICE-D_N joins J8_A7 DN1 and J8_B7 DN2 to U5_AD4 D-. Tying both receptacle rows together makes the port work in either plug orientation, as the USB Type-C specification requires for a USB 2.0 receptacle. The tie also leaves a short stub on each line, which is acceptable at USB 2.0 signalling rates if it is kept short in layout.

USB 2.0 is a DC-coupled interface, and neither line carries a series capacitor or a series resistor. Line termination and the device-side pull-up sit inside the transceiver at U5.

The USB 2.0 specification calls for a 90 Ω differential pair. Both nets are grouped as a USB differential pair, but no 90 Ω impedance class is assigned to them.

U15 (PRTR5V0U2X) protects the pair. U15_2 IO1 is on D_P, U15_3 IO2 is on D_N, U15_4 VCC is on +VBUS and U15_1 GND is on GND. U15 adds 1 pF typical, 1.5 pF maximum, from each line to ground, and 0.6 pF typical between the lines (Nexperia PRTR5V0U2X datasheet p.4, source: Tomachie). Both lines therefore see the same loading. U15 is rated for ±8 kV IEC 61000-4-2 contact discharge (p.3). Its clamping voltage is 17 V typical at 2.5 A, 8/20 µs (p.4). The protection ordering at J8 is judged in the EMC/ESD review.

TP3 and TP4 sit directly on D_P and D_N. Each adds pad capacitance and a possible stub.

VBUS and DECUSB decoupling for the USB regulator, and the CC1/CC2 Rd resistors, are covered in the power review.

9.3 Observations

AI-Assisted — The USB 2.0 pair is wired correctly. D+ and D- run straight through with no polarity swap, both receptacle rows are tied for flip support, and U15 loads the two lines equally.

The open items are layout and margin questions rather than wiring defects. The first is the 90 Ω differential impedance class, which is not attached to USB-DEVICE-D_P and USB-DEVICE-D_N. Assigning it in the schematic carries the constraint into layout.

The second is U15's 17 V typical clamp level, set against U5's D+ and D- pins. U5 is stated at 2 kV HBM, Class 2, for the aQFN73 package (nRF52840 datasheet page 411). That is a component-level ESD rating, not a rating for the 8/20 µs waveform at which U15's clamp is specified, so the two figures are not directly comparable.

The third is the stub created by TP3 and TP4, which is minimised by placing the pads directly on the routed pair.

The QSPI flash link (U12) and the FRAM SPI link (U13) are single-ended buses and are reviewed outside this section.

9.4 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.4.1	USB (J8, U5)	USB 2.0	USB-DEVICE-D_P and USB-DEVICE-D_N are grouped as a differential pair, but no 90 Ω differential impedance class is assigned, although the USB 2.0 specification calls for 90 Ω. Remedy: assign a 90 Ω differential net class to the pair in the schematic.	Review
9.4.2	USB ESD (U15, U5)	USB 2.0	U15 clamps at 17 V typical at 2.5 A, 8/20 µs (Nexperia PRTR5V0U2X datasheet p.4, source: Tomachie). Check that U5_AD6 D+ and U5_AD4 D- are rated for this waveform. U5 is stated only at 2 kV HBM, Class 2, for the aQFN73 package (nRF52840 datasheet page 411, Datasheet).	Review
9.4.3	USB test access (TP3, TP4)	USB 2.0	TP3 on USB-DEVICE-D_P and TP4 on USB-DEVICE-D_N add pad capacitance and a possible stub to the pair. Place the pads directly on the routed pair with no branch.	Review
9.4.4	USB clock (X1, U5)	32 MHz HFXO	X1 has 8 pF load capacitors on each terminal: C22 on U5_B24 XC1 and C21 on U5_A23 XC2, presenting 4 pF in series. Nordic's reference circuitry fits 12 pF per pin (nRF52840 datasheet page 937, Datasheet). That is an application-circuit figure, not a minimum, and the stray capacitance it assumes is not stated. The 4 pF stray implied by X1's 8 pF load capacitance in the schematic description therefore cannot be judged.	Review
9.4.5	USB (J8, U5)	USB 2.0	USB-DEVICE-D_P joins J8_A6 DP1 and J8_B6 DP2 to U5_AD6 D+. USB-DEVICE-D_N joins J8_A7 DN1 and J8_B7 DN2 to U5_AD4 D-. There is no polarity swap, and both receptacle rows are tied for orientation-independent operation, as the USB Type-C specification requires for a USB 2.0 receptacle.	✓
9.4.6	USB (J8, U5)	USB 2.0	Neither line has a series capacitor. USB 2.0 is DC-coupled, so no AC coupling is required (USB 2.0 specification).	✓
9.4.7	USB (J8)	USB 2.0	J8 (GCT USB4145-03-0230-C) is a USB 2.0 Type-C receptacle, the connector the interface standard names, and it is suitable for the signal rate.	✓
9.4.8	USB ESD (U15)	USB 2.0	U15 (PRTR5V0U2X) adds 1 pF typical and 1.5 pF maximum from each line to ground, and 0.6 pF typical between the lines, at 1 MHz and 25 °C. Both lines are loaded equally. Source: Nexperia PRTR5V0U2X datasheet p.4, source: Tomachie.	✓
9.4.9	USB ESD (U15)	USB 2.0	U15 is rated for ±8 kV IEC 61000-4-2 contact discharge (Nexperia PRTR5V0U2X datasheet p.3, source: Tomachie). Its I/O pins sit on D_P (U15_2) and D_N (U15_3), its VCC (U15_4) on +VBUS and its GND (U15_1) on GND.	✓

9.5 Citations

AI-Assisted —

References
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 U12 QSPI

U12 (MX25R6435FZNIL0) - QSPI [4-bit data]
Signal	Pin Name	Pin #	Net Name	Test Point
CLOCK	SCLK	6	QSPI-SCLK / P0.14	-
DATA_0	SIO0/SI	5	P0.21 / QSPI-D0	-
DATA_1	SIO1/SO	2	QSPI-D1 / P0.22	-
DATA_2	SIO2/WP	3	QSPI-D2 / P0.20	-
DATA_3	SIO3/RESET	7	QSPI-D3 / P0.23	-
SELECT	CS	1	QSPI-CS / P0.24	-
DESIGN_WARNING: Test points would be needed on P0.21, QSPI-CS, QSPI-D1, QSPI-D2, QSPI-D3 and QSPI-SCLK if direct on-board programming is desired over indirect programming via the FPGA/CPU (U5)
Test points on U12's SPI nets (QSPI-SCLK, P0.21, QSPI-D1, QSPI-D2, QSPI-D3, QSPI-CS) let a flying-probe or bed-of-nails fixture load it three ways: program it directly; hold U12 deselected and boot U5 from a pre-programmed memory in the fixture, to run test code instead of the board's image; or boot U5 from that fixture memory and have it copy the image into U12 a block at a time, often the fastest way to program.
U12 is in-system programmable via U5 (nRF52840-QIAA) over SWD. A debug probe on the SWD port loads a programming routine into U5, which then drives the memory bus

10.2 AI-Assisted Analysis

10.2.1 QSPI Flash (U12)

AI-Assisted — U12 is a Macronix MX25R6435FZNIL0, a 64 Mbit serial NOR flash. It connects point-to-point to the nRF52840 host U5 as a quad-I/O device. QSPI-SCLK (U5 P0.14) drives U12_6 SCLK and QSPI-CS (U5 P0.24) drives U12_1 C̅S̅. The four data lines run as QSPI-D0 on P0.21 to U12_5 SIO0, QSPI-D1 on P0.22 to U12_2 SIO1, QSPI-D2 on P0.20 to U12_3 SIO2/W̅P̅, and QSPI-D3 on P0.23 to U12_7 SIO3/R̅E̅S̅E̅T̅. Each of the six nets carries only the flash pin and the host pin, so there is no shared load and no stub. The data-pin order is non-sequential on the host side, and the host's QSPI pin selection must follow this mapping.

U12 and U5 share the VDD rail at 2.7 V, so no level translation is involved. U12 powers up in Ultra Low Power Mode, which limits 4READ/QREAD to 8 MHz and single-I/O FAST_READ to 33 MHz. High Performance Mode raises quad reads and quad page program to 80 MHz. Switching between the two modes requires a WRSR at no more than 33 MHz and takes up to 20 µs (tWMS). In High Performance Mode, tCLQV is 8 ns at 30 pF and 6 ns at 15 pF. The pins load the bus with 6 pF input and 8 pF output capacitance, against U5's 3 pF pad capacitance. All six lines are connected directly, with no series resistors.

U12 has no TEN-class test pin. Both the HOLD# and the RESET# functions sit on the SIO3 position; this ordering option has R̅E̅S̅E̅T̅. Source: Macronix datasheet (source: Tomachie).

10.3 Observations

AI-Assisted — Three host-dependent conditions govern U12 at power-up and reset. They are C̅S̅ deselect, the R̅E̅S̅E̅T̅/SIO3 level, and the W̅P̅/SIO2 level.

The datasheet states that the internal pull-ups on W̅P̅/SIO2 and R̅E̅S̅E̅T̅/SIO3 are disabled once those pins are physically connected (page 8). It also states that a R̅E̅S̅E̅T̅ low of 10 µs or more resets the device and can terminate a program or erase operation with data loss (page 62). With no external pull resistor on QSPI-CS, QSPI-D2 or QSPI-D3, the level on these three pins while U5 is not driving them is set entirely by U5's pin state. Pull-ups to VDD on those three nets would follow U12's own supply, because both parts share that rail. Such pull-ups do not conflict with quad-I/O operation.

Once the Quad Enable bit is set, W̅P̅ hardware protection of BP3–BP0 and SRWD is disabled (page 10). This is inherent to quad operation, so write protection then rests on the status-register block-protect bits under firmware control.

U12 VCC decoupling is shared on VDD with U5, U13, U4 and U10. The power review already reported the shortfall in 0.1 µF parts on that rail; the flash's own requirement is listed in the table.

None of the six QSPI nets carries a test point, although the board carries 27 test points elsewhere.

10.4 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.4.1	QSPI Flash (U12)	Logic levels, host to flash	At VCC = 2.7 V, U12 requires VIH ≥ 0.8 × VCC = 2.16 V and VIL ≤ 0.2 × VCC = 0.54 V on SCLK, C̅S̅ and SIO0–SIO3 (Macronix datasheet page 66, source: Tomachie). Check that U5 VOH and VOL on P0.14, P0.24 and P0.20–P0.23 are compatible. The U5 VOH value was not available at report generation time.	Review
10.4.2	QSPI Flash (U12)	Logic levels, flash to host	U12 drives VOH ≥ VCC − 0.2 V = 2.5 V at −100 µA and VOL ≤ 0.2 V at 100 µA (Macronix datasheet page 66, source: Tomachie). Check that U5 VIH and VIL on P0.20–P0.23 are compatible. The U5 VIH value was not available at report generation time.	Review
10.4.3	QSPI Flash (U12)	Clock frequency and operating mode	U12 allows 4READ/QREAD at up to 8 MHz in Ultra Low Power Mode (the power-up mode, page 68) and up to 80 MHz in High Performance Mode (page 70). The WRSR that switches between these modes must run at no more than 33 MHz (page 71). Check that U5's QSPI clock setting matches the mode firmware selects in U12. The U5 QSPI clock limit was not available at report generation time. Source: Macronix datasheet (source: Tomachie).	Review
10.4.4	QSPI Flash (U12)	C̅S̅ power-up level	QSPI-CS connects U12_1 C̅S̅ directly to U5 P0.24, with no pull-up. The datasheet states that a pull-up on C̅S̅ may ensure a safe power-up and power-down level (page 63), and that C̅S̅ must follow VCC (pages 72–74). Fit a pull-up from QSPI-CS to VDD, such as the 100kΩ already used on U13. It tracks U12 VCC and holds the flash deselected while U5 P0.24 is not driven. Source: Macronix datasheet (source: Tomachie).	Review
10.4.5	QSPI Flash (U12)	Power-up delay tVSL	U12 C̅S̅ must not be asserted until tVSL = 800 µs after VCC reaches 1.65 V (Macronix datasheet page 74, source: Tomachie). Check that U5's first access to U12 occurs at least 800 µs after VDD exceeds 1.65 V.	Review
10.4.6	QSPI Flash (U12)	R̅E̅S̅E̅T̅/SIO3 level	U12_7 R̅E̅S̅E̅T̅/SIO3 loses its internal pull-up because it is connected (page 8). A low of 10 µs or more resets the flash and can abort a program or erase with data loss (page 62). QSPI-D3 has no external pull-up, so its level outside QSPI transfers is set only by U5 P0.23. Check that U5 holds P0.23 high from power-up and through a U5 reset. Otherwise, fit a pull-up from QSPI-D3 to VDD, which keeps U12 out of reset whenever the host is not driving the line. Source: Macronix datasheet (source: Tomachie).	Review
10.4.7	QSPI Flash (U12)	W̅P̅/SIO2 write protection	U12_3 W̅P̅/SIO2 is driven from U5 P0.20 on QSPI-D2, with no pull resistor. The internal pull-up is disabled because the pin is connected (page 8). With the Quad Enable bit set, W̅P̅ hardware protection of BP3–BP0 and SRWD is disabled (page 10), so protection of the array rests on the status-register block-protect bits set by firmware. This is inherent to the quad-I/O choice. Source: Macronix datasheet (source: Tomachie).	Review
10.4.8	QSPI Flash (U12)	Series termination	QSPI-SCLK and QSPI-D0 to QSPI-D3 connect directly, with no series resistors. In High Performance Mode, U12 output valid tCLQV is 8 ns at 30 pF (page 70). Footprints for series resistors at the U5 end of QSPI-SCLK, and at the source end of the data lines, would allow edge-rate control if ringing appears at the chosen clock. Source: Macronix datasheet (source: Tomachie).	Review
10.4.9	QSPI Flash (U12)	VCC decoupling	The datasheet recommends about 0.1 µF close to the VCC pins (page 63). U12_8 shares VDD with U5, U13, U4 and U10, and that rail carries C6 (4.7µF) and six 0.1µF parts (C1–C4, C25, C28). The power review has already reported that count as short. Place one 0.1µF directly at U12_8. Source: Macronix datasheet (source: Tomachie).	Review
10.4.10	QSPI Flash (U12)	Test access	None of the six QSPI nets (QSPI-SCLK, QSPI-CS, P0.21, QSPI-D1, QSPI-D2, QSPI-D3) carries a test point. Probing the flash bus during bring-up or production test therefore requires access at U12's own pads.	Review
10.4.11	QSPI Flash (U12)	Supply	U12_8 VCC is on VDD at 2.7 V. This is inside the 1.65–3.6 V operating range (page 1), above the 1.5 V maximum write-inhibit threshold VWI (page 74), and below the 4.0 V VCC absolute maximum (page 64). U12_4 GND and U12_9 exposed pad are on GND. Source: Macronix datasheet (source: Tomachie).	✓
10.4.12	QSPI Flash (U12)	QSPI connectivity	Each of the six signals is a dedicated point-to-point net between U12 and U5, with no shared load and no direction conflict: SCLK on QSPI-SCLK/P0.14, C̅S̅ on QSPI-CS/P0.24, SIO0 on P0.21, SIO1 on P0.22, SIO2 on P0.20 and SIO3 on P0.23. Pin functions are per the Macronix datasheet page 8 (source: Tomachie).	✓
10.4.13	QSPI Flash (U12)	Pin absolute maximum	Both parts are supplied from VDD at 2.7 V. U12 inputs tolerate VCC + 0.5 V = 3.2 V (Macronix datasheet page 64, source: Tomachie). U5 I/O pins tolerate VDD + 0.3 V = 3.0 V (Nordic nRF52840 datasheet page 972, Datasheet). Neither side drives above 2.7 V, so both limits are met.	✓

10.5 Citations

AI-Assisted —

References
EEEFK1V (Panasonic Industry) — datasheet, cited pages 1,5 industrial.panasonic.com/cdbs/www-data/pdf/RDE0000/ABA000...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...

11 Functional Analysis

11 device(s) to review across 6 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
U2	COMMUNICATION	TJA1021T/20/CM,118	1 Transceiver Full Duplex 1 SOIC-8 LIN Transceivers ROHS	-	-
U11	DEVICE	TLV271CW5-7	Single 1pA 2V/us 1.9MHz SOT-25 Operational Amplifier ROHS	-	-
U13	DEVICE	FM25L16B-GTR	16Kbit 20MHz SPI SOIC-8 FRAM ROHS	-	-
U14	DEVICE	MAX98357AETE+T	Monaural 3.2Wx2@4O TQFN-16-EP(3x3) Audio Amplifiers ROHS	-	-
X1	DEVICE	ECS-320-8-37B-CKY-TR	32MHz 8pF ±10ppm SMD2016-4P	-	-
X2	DEVICE	NX3215SA-32.768K-STD-MUA-9	32.768kHz 9pF ±20ppm SMD3215-2P	-	-
D2	DIODE	BZX84B16-7-F	DIODE ZENER 16V 300MW SOT23	-	-
D3	DIODE	BAS16-7-F	DIODE SWITCHING 75V 200MA SOT23	-	-
U15	Prot.	PRTR5V0U2X,215	6V Unidirectional 5.5V SOT-143 ESD and Surge Protection (TVS/ESD) ROHS	-	-
Q2	Trans.	BSS84-7-F	MOSFET P-CH 50V 130MA SOT23-3	-	-
U5	WIRELESS	NRF52840-QIAA-R	Cortex M4 MCU IC RF TXRX+MCU 802.15.4 73QFN	SWD	-

11.1 Reset-Time Strap Configuration

Each device below takes part of its start-up configuration from resistors the board fits on pins it samples at reset. Every setting is resolved against that device's own datasheet tables - the combination this board selects, and whether the datasheet marks that combination reserved or invalid.

RefDes	Configuration	This Board Selects	Read From	Status
U5	NRF52840-QIAA-R	No reset-time straps: probe: the pages show no reset-time configuration		✓

11.2 Functional Analysis

11.2.1 LIN Transceiver U2 with Commander Switch Q2, Gate Clamp D2 and Series Diode D3

AI-Assisted — U2 (TJA1021T/20) takes VBAT on U2_7 from NetQ1_3, the drain of Q1. Its supply is therefore switched from +VIN-PROTECT under the control of LIN-PWR (U5 P0.27), which R6 (1MΩ) holds low at reset. The 9-16 V band lies inside the 5.5-27 V static characterisation range, and the 18 V excursion lies inside the 40 V VBAT absolute maximum (NXP TJA1021 datasheet p.10-11, source: Tomachie).

RXD (U2_1) is open-drain, and R11 (10kΩ) pulls LIN-RX-OUT to VDD as the datasheet requires. TXD (U2_4) and SLP_N (U2_2) are driven directly by U5 P0.29 and P0.31. The 140-1200 kΩ internal pull-down on SLP_N keeps the transceiver out of Normal mode until firmware drives the pin.

WAKE_N (U2_3) is held at VBAT by R8 (100kΩ), and Q5 pulls it low for a local wake. R8 returns to the switched VBAT node, so WAKE_N never sits above an unpowered VBAT.

INH (U2_8) feeds the commander termination. Q2 switches INH through D3 and R7 (1kΩ) onto LIN-IO, which is the 1 kΩ-plus-series-diode arrangement the datasheet gives for a commander node (p.16). Q3, driven from LIN-CMDR with R5 (1MΩ) to GND, turns Q2 on. The node therefore powers up as a responder, and firmware selects commander. With LIN-IO held low at 16 V, INH sources about 15.5 mA, which is 15.3 mA through R7 plus 0.15 mA in the R2/R3 gate divider.

D3 also stops LIN-IO from back-feeding INH when U2 is unpowered. D2 is Q2's gate clamp. Its conduction point is above the normal-band gate-source voltage; Q2's VGS margin itself is reported in the power review. LIN-IO carries no capacitor to ground, only D4's 14-17 pF.

11.2.2 Input Voltage Monitor Buffer U11

AI-Assisted — U11 (TLV271CW5-7) is wired as a unity-gain follower. OUT (U11_1) and the inverting input (U11_4) share P0.02, which runs to U5 AIN0. The non-inverting input (U11_3) sits on the R26 (100kΩ) / R28 (10kΩ) divider, which Q7 switches onto +VIN-PROTECT. U11's supply, Q8 and therefore Q7 are all controlled by P0.03. The divider is energised only while U11 is powered, so +IN never sits above an unpowered supply.

The divider presents 0.0909 × VIN to +IN:
- 1.09 V at 12 V.
- 1.455 V at the 16 V band top.
- 1.481 V at 16 V at the 1% tolerance corner (R28 high, R26 low).
- 1.636 V at the 18 V excursion.

The recommended common-mode input range is 0 V to VDD − 1.35 V (Diodes Incorporated TLV271 datasheet p.3, source: Tomachie). Supplied from P0.03 at no more than 2.7 V, U11 has a 1.35 V ceiling. That ceiling is reached at VIN = 14.85 V, and lower still once the GPIO's own output drop is subtracted. The top of the stated +VIN band is therefore measured with U11 outside its recommended operating conditions.

Changing R28 to 6.8kΩ places 16 V at 1.02 V and 18 V at 1.15 V (1.04 V and 1.17 V at the tolerance corner). U5's ADC scaling then has to suit the lower level.

The Supply Current vs. Supply Voltage graph (p.8, 25 °C) shows the current still climbing steeply at 2.7 V: 183 µA at 2.5 V, 250 µA at 2.7 V and 291 µA at 3.0 V. This adds to the power review's finding on the P0.03 supply. The output drives only U5's pad, so no series isolation resistor is required. The datasheet specifies the C grade for 0 to +70 °C.

11.2.3 SPI FRAM U13

AI-Assisted — U13 (FM25L16B) is a point-to-point SPI slave of U5:
- FRAM-CLK (P0.25) drives C on U13_6.
- P1.04 drives D on U13_5.
- Q on U13_2 returns on P1.03.
- FRAM-CS (P1.02) drives C̅S̅ on U13_1.

Directions agree on every net, and no other device shares them. Its supply margin on VDD is covered in the power review.

H̅O̅L̅D̅ (U13_7) is pulled to VDD by R38 (100kΩ). This meets the datasheet requirement that an unused H̅O̅L̅D̅ be tied to VDD (Infineon FM25L16B datasheet p.3, source: Tomachie). The ±1 µA input leakage drops at most 0.1 V across R38, so the pin stays well above VIH = 0.7 × VDD = 1.89 V.

W̅P̅ (U13_3) is held high by R14 (100kΩ) alone, and nothing on the board can pull it low. The status-register write protection that W̅P̅ provides once WPEN is set is therefore never available. A stray write can always change the block-protect bits.

C̅S̅ has no pull-up, and the datasheet states no internal bias on it. What holds U13 deselected before firmware runs therefore rests on the reset state of U5 P1.02.

The datasheet also requires:
- 1 ms (tPU) from VDD reaching its minimum to the first C̅S̅ low.
- A VDD ramp no faster than 30 µs/V.
- An SCK clock of at most 20 MHz.

11.2.4 Class-D Amplifier U14

AI-Assisted — U14 (MAX98357A) has VDD on U14_7 and U14_8, both on +5v0 and inside the 2.5-5.5 V range. U14_3, U14_11, U14_15 and the exposed pad U14_17 are on GND.

GAIN_SLOT (U14_2) returns to GND through R33 (100kΩ). This selects 15 dB gain in I²S/left-justified mode (Maxim MAX98357A datasheet p.5, source: Tomachie). Tied directly to GND it would give 12 dB, and left open 9 dB.

SD_MODE (U14_4) is driven directly from U5 P0.05:
- Undriven, the internal 100 kΩ pull-down holds shutdown.
- A 2.7 V high is above the B2 trip point (1.5 V maximum), which selects the left channel (p.7).

The risk lies in power sequencing. +5v0 is produced only by U7, while U5 can run from +VBUS through D7 with +5v0 absent. A high on P0.05 in that state exceeds SD_MODE's VDD + 0.3 V absolute maximum (p.4) on an unpowered U14. For the case where VDD can fall below the controlling I/O supply, the datasheet calls for about 2 kΩ in series with SD_MODE (printed p.17). DIN, BCLK and LRCLK are rated 6 V absolute, independent of VDD, and carry no such restriction.

The outputs reach J6 crossed relative to their labels. OUTP (U14_9) runs through L6 to SP-, and OUTN (U14_10) runs through L5 to SP+.

11.2.5 Crystals X1 and X2

AI-Assisted — X1 (ECS-320-8-37B-CKY-TR, 32 MHz, CL 8 pF) connects:
- X1_1 to U5_B24 XC1, with C22 (8pF) to GND.
- X1_3 to U5_A23 XC2, with C21 (8pF) to GND.

Its load-capacitor match is reported in the signal-integrity review. The ±10 ppm tolerance plus ±10 ppm stability, with 1 ppm first-year aging, is far inside the ±0.25 % (2500 ppm) the USB 2.0 specification allows a full-speed device. The KY option is rated -30 to +85 °C (ECS ECX-1637B datasheet p.1, source: Tomachie), narrower at the cold end than the -40 °C rating of U5, U13 and X2.

X2 (NX3215SA-32.768K-STD-MUA-9, CL 9 pF) connects:
- X2_2 to P0.00/XL1, with C23 (8pF) to GND.
- X2_1 to P0.01/XL2, with C24 (8pF) to GND.

Across the crystal, through ground, the two capacitors present CL = 8 × 8 / (8 + 8) = 4 pF plus pin and board stray. Reaching 9 pF therefore needs 5 pF of stray. Nordic's reference fits 12 pF per pin, but the CL of the crystal Nordic drew is not stated, so the stray that reference assumes cannot be derived. This choice cannot be judged against the vendor reference.

X2's 70 kΩ maximum ESR and -40 to +85 °C range are recorded (NDK NX3215SA datasheet p.1, source: Tomachie).

11.2.6 USB ESD Array U15

AI-Assisted — U15 (PRTR5V0U2X) is wired as follows:
- I/O1 (U15_2) on USB-DEVICE-D_P.
- I/O2 (U15_3) on USB-DEVICE-D_N.
- VCC (U15_4) on +VBUS.
- GND (U15_1) on GND.

Its capacitance, clamping level and VCC standoff are settled in the signal-integrity and power reviews. The remaining functional check is the I/O standoff. Its 5.5 V VRWM (Nexperia PRTR5V0U2X datasheet p.3, source: Tomachie) is adequate for the 3.6 V maximum the USB 2.0 specification allows on D+ and D-. The VCC-to-GND diode keeps the lines protected even with VBUS absent.

11.2.7 Wireless MCU U5

AI-Assisted — U5 (nRF52840) has its five VDD pins at 2.7 V. This is inside the 1.7-3.6 V range and above the 1.75 V power-on-reset requirement (Nordic nRF52840 datasheet p.410, Datasheet). VSS, VSS_PA and the centre pad are on GND.

The antenna pin U5_H23 is unconnected, with no feed or matching network. The 2.4 GHz radio is therefore unusable as built, which is evidently a deliberate assembly choice.

The REG1 DC/DC path runs from DCC (U5_B3) through L3 (10uH) and L2 (15nH) to the shared DEC4/DEC6 node. On TDK's INDUCTANCE VS. DC BIAS graph (MLZ1608 datasheet p.3, M100W curve, source: Tomachie), L3 holds:
- About 10.9 µH up to 5 mA.
- 10.5 µH at 30 mA.
- 8.95 µH at 59 mA.

Its saturation current is 90 mA. The REG1 load current is not stated, so the operating point is not fixed.

SWD is wired as follows:
- SWDIO (U5_AC24) to J7_2 and TP21.
- SWDCLK (U5_AA24) to J7_4 and TP22.
- P0.18/RESET to J7_3 and TP23.
- J7_1 on VDD and J7_5 on GND.

J7_6 (SWO) is unconnected. The trace-capable pins P0.07, P0.12 and P1.09 carry the I²S lines to U14, and P0.11 carries BOARD-ID2.

BOARD-ID0 to BOARD-ID2 (P0.09/NFC1, P0.10/NFC2, P0.11) each have only a 100kΩ pull-down. Enabling the 11-16 kΩ internal pull-up would put each pin at 2.33-2.43 V, so they read correctly only with internal pulls disabled. P0.09 and P0.10 additionally need their NFC function released.

GREEN-LED (P1.00) and RED-LED (P1.01) drive the Q10 and Q9 gates with no resistor to GND. The other GPIO-driven FETs have one: Q3, Q4, Q5 and Q8 use R5, R6, R10 and R29 (1MΩ).

Every on-board signal entering U5 comes from a VDD-supplied part or a VDD pull-up, within the VDD + 0.3 V I/O limit.

11.2.8 USB Reference Clock (X1, 32 MHz HFXO)

AI-Assisted — USB timing on U5 comes from the 32 MHz high-frequency crystal oscillator. X1 (ECS-320-8-37B-CKY-TR) is connected to U5_B24 XC1 on NetC22_1 and to U5_A23 XC2 on NetC21_1. Each terminal carries an 8 pF C0G load capacitor to GND: C22 on XC1 and C21 on XC2. The crystal sees 4 pF from the pair in series.

The schematic description gives X1 an 8 pF load capacitance. That implies the design assumes about 4 pF of oscillator-pin and trace stray capacitance.

Nordic's reference circuitry fits 12 pF from each of XC1 and XC2 to GND, which presents 6 pF in series (nRF52840 datasheet page 937, Datasheet). The datasheet does not state the load capacitance of the crystal Nordic drew. The stray capacitance Nordic assumed therefore cannot be derived, and the 4 pF stray this design implies cannot be judged against it. The 8 pF fitted against the 12 pF reference figure is a deviation from an application circuit, not a stated minimum. No datasheet for X1 is in the review data, so its own load-capacitance requirement is taken only from the schematic description.

11.3 Findings

AI-Assisted —

#	Device	Finding	Severity
11.3.1	TLV271CW5-7 (U11)	+IN (U11_3) sits on R26 (100kΩ) / R28 (10kΩ), which gives 0.0909 × VIN: 1.455 V at the 16 V band top and 1.481 V at the 1% corner. U11 is supplied from P0.03 at no more than 2.7 V. The recommended common-mode range is 0 to VDD − 1.35 V = 1.35 V (p.3), so readings above about 14.85 V are taken outside the recommended operating conditions. Change R28 to 6.8kΩ: this places 16 V at 1.02 V and 18 V at 1.15 V, and U5's ADC scaling then has to suit the lower level. Source: Diodes Incorporated TLV271 datasheet (source: Tomachie).	High
11.3.2	MAX98357AETE+T (U14)	SD_MODE (U14_4) is driven directly by U5 P0.05. +5v0 comes only from U7, while U5 can run from +VBUS through D7 with +5v0 absent. A high on P0.05 in that state exceeds SD_MODE's VDD + 0.3 V absolute maximum (p.4). Add about 2 kΩ in series in SP-SD, as the datasheet specifies where VDD can fall below the controlling I/O supply (printed p.17), or hold P0.05 low while +5v0 is absent. Source: Maxim MAX98357A datasheet (source: Tomachie).	Medium
11.3.3	FM25L16B-GTR (U13)	W̅P̅ (U13_3) is held high by R14 (100kΩ) to VDD, and nothing can drive it low. Status-register write protection under WPEN is therefore never available, and the block-protect bits stay writable. Route W̅P̅ to a spare U5 GPIO (P0.16, P0.17, P0.19, P0.26, P1.08, P1.10, P1.12 or P1.14 are unused) with a pull-down, so that firmware raises it only to write the status register. Source: Infineon FM25L16B datasheet p.3 (source: Tomachie).	Low
11.3.4	MAX98357AETE+T (U14)	The speaker outputs are crossed relative to their labels: OUTP (U14_9) reaches SP- (J6_1) through L6, and OUTN (U14_10) reaches SP+ (J6_2) through L5. Rename the nets, or swap the ferrite connections, so that SP+ carries OUTP and speaker polarity is assembled as marked.	Low
11.3.5	NRF52840-QIAA-R (U5), Q9, Q10	GREEN-LED (P1.00) and RED-LED (P1.01) drive the Q10 and Q9 gates with no resistor to GND. The gates float while U5 is in reset or before firmware configures the pins, so D15 and D16 can light unpredictably. Add 1MΩ from each gate to GND, as R5, R6, R10 and R29 already do on Q3, Q4, Q5 and Q8.	Low
11.3.6	TJA1021T/20 (U2)	TXD (U2_4) and SLP_N (U2_2) are driven by U5 P0.29 and P0.31 from VDD = 2.7 V. They need VIH of at least 2 V and VIL of at most 0.8 V (NXP TJA1021 datasheet p.12, source: Tomachie). Check that U5's VOH at 2.7 V, under its drive load, is at least 2 V. The U5 VOH value was not available at report generation time.	Review
11.3.7	TJA1021T/20 (U2)	No external pull-up is fitted on LIN-TX-IN. Datasheet p.8 asks for one to the MCU supply if wake-source recognition on TXD is used. U5's 11-16 kΩ internal pull-up on P0.29 (nRF52840 datasheet p.371) serves the purpose, because TXD's weak pull-down is at least 140 kΩ. Check that firmware enables it before reading TXD in Standby.	Review
11.3.8	TJA1021T/20 (U2)	LIN-IO has no capacitor to GND; only D4 adds 14-17 pF. Datasheet p.16 notes a commander LIN capacitance of typically 1 nF, as specified by the vehicle manufacturer. That figure is an application value, not a minimum. Fit the capacitance the target LIN network specification calls for. Source: NXP TJA1021 datasheet (source: Tomachie).	Review
11.3.9	TLV271CW5-7 (U11)	Supply Current vs. Supply Voltage graph (p.8, TA = 25 °C): the current is 183 µA at 2.5 V, 250 µA at 2.7 V and 291 µA at 3.0 V. At its 2.7 V GPIO supply, U11 operates on the steep part of the curve rather than its plateau. This adds to the power review's P0.03 supply finding. Source: Diodes Incorporated TLV271 datasheet (source: Tomachie).	Review
11.3.10	TLV271CW5-7 (U11)	The datasheet gives the C grade a 0 to +70 °C operating range (p.3), narrower than the -40 to +85 °C of U5, U13 and U14. The design states no maximum ambient. Source: Diodes Incorporated TLV271 datasheet (source: Tomachie).	Review
11.3.11	FM25L16B-GTR (U13)	C̅S̅ (U13_1) has no pull-up, and the datasheet states no internal bias on it. Whether U13 stays deselected before firmware configures the host depends on the reset state of U5 P1.02. The U5 P1.02 reset-state value was not available at report generation time.	Review
11.3.12	FM25L16B-GTR (U13)	At VDD = 2.7 V, U13 needs VIH of at least 1.89 V and VIL of at most 0.81 V. It drives VOH of at least 1.9 V at −2 mA and VOL of at most 0.4 V at 2 mA, with fSCK up to 20 MHz (p.12, p.14). Check that U5's VOH, VIH and VIL on P0.25, P1.02, P1.03 and P1.04 are compatible, and that its SPI clock to U13 is configured at or below 20 MHz. Source: Infineon FM25L16B datasheet (source: Tomachie).	Review
11.3.13	FM25L16B-GTR (U13)	U13 requires 1 ms (tPU) from VDD reaching its minimum to the first C̅S̅ low, and a VDD ramp no faster than 30 µs/V (p.17). Check that U5's first access to U13 occurs at least 1 ms after VDD reaches 2.7 V, and that the VDD ramp from U5's REG0 is no faster than 30 µs/V. Source: Infineon FM25L16B datasheet (source: Tomachie).	Review
11.3.14	MAX98357AETE+T (U14)	GAIN_SLOT (U14_2) returns to GND through R33 (100kΩ), which selects 15 dB gain in I²S/left-justified mode. Tied directly to GND it would give 12 dB, and left open 9 dB (p.5). With SD_MODE driven high at 2.7 V, above the B2 trip point of 1.5 V maximum, the left channel is selected (p.7). Source: Maxim MAX98357A datasheet (source: Tomachie).	Review
11.3.15	MAX98357AETE+T (U14)	DIN (U14_1), BCLK (U14_16) and LRCLK (U14_14) are driven by U5 P0.12, P0.07 and P1.09. They need VIH of at least 1.3 V and VIL of at most 0.6 V (p.6-7), and are rated 6 V absolute, independent of VDD. Check that U5's VOH and VOL at VDD = 2.7 V meet these levels. Source: Maxim MAX98357A datasheet (source: Tomachie).	Review
11.3.16	ECS-320-8-37B-CKY-TR (X1)	The KY option is rated -30 to +85 °C (p.1), narrower at the cold end than U5, U13 and X2 (-40 °C). The design states no minimum ambient. Source: ECS ECX-1637B datasheet (source: Tomachie).	Review
11.3.17	NX3215SA-32.768K-STD-MUA-9 (X2)	C23 and C24 (8pF each) present CL = 8 × 8 / (8 + 8) = 4 pF across the crystal through ground, plus stray. Meeting X2's 9 pF needs 5 pF of stray. Nordic's reference fits 12 pF per pin but does not state the CL of its crystal, so its assumed stray cannot be derived, and this choice cannot be checked against the vendor reference. Sources: NDK NX3215SA datasheet p.1 (source: Tomachie); nRF52840 datasheet p.937, Datasheet.	Review
11.3.18	NRF52840-QIAA-R (U5)	The antenna pin U5_H23 is unconnected, with no feed or matching network. The 2.4 GHz radio is therefore unusable as built.	Review
11.3.19	NRF52840-QIAA-R (U5), L3	REG1 runs from DCC (U5_B3) through L3 (10uH) and L2 (15nH) to the DEC4/DEC6 node. The INDUCTANCE VS. DC BIAS graph (TDK MLZ1608 datasheet p.3, M100W curve, source: Tomachie) gives about 10.9 µH up to 5 mA, 10.5 µH at 30 mA and 8.95 µH at 59 mA, with saturation current at 90 mA. The REG1 load current would have to be stated to fix L3's operating point.	Review
11.3.20	NRF52840-QIAA-R (U5)	BOARD-ID0 to BOARD-ID2 (P0.09/NFC1, P0.10/NFC2, P0.11) each have only a 100kΩ pull-down to GND. With the 11-16 kΩ internal pull-up enabled, each would sit at 2.33-2.43 V and read high. They read correctly only with internal pulls disabled, and P0.09 and P0.10 only once their NFC function is released to GPIO. Source: Nordic nRF52840 datasheet p.371, Datasheet.	Review
11.3.21	TJA1021T/20 (U2)	VBAT (U2_7) is on NetQ1_3, switched from +VIN-PROTECT by Q1 under LIN-PWR (P0.27; R6 1MΩ holds it off at reset). The 9-16 V band is inside the 5.5-27 V static range and the 18 V excursion is inside the 40 V VBAT absolute maximum. GND (U2_5) is on GND. Source: NXP TJA1021 datasheet p.10-11 (source: Tomachie).	✓
11.3.22	TJA1021T/20 (U2)	RXD (U2_1) is open-drain, with R11 (10kΩ) from LIN-RX-OUT to VDD as datasheet p.16 requires. The pull-up current is 0.27 mA against an IOL of at least 1.5 mA at 0.4 V, and the 2.7 V high is within the 6 V absolute maximum. Source: NXP TJA1021 datasheet (source: Tomachie).	✓
11.3.23	TJA1021T/20 (U2)	WAKE_N (U2_3) sits on NetQ5_3. R8 (100kΩ) holds it at the switched VBAT, meeting VIH of at least VBAT − 1 V. Q5 (BSS138K, gate LIN-WAKE with R10 1MΩ pull-down) pulls it below the VIL maximum of VBAT − 3.3 V. Q5 has a maximum Vth of 1.2 V and RDS(on) characterised at 1.8 V and 2.5 V gate drive, so the 2.7 V GPIO enhances it fully. Its 50 V VDS derated 30% (mosfet_vds_pct = 70) permits 35 V, against 16 V applied. Sources: NXP TJA1021 p.12, onsemi BSS138K datasheet p.2 (source: Tomachie).	✓
11.3.24	TJA1021T/20 (U2)	The commander termination runs from INH (U2_8) through Q2, D3 and R7 (1kΩ) to LIN-IO. This matches the 1 kΩ plus series diode the datasheet gives for a commander (p.16). Q3 enables it under LIN-CMDR, and R5 (1MΩ) holds the node as a responder at reset. INH sources about 15.5 mA with LIN-IO held low at 16 V. Against the −50 mA INH absolute maximum, derated 30% (ic_output_current_pct = 70) to 35 mA, this is correctly sized. Source: NXP TJA1021 datasheet p.10 (source: Tomachie).	✓
11.3.25	BSS84-7-F (Q2)	Q2 carries about 15.5 mA, against −130 mA derated 40% (mosfet_id_pct = 60) to 78 mA. VDS is at most 16 V (18 V excursion), against −50 V derated 30% (mosfet_vds_pct = 70) to 35 V. R2 (100kΩ) from gate to source holds it off whenever Q3 is off. Both ratings are correctly sized. The VGS margin is reported in the power review. Source: Diodes Incorporated BSS84 datasheet p.2 (source: Tomachie).	✓
11.3.26	BZX84B16-7-F (D2)	D2 is wired as Q2's gate clamp, with its anode on the gate (NetD2_1) and its cathode on the source (NetD2_3); the orientation is consistent. Its maximum zener voltage of 16.32 V at 5 mA is below Q2's ±20 V VGS rating, judged un-derated, so it bounds the 18 V excursion. The normal-band VGS of 14.57 V is below the 15.68 V minimum, so D2 draws no standing current. Sources: Vishay BZX84B16 datasheet p.3, Diodes Incorporated BSS84 datasheet p.2 (source: Tomachie).	✓
11.3.27	BAS16-7-F (D3)	D3 is the series diode of the LIN commander pull-up: anode on NetD3_1 (Q2 drain), cathode toward R7 and LIN-IO. It blocks LIN-IO from back-feeding INH when U2 is unpowered. VF is at most 855 mV at 10 mA and 1 V at 50 mA, so the forward drop at the 15.3 mA operating point is about 0.9 V. Source: BAS16 datasheet p.3, Datasheet.	✓
11.3.28	TLV271CW5-7 (U11)	OUT (U11_1) and −IN (U11_4) share P0.02, forming a unity-gain follower into U5 AIN0. The output load is U5's pad alone, far below the 100 pF above which a series isolation resistor of at least 20 Ω is needed (p.13). Source: Diodes Incorporated TLV271 datasheet (source: Tomachie).	✓
11.3.29	TLV271CW5-7 (U11)	Q8, and through it Q7, which switches the divider onto +VIN-PROTECT, are gated from the same P0.03 that supplies U11. +IN is therefore not driven while U11 is unpowered, which respects the VDD + 0.2 V input absolute maximum (p.3). Source: Diodes Incorporated TLV271 datasheet (source: Tomachie).	✓
11.3.30	FM25L16B-GTR (U13)	H̅O̅L̅D̅ (U13_7) is pulled to VDD by R38 (100kΩ), meeting the requirement that an unused H̅O̅L̅D̅ be tied to VDD (p.3). The ±1 µA leakage drops at most 0.1 V, leaving the pin well above VIH = 1.89 V. VSS (U13_4) is on GND. Source: Infineon FM25L16B datasheet (source: Tomachie).	✓
11.3.31	FM25L16B-GTR (U13)	The SPI wiring is point-to-point with no direction conflict: FRAM-CLK (P0.25) to C on U13_6, P1.04 to D on U13_5, Q on U13_2 to P1.03, and FRAM-CS (P1.02) to C̅S̅ on U13_1. Source: Infineon FM25L16B datasheet (source: Tomachie).	✓
11.3.32	MAX98357AETE+T (U14)	VDD (U14_7, U14_8) is on +5v0, inside the 2.5-5.5 V range. U14_3, U14_11, U14_15 and EP U14_17 are on GND. Source: Maxim MAX98357A datasheet p.4 (source: Tomachie).	✓
11.3.33	ECS-320-8-37B-CKY-TR (X1)	X1_1 connects to U5_B24 XC1 and X1_3 to U5_A23 XC2, each with an 8pF capacitor to GND (C22, C21); the load match is in the signal-integrity review. Tolerance (±10 ppm) plus stability (±10 ppm), with 1 ppm aging, is far inside the USB 2.0 full-speed ±2500 ppm. Source: ECS ECX-1637B datasheet p.1 (source: Tomachie).	✓
11.3.34	NX3215SA-32.768K-STD-MUA-9 (X2)	X2_2 connects to P0.00/XL1 and X2_1 to P0.01/XL2, each with its load capacitor to GND. X2 has a maximum ESR of 70 kΩ and is rated -40 to +85 °C. Source: NDK NX3215SA datasheet p.1 (source: Tomachie).	✓
11.3.35	PRTR5V0U2X,215 (U15)	The I/O1 and I/O2 standoff (VRWM) is 5.5 V, which is adequate for the 3.6 V maximum the USB 2.0 specification allows on D+ and D-. Source: Nexperia PRTR5V0U2X datasheet p.3 (source: Tomachie).	✓
11.3.36	NRF52840-QIAA-R (U5)	VDD (W1, A22, B1, AD23, AD14) is at 2.7 V, inside the 1.7-3.6 V range and above the 1.75 V power-on-reset requirement. VSS (U5_B7), VSS_PA (U5_F23) and the centre pad are on GND. Source: Nordic nRF52840 datasheet p.410, Datasheet.	✓
11.3.37	NRF52840-QIAA-R (U5)	SWD is wired: SWDIO (U5_AC24) to J7_2 and TP21, SWDCLK (U5_AA24) to J7_4 and TP22, and P0.18/RESET to J7_3 and TP23, with J7_1 on VDD and J7_5 on GND. J7_6 (SWO) is unconnected. The trace pins P0.07 (TRACECLK), P0.12 (TRACEDATA1) and P1.09 (TRACEDATA3) carry I²S to U14, and P0.11 (TRACEDATA2) carries BOARD-ID2. Source: Nordic nRF52840 datasheet.	✓
11.3.38	NRF52840-QIAA-R (U5)	Every on-board signal into U5 comes from a VDD-supplied part (U4, U10, U11, U12, U13) or a VDD pull-up (R11). Each stays within the VDD + 0.3 V = 3.0 V I/O absolute maximum. Source: Nordic nRF52840 datasheet p.411, Datasheet.	✓

11.4 Citations

AI-Assisted —

References
BAS16 (Nexperia) — datasheet www.diodes.com/datasheets/ds12003.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
EEEFK1V (Panasonic Industry) — datasheet, cited pages 1,5 industrial.panasonic.com/cdbs/www-data/pdf/RDE0000/ABA000...
GCJ188R91H104KA01D (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/24e69d76f59b023f447ab5...
GCJ32EC71H106KA01 (Murata) — datasheet www.mouser.com/datasheet/2/281/GCJ32EC71H106KA01_01-19641...
GCM155R71C473KA37 (Murata Manufacturing Co., Ltd.) — datasheet static.chipdip.ru/lib/891/DOC031891133.pdf
GCM155R71H104KE02 (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/b385f789d1f9e1d12e8261...
GCM188R71C105KA64 (Murata) — datasheet www.mouser.com/datasheet/2/281/GCM188R71C105KA64_01-19672...
GCM21BR71A106KE22K (Murata) — datasheet ds.murata.co.jp/simserve/characteristics?ModeType=normal&...
GCM21BR71C475KA73 (Murata Manufacturing Co., Ltd.) — datasheet static6.arrow.com/aropdfconversion/5a59cb646dab411de77815...
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...

12 Designer Annotated Nets

No additional annotations are present beyond those already reported in previous sections.

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J8	USB4145-03-0230-C	J8 (USB4145-03-0230-C): Shell pins share the logic GND net, so the shield-bond strategy is not captured as design intent.	USB Type-C R2.5 §3.2.1 requires the receptacle shell to be connected to the PCB ground plane; a shield net bonded to logic GND through R\|\|C satisfies it and does not leave the shell floating. Assign a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD) so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MΩ \|\| 4.7 nF (≥2 kV) from the shield net to logic GND. IEC 61000-4-2.

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed: 4 connector-facing signal(s). 0 protected, 2 unprotected, 2 to review, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
CC1	J8	No ESD Protection
CC2	J8	No ESD Protection

13.2.2 Protected Signal Nets

Signal Net	Connector	Protection Device	Device Type	Rail Connection	Orientation	Status
USB-DEVICE-D_N	J8			—	—	Review: no transformer on the board between J8 and U15, so the isolation is expected inside J8 (integrated magnetics); J8's datasheet confirms it on the AI run
USB-DEVICE-D_P	J8			—	—	Review: no transformer on the board between J8 and U15, so the isolation is expected inside J8 (integrated magnetics); J8's datasheet confirms it on the AI run

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture: Grounding, Filtering and Shielding

AI-Assisted — The board has one ground domain, GND, and no chassis or earth net is drawn. Every harness return lands on GND: J1_4, J2_4, J3_3, J3_4, J4_4 and J5_3. The J8 shell contacts S1 to S4 also sit directly on GND. This is consistent for a module in a non-conductive housing. With no chassis, ESD current entering any contact flows through the logic ground plane.

Six of the eight ports are solder wire pads (J1 to J6) leading into a vehicle harness. For these, the relevant immunity tests are ISO 10605 discharge and ISO 7637-2 conducted transients, and the relevant emission limits are CISPR 25.

The filtering seen at the ports is limited:
- J6 speaker lines: series ferrites L5 and L6 (MPZ2012S221AT000, 220Ω@100MHz) only.
- J3 and J4 logic lines: 100Ω series resistors (R9, R12, R27, R30) between the clamp and the IC.
- J5 loop line: R32 (100Ω) to U5 P1.13.
- J8 USB pair: no series or common-mode element.

Transient clamps are fitted on every logic line that leaves the board through a wire pad:
- D4 (PESD1IVN24-AX) on LIN-IO.
- D5, D8, D12, D13, D14 (PESD5V0S1BA-115) on NP0-EXT, BTN0-EXT, NP1-EXT, AUX1-EXT and CHG-LOOP.
- U15 on the USB data pair.

The power and speaker contacts carry no clamp. Missing TVS is reported as an observation, not an error.

13.3.2 USB Type-C Receptacle J8

AI-Assisted — J8 is a vertical SMT USB 2.0 Type-C receptacle. It is the board's only consumer-facing, hot-plug cable port and needs IEC 61000-4-2 / ISO 10605 robustness at the contact.

The Type-C grounding facts are as follows:
- GND pins A1, A12, B1 and B12 are hard to GND, which is correct.
- The symbol carries no mid-plate pin.
- The shell contacts S1 to S4 share the logic GND net, so the shield-bond strategy is not captured as design intent.

This review judges J8 at professional level, because an automotive module will be ESD-tested. A shield pour stitched straight into GND is the hobby-level simplification.

U15 sits on USB-DEVICE-D_P (U15_2) and USB-DEVICE-D_N (U15_3), with U15_1 on logic GND. The clamp therefore references the same ground as U5, which is correct. U15_4 sits on +VBUS, so U15's rail diode is the clamp on the J8 VBUS contacts; the power review already settled its standoff. U5 is rated 2 kV HBM and 450 V CDM for the aQFN73 package (Nordic nRF52840 datasheet p.411, Datasheet). These are component-level ratings, so system-level discharge depends on U15.

CC1 and CC2 reach only the 5.1kΩ Rd resistors R37 and R36. No semiconductor sits behind them.

The data pair has no common-mode choke. At full-speed USB this is mainly a CISPR 25 radiated-emission consideration for the attached cable.

13.3.3 LIN and Supply Wire Pads J1, J2, J5

AI-Assisted — J1 and J2 are parallel wire pads that pass the LIN bus, +VIN and GND through the board. LIN-IO connects directly to U2_6, so D4 is the only and last clamp before the transceiver, with no series element between them.

D4's part description gives 24 V working and 42 V clamping. U2 LIN is limited to ±40 V DC. It is also rated ±6 kV IEC 61000-4-2 on its own, and is characterised for ISO 7637 pulses 1, 2a, 3a and 3b through a 1 nF coupling capacitor (NXP TJA1021 datasheet p.10, source: Tomachie). D4's clamping figure is a surge-pulse value, so it cannot be compared directly with the DC limit. The functional review already reports the absent LIN-to-GND capacitor, which also governs emissions.

+VIN enters on J1_1, J2_1 and J5_1 with no transient clamp on that contact. Exposure to ISO 7637-2 and ISO 16750-2 pulses is judged against the withstand ratings the power review lists.

J5_2 CHG-LOOP carries D14 at the pad. R32 (100Ω) then leads to U5 P1.13, and R31 (100kΩ) to P1.15. U5 I/O is limited to VDD + 0.3 V, which is 3.0 V at VDD = 2.7 V. D14 is the last external clamp, and R32 limits pulse current into U5's internal diodes to about (14 V − 3.0 V)/100Ω = 110 mA.

13.3.4 Accessory Ports J3 and J4

AI-Assisted — J3 and J4 are 22 AWG wire pads to external accessories, so they are external and harness-exposed.

The outputs are as follows:
- NP0-EXT (J3_2) and NP1-EXT (J4_2) are driven from U3_4 and U9_4 Y through R9 and R27 (100Ω).
- D5 and D12 sit on the pad side of those resistors.
- U3 and U9 run from +5v0. Their Y output is limited to VCC + 0.5 V, with ±20 mA output clamp current (TI SN74LV1T34 datasheet p.5, Datasheet).
- A 14 V clamp level behind 100Ω drives about (14 V − 5.5 V)/100Ω = 85 mA into the output clamp. That is a pulse figure against a DC limit.

The inputs are as follows:
- BTN0-EXT (J3_5) and AUX1-EXT (J4_3) reach U4_2 and U10_2 A through R12 and R30 (100Ω), with D8 and D13 at the pads.
- These inputs are 5 V tolerant to 7.0 V absolute, with no stated positive clamp to VCC.
- Because of that, a positive transient at the D8 or D13 clamp level reaches the pin with little drop across the resistor.

U3 drives NP0-EXT up to 5.034 V, the top of the +5v0 band. This is above the 5 V working voltage of D5 and D12.

J3_1 and J4_1 bring U1 and U8 OUT straight to the pads with no clamp. U1 and U8 OUT are limited to VIN + 0.3 V and rated 2000 V HBM (Diodes AP22804 datasheet p.3, source: Tomachie). J3_6 places +5v0 on a pad, also with no clamp.

13.3.5 Speaker Output J6 and Debug Pads J7

AI-Assisted — J6 carries the U14 Class D outputs to an off-board speaker through L5 and L6. U14_9 OUTP and U14_10 OUTN are the endpoints. Both are limited to VDD + 0.3 V, about 5.3 V on +5v0 (Maxim MAX98357A datasheet p.4, source: Tomachie).

The beads add 220Ω at 100 MHz in series. No capacitor to GND sits on SP+ or SP-, and the U14 side has no clamp. A bead with no shunt element gives only series attenuation. The speaker harness therefore radiates the switching edges and their harmonics, which is a CISPR 25 radiated-emission risk. The same harness is also an ESD entry path, because nothing clamps the output pins. The functional review already reports the swapped SP+/SP- labelling.

J7 is a TC2030 Tag-Connect footprint carrying SWDIO, SWDCLK, RESET, VDD and GND to U5. It is used only at programming and debug, is not reachable in service, and needs no external ESD protection.

13.4 Observations

AI-Assisted — The port protection is broadly in place. Every external logic line carries a bidirectional TVS at the pad, the LIN line has an automotive-rated clamp, and the USB pair has an array referenced to logic GND. What remains is coordination and robustness, not missing parts.

The PESD5V0S1BA clamps (D5, D8, D12, D13, D14) clamp at 14 V, against IC pins limited to 3.0 V, 5.5 V and 7.0 V. Only 100Ω separates each clamp from its IC, and the input buffers U4 and U10 have no positive clamp of their own to share the energy.

The same 5 V parts sit on wire pads next to +VIN in harnesses where a short to battery is a standard ISO 16750-2 test. The series resistors are on the IC side, so nothing limits the current a 9-16 V short (18 V excursion) drives into the TVS.

Three contacts carry no filtering or clamping:
- J6 speaker outputs
- J3_1 and J4_1 switched 5 V outputs
- J3_6 +5v0

The J8 shell shares the logic GND net with no dedicated shield net. For an automotive product that will be ESD-tested, a dedicated shield net with an R||C bond, placed at the connector, sets where the strike enters the ground plane. In a housing with no chassis, the charge still ends up on the board; the bond changes the entry point and the waveform, not the destination.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J8	Shell contacts share the logic GND net, so the shield-bond strategy is not captured as design intent. Assign a dedicated SHIELD_GND_J8 net so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MOhm \|\| 4.7 nF (>= 2 kV) from SHIELD_GND_J8 to logic GND. USB Type-C R2.5 section 3.2.1; IEC 61000-4-2.	Medium
13.5.2	J8	USB-DEVICE-D_P and USB-DEVICE-D_N run from J8 to U5_AD6 and U5_AD4 with no common-mode filtering. For a cable port on an automotive module, investigate a USB-rated common-mode choke at J8 against CISPR 25 radiated limits.	Review
13.5.3	J1, J2	D4 (PESD1IVN24-AX, 24 V working, 42 V clamping per its part description) is the only clamp on LIN-IO, with no series element before U2_6 LIN. U2 LIN is limited to ±40 V DC and rated ±6 kV IEC 61000-4-2 (NXP TJA1021 datasheet p.10, source: Tomachie). The 42 V figure is a surge-pulse clamping value and the 40 V figure is a DC limiting value, so the two are not directly comparable. Check D4's clamping at the ISO 7637-2 pulse levels against U2's LIN transient ratings.	Review
13.5.4	J1, J2, J5	The +VIN contacts J1_1, J2_1 and J5_1 have no transient clamp; no diode-class part sits on +VIN. The power review reports the C7, Q6 and U7 withstand ratings on this node. ISO 7637-2; ISO 16750-2.	Review
13.5.5	J5	CHG-LOOP (J5_2) has D14 (PESD5V0S1BA-115, 14 V clamping per its part description) at the pad. R32 (100Ω) then leads to U5_A16 P1.13, whose I/O limit is VDD + 0.3 V = 3.0 V (Nordic nRF52840 datasheet p.972, Datasheet). R32 limits pulse current into U5 to about 110 mA. Check this against U5's I/O injection capability, or add a lower-clamping second stage at U5.	Review
13.5.6	J3, J4	D5 and D12 (PESD5V0S1BA-115, 14 V clamping) sit at J3_2 and J4_2. R9 and R27 (100Ω) then lead to U3_4 and U9_4 Y, which are limited to VCC + 0.5 V with ±20 mA output clamp current (TI SN74LV1T34 datasheet p.5, Datasheet). The 14 V clamp behind 100Ω gives about 85 mA. That is a pulse level against a DC clamp-current limit, so the two are not directly comparable. Check the outputs under the clamp's pulse current.	Review
13.5.7	J3, J4	D8 and D13 (PESD5V0S1BA-115, 14 V clamping) sit at J3_5 and J4_3. R12 and R30 (100Ω) then lead to U4_2 and U10_2 A. These inputs are 5 V tolerant to a 7.0 V absolute maximum, with no stated positive clamp to VCC (TI SN74LV1T34 datasheet p.5, Datasheet). The clamp level therefore reaches the pin with little drop. Investigate a lower-clamping TVS, or a larger series resistance with a second clamp at the input.	Review
13.5.8	J3, J4	U3 and U9 drive NP0-EXT and NP1-EXT up to 5.034 V, the top of the +5v0 band. This is above the 5 V working voltage of D5 and D12 (PESD5V0S1BA-115 part description), which places them at the edge of conduction at the high end of the rail.	Review
13.5.9	J3, J4, J5	The PESD5V0S1BA-115 clamps (D5, D8, D12, D13, D14) sit directly on wire pads J3_2, J3_5, J4_2, J4_3 and J5_2, with the 100Ω resistors on the IC side. A harness short to +VIN (9-16 V, 18 V excursion) drives unlimited current into a 5 V working-voltage TVS. Investigate short-to-battery robustness against ISO 16750-2.	Review
13.5.10	J3, J4	J3_1 (+5v0-CH0) and J4_1 (+5v0-CH1) connect U1_1 and U8_1 OUT directly to the pads with no transient clamp. OUT is limited to VIN + 0.3 V and rated 2000 V HBM (Diodes AP22804 datasheet p.3, source: Tomachie). Investigate a 5 V-rated TVS at each pad for harness discharge to ISO 10605.	Review
13.5.11	J3	J3_6 places +5v0 on a pad with no transient clamp; D6, D15 and D16 on +5v0 are a series diode and indicator LEDs, not clamps. The bulk capacitors C12 and C13 (150µF) on +5v0 absorb low-energy discharge. ISO 10605.	Review
13.5.12	J6	SP+ and SP- carry only the series ferrites L5 and L6 (220Ω@100MHz) from U14 OUTN and OUTP, with no capacitor to GND. The speaker harness carries the Class D switching edges. Investigate a small capacitor to GND at each bead's J6 side against CISPR 25 radiated limits.	Review
13.5.13	J6	SP+ (J6_2) and SP- (J6_1) have no transient clamp. U14_9 OUTP and U14_10 OUTN are limited to VDD + 0.3 V (Maxim MAX98357A datasheet p.4, source: Tomachie), with only the beads in series. Investigate a low-capacitance clamp at J6, rated above the 5 V output swing. ISO 10605.	Review
13.5.14	J8	GND pins J8_A1, J8_A12, J8_B1 and J8_B12 are hard to logic GND. The J8 symbol carries no mid-plate pin. USB Type-C R2.5.	✓
13.5.15	J8	U15 I/O pins sit on USB-DEVICE-D_P (U15_2) and USB-DEVICE-D_N (U15_3), with U15_1 on logic GND. The array references the same ground as U5, not a shield net, which is correct. IEC 61000-4-2.	✓
13.5.16	J8	CC1 (J8_A5) and CC2 (J8_B5) reach only the 5.1kΩ Rd resistors R37 and R36 to GND, with no semiconductor endpoint. No clamp is needed on these contacts. USB Type-C R2.5.	✓
13.5.17	J7	J7 (TC2030) is a programming and debug footprint for U5 SWD. It is not reachable in service and needs no external ESD protection.	✓
13.5.18	All	All harness returns (J1_4, J2_4, J3_3, J3_4, J4_4, J5_3) and the J8 shell are on the single GND domain, and no chassis net is drawn. The ground architecture is consistent for a module with no chassis bond.	✓

13.6 Citations

AI-Assisted —

References
BAS16 (Nexperia) — datasheet www.diodes.com/datasheets/ds12003.pdf
BZX84C12 (Diodes Incorporated) — datasheet www.diodes.com/datasheet/download/BZX84C2V4+-+BZX84C51.pdf
nRF52840 (Nordic Semiconductor) — datasheet, cited pages 2 datasheet.lcsc.com/datasheet/pdf/bed1abb9fbc0bd0d38d58863...
SN74LV1T34 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/sn74lv1t34.pdf

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on LSSI buses	Yes	Place test points on every LSSI bus signal (JTAG, SWD, I2C, I3C, MDIO, SPI, QSPI, UART) that has none
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Insert on feedback pins	Yes	Place a test point on each regulator feedback / set net that has none, so its divider can be checked
Insert on power-good nets	No	Place a test point on each used power-good net that has none and no boundary scan
Insert on NVM programming nets	No	Place test points on the nets used to program on-board memory (QSPI, etc.)
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	8
Rails with TPs	7
Rails without TPs	1

1 power rail(s) need test points in the submitted design.

10 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+5v0		TP18	✓
+VBUS		TP1	✓
+VIN		TP27	✓
+VIN-PROTECT		TP5	✓
GND		TP2, TP24, TP25, TP26	✓
NetC10_2		-	NEEDS TP
NetC14_1		TP18 on +5v0, across R15	✓
VDD		TP17	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP28	NetC10_2	cricket-node-hw--top-level_B.SchDoc
TP32	GND	cricket-node-hw--top-level_B.SchDoc
TP33	GND	cricket-node-hw--top-level_B.SchDoc
TP34	GND	cricket-node-hw--top-level_B.SchDoc
TP35	GND	cricket-node-hw--top-level_B.SchDoc
TP36	GND	cricket-node-hw--top-level_B.SchDoc
TP37	GND	cricket-node-hw--top-level_B.SchDoc

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP29	NetD15_C	cricket-node-hw--top-level_B.SchDoc
TP30	NetD16_C	cricket-node-hw--top-level_B.SchDoc
TP31	NetR17_1	cricket-node-hw--top-level_B.SchDoc

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U7	AP64352SP-13	EN	3	tied to VCC - recommend pull-up resistor and test point

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.5 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
SMT_TP-1MM	SMT Testpoint 1MM	18
SMT_TP-1MM-OCTAGON	SMT Testpoint 1MM	2
SMT_TP-1MM-RECT	SMT Testpoint 1MM	2
SMT_TP-1MM-ROUNDED-RECT	SMT Testpoint 1MM	3
SMT_TP-CHAMFERED-RECT	SMT Testpoint 1MM	1
SMT_TP_OBROUND	SMT Testpoint 1MM	1

14.5.1 By Sheet

Test Point	Net Name	Footprint
cricket-node-hw--top-level_B (27 test points)
TP1	+VBUS	SMT_TP-1MM-OCTAGON
TP2	GND	SMT_TP-1MM-OCTAGON
TP3	USB-DEVICE-D_P	SMT_TP-1MM-ROUNDED-RECT
TP4	USB-DEVICE-D_N	SMT_TP-1MM-ROUNDED-RECT
TP5	+VIN-PROTECT	SMT_TP-1MM
TP6	NP0-EXT	SMT_TP-1MM
TP7	BTN0-EXT	SMT_TP-1MM
TP8	+5v0-CH0	SMT_TP-1MM
TP9	P1.06	SMT_TP_OBROUND
TP10	NP1-EXT	SMT_TP-CHAMFERED-RECT
TP11	AUX1-EXT	SMT_TP-1MM
TP12	+5v0-CH1	SMT_TP-1MM
TP13	LIN-IO	SMT_TP-1MM-ROUNDED-RECT
TP14	SP+	SMT_TP-1MM
TP15	SP-	SMT_TP-1MM
TP16	CHG-LOOP	SMT_TP-1MM-RECT
TP17	VDD	SMT_TP-1MM
TP18	+5v0	SMT_TP-1MM-RECT
TP19	P0.13	SMT_TP-1MM
TP20	TEST1	SMT_TP-1MM
TP21	SWDIO	SMT_TP-1MM
TP22	SWDCLK	SMT_TP-1MM
TP23	RESET	SMT_TP-1MM
TP24	GND	SMT_TP-1MM
TP25	GND	SMT_TP-1MM
TP26	GND	SMT_TP-1MM
TP27	+VIN	SMT_TP-1MM

14.5.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP1	+VBUS	cricket-node-hw--top-level_B	SMT_TP-1MM-OCTAGON
TP2	GND	cricket-node-hw--top-level_B	SMT_TP-1MM-OCTAGON
TP3	USB-DEVICE-D_P	cricket-node-hw--top-level_B	SMT_TP-1MM-ROUNDED-RECT
TP4	USB-DEVICE-D_N	cricket-node-hw--top-level_B	SMT_TP-1MM-ROUNDED-RECT
TP5	+VIN-PROTECT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP6	NP0-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP7	BTN0-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP8	+5v0-CH0	cricket-node-hw--top-level_B	SMT_TP-1MM
TP9	P1.06	cricket-node-hw--top-level_B	SMT_TP_OBROUND
TP10	NP1-EXT	cricket-node-hw--top-level_B	SMT_TP-CHAMFERED-RECT
TP11	AUX1-EXT	cricket-node-hw--top-level_B	SMT_TP-1MM
TP12	+5v0-CH1	cricket-node-hw--top-level_B	SMT_TP-1MM
TP13	LIN-IO	cricket-node-hw--top-level_B	SMT_TP-1MM-ROUNDED-RECT
TP14	SP+	cricket-node-hw--top-level_B	SMT_TP-1MM
TP15	SP-	cricket-node-hw--top-level_B	SMT_TP-1MM
TP16	CHG-LOOP	cricket-node-hw--top-level_B	SMT_TP-1MM-RECT
TP17	VDD	cricket-node-hw--top-level_B	SMT_TP-1MM
TP18	+5v0	cricket-node-hw--top-level_B	SMT_TP-1MM-RECT
TP19	P0.13	cricket-node-hw--top-level_B	SMT_TP-1MM
TP20	TEST1	cricket-node-hw--top-level_B	SMT_TP-1MM
TP21	SWDIO	cricket-node-hw--top-level_B	SMT_TP-1MM
TP22	SWDCLK	cricket-node-hw--top-level_B	SMT_TP-1MM
TP23	RESET	cricket-node-hw--top-level_B	SMT_TP-1MM
TP24	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP25	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP26	GND	cricket-node-hw--top-level_B	SMT_TP-1MM
TP27	+VIN	cricket-node-hw--top-level_B	SMT_TP-1MM

14.6 Powered-off Testing

24 nets with test points: 23 pins with opens coverage, 4 pins with partial opens, 197 pins with shorts coverage.

Open pin faults may be masked when two or more IC pins share a net (current flow through one internal pin ESD diode may mask the open on another).

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
C12_1	+5v0	Capacitor	-	●
C13_1	+5v0	Capacitor	-	●
C26_2	+5v0	Capacitor	-	●
C27_2	+5v0	Capacitor	-	●
D6_1	+5v0	Passive	-	●
D15_A	+5v0	Passive	-	●
D16_A	+5v0	Passive	-	●
J3_6	+5v0	Connector	-	●
R15_2	+5v0	Passive	-	●
R16_2	+5v0	Passive	-	●
U1_5	+5v0	IC	-	●
U3_5	+5v0	IC	-	●
U8_5	+5v0	IC	-	●
U9_5	+5v0	IC	-	●
U14_7	+5v0	IC	-	●
U14_8	+5v0	IC	-	●
J3_1	+5v0-CH0	Connector	-	●
U1_1	+5v0-CH0	IC	●	●
J4_1	+5v0-CH1	Connector	-	●
U8_1	+5v0-CH1	IC	●	●
D7_1	+VBUS	Passive	-	●
J8_A4	+VBUS	Connector	-	●
J8_A9	+VBUS	Connector	-	●
J8_B4	+VBUS	Connector	-	●
J8_B9	+VBUS	Connector	-	●
U5_AD2	+VBUS	IC	-	●
U15_4	+VBUS	IC	-	●
J1_1	+VIN	Connector	-	●
J2_1	+VIN	Connector	-	●
J5_1	+VIN	Connector	-	●
Q6_2,4	+VIN	Transistor	-	●
C7_1	+VIN-PROTECT	Capacitor	-	●
C8_1	+VIN-PROTECT	Capacitor	-	●
D1_3	+VIN-PROTECT	Passive	-	●
D9_3	+VIN-PROTECT	Passive	-	●
D11_3	+VIN-PROTECT	Passive	-	●
Q1_2	+VIN-PROTECT	Transistor	-	●
Q6_3	+VIN-PROTECT	Transistor	-	●
Q7_2	+VIN-PROTECT	Transistor	-	●
R1_2	+VIN-PROTECT	Passive	-	●
R24_2	+VIN-PROTECT	Passive	-	●
U7_2	+VIN-PROTECT	IC	-	●
U7_3	+VIN-PROTECT	IC	-	●
D13_2	AUX1-EXT	Passive	●	●
J4_3	AUX1-EXT	Connector	-	●
R30_2	AUX1-EXT	Passive	-	●
D8_2	BTN0-EXT	Passive	●	●
J3_5	BTN0-EXT	Connector	-	●
R12_2	BTN0-EXT	Passive	-	●
D14_2	CHG-LOOP	Passive	●	●
J5_2	CHG-LOOP	Connector	-	●
R31_1	CHG-LOOP	Passive	-	●
R32_2	CHG-LOOP	Passive	-	●
C1_1	GND	Capacitor	-	●
C2_1	GND	Capacitor	-	●
C3_1	GND	Capacitor	-	●
C4_1	GND	Capacitor	-	●
C6_1	GND	Capacitor	-	●
C7_2	GND	Capacitor	-	●
C8_2	GND	Capacitor	-	●
C9_1	GND	Capacitor	-	●
C10_1	GND	Capacitor	-	●
C11_1	GND	Capacitor	-	●
C12_2	GND	Capacitor	-	●
C13_2	GND	Capacitor	-	●
C14_2	GND	Capacitor	-	●
C15_1	GND	Capacitor	-	●
C16_1	GND	Capacitor	-	●
C17_1	GND	Capacitor	-	●
C18_1	GND	Capacitor	-	●
C19_1	GND	Capacitor	-	●
C20_1	GND	Capacitor	-	●
C21_2	GND	Capacitor	-	●
C22_2	GND	Capacitor	-	●
C23_1	GND	Capacitor	-	●
C24_1	GND	Capacitor	-	●
C25_1	GND	Capacitor	-	●
C26_1	GND	Capacitor	-	●
C27_1	GND	Capacitor	-	●
C28_1	GND	Capacitor	-	●
D4_1	GND	Passive	●	●
D5_1	GND	Passive	●	●
D8_1	GND	Passive	●	●
D12_1	GND	Passive	●	●
D13_1	GND	Passive	●	●
D14_1	GND	Passive	●	●
J1_4	GND	Connector	-	●
J2_4	GND	Connector	-	●
J3_3	GND	Connector	-	●
J3_4	GND	Connector	-	●
J4_4	GND	Connector	-	●
J5_3	GND	Connector	-	●
J7_5	GND	Connector	-	●
J8_A1	GND	Connector	-	●
J8_A12	GND	Connector	-	●
J8_B1	GND	Connector	-	●
J8_B12	GND	Connector	-	●
J8_S1	GND	Connector	-	●
J8_S2	GND	Connector	-	●
J8_S3	GND	Connector	-	●
J8_S4	GND	Connector	-	●
Q3_2	GND	Transistor	-	●
Q4_2	GND	Transistor	-	●
Q5_2	GND	Transistor	-	●
Q8_2	GND	Transistor	-	●
Q9_2	GND	Transistor	-	●
Q10_2	GND	Transistor	-	●
R5_1	GND	Passive	●	●
R6_1	GND	Passive	-	●
R10_1	GND	Passive	-	●
R18_2	GND	Passive	-	●
R19_1	GND	Passive	-	●
R20_1	GND	Passive	-	●
R21_1	GND	Passive	-	●
R22_2	GND	Passive	-	●
R23_2	GND	Passive	-	●
R28_2	GND	Passive	-	●
R29_1	GND	Passive	-	●
R33_2	GND	Passive	-	●
R36_1	GND	Passive	-	●
R37_1	GND	Passive	-	●
U1_2	GND	IC	-	●
U2_5	GND	IC	-	●
U3_3	GND	IC	-	●
U4_3	GND	IC	-	●
U5_B7	GND	IC	-	●
U5_F23	GND	IC	-	●
U5_74	GND	IC	-	●
U7_7	GND	IC	-	●
U7_9	GND	IC	-	●
U8_2	GND	IC	-	●
U9_3	GND	IC	-	●
U10_3	GND	IC	-	●
U11_2	GND	IC	-	●
U12_4	GND	IC	-	●
U12_9	GND	IC	-	●
U13_4	GND	IC	-	●
U14_3	GND	IC	-	●
U14_11	GND	IC	-	●
U14_15	GND	IC	-	●
U14_17	GND	IC	-	●
U15_1	GND	IC	-	●
D4_2	LIN-IO	Passive	●	●
J1_3	LIN-IO	Connector	-	●
J2_3	LIN-IO	Connector	-	●
R7_2	LIN-IO	Passive	-	●
U2_6	LIN-IO	IC	●	●
D5_2	NP0-EXT	Passive	●	●
J3_2	NP0-EXT	Connector	-	●
R9_2	NP0-EXT	Passive	-	●
D12_2	NP1-EXT	Passive	●	●
J4_2	NP1-EXT	Connector	-	●
R27_2	NP1-EXT	Passive	-	●
U5_AD8	P0.13	IC	●	●
Q3_1	P1.06	Transistor	-	●
R5_2	P1.06	Passive	●	●
U5_R24	P1.06	IC	●	●
J7_3	RESET	Connector	-	●
U5_AC13	RESET	IC	●	●
J6_2	SP+	Connector	-	●
L5_2	SP+	Passive	-	●
J6_1	SP-	Connector	-	●
L6_2	SP-	Passive	-	●
J7_4	SWDCLK	Connector	-	●
U5_AA24	SWDCLK	IC	●	●
J7_2	SWDIO	Connector	-	●
U5_AC24	SWDIO	IC	●	●
U5_AD10	TEST1	IC	●	●
J8_A7	USB-DEVICE-D_N	Connector	-	●
J8_B7	USB-DEVICE-D_N	Connector	-	●
U5_AD4	USB-DEVICE-D_N	IC	◐	●
U15_3	USB-DEVICE-D_N	IC	◐	●
J8_A6	USB-DEVICE-D_P	Connector	-	●
J8_B6	USB-DEVICE-D_P	Connector	-	●
U5_AD6	USB-DEVICE-D_P	IC	◐	●
U15_2	USB-DEVICE-D_P	IC	◐	●
C1_2	VDD	Capacitor	-	●
C2_2	VDD	Capacitor	-	●
C3_2	VDD	Capacitor	-	●
C4_2	VDD	Capacitor	-	●
C6_2	VDD	Capacitor	-	●
C25_2	VDD	Capacitor	-	●
C28_2	VDD	Capacitor	-	●
J7_1	VDD	Connector	-	●
L1_1	VDD	Passive	-	●
R11_1	VDD	Passive	-	●
R14_2	VDD	Passive	-	●
R38_2	VDD	Passive	-	●
U4_5	VDD	IC	-	●
U5_AD14	VDD	IC	-	●
U5_AD23	VDD	IC	-	●
U5_A22	VDD	IC	-	●
U5_B1	VDD	IC	-	●
U5_W1	VDD	IC	-	●
U10_5	VDD	IC	-	●
U12_8	VDD	IC	-	●
U13_8	VDD	IC	-	●

14.7 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

6 power rail nets with test points: 41 source-path pins (opens + shorts), 117 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
C12_1	+5v0	Sink	-	●
C13_1	+5v0	Sink	-	●
C26_2	+5v0	Sink	-	●
C27_2	+5v0	Sink	-	●
D6_1	+5v0	Sink	-	●
D15_A	+5v0	Sink	-	●
D16_A	+5v0	Sink	-	●
J3_6	+5v0	Sink	-	●
R15_2	+5v0	Sink	-	●
R16_2	+5v0	Sink	-	●
TP18_1	+5v0	Sink	-	●
U1_5	+5v0	Sink	-	●
U3_5	+5v0	Sink	-	●
U8_5	+5v0	Sink	-	●
U9_5	+5v0	Sink	-	●
U14_7	+5v0	Sink	-	●
U14_8	+5v0	Sink	-	●
D7_1	+VBUS	Sink	-	●
J8_A4	+VBUS	Sink	-	●
J8_A9	+VBUS	Sink	-	●
J8_B4	+VBUS	Sink	-	●
J8_B9	+VBUS	Sink	-	●
TP1_1	+VBUS	Sink	-	●
U5_AD2	+VBUS	Sink	-	●
U15_4	+VBUS	Sink	-	●
J1_1	+VIN	Sink	-	●
J2_1	+VIN	Sink	-	●
J5_1	+VIN	Sink	-	●
Q6_2,4	+VIN	Sink	-	●
TP27_1	+VIN	Sink	-	●
C7_1	+VIN-PROTECT	Sink	-	●
C8_1	+VIN-PROTECT	Sink	-	●
D1_3	+VIN-PROTECT	Sink	-	●
D9_3	+VIN-PROTECT	Sink	-	●
D11_3	+VIN-PROTECT	Sink	-	●
Q1_2	+VIN-PROTECT	Sink	-	●
Q6_3	+VIN-PROTECT	Sink	-	●
Q7_2	+VIN-PROTECT	Sink	-	●
R1_2	+VIN-PROTECT	Sink	-	●
R24_2	+VIN-PROTECT	Sink	-	●
TP5_1	+VIN-PROTECT	Sink	-	●
U7_2	+VIN-PROTECT	Sink	-	●
U7_3	+VIN-PROTECT	Sink	-	●
C1_1	GND	Sink	-	●
C2_1	GND	Sink	-	●
C3_1	GND	Sink	-	●
C4_1	GND	Sink	-	●
C6_1	GND	Sink	-	●
C7_2	GND	Sink	-	●
C8_2	GND	Sink	-	●
C9_1	GND	Sink	-	●
C10_1	GND	Sink	-	●
C11_1	GND	Sink	-	●
C12_2	GND	Sink	-	●
C13_2	GND	Sink	-	●
C14_2	GND	Sink	-	●
C15_1	GND	Series (U7 → C15)	●	●
C16_1	GND	Series (U5 → C16)	●	●
C17_1	GND	Series (U5 → C17)	●	●
C18_1	GND	Series (U5 → C18)	●	●
C19_1	GND	Series (U5 → C19)	●	●
C20_1	GND	Series (U5 → C20)	●	●
C21_2	GND	Series (U5 → C21)	●	●
C22_2	GND	Series (U5 → C22)	●	●
C23_1	GND	Series (U5 → C23)	●	●
C24_1	GND	Series (U5 → C24)	●	●
C25_1	GND	Sink	-	●
C26_1	GND	Sink	-	●
C27_1	GND	Sink	-	●
C28_1	GND	Sink	-	●
D4_1	GND	Sink	-	●
D5_1	GND	Sink	-	●
D8_1	GND	Sink	-	●
D12_1	GND	Sink	-	●
D13_1	GND	Sink	-	●
D14_1	GND	Sink	-	●
J1_4	GND	Sink	-	●
J2_4	GND	Sink	-	●
J3_3	GND	Sink	-	●
J3_4	GND	Sink	-	●
J4_4	GND	Sink	-	●
J5_3	GND	Sink	-	●
J7_5	GND	Sink	-	●
J8_A1	GND	Sink	-	●
J8_A12	GND	Sink	-	●
J8_B1	GND	Sink	-	●
J8_B12	GND	Sink	-	●
J8_S1	GND	Sink	-	●
J8_S2	GND	Sink	-	●
J8_S3	GND	Sink	-	●
J8_S4	GND	Sink	-	●
Q3_2	GND	Sink	-	●
Q4_2	GND	Sink	-	●
Q5_2	GND	Sink	-	●
Q8_2	GND	Sink	-	●
Q9_2	GND	Sink	-	●
Q10_2	GND	Sink	-	●
R5_1	GND	Series (U5 → R5)	●	●
R6_1	GND	Series (U5 → R6)	●	●
R10_1	GND	Series (U5 → R10)	●	●
R18_2	GND	Sink	-	●
R19_1	GND	Series (U5 → R19)	●	●
R20_1	GND	Series (U5 → R20)	●	●
R21_1	GND	Series (U5 → R21)	●	●
R22_2	GND	Series (U7 → R22)	●	●
R23_2	GND	Series (U7 → R23)	●	●
R28_2	GND	Series (U11 → R28)	●	●
R29_1	GND	Series (U5 → R29)	●	●
R33_2	GND	Series (U14 → R33)	●	●
R36_1	GND	Sink	-	●
R37_1	GND	Sink	-	●
TP2_1	GND	Sink	-	●
TP24_1	GND	Sink	-	●
TP25_1	GND	Sink	-	●
TP26_1	GND	Sink	-	●
U1_2	GND	Sink	-	●
U2_5	GND	Sink	-	●
U3_3	GND	Sink	-	●
U4_3	GND	Sink	-	●
U5_B7	GND	Series path	●	●
U5_F23	GND	Series path	●	●
U5_74	GND	Series path	●	●
U7_7	GND	Series path	●	●
U7_9	GND	Series path	●	●
U8_2	GND	Sink	-	●
U9_3	GND	Sink	-	●
U10_3	GND	Sink	-	●
U11_2	GND	Series path	●	●
U12_4	GND	Sink	-	●
U12_9	GND	Sink	-	●
U13_4	GND	Sink	-	●
U14_3	GND	Series path	●	●
U14_11	GND	Series path	●	●
U14_15	GND	Series path	●	●
U14_17	GND	Series path	●	●
U15_1	GND	Sink	-	●
C1_2	VDD	Sink	-	●
C2_2	VDD	Sink	-	●
C3_2	VDD	Sink	-	●
C4_2	VDD	Sink	-	●
C6_2	VDD	Sink	-	●
C25_2	VDD	Sink	-	●
C28_2	VDD	Sink	-	●
J7_1	VDD	Sink	-	●
L1_1	VDD	Series (U5 → L1)	●	●
R11_1	VDD	Series (U5 → R11)	●	●
R14_2	VDD	Series (U13 → R14)	●	●
R38_2	VDD	Series (U13 → R38)	●	●
TP17_1	VDD	Sink	-	●
U4_5	VDD	Sink	-	●
U5_AD14	VDD	Series path	●	●
U5_AD23	VDD	Series path	●	●
U5_A22	VDD	Series path	●	●
U5_B1	VDD	Series path	●	●
U5_W1	VDD	Series path	●	●
U10_5	VDD	Sink	-	●
U12_8	VDD	Sink	-	●
U13_8	VDD	Series path	●	●

14.8 Boundary Scan Testability

14.8.1 Test Coverage

Net fault coverage classification for boundary scan testing (BSCAN-Only scenario). Signal nets: 110, BSCAN nets: 0, BSCAN pins: 0 (drivers: 0, observers: 0), Connector nets: 19, Test point nets: 18

Fault Coverage Class Definitions

Fault Coverage Class 1: Full opens and shorts fault coverage on the nets listed in this class.

Fault Coverage Class 2: Shorts fault coverage on the nets listed in this class. Opens coverage is provided on the boundary scan portion of each net through series components.

Fault Coverage Class 3: No opens coverage on the nets listed in this class. Shorts will be detected between the nets listed in this class and the nets listed in the following classes:

Fault Coverage Class 1
Fault Coverage Class 2

Fault Coverage Class 4: Opens will be detected on the nets listed in this class only if they cause a boundary scan input or tester pin to float to a logic state that is different from the net's constant state. Shorts will be detected between the nets listed in this class and the nets listed in the following classes:

Fault Coverage Class 1
Fault Coverage Class 2

Fault Coverage Class 5: The nets listed in this class are the Test Access Port signals (TCK, TMS, TRST, TDI, TDO), boundary scan compliance enable pins, level translators and passives that are connected to the TAP.

Fault Coverage Class 6: No fault coverage on the nets listed in this class.

General Notes

The above discussion about opens coverage does not apply to any connector leads that might be on each net. Opens are not covered on any connector leads unless a tester pin is connected to that lead with a mating connector. Connector leads are listed in the net descriptions and are marked with asterisks (*).

Shorts will never be detected between two nets of any class that are connected together with transparent series components.

Nets that are described as "resistively isolated" may not have the shorts detection described for their class above. This is because these nets are tested through transparent series components whose impedance might be high enough to isolate the effect of a short so that it causes no failure.

Differential nets may not have the shorts detection described for their class above. This is because the redundancy inherent in differential signalling can make some shorts undetectable, such as a short to a logic level between 0 and 1.

Opens coverage on pull-ups and pull-downs is described as "possible" because opens on these leads can be detected only if the affected inputs float to the complement of their pulled state.

Fault Coverage Summary (BSCAN-Only)
Class	Description	Nets
Class 1	Full coverage	0 nets
Class 2	Through series / connector	0 nets
Class 3	No opens, shorts to 1-2	0 nets
Class 4	Pulled nets	0 nets
Class 5	TAP signals	0 nets
Class 6	No coverage	110 nets
Total		110 nets

Coverage Percentages
Metric	BSCAN-Only
Opens Coverage	0.0%
Shorts Coverage	0.0%