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matt-poe-prototype Design Analysis

1 Design Summary

87
out of 100
Design TypeFlat (1 sheets)
Total Components52
Total Pins157
Total Nets34
Total Test Points0
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AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. ECONOMY MODE — review needed: this cost-reduced analysis tier can produce misjudgements compared to standard mode.
Based on user-selected TP insertion settings, 9 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.
The inserted test point count is unusually high because Optical (AOI) and X-ray (AXI) inspection contributes no coverage — none of the footprint names are recognized as IPC-7351B or IPC-7251 compliant. Repair the library footprint names to follow IPC naming and resubmit; the inserted test point count will drop to typical levels.

1.1 Design Overview

AI-Assisted — This design implements a Power-over-Ethernet powered-device (PD) front end feeding an isolated flyback pre-regulator and a downstream synchronous buck point-of-load converter. The board is a single-sheet prototype with no processor, memory, or high-speed digital interface — its function is entirely power conversion and PoE interfacing.

PoE input arrives at connector J2 (a 2x2 header) on nets TR0 through TR3. These feed a full-bridge rectifier built from two TB310S diode arrays (D1, D2), giving polarity-insensitive PoE input handling for both MDI orientations. The rectified input is protected by a SMAJ58A unidirectional TVS (D3) referenced from the input rail to GNDPWR, and is bypassed with 220nF and 100nF ceramic capacitors before reaching U2.

U2 (TPE15017) is an integrated PoE PD interface and isolated flyback DC/DC controller with an integrated hot-swap MOSFET. It performs detection and IEEE 802.3af classification — the CLASS pin resistor value on this board (41.2Ω) corresponds to Class 3 signaling. U2 drives the primary of transformer T1 (EP475SG-10, 2:1:1.1 turns ratio, 37µH primary inductance) in a flyback topology; the secondary is rectified by D4 (SBRT20U60SP5-7 super-barrier rectifier) onto the +12V rail, decoupled with 66.1µF of ceramic capacitance across the rail.

The +12V rail sources U4 (AP62250WU-7), a synchronous buck converter that steps the isolated 12V down to a nominal 5V output (Net-(5V-TP5-Pad1)) through inductor L2 (2.2µH) and 44µF of output ceramic capacitance. The feedback network (R9: 52.3kΩ, R10: 10kΩ) sets a divider ratio of 0.161, which against the AP62250's 0.8V reference yields an output close to 5V, consistent with the rail's "5V" designation.

Test access is provided at GND-TP3, 12V-TP4, 5V-TP5, PG-TP1, and SW-TP2, along with jumper positions JP1-JP4 for configuration or measurement breaks. Ground domains are separated as GND (secondary/output side) and GNDPWR (PoE input/primary side), consistent with the transformer-isolated architecture. Operating temperature capability spans -40°C to +125°C for the PoE controller and -40°C to +85°C for the buck regulator, both suited to the ambient range implied by the surrounding thick-film resistors rated to +155°C.

1.2 Processed Sheets

#Sheet Name
1matt-poe-prototype.kicad_sch

1.3 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint NamingStatus
28 SMT footprints do not follow IPC-7351B naming
1 footprints (connectors, specialty) — compliance unknown
1 footprints could not be classified for inspection

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Value Property Check
TypeCheckCountComponentsStatus
CapacitorsValues in VALUE or Capacitance2C7, C6✓
CapacitorsVALUE holds both the capacitance and a voltage rating (e.g. "0.1uF 50V", "10uF 6.3V"). Tomachie has already separated the two and uses the capacitance as the value, so the analysis and the AI read a clean magnitude and are not misled by the embedded rating — the misinterpretation risk is low. This is a cleanliness note, not a parsing failure: to keep the schematic self-describing and safe for downstream BOM/ICT/AOI tools that read VALUE literally, move the voltage into a dedicated Voltage property. (C3 currently has VALUE="22nF 50V")19C3, C2, C13, C18, C14, C4, C1, C20 (+11 more)
ResistorsValues in VALUE or Resistance10R10, R3, R2, R4, R5, R1, R6, R9 (+2 more)✓
InductorsValues in VALUE or Inductance2L1, L2✓

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

1 unconnected pin(s) found:
1 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.
Refdes_PinPin FunctionPin PropertyDevice TypeNet NameNotes
JP4_22UnknownPZ200V-11-02P+5V

3.2 Implied/Hidden Net Connections

No components with implied/hidden net connections found.

3.3 Open-Collector Pull-up Audit

Examined 0 candidate pin(s) on 0 net(s).

3.4 Diode Polarity / Orientation

Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires that pin 1, the cathode, is on the left with the footprint at zero rotation. Tomachie will call out schematic-symbol problems that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, or a novice may wrongly indict a correct part — keeping consistent is the least-expensive path for everyone who handles the PCB.
DiodeConnectionsOrientationSeverity
D3
SMAJ58A
unidirectional · pin_names		Pin 1 (K): Net-(D3-K)
Pin 2 (A): GNDPWR		Consistent
D4
SBRT20U60SP5-7
array · multi-pin		Pin 1: Net-(D4-Pad1)
Pin 2: Net-(D4-Pad1)
Pin 3: +12V		3-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.Information
D2
TB310S
array · multi-pin		Pin 2 (AC): TR3
Pin 4 (-): GNDPWR
Pin 1 (AC): TR2
Pin 3 (+): Net-(D1-+)		4-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.Information
D1
TB310S
array · multi-pin		Pin 1 (AC): Net-(D1-AC)
Pin 2 (AC): TR1
Pin 3 (+): Net-(D1-+)
Pin 4 (-): GNDPWR		4-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.Information

3.5 Summary

Total NO_ERC markers in design7
Pins needing attention (warnings)1
Pins for information only0

4 Power Overview

Power rails3
Power management sources identified1
Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
RailVoltageSourceConsumers
GND---
GNDPWR---
Net-(5V-TP5-Pad1)-U4
AP62250WU-7		-

5 Connector Pinouts

Total connectors1

5.1 J2 61300421821

J2 - 61300421821 (61300421821)
PinPin NameNetNotes
1Pin_1TR1
2Pin_2TR0
3Pin_3TR3
4Pin_4TR2

6 Indicator Documentation

No indicator devices (LED*, LD*, D* LEDs) found in design.

7 Switch Documentation

No switches or push buttons found in design.

8 Low-Speed Serial Interfaces (LSSI)

No functional interfaces detected with test access.

9 High-Speed Serial Interfaces (HSSI)

No controlled impedance nets detected in design.

10 Memory Interface Analysis

No memory devices with detectable bus interfaces found.

11 Functional Analysis

11 device(s) to review across 2 category(ies)

Device Inventory
RefDesCategoryPart NumberDescriptionInterfacesHSSI
12V-TP4DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
5V-TP5DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
GND-TP3DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
JP1DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
JP2DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
JP3DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
JP4DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
PG-TP1DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
SW-TP2DEVICEPZ200V-11-02P-40℃~+105℃ 1 1.5A 1x2P 2.8mm 250V 2P 2mm 2mm 3.9mm Black Brass Pin Header Through Hole 插件,P=2mm Pin Headers ROHS--
U2DEVICETPE15017Integrated PoE Frontend & DC/DC controller with FETs--
D4Rect.SBRT20U60SP5-720A 320A 400uA 480mV@20A 60V PowerDI-5 Super Barrier Rectifiers (SBR) ROHS -55℃~+150℃--

12 Designer Annotated Nets

No designer-annotated nets found.

13 EMC & ESD Protection Checks

Shielded connectors were not found in this design so EMC checks were not performed.

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

OptionSettingDescription
Test Point Insertion
Insert on power railsYesPlace test points on power rail nets in schematic
Insert on all netsNoExtend TP insertion to signal nets beyond power rails
Exclude HSSI netsYesExclude HSSI/differential pair nets from TP insertion
Exclude DRAM netsYesExclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)YesExclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)NoExclude nets with partial boundary scan opens coverage
Exclude BSCAN shortsNoExclude nets with boundary scan shorts coverage
GND test points6Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ0%Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage0%Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance0.000 ohmLower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance1.000 ohmUpper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
OpticalAOIAutomated Optical Inspection of visible solder joints
AXIYesAutomated X-ray Inspection of hidden solder joints (BGA, QFN)
ATENoneNo automated test equipment
Test Access
JTAG/LSSI ConnectorYesConnector access to JTAG, SPI, I2C buses
IO ConnectorsNoIO connectors available for external stimulus/observation
TP AccessNoneNo physical probe access to test points
LoopbackNoneNo loopback cables
Test Types
Powered-Off Shorts/OpensNoUnpowered shorts and opens detection via probe access
PassivesNoR, C, L value measurement via probe or fixture access
Active AnalogNoVoltage regulator, reference, and op-amp output verification
Non-BSCAN DigitalNoDigital ICs without boundary scan: pin observability analysis
Boundary Scan1149.1IEEE 1149.1-2013 structural boundary scan
LSSINoJTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG FunctionalNoFunctional verification beyond structural scan
Require Rail TPs for Diode TestNoRequire TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices—Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate StimulusNoCount boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default MethodDirectProgram via direct pin access; TPs on flash data/control lines
Environment
Test environmentlabPrototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found5
Rails with TPs0
Rails without TPs5
5 power rail(s) need test points in the submitted design.
9 test point(s) inserted in modified output. Download modified schematics to see placements.
Power Rail Coverage
Net NameAnnotationTest PointStatus
+12V- NEEDS TP
+5V- NEEDS TP
GND- NEEDS TP
GNDPWR- NEEDS TP
Net-(5V-TP5-Pad1)- NEEDS TP
Inserted Test Points (Modified Output)
Test PointNetSheet
TP1+12Vmatt-poe-prototype.kicad_sch
TP2GNDmatt-poe-prototype.kicad_sch
TP3GNDPWRmatt-poe-prototype.kicad_sch
TP4Net-(5V-TP5-Pad1)matt-poe-prototype.kicad_sch
TP5+5Vmatt-poe-prototype.kicad_sch
TP6GNDmatt-poe-prototype.kicad_sch
TP7GNDmatt-poe-prototype.kicad_sch
TP8GNDmatt-poe-prototype.kicad_sch
TP9GNDmatt-poe-prototype.kicad_sch

14.3 Current Test Points

Total test points0
No test points found in design.

14.4 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.5 Inspection

Total: 50 components, 118 of 136 pins with inspection coverage.

14.5.1 AOI

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
FootprintSize (mil)Pkg TypeClassificationMethodCountPinsRefdes
Opens + Shorts (all joints visible)
JLCImport
XFMR_EP13_EP475SG-10SOT (Small Outline Transistor)Designator110T1
0603WAF3303T5EChip PassiveDesignator12R6
CL10B224KA8NNNCChip PassiveDesignator36C1, C2, C8
C_0603_C21122Chip PassiveDesignator12C3
C_0805_C28233Chip PassiveDesignator48C12, C17, C19, C5
C_0805_C377773Chip PassiveDesignator12C4
C_0805_C437557Chip PassiveDesignator12C9
C_1206_C170101Chip PassiveDesignator24C10, C11
C_1210_C778721Chip PassiveDesignator510C14, C15, C16, C20, C21
DFE252012F-100M_P2Chip PassiveDesignator12L1
FRC0603J912_TSChip PassiveDesignator12R4
GCM1885C2A221JA16DChip PassiveDesignator12C13
GRM21BZ71E106KE15LChip PassiveDesignator12C18
L_1210_C18724399Chip PassiveDesignator12L2
R_0603_C21189Chip PassiveDesignator12R3
R_0603_C246850Chip PassiveDesignator12R2
R_0603_C25962Chip PassiveDesignator12R1
R_0603_C4197Chip PassiveDesignator12R7
R_0603_C4211Chip PassiveDesignator12R5
R_0805_C17414Chip PassiveDesignator12R10
R_0805_C17740Chip PassiveDesignator12R9
R_1206_C17903Chip PassiveDesignator12R8
jlcpcbfootprint
C1808Chip PassiveDesignator24C6, C7
JLCImport
ABS_TB310SSOD (Diode Package)Designator28D1, D2
SBRT20U60SP5-7SOD (Diode Package)Designator13D4
SMAJ58A_C19077554SOD (Diode Package)Designator12D3
Subtotal: 38 components, 89 pins
Opens only (leads visible, shorts unreliable)
JLCImport
AP62250WU-7SOIC/SOPDesignator16U4
Subtotal: 1 components, 6 pins
Presence check (manual verification)
Connector_PinSocket_2.54mm
PinSocket_2x02_P2.54mm_VerticalConnectorDesignator14J2
Subtotal: 1 components, 4 pins

14.5.2 AXI

Assumed Classification (Non-IPC Footprints)
Hidden-joint classification inferred from Pkg Type property or designator prefix. Footprint names are not IPC-7351B or IPC-7251.
FootprintSize (mil)Pkg TypeClassificationMethodCountPinsRefdes
MPS
QFN-19_MP8017_MNPQFN/DFN (No-Lead)Footprint119U2
Subtotal: 1 components, 19 pins

14.5.3 Unclassified Components

These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
FootprintSize (mil)Pkg TypeClassificationMethodCountPinsRefdes
JLCImport
PZ200V-11-02PUnclassifiedUnknown91812V-TP4, 5V-TP5, GND-TP3, JP1, JP2, JP3, JP4, PG-TP1 ...+1 more
Subtotal: 9 components, 18 pins

14.6 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.6.1 Fault Coverage Summary

Fault Coverage Summary (138 pins)
Test MethodOpensShorts
X-ray (AXI)0 (0.0%)0 (0.0%)
Optical (AOI)0 (0.0%)0 (0.0%)
Electrical
   Powered-off Testing0 (0.0%)0 (0.0%)
   Boundary Scan0 (0.0%)0 (0.0%)
   LSSI--
   Total19 (13.8%)47 (34.1%)
Total Fault Coverage19 (13.8%)47 (34.1%)
No coverage119 (86.2%)91 (65.9%)

14.6.2 Uncovered Pins (91)

These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
Pin ⇅Net ⇅
T1_1
T1_2
T1_3Net-(U2-SW)
T1_4
T1_5Net-(C11-Pad2)
T1_7
T1_8
T1_9
T1_10Net-(D4-Pad1)
D4_1Net-(D4-Pad1)
D4_2Net-(D4-Pad1)
SW-TP2_2Net-(U2-SW)
SW-TP2_1Net-(U2-SW)
C3_1Net-(C3-Pad1)
JP3_2Net-(U4-VIN)
C2_1Net-(U2-SS)
5V-TP5_2Net-(5V-TP5-Pad1)
5V-TP5_1Net-(5V-TP5-Pad1)
C13_1Net-(C13-Pad1)
U4_2Net-(U4-SW)
U4_3Net-(U4-VIN)
U4_4Net-(U4-FB)
U4_5
U4_6Net-(U4-BST)
L1_2Net-(C11-Pad2)
L1_1Net-(U2-VBUS)
C18_1Net-(U4-VIN)
D2_2TR3
D2_1TR2
D2_3Net-(D1-+)
JP1_2Net-(D1-AC)
JP1_1TR0
D1_1Net-(D1-AC)
D1_2TR1
D1_3Net-(D1-+)
R10_1Net-(U4-FB)
C4_2Net-(U2-VCC)
C1_2Net-(D3-K)
C1_1Net-(U2-CP)
C20_1Net-(5V-TP5-Pad1)
R3_2Net-(U2-M{slash}D)
R2_2Net-(U2-CLASS)
L2_2Net-(5V-TP5-Pad1)
L2_1Net-(U4-SW)
R4_2Net-(U2-FSW)
C12_2Net-(C11-Pad2)
C21_1Net-(5V-TP5-Pad1)
JP4_1Net-(5V-TP5-Pad1)
R5_1Net-(C3-Pad1)
R5_2Net-(U2-COMP)
R1_1Net-(U2-DET)
R1_2Net-(D3-K)
R6_2Net-(U2-VDIODE)
C19_1Net-(U4-SW)
C19_2Net-(U4-BST)
JP2_1Net-(D1-+)
JP2_2Net-(D3-K)
C5_2Net-(D3-K)
D3_1Net-(D3-K)
C9_2Net-(C11-Pad2)
C9_1Net-(U2-SNBR)
U2_14Net-(U2-SW)
U2_19Net-(U2-VBUS)
U2_2Net-(U2-CP)
U2_1Net-(D3-K)
U2_18Net-(U2-VBUS)
U2_17Net-(U2-SNBR)
U2_9Net-(U2-VDIODE)
U2_8Net-(U2-COMP)
U2_5Net-(U2-M{slash}D)
U2_13Net-(U2-BST)
U2_7Net-(U2-SS)
U2_3Net-(U2-DET)
U2_4Net-(U2-CLASS)
U2_10Net-(U2-VCC)
U2_6Net-(U2-FSW)
U2_12Net-(U2-FB)
C11_2Net-(C11-Pad2)
R9_2Net-(5V-TP5-Pad1)
R9_1Net-(U4-FB)
J2_1TR1
J2_3TR3
J2_2TR0
J2_4TR2
C8_1Net-(U2-BST)
C8_2Net-(U2-SW)
R7_2Net-(U2-SW)
R7_1Net-(U2-FB)
R8_1Net-(D4-Pad1)
R8_2Net-(C13-Pad1)
C10_2Net-(U2-VBUS)

14.6.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅Net ⇅E Opens ⇅E Shorts ⇅O Opens ⇅O Shorts ⇅X Opens ⇅X Shorts ⇅
T1_1------
T1_2------
T1_3Net-(U2-SW)------
T1_4------
T1_5Net-(C11-Pad2)------
T1_6GND-●----
T1_7------
T1_8------
T1_9------
T1_10Net-(D4-Pad1)------
D4_1Net-(D4-Pad1)------
D4_2Net-(D4-Pad1)------
D4_3+12V-●----
SW-TP2_2Net-(U2-SW)------
SW-TP2_1Net-(U2-SW)------
C3_2GNDPWR●●----
C3_1Net-(C3-Pad1)------
JP3_1+12V-●----
JP3_2Net-(U4-VIN)------
C7_2GND-●----
C7_1GNDPWR-●----
C2_2GNDPWR●●----
C2_1Net-(U2-SS)------
5V-TP5_2Net-(5V-TP5-Pad1)------
5V-TP5_1Net-(5V-TP5-Pad1)------
C6_1GNDPWR-●----
C6_2GND-●----
C13_1Net-(C13-Pad1)------
C13_2+12V-●----
H2_1GND-●----
U4_1GND●●----
U4_2Net-(U4-SW)------
U4_3Net-(U4-VIN)------
U4_4Net-(U4-FB)------
U4_5------
U4_6Net-(U4-BST)------
L1_2Net-(C11-Pad2)------
L1_1Net-(U2-VBUS)------
12V-TP4_2+12V-●----
12V-TP4_1+12V-●----
C18_2GND●●----
C18_1Net-(U4-VIN)------
D2_2TR3------
D2_4GNDPWR-●----
D2_1TR2------
D2_3Net-(D1-+)------
JP1_2Net-(D1-AC)------
JP1_1TR0------
D1_1Net-(D1-AC)------
D1_2TR1------
D1_3Net-(D1-+)------
D1_4GNDPWR-●----
PG-TP1_1GNDPWR-●----
PG-TP1_2GNDPWR-●----
C14_1+12V-●----
C14_2GND-●----
R10_1Net-(U4-FB)------
R10_2GND●●----
C4_2Net-(U2-VCC)------
C4_1GNDPWR●●----
C1_2Net-(D3-K)------
C1_1Net-(U2-CP)------
C20_2GND●●----
C20_1Net-(5V-TP5-Pad1)------
R3_2Net-(U2-M{slash}D)------
R3_1GNDPWR●●----
R2_2Net-(U2-CLASS)------
R2_1GNDPWR●●----
L2_2Net-(5V-TP5-Pad1)------
L2_1Net-(U4-SW)------
C17_2GND-●----
C17_1+12V-●----
H1_1GND-●----
R4_2Net-(U2-FSW)------
R4_1GNDPWR●●----
C12_1GNDPWR●●----
C12_2Net-(C11-Pad2)------
C16_1+12V-●----
C16_2GND-●----
C21_2GND●●----
C21_1Net-(5V-TP5-Pad1)------
JP4_1Net-(5V-TP5-Pad1)------
JP4_2+5V-●----
R5_1Net-(C3-Pad1)------
R5_2Net-(U2-COMP)------
R1_1Net-(U2-DET)------
R1_2Net-(D3-K)------
C15_1+12V-●----
C15_2GND-●----
R6_1GNDPWR●●----
R6_2Net-(U2-VDIODE)------
C19_1Net-(U4-SW)------
C19_2Net-(U4-BST)------
JP2_1Net-(D1-+)------
JP2_2Net-(D3-K)------
C5_2Net-(D3-K)------
C5_1GNDPWR●●----
D3_1Net-(D3-K)------
D3_2GNDPWR-●----
C9_2Net-(C11-Pad2)------
C9_1Net-(U2-SNBR)------
U2_14Net-(U2-SW)------
U2_19Net-(U2-VBUS)------
U2_2Net-(U2-CP)------
U2_1Net-(D3-K)------
U2_18Net-(U2-VBUS)------
U2_17Net-(U2-SNBR)------
U2_9Net-(U2-VDIODE)------
U2_8Net-(U2-COMP)------
U2_11GNDPWR●●----
U2_5Net-(U2-M{slash}D)------
U2_13Net-(U2-BST)------
U2_7Net-(U2-SS)------
U2_3Net-(U2-DET)------
U2_4Net-(U2-CLASS)------
U2_10Net-(U2-VCC)------
U2_6Net-(U2-FSW)------
U2_12Net-(U2-FB)------
U2_16GNDPWR●●----
U2_15GNDPWR●●----
C11_1GNDPWR●●----
C11_2Net-(C11-Pad2)------
R9_2Net-(5V-TP5-Pad1)------
R9_1Net-(U4-FB)------
J2_1TR1------
J2_3TR3------
J2_2TR0------
J2_4TR2------
C8_1Net-(U2-BST)------
C8_2Net-(U2-SW)------
R7_2Net-(U2-SW)------
R7_1Net-(U2-FB)------
R8_1Net-(D4-Pad1)------
R8_2Net-(C13-Pad1)------
GND-TP3_2GND-●----
GND-TP3_1GND-●----
C10_1GNDPWR●●----
C10_2Net-(U2-VBUS)------

14.7 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.7.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Test MethodPCOLASOpensSolder Quality
Electrical Test34.0%0.0%0.0%0.0%0.0%16.5%14.0%0.0%
Optical Inspection (AOI)0.0%0.0%0.0%0.0%0.0%0.0%0.0%0.0%
X-Ray Inspection (AXI)0.0%0.0%0.0%0.0%0.0%0.0%0.0%0.0%
Combined34.0%0.0%0.0%0.0%0.0%16.5%14.0%0.0%

14.7.2 PCB Device/Pin Count

Devices (PCOLA): 50
Pins (SOQ): 136

14.7.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
DimensionScoreCoverage
PCOLA6800 / 100,0006.8%
SOQ10172 / 100,00010.2%
Combined8486 / 100,0008.5%
Electrical vs Inspection
SourcePCOLA ScoreSOQ Score
Electrical Test6800 / 100,00010172 / 100,000
Optical/X-ray Inspection0 / 100,0000 / 100,000
Combined (max)6800 / 100,00010172 / 100,000

14.7.4 PCOLA (50 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅RefDes ⇅Type / Footprint ⇅Class ⇅P ⇅C ⇅O ⇅L ⇅A ⇅Method ⇅
10%T1EP475SG-10 / XFMR_EP13_EP475SG-10 *Transistor◐○○○○Powered_Off
10%D4SBRT20U60SP5-7 / SBRT20U60SP5-7 *Diode◐○○○○Powered_Off
10%C5100nF 100V / C_0805_C28233 *Capacitor◐○○—○Powered_Off
10%C322nF 50V / C_0603_C21122 *Capacitor◐○○—○Powered_Off
10%JP3PZ200V-11-02P / PZ200V-11-02P *Other◐○○○○Powered_Off
10%C71nF / C1808 *Capacitor◐○○—○Powered_Off
10%C2220nF 25V / CL10B224KA8NNNC *Capacitor◐○○—○Powered_Off
10%D3SMAJ58A / SMAJ58A_C19077554 *Diode◐○○○○Powered_Off
10%C61nF / C1808 *Capacitor◐○○—○Powered_Off
10%C13220pF 100V / GCM1885C2A221JA16D *Capacitor◐○○—○Powered_Off
10%U4AP62250WU-7 / AP62250WU-7 *IC◐○○○○Powered_Off
10%U2TPE15017 / QFN-19_MP8017_MNP *IC◐○○○○Powered_Off
10%12V-TP4PZ200V-11-02P / PZ200V-11-02P *Other◐○○○○Powered_Off
10%C1810uF 25V / GRM21BZ71E106KE15L *Capacitor◐○○—○Powered_Off
10%D2TB310S / ABS_TB310S *Diode◐○○○○Powered_Off
10%C112.2uF 100V / C_1206_C170101 *Capacitor◐○○—○Powered_Off
10%D1TB310S / ABS_TB310S *Diode◐○○○○Powered_Off
10%PG-TP1PZ200V-11-02P / PZ200V-11-02P *Other◐○○○○Powered_Off
10%C1422uF 35V / C_1210_C778721 *Capacitor◐○○—○Powered_Off
10%R1010kΩ / R_0805_C17414 *Resistor◐○○—○Powered_Off
10%C42.2uF 50V / C_0805_C377773 *Capacitor◐○○—○Powered_Off
10%GND-TP3PZ200V-11-02P / PZ200V-11-02P *Other◐○○○○Powered_Off
10%C2022uF 35V / C_1210_C778721 *Capacitor◐○○—○Powered_Off
10%R30Ω / R_0603_C21189 *Resistor◐○○—○Powered_Off
10%R241.2Ω / R_0603_C246850 *Resistor◐○○—○Powered_Off
10%JP4PZ200V-11-02P / PZ200V-11-02P *Other◐○○○○Powered_Off
10%C17100nF 100V / C_0805_C28233 *Capacitor◐○○—○Powered_Off
10%R49.1kΩ / FRC0603J912_TS *Resistor◐○○—○Powered_Off
10%C12100nF 100V / C_0805_C28233 *Capacitor◐○○—○Powered_Off
10%C1622uF 35V / C_1210_C778721 *Capacitor◐○○—○Powered_Off
10%C2122uF 35V / C_1210_C778721 *Capacitor◐○○—○Powered_Off
10%C1522uF 35V / C_1210_C778721 *Capacitor◐○○—○Powered_Off
10%R6330kΩ / 0603WAF3303T5E *Resistor◐○○—○Powered_Off
10%C102.2uF 100V / C_1206_C170101 *Capacitor◐○○—○Powered_Off
0%SW-TP2PZ200V-11-02P / PZ200V-11-02P *Other○○○○○
0%5V-TP5PZ200V-11-02P / PZ200V-11-02P *Other○○○○○
0%L110uH / DFE252012F-100M_P2 *Inductor○○○—○
0%JP1PZ200V-11-02P / PZ200V-11-02P *Other○○○○○
0%C1220nF 25V / CL10B224KA8NNNC *Capacitor○○○—○
0%R53kΩ / R_0603_C4211 *Resistor○○○—○
0%C94.7uF 50V / C_0805_C437557 *Capacitor○○○—○
0%C19100nF 100V / C_0805_C28233 *Capacitor○○○—○
0%R124.9kΩ / R_0603_C25962 *Resistor○○○—○
0%JP2PZ200V-11-02P / PZ200V-11-02P *Other○○○○○
0%J2Conn_02x02_Odd_Even / PinSocket_2x02_P2.54mm_Vertical *Connector○○○—○
0%C8220nF 25V / CL10B224KA8NNNC *Capacitor○○○—○
0%R7240kΩ / R_0603_C4197 *Resistor○○○—○
0%R820Ω / R_1206_C17903 *Resistor○○○—○
0%L22.2uH / L_1210_C18724399 *Inductor○○○—○
0%R952.3kΩ / R_0805_C17740 *Resistor○○○—○

14.7.5 SOQ (136 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅Pin ⇅Net ⇅S ⇅O ⇅Q ⇅
50%C4_1GNDPWR◐●○
50%C2_2GNDPWR◐●○
50%R3_1GNDPWR◐●○
50%C3_2GNDPWR◐●○
50%U4_1GND◐●○
50%C10_1GNDPWR◐●○
50%C18_2GND◐●○
50%R2_1GNDPWR◐●○
50%R10_2GND◐●○
50%C20_2GND◐●○
50%R4_1GNDPWR◐●○
50%C12_1GNDPWR◐●○
50%C21_2GND◐●○
50%U2_11GNDPWR◐●○
50%R6_1GNDPWR◐●○
50%C5_1GNDPWR◐●○
50%C11_1GNDPWR◐●○
50%U2_16GNDPWR◐●○
50%U2_15GNDPWR◐●○
17%C15_1+12V◐○○
17%C7_2GND◐○○
17%C7_1GNDPWR◐○○
17%JP3_1+12V◐○○
17%PG-TP1_2GNDPWR◐○○
17%D2_4GNDPWR◐○○
17%C6_1GNDPWR◐○○
17%C17_2GND◐○○
17%C17_1+12V◐○○
17%C6_2GND◐○○
17%C14_1+12V◐○○
17%C16_1+12V◐○○
17%C16_2GND◐○○
17%C13_2+12V◐○○
17%JP4_2+5V◐○○
17%C14_2GND◐○○
17%T1_6GND◐○○
17%D4_3+12V◐○○
17%D3_2GNDPWR◐○○
17%D1_4GNDPWR◐○○
17%PG-TP1_1GNDPWR◐○○
17%12V-TP4_2+12V◐○○
17%12V-TP4_1+12V◐○○
17%GND-TP3_2GND◐○○
17%GND-TP3_1GND◐○○
17%C15_2GND◐○○
0%U4_3Net-(U4-VIN)○○○
0%U4_4Net-(U4-FB)○○○
0%U4_5○○○
0%U4_6Net-(U4-BST)○○○
0%L1_2Net-(C11-Pad2)○○○
0%L1_1Net-(U2-VBUS)○○○
0%C18_1Net-(U4-VIN)○○○
0%D2_2TR3○○○
0%D2_1TR2○○○
0%D2_3Net-(D1-+)○○○
0%JP1_2Net-(D1-AC)○○○
0%JP1_1TR0○○○
0%D1_1Net-(D1-AC)○○○
0%D1_2TR1○○○
0%D1_3Net-(D1-+)○○○
0%R10_1Net-(U4-FB)○○○
0%C4_2Net-(U2-VCC)○○○
0%C1_2Net-(D3-K)○○○
0%C1_1Net-(U2-CP)○○○
0%C20_1Net-(5V-TP5-Pad1)○○○
0%R3_2Net-(U2-M{slash}D)○○○
0%R2_2Net-(U2-CLASS)○○○
0%L2_2Net-(5V-TP5-Pad1)○○○
0%T1_1○○○
0%T1_2○○○
0%T1_3Net-(U2-SW)○○○
0%R4_2Net-(U2-FSW)○○○
0%T1_4○○○
0%T1_5Net-(C11-Pad2)○○○
0%C12_2Net-(C11-Pad2)○○○
0%T1_7○○○
0%T1_8○○○
0%T1_9○○○
0%C21_1Net-(5V-TP5-Pad1)○○○
0%JP4_1Net-(5V-TP5-Pad1)○○○
0%T1_10Net-(D4-Pad1)○○○
0%R5_1Net-(C3-Pad1)○○○
0%R5_2Net-(U2-COMP)○○○
0%R1_1Net-(U2-DET)○○○
0%R1_2Net-(D3-K)○○○
0%L2_1Net-(U4-SW)○○○
0%D4_1Net-(D4-Pad1)○○○
0%D4_2Net-(D4-Pad1)○○○
0%R6_2Net-(U2-VDIODE)○○○
0%C19_1Net-(U4-SW)○○○
0%C19_2Net-(U4-BST)○○○
0%JP2_1Net-(D1-+)○○○
0%JP2_2Net-(D3-K)○○○
0%C5_2Net-(D3-K)○○○
0%SW-TP2_2Net-(U2-SW)○○○
0%D3_1Net-(D3-K)○○○
0%SW-TP2_1Net-(U2-SW)○○○
0%C9_2Net-(C11-Pad2)○○○
0%C9_1Net-(U2-SNBR)○○○
0%U2_14Net-(U2-SW)○○○
0%U2_19Net-(U2-VBUS)○○○
0%C3_1Net-(C3-Pad1)○○○
0%U2_1Net-(D3-K)○○○
0%U2_18Net-(U2-VBUS)○○○
0%U2_17Net-(U2-SNBR)○○○
0%U2_9Net-(U2-VDIODE)○○○
0%U2_8Net-(U2-COMP)○○○
0%JP3_2Net-(U4-VIN)○○○
0%U2_5Net-(U2-M{slash}D)○○○
0%U2_13Net-(U2-BST)○○○
0%U2_7Net-(U2-SS)○○○
0%U2_3Net-(U2-DET)○○○
0%U2_4Net-(U2-CLASS)○○○
0%U2_10Net-(U2-VCC)○○○
0%U2_6Net-(U2-FSW)○○○
0%U2_12Net-(U2-FB)○○○
0%C2_1Net-(U2-SS)○○○
0%5V-TP5_2Net-(5V-TP5-Pad1)○○○
0%U2_2Net-(U2-CP)○○○
0%C11_2Net-(C11-Pad2)○○○
0%R9_2Net-(5V-TP5-Pad1)○○○
0%R9_1Net-(U4-FB)○○○
0%J2_1TR1○○○
0%J2_3TR3○○○
0%J2_2TR0○○○
0%J2_4TR2○○○
0%C8_1Net-(U2-BST)○○○
0%C8_2Net-(U2-SW)○○○
0%R7_2Net-(U2-SW)○○○
0%R7_1Net-(U2-FB)○○○
0%R8_1Net-(D4-Pad1)○○○
0%R8_2Net-(C13-Pad1)○○○
0%5V-TP5_1Net-(5V-TP5-Pad1)○○○
0%C13_1Net-(C13-Pad1)○○○
0%U4_2Net-(U4-SW)○○○
0%C10_2Net-(U2-VBUS)○○○

14.7.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

MethodPCOLASOpensQ
AOIFullFullFull—PartialPartialPartialPartial
AXI————PartialPartialPartialPartial
JTAG/BSCANFullFullFullPartial—FullFull—
BSCAN_PassivesFullFullFullFull—FullFull—
I2CPartialPartial—Partial—PartialPartial—
SPIPartialPartial—Partial—PartialPartial—
UART———Partial————
Passive_MeasFullFullFullFull—FullFull—
Powered_OffPartial————PartialFull—

15 Component Properties

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
GradeRatingDescription
AExcellentHas Power pins AND properly typed I/O pins (>=90% typed)
BGood>=70% typed OR (>=50% typed AND has Power)
CFairMix of typed and Passive pins (>=40% typed)
DPoorMostly Passive with few typed pins (>=10% typed)
FFailAll pins Passive/Unknown (<10% typed, no ERC)
IC Library Model Grades (sorted worst to best)
RefDesGrdPinsPwrInOutIOOCOEHiZPasPart NumberCreator
U4C606000000AP62250WU-7
U2B1999100000TPE15017

15.1.1 Library Quality Summary

Total ICs evaluated2
Grade A (excellent)0 (0.0%)
Grade B (good)1 (50.0%)
Grade C (fair)1 (50.0%)
Grade D (poor)0 (0.0%)
Grade F (fail)0 (0.0%)
OVERALL LIBRARY QUALITYB (3.40/4.00)

15.2 Component Library Validation

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (4 models)
Library NameIndustry NamePart NumberRefDesPinsDistributionIssues
AP62250WU-7AP62250WU-7-U46?:6 No Power pins - may use separate power symbol; Only 0 pin type used - no electrical differentiation; 100% of pins are Unknown type; Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Unknown, SW=Unknown, VIN=Unknown, BST=Unknown]
EP475SG-10EP475SG-10-T10Manufacturer part-number field 'MPN' = '750311439' conflicts with the part identity 'EP475SG-10' from the Value field. The library part carries disagreeing manufacturer part numbers - one field is stale. Analysis and datasheet lookup use 'EP475SG-10'; correct the library entry so the part number is unambiguous.
TB310STB310S-D1, D20Manufacturer part-number field 'MPN' = 'ABS10' conflicts with the part identity 'TB310S' from the Value field. The library part carries disagreeing manufacturer part numbers - one field is stale. Analysis and datasheet lookup use 'TB310S'; correct the library entry so the part number is unambiguous.
TPE15017TPE15017-U219Pwr:9 O:1 ?:9 47% of pins are Unknown type; Power-named pins not typed as Power - library pin types incomplete; Manufacturer part-number field 'ALTMPN' = 'MP8017GL-Z' conflicts with the part identity 'TPE15017' from the Value field. The library part carries disagreeing manufacturer part numbers - one field is stale. Analysis and datasheet lookup use 'TPE15017'; correct the library entry so the part number is unambiguous. [SW=Unknown]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Shielded Connector Model Quality

Shielded connectors with missing pin names0
All shielded connectors have proper pin names for EMC analysis.

15.4 Footprints and Other Models

Components with model data9
Component Model Assignments
RefDesIndustry NamePinsModel TypeModel
D1TB310S4FootprintJLCImport:ABS_TB310S
D2TB310S4FootprintJLCImport:ABS_TB310S
D4SBRT20U60SP5-73FootprintJLCImport:SBRT20U60SP5-7
H1GND1FootprintMountingHole:MountingHole_2.7mm_M2.5_Pad_TopBottom
H2GND1FootprintMountingHole:MountingHole_2.7mm_M2.5_Pad_TopBottom
J2613004218214FootprintConnector_PinSocket_2.54mm:PinSocket_2x02_P2.54mm_Vertical
T1EP475SG-1010FootprintJLCImport:XFMR_EP13_EP475SG-10
U2TPE1501719FootprintMPS:QFN-19_MP8017_MNP
U4AP62250WU-76FootprintJLCImport:AP62250WU-7

15.5 IC Pin Electrical Properties

Unique IC models2
Total IC instances2
IC Library Models
Industry NameLibrary NameRefDesNotes
AP62250WU-7AP62250WU-7U4
TPE15017TPE15017U2

15.5.1 AP62250WU-7 (AP62250WU-7)

PinPin NameElectricalNotes
1GNDUnknown
2SWUnknown
3VINUnknown
4FBUnknown
5ENUnknown
6BSTUnknown

15.5.2 TPE15017 (TPE15017)

PinPin NameElectricalNotes
1VDDPower In
2CPPower In
3DETUnknown
4CLASSUnknown
5M/DUnknown
6FSWUnknown
7SSUnknown
8COMPOutput
9VDIODEUnknown
10VCCPower In
11AGNDPower In
12FBUnknown
13BSTPower In
14SWUnknown
15PGNDPower In
16PGNDPower In
17SNBRUnknown
18VBUSPower In
19VBUSPower In
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