11-10080yoshi-mainboardA Design Analysis

1 Design Summary

out of 100

Depth of review, as a baseline: 39 verified datasheet parameters applied and 95 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

Design Type	Flat (1 sheets)
Total Components	48
Total Pins	222
Total Nets	35
Total Test Points	0
Not Fitted (DNP)	1

Improve your score:

Improve fault coverage (opens/shorts) +6
Improve JTAG/I2C/SPI bus accessibility +2
Improve schematic library models +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1

Points deducted for open High/Medium AI findings:

0 High, 7 Medium -3.5

AI findings to review:

Power findings — 2 Low, 8 Review
HSSI findings — 2 Medium, 1 Low, 3 Review
Memory findings — 1 Medium, 3 Low, 4 Review
Functional findings — 1 Medium, 3 Review
EMC/ESD findings — 3 Medium, 1 Low, 2 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 7 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — Architecture. The board is a single-sheet, USB Type-C powered motion-sensing module built around an NXP MCXA156VMP Arm Cortex-M microcontroller in a 64-ball LFBGA, offering 1 MB of on-chip flash and 128 KB of SRAM. The MCU is the sole active controller: it hosts the USB device interface, the serial links to both inertial sensors, the quad-SPI link to external NOR flash, and the debug port. The board carries 48 components across 35 nets, with a single mechanical M2.2 mounting provision (M1).

Sensing and memory. Two independent inertial devices are fitted. U2 is an Analog Devices ADXL355 low-noise three-axis MEMS accelerometer in a 14-lead LCC, and U3 is a TDK InvenSense IIM-42352 three-axis industrial accelerometer in a 2.5 x 3.0 mm LGA, operated on this board as a SPI target of the MCU with a dedicated chip select. Per the InvenSense datasheet (page 10), the IIM-42352 provides selectable ±2 g to ±16 g full scale, 16-bit output, 70 µg/√Hz noise density and output data rates to 32 kHz. Non-volatile storage is a Winbond W25Q128JV 128 Mbit serial NOR flash (U6) in an 8-pad WSON, connected as a 4-bit quad-SPI memory to the MCU; the IQ option suffix fixes QE=1 and 25 % default output drive, so quad mode is available without status-register configuration, and the part supports up to 133 MHz at 3.0–3.6 V per the Winbond datasheet.

Interfaces. The board's external interface is a single USB Type-C receptacle (J1, USB4145-03-0230-C) providing bus power, both CC contacts, two USB 2.0 differential pairs and the SBU pair. The MCU's USB full-speed device controller with VBUS detection serves the Type-C data link; a Nexperia PRTR5V0U2X dual-channel rail-to-rail ESD array (U5) is fitted on the connector side. An I2C interface from the MCU is routed to the SBU contacts of J1, making the sideband channel a serviceable configuration/debug bus. A serial-wire debug port on the MCU provides programming and run-control access.

Power. The board runs from two rails. +VBUS enters from the Type-C receptacle's VBUS contacts and spans 8 connection points. The single regulator is U9, a Texas Instruments TPS7A2033DQNR ultra-low-noise, low-IQ LDO in the X2SON (DQN) package, whose OUT pin is the source of the +3v3 rail, distributed to 25 pins. The fixed 3.3 V option is encoded in the part number and matches the rail name. Per the TI datasheet, this device supports 1.6 V to 6.0 V input, 300 mA maximum output, 6.5 µA typical quiescent current and 7 µVRMS output noise at 300 mA — well suited to supplying low-noise MEMS sensor rails. GND is the common return with 44 connections.

Temperature. The narrowest operating window among the fitted devices is −40 °C to +85 °C, set by the W25Q128JV industrial grade and the PRTR5V0U2X. The IIM-42352 is rated −40 °C to +105 °C and the TPS7A2033 to a 125 °C junction temperature, so the board is an industrial-temperature-capable assembly bounded at +85 °C ambient.

1.2 Processed Sheets

#	Sheet Name
1	11-10080__yoshi-mainboard__A.kicad_sch

1.3 Structured DNP (Not Fitted)

Parts marked do-not-populate at the part level, outside of assembly variants. They remain present in the netlist but are not assembled.

Status	RefDes	Part Type	Value	Footprint
DNP	U2	ADXL355BEZ-RL7	ADXL355BEZ-RL7	LCC14P127_600X600X225L91X50N:LCC14P127_600X600X225L91X50N

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
1 of 10 unique footprints are IPC-7351B or IPC-7251	✓
7 SMT footprints do not follow IPC-7351B naming
1 footprints (connectors, specialty) — compliance unknown
1 footprints could not be classified for inspection

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	14	C7, C9, C1, C2, C3, C4, C13, C16 (+6 more)	✓
Resistors	Values in VALUE or Resistance	5	R1, R4, R2, R3, R5	✓

2.1 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the ordering part number. This check decodes the part number and compares the two. Where they disagree both readings are shown and neither is assumed correct - if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose ordering scheme is not recognized are reported as not checked rather than passed.

Part Number	Decoded from Part Number	Stated on Schematic	Count	Components	Status
GCM188R70J225KE22D Manufacturer Part Number / Murata	2.2uF 6.3V +/-10% 0603	2.2µF x4 [C11]	4	C11, C13, C14, C16	✓
ERJ-2RKF5101X Manufacturer Part Number / Panasonic	5.1k +/-1% 0402	5.1kΩ x3 [R1]	3	R1, R2, R5	✓
ERJ-2RKF33R0X Manufacturer Part Number / Panasonic	33R +/-1% 0402	33Ω x2 [R3]	2	R3, R4	✓
GCM188R71C105KA64D Manufacturer Part Number / Murata	1uF 16V +/-10% 0603	1µF x2 [C3]	2	C3, C4	✓
Not cross-checked Capacitors	AC0402KRX7R7BB104	8 part(s) using 1 ordering scheme(s) could not be decoded, so their value, voltage and tolerance were NOT cross-checked against the part number. This is a limit of the check, not a finding against the design.	8	C1, C2, C5, C6, C7, C9, C10, C12

2.2 Derating Check

Derating profile	commercial_default
Maximum ambient	40 °C
Checks performed	4

A part is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Capacitors qualify most often; a resistor or inductor appears under the same conditions. All other derating checks - current, power dissipation, temperature margins, and any check needing an operating point - are provided by the AI analysis within its report sections.

Derating is how much is taken off a part's catalogue rating. What remains is the most of that rating the part may be worked at - a 16 V capacitor derated 15% has a maximum permitted value of 13.6 V - and the part is correctly sized when the voltage its position applies stays within it, taken at the worst case of the rail's stated range. This judges DC working voltage only; ripple and switching transients are not included in the compared value.

6 part(s) sit across a resolved power rail with no stated voltage rating and could not be checked: C1, C2, C5, C6, C7, C9. Record each rating in a Voltage property.

Part Voltage Rating vs Applied Voltage
RefDes	Net Name	Rated Voltage	Max Permitted	Applied Voltage	% of Rating	Derating Applied	Status
C16	+3v3	6.30 V (pn)	5.36 V	3.30 V	52.4%	15% (capacitor_voltage_pct = 85)	✓
C14	+3v3	6.30 V (pn)	5.36 V	3.30 V	52.4%	15% (capacitor_voltage_pct = 85)	✓
C4	+VBUS	16.00 V (pn)	13.60 V	5.00 V	31.2%	15% (capacitor_voltage_pct = 85)	✓
C3	+3v3	16.00 V (pn)	13.60 V	3.30 V	20.6%	15% (capacitor_voltage_pct = 85)	✓

Derating Settings Used in This Analysis
Parameter	Value	Applied
capacitor_voltage_pct	15% (85)	Checked in the table above (4 part(s))
capacitor_aluminum_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_mno2_voltage_pct	50% (50)	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
capacitor_ripple_current_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
capacitor_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_temperature_margin_c	20 °C	Applied by the AI analysis where the rating is in evidence
resistor_power_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
resistor_temperature_margin_c	20 °C	Applied by the AI analysis where the rating is in evidence
regulator_input_voltage_pct	10% (90)	Applied by the AI analysis where the rating is in evidence
regulator_output_current_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
regulator_power_dissipation_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_margin_c	25 °C	Applied by the AI analysis where the rating is in evidence
ic_supply_voltage_absolute_max_pct	15% (85)	Applied by the AI analysis where the rating is in evidence
ic_input_voltage_absolute_max_pct	15% (85)	Applied by the AI analysis where the rating is in evidence
ic_output_current_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
ic_power_dissipation_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_margin_c	25 °C	Applied by the AI analysis where the rating is in evidence
connector_current_per_contact_pct	30% (70)	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
connector_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

28 unconnected pin(s) found:

28 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
U1_A2	P1_5/FREQME_CLK_IN1/LPSPI0_PCS2/LPUART2_TXD/CT1_MAT3/FLEXIO0_D13/A0_21	Passive	MCXA156VMP	Net-(U1C-P1_5/FREQME_CLK_IN1/LPSPI0_PCS2/LPUART2_TXD/CT1_MAT3/FLEXIO0_D13/A0_21)
U1_A3	P1_4/FREQME_CLK_IN0/LPSPI0_PCS3/LPUART2_RXD/CT1_MAT2/FLEXIO0_D12/A0_20	Passive	MCXA156VMP	Net-(U1C-P1_4/FREQME_CLK_IN0/LPSPI0_PCS3/LPUART2_RXD/CT1_MAT2/FLEXIO0_D12/A0_20)
U1_A6	P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT/A0_14	Passive	MCXA156VMP	Net-(U1C-P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT/A0_14)
U1_A9	P3_1/TRIG_IN1/LPUART3_TXD/CT_INP17/PWM0_B0/FLEXIO0_D9/PWM1_X1	Passive	MCXA156VMP	Net-(U1D-P3_1/TRIG_IN1/LPUART3_TXD/CT_INP17/PWM0_B0/FLEXIO0_D9/PWM1_X1)
U1_B6	P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2	Passive	MCXA156VMP	Net-(U1C-P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2)
U1_C3	P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1	Passive	MCXA156VMP	Net-(U1C-P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1)
U1_C5	P0_16/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0	Passive	MCXA156VMP	Net-(U1C-P0_16/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0)
U1_E2	P1_30/TRIG_OUT3/LPI2C0_SDA/CT_INP16/FLEXIO0_D30	Passive	MCXA156VMP	-	No net
U1_E7	P3_27/TRIG_OUT7/LPI2C3_SCL/LPUART4_TXD/CT_INP13/CT3_MAT1/FLEXIO0_D27	Passive	MCXA156VMP	-	No net
U1_F2	P1_31/TRIG_IN4/LPI2C0_SCL/CT_INP17/FLEXIO0_D31	Passive	MCXA156VMP	-	No net
U1_F8	P3_13/LPUART2_CTS_B/LPUART3_RXD/CT1_MAT3/PWM0_X1/FLEXIO0_D21/PWM1_B2	Passive	MCXA156VMP	-	No net
U1_F9	P3_12/LPUART2_RTS_B/LPUART3_TXD/CT1_MAT2/PWM0_X0/FLEXIO0_D20/PWM1_A2	Passive	MCXA156VMP	-	No net
U1_G1	P2_1/TRIG_IN7/LPUART0_TXD/LPUART4_RTS_B/CT_INP17/CT2_MAT1/FLEXIO0_D9/A0_A1	Passive	MCXA156VMP	-	No net
U1_G2	P2_0/TRIG_IN6/LPUART0_RXD/LPUART4_CTS_B/CT_INP16/CT2_MAT0/FLEXIO0_D8/A0_A0	Passive	MCXA156VMP	-	No net
U1_G7	P3_28/TRIG_IN11/LPI2C3_SDA/LPUART4_RXD/CT_INP12/CT3_MAT2/FLEXIO0_D28	Passive	MCXA156VMP	-	No net
U1_G8	P3_14/LPUART2_RXD/LPUART3_CTS_B/CT_INP6/PWM0_X2/FLEXIO0_D22/PWM1_A1	Passive	MCXA156VMP	-	No net
U1_H1	P2_2/TRIG_IN6/LPUART0_RTS_B/LPUART2_TXD/CT_INP12/CT2_MAT2/FLEXIO0_D10/A0_A4/DAC0	Passive	MCXA156VMP	-	No net
U1_H2	P2_5/LPUART2_RTS_B/CT_INP15/CT1_MAT1/FLEXIO0_D13/A1_A1	Passive	MCXA156VMP	-	No net
U1_H3	P2_6/TRIG_OUT4/LPSPI1_PCS1/LPUART4_RXD/CT_INP18/CT1_MAT2/FLEXIO0_D14/A1_A3	Passive	MCXA156VMP	-	No net
U1_H4	P2_7/TRIG_IN5/LPUART4_TXD/CT_INP19/CT1_MAT3/FLEXIO0_D15/A0_A7	Passive	MCXA156VMP	-	No net
U1_H5	P2_15/TRIG_OUT4/LPSPI1_SDI/LPUART1_RTS_B/CT4_MAT3/CT0_MAT2/FLEXIO0_D23/A0_A2	Passive	MCXA156VMP	-	No net
U1_H8	P3_15/LPUART2_TXD/LPUART3_RTS_B/CT_INP7/FLEXIO0_D23/PWM1_B1	Passive	MCXA156VMP	-	No net
U1_H9	P3_29/ISPMODE_N/LPI2C3_HREQ/CT_INP3/CT3_MAT3/FLEXIO0_D29/A1_22	Passive	MCXA156VMP	-	No net
U1_J1	P2_3/TRIG_IN7/LPUART0_CTS_B/LPUART2_RXD/CT_INP13/CT2_MAT3/FLEXIO0_D11/A1_A4	Passive	MCXA156VMP	-	No net
U1_J2	P2_4/LPUART2_CTS_B/CT_INP14/CT1_MAT0/FLEXIO0_D12/A1_A0	Passive	MCXA156VMP	-	No net
U1_J5	P2_13/TRIG_IN8/LPSPI1_SDO/LPUART1_TXD/CT4_MAT1/CT0_MAT1/FLEXIO0_D21/CAN0-TX/A1_A5	Passive	MCXA156VMP	-	No net
U1_J8	P3_31/TRIG_IN10/LPI2C3_SDAS/LPUART4_CTS_B/CT0_MAT3/FLEXIO0_D31/A1_20	Passive	MCXA156VMP	-	No net
U1_J9	P3_30/TRIG_OUT6/LPI2C3_SCLS/LPUART4_RTS_B/CT0_MAT2/FLEXIO0_D30/A1_21	Passive	MCXA156VMP	-	No net

3.2 Implied/Hidden Net Connections

No components with implied/hidden net connections found.

3.3 Open-Collector Pull-up Audit

Examined 0 candidate pin(s) on 0 net(s).

3.4 Summary

Total NO_ERC markers in design	2
Pins needing attention (warnings)	28
Pins for information only	0

4 Power Overview

Power rails	3
Power management sources identified	1

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

+VBUS: 5 V assumed by USB convention, because a USB connector power pin is on this net. A design that negotiates a higher USB Power Delivery voltage must state the rail's actual nominal, minimum and maximum voltage — preferably recorded in the design itself, otherwise entered when prompted before the AI review starts. Until it is stated, the assumed 5 V is taken as the intended level.

Power Rails
Rail	Voltage	Source	Consumers
+VBUS	5.00V	J1 External	U5 (PRTR5V0U2X,215), U9 (TPS7A2033DQNR)
+3v3	3.30V	U9 TPS7A2033DQNR	U1 (MCXA156VMP), U2 (ADXL355BEZ-RL7), U3 (IIM-42352), U6 (W25Q128JVPIQ)
GND	-	J1 External	-

4.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.2.1 Power Tree Overview

AI-Assisted — The board is entirely bus-powered. J1, a GCT USB4145-03-0230-C Type-C receptacle, brings +VBUS onto the board at 5.00 V; both VBUS_A pins (A4, A9) and both VBUS_B pins (B4, B9) are paralleled onto the rail, and all four GND pins plus the four shield tabs (S1-S4) land on GND, which is also the chassis reference through M1. Sink attachment is declared by R2 (5.1 kOhm) from CC1 to GND and R1 (5.1 kOhm) from CC2 to GND, the standard Rd terminations; both CC lines are also observed by the MCU (U1 pins A1 and B1).

+VBUS feeds exactly two devices: U5, the Nexperia PRTR5V0U2X rail-to-rail ESD array whose VCC (pin 4) sits on the rail and whose GND (pin 1) is on GND, and U9, the Texas Instruments TPS7A2033DQNR LDO. There is one conversion stage: U9 IN (pin 4) on +VBUS, OUT (pin 1) on +3v3, and both ground returns (pins 2 and 5) on GND, so every supply- and ground-class terminal of the regulator has a genuine DC path.

+3v3 is the only internal rail and carries the whole load: the NXP MCXA156VMP microcontroller U1 (VDD, VDD_P3, VDD_ANA, VREFH and VDD_USB), the TDK InvenSense IIM-42352 IMU U3 (VDD, VDDIO), the Winbond W25Q128JVPIQ QSPI flash U6 (VCC, plus \WP and \HOLD held high), and the pads of U2 (ADXL355BEZ-RL7), which is marked do-not-install. TP4 gives rail access and TP5 gives ground access. There is no second domain, no load switch and no sequencing logic - a single-rail architecture appropriate to a 48-part sensor mainboard.

4.2.2 TPS7A2033DQNR LDO (U9)

AI-Assisted — The ordering part number fixes the option: the "33" suffix is the 3.3 V fixed-output version (TI TPS7A20 datasheet, page 45), so no feedback divider, SET resistor or NVM programming is involved and the output is 3.30 V within a +/-1.5% tolerance for VOUT >= 1.85 V in the DQN package (page 6). Load and line regulation are 13 mV max and 0.03 %/V typ.

EN (pin 3) is strapped to +VBUS, i.e. to IN. This is the standard self-enabling arrangement: the internal 500 kOhm smart-enable pulldown that would otherwise hold EN low is overridden, and the regulator releases once VIN clears the DQN rising UVLO (1.35 V typ, 1.59 V max) and EN clears VEN_HI = 0.9 V min. Start-up is 750 us typ / 1150 us max to 95% of VOUT. That matters for U3: the IIM-42352 requires a monotonic supply ramp of 0.01 ms to 3 ms measured 10% to 90% (TDK datasheet, page 12), and the LDO's worst-case 1.15 ms soft-start sits inside that window, so the IMU powers up in a defined state without external ramp shaping.

Input bypassing is C4, 1 uF, 16 V X7R 0603, exactly the 1 uF nominal ceramic the datasheet asks for at IN (page 5). Output capacitance on +3v3 totals 6 uF (2 x 2.2 uF, 1 x 1 uF, 6 x 0.1 uF), all X7R ceramic; the stability window is 0.47 uF to 200 uF effective with ESR up to 100 mOhm (page 5). Even allowing DC-bias loss on the 6.3 V 0603 parts at 3.3 V, effective capacitance stays far inside that window, and 0402/0603 X7R ESR is a few tens of milliohms.

The device has no PGOOD or status output, so no open-collector pull-up question arises.

4.2.3 Load Current and Thermal Headroom

AI-Assisted — U9 is rated 300 mA max output with a current limit of 520 mA typ (360 mA min) and 160 mA typ short-circuit current. The +3v3 load is an MCXA156 Cortex-M33 class MCU, a 128 Mbit QSPI flash and one IMU drawing 0.28 mA typ in low-noise 3-axis mode (TDK datasheet, page 11); this is a tens-of-milliamps rail, so the 80% derated ceiling of 240 mA (regulator_output_current_pct = 80) is not approached. The 300 mA part is comfortably oversized for the position - benign margin, not a defect.

Thermal behaviour follows directly. The DQN X2SON package has theta_JA = 166.1 C/W (TI datasheet, page 6). At the dropout of 1.7 V across the pass element and an assumed 100 mA rail draw, dissipation is 0.17 W and the rise is 0.17 W x 166.1 C/W = 28 C, giving Tj = 68 C from the stated 40 C maximum ambient - 57 C below the 125 C operating junction limit and satisfying the 25 C margin required (junction_temperature_margin_C = 25). The same package driven at its full 300 mA capability would dissipate 0.51 W and rise 85 C to Tj = 125 C, which would breach that margin; the loads present do not put it there, but the headroom is set by the tiny package, not by the silicon.

Dropout is not a constraint: 140 mV max at 300 mA for 2.5 V <= VOUT < 5.5 V in the DQN package, against 1.7 V of available headroom from a 5 V bus, so regulation holds even at the low end of the USB VBUS tolerance band.

4.2.4 USB Port Protection and Rail Derating

AI-Assisted — U5 protects the two data lines only: IO1 (pin 2) on USB-DP and IO2 (pin 3) on USB-DM, both of which are the connector-side nets, with R4 and R3 (33 Ohm each) in series to the MCU's USB0_DP and USB0_DM. Placing the array on the connector side of the series resistors is correct - the resistors then add impedance between the clamp and the die. The device is a bidirectional rail-to-rail array (VCL specified at both +2.5 A and -2.2 A, 8/20 us), so neither IO pin has a required orientation.

The clamping figure of 17 V typ at 2.5 A, 8/20 us cannot be closed against the MCXA156 USB pin ratings, because no transient (8/20 us or IEC 61000-4-2) withstand figure for those pins is available here; comparing a surge clamp voltage against a DC absolute-maximum is not a valid comparison, so this is reported as an open item rather than a protection gap. The array itself is rated +/-8 kV IEC 61000-4-2 contact.

On the standoff side, the PRTR5V0U2X is a 5.5 V max working-voltage part and its VCC pin sits on +VBUS. A USB Type-C sink must tolerate 5.5 V on VBUS, which equals - and does not exceed - the standoff, so the part does not conduct in normal operation but has no margin above the top of the bus tolerance band.

+VBUS carries no fuse, no series protection and no rail-level TVS between J1 and the two devices on it. On a bus-powered sink the host or hub supplies the current limit, so this is a documented architectural dependency rather than a board fault; note that any VBUS transient reaches U9 IN and U5 VCC unattenuated apart from C4.

4.3 Observations

AI-Assisted — Rail voltage ratings all pass. C4 is a 16 V part; derated 15% (capacitor_voltage_pct = 85) its maximum permitted value is 13.6 V, and 5 V - 5.5 V at the top of the Type-C band - is applied to it: correctly sized, though a 16 V part is more than this position asks for and is noted only as benign margin. C3 is likewise a 16 V part permitting 13.6 V derated against 3.3 V applied. C14 and C16 are 6.3 V parts; derated 15% they permit 5.355 V against 3.3 V applied - correctly sized, with the caveat that a 6.3 V 0603 X7R at 3.3 V bias gives up a substantial fraction of its nominal value, which the 6 uF rail total absorbs. C1, C2, C5, C6, C7, C9 and C10-C13 carry no voltage rating in the schematic, and R5, R1, R2, R3 and R4 state a package power class rather than a numeric wattage; these ratings are simply absent from the drawing and cannot be weighed, which is a documentation gap, not a defect. Where a rating is known only from the part number (C3, C4, C14, C16), it should also appear in a named Voltage property so BOM and test tools read it.

U2 (ADXL355BEZ-RL7) is do-not-install, yet its two internal-regulator bypass groups remain fitted: C10 (0,1 uF) and C11 (2,2 uF) on Net-(U2-V1P8ANA), C12 (0,1 uF) and C13 (2,2 uF) on Net-(U2-V1P8DIG). With the device absent these four capacitors sit on nets whose only other member is an unpopulated pad - harmless electrically, but they should be moved into the same install variant as U2 through the eCAD variant mechanism so the assembly and test netlists agree.

The MCU's ADC reference is taken straight off the rail: VREFH (pin F4) on +3v3 and VREFL (pin E4) on GND, with no dedicated reference filter. The chosen LDO makes that defensible - 7 uVRMS output noise over 10 Hz to 100 kHz at VOUT = 2.8 V, 300 mA, and PSRR of 95 dB at 1 kHz falling to 60 dB at 100 kHz (TI datasheet, page 7) - but any ADC accuracy requirement will depend on rail-local layout, since there is no series element separating the analog reference from the digital loads.

Twenty-one MCU port pins are unconnected in the schematic, and U3 pins 10 and 11 (RESV) are intentionally left open, which is consistent with the IIM-42352 pin table. No rail on this design is left without an identified source.

4.4 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.4.1	J1 (USB4145-03-0230-C)	+VBUS	No fuse, series element or rail-level TVS between the connector and U9 IN / U5 VCC; bus-powered sink relies on the host or hub current limit - architectural dependency to be recorded, not a board fault.	Low
4.4.2	U2 (ADXL355BEZ-RL7)	+3v3	Device marked do-not-install while its bypass capacitors C10 (0,1 uF), C11 (2,2 uF) on Net-(U2-V1P8ANA) and C12 (0,1 uF), C13 (2,2 uF) on Net-(U2-V1P8DIG) remain fitted onto otherwise dead nets; express the option through the eCAD variant feature so assembly and test netlists agree.	Low
4.4.3	U9 (TPS7A2033DQNR)	+3v3	300 mA rating against a load of one MCU, one QSPI flash and a 0,28 mA IMU; the 80% derated ceiling of 240 mA is not approached - benign capability margin, no change recommended.	Review
4.4.4	U9 (TPS7A2033DQNR)	+3v3	theta_JA = 166,1 C/W (TI datasheet, p.6): at 1,7 V dropout and 100 mA the rise is 0,17 W x 166,1 = 28 C, Tj = 68 C from 40 C ambient, 57 C below the 125 C limit. At the full 300 mA capability the rise would be 85 C and the 25 C junction margin would be lost - headroom is package-limited.	Review
4.4.5	U5 (PRTR5V0U2X,215)	USB-DP / USB-DM	Clamping 17 V typ at 2,5 A, 8/20 us cannot be compared with the MCXA156 USB pin limits: no 8/20 us or IEC 61000-4-2 transient withstand figure for those pins is available, so the protection margin cannot be closed on this data.	Review
4.4.6	U5 (PRTR5V0U2X,215)	+VBUS	Standoff (max working) voltage 5,5 V with VCC on +VBUS; a Type-C sink must tolerate 5,5 V, which equals the standoff - no margin above the top of the bus tolerance band.	Review
4.4.7	U5 (PRTR5V0U2X,215)	+VBUS	Nexperia datasheet rev. v.4 (2023-04-01) states the product moved to non-automotive qualification; acceptable for a commercial board, relevant only if automotive qualification is later required.	Review
4.4.8	C1, C2, C5, C6, C7, C9, C10-C13	+3v3 / U2 internal rails	Voltage rating not stated in the schematic data for these capacitors; ratings for C3, C4, C14 and C16 are known only from the part number and should also be carried in a named Voltage property for BOM and test tools.	Review
4.4.9	R1-R5	+3v3 / CC / USB	Power dissipation stated only as a package class, with no numeric wattage property, so the 40% power derating cannot be applied numerically; currents in these positions are milliamp-scale.	Review
4.4.10	U1 (MCXA156VMP)	+3v3	VREFH tied to +3v3 and VREFL to GND with no dedicated reference filtering; acceptable given 7 uVRMS LDO noise and 95 dB PSRR at 1 kHz, but ADC accuracy will hinge on rail-local layout (TI TPS7A20 datasheet, p.7).	Review
4.4.11	U9 (TPS7A2033DQNR)	+VBUS / +3v3	Fixed 3.3 V option selected by the part number suffix (TI TPS7A20 datasheet, p.45); IN, OUT and both GND pins (2, 5) have verified DC paths to +VBUS, +3v3 and GND.	✓
4.4.12	U9 (TPS7A2033DQNR)	+3v3	Output capacitance 6 uF total X7R ceramic against the required 0,47 uF to 200 uF effective window, ESR limit 100 mOhm (TI datasheet, p.5) - stable with margin even after DC-bias loss.	✓
4.4.13	U9 (TPS7A2033DQNR)	+VBUS	Input bypass C4 = 1 uF ceramic matches the 1 uF nominal IN capacitor required (TI datasheet, p.5); one leg on GND.	✓
4.4.14	U9 (TPS7A2033DQNR)	+VBUS	EN strapped to IN: the internal 500 kOhm smart-enable pulldown is overridden and the rail self-enables above UVLO 1,35 V typ and VEN_HI 0,9 V min - valid auto-enable arrangement, reviewed and accepted (TI datasheet, p.7).	✓
4.4.15	U9 (TPS7A2033DQNR)	+3v3	Start-up 750 us typ / 1150 us max sits inside the IIM-42352 monotonic ramp window of 0,01 ms to 3 ms (TDK datasheet, p.12) - power-on state of U3 is defined.	✓
4.4.16	U9 (TPS7A2033DQNR)	+VBUS	Recommended VIN 1,6 V to 6,0 V judged un-derated and abs-max 6,5 V derated 10% (regulator_input_voltage_pct = 90) permits 5,85 V; 5,5 V at the top of the Type-C band is applied - correctly rated.	✓
4.4.17	U9 (TPS7A2033DQNR)	+3v3	Dropout 140 mV max at 300 mA for 2,5 V <= VOUT < 5,5 V, DQN package, against 1,7 V available headroom - regulation maintained across the USB VBUS tolerance band.	✓
4.4.18	U5 (PRTR5V0U2X,215)	USB-DP / USB-DM	ESD array placed on the connector side of the 33 Ohm series resistors R3/R4, bidirectional topology confirmed by clamping specified at both +2,5 A and -2,2 A - no orientation requirement, correct placement.	✓
4.4.19	J1 (USB4145-03-0230-C)	CC1 / CC2	R2 (5,1 kOhm) from CC1 to GND and R1 (5,1 kOhm) from CC2 to GND provide the Rd sink terminations on both CC lines, each also monitored by U1.	✓
4.4.20	C4	+VBUS	16 V part; derated 15% (capacitor_voltage_pct = 85) the maximum permitted value is 13,6 V and 5,5 V worst case is applied - correctly sized, rating well beyond what the position asks.	✓
4.4.21	C3	+3v3	16 V part; derated 15% permits 13,6 V, 3,3 V applied - correctly sized; a 16 V rating is more than this position needs but is the smallest practical stocking class.	✓
4.4.22	C14 / C16	+3v3	6,3 V parts; derated 15% the maximum permitted value is 5,355 V and 3,3 V is applied - correctly sized, though DC bias at 3,3 V removes a significant share of the nominal 2,2 uF.	✓
4.4.23	U3 (IIM-42352)	+3v3	VDD and VDDIO operating range 1,71 V to 3,6 V (TDK datasheet, p.11); 3,3 V applied - within the recommended range, judged un-derated. Abs-max 4 V.	✓
4.4.24	U1 (MCXA156VMP)	+3v3	Five supply pins (VDD, VDD_P3, VDD_ANA, VREFH, VDD_USB) share the rail's 6 uF of bypassing; per-pin placement is a layout item, capacitor count and mix are appropriate at schematic stage.	✓
4.4.25	U9 (TPS7A2033DQNR)	+3v3	No PGOOD or status output on this device, so no open-collector pull-up or status-monitoring arrangement applies; rail presence is probeable at TP4 with ground at TP5.	✓

4.5 Citations

AI-Assisted —

References
IIM-42352 (InvenSense, a TDK Group Company) — datasheet, cited pages 1,18 product.tdk.com/system/files/dam/doc/product/sensor/morti...
PRTR5V0U2X (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf
TPS7A2033 (Texas Instruments) — datasheet, cited pages 1,3,4,5,46 www.ti.com/lit/ds/symlink/tps7a20.pdf

5 Connector Pinouts

Total connectors

5.1 J1 USB4145-03-0230-C

J1 - USB4145-03-0230-C
Pin	Pin Name	Net	Notes
A1	GND_A	GND
A4	VBUS_A	+VBUS
A5	CC1	CC1
A6	DP1	USB-DP
A7	DN1	USB-DM
A8	SBU1	SBU1
A9	VBUS_A	+VBUS
A12	GND_A	GND
B1	GND_B	GND
B4	VBUS_B	+VBUS
B5	CC2	CC2
B6	DP2	USB-DP
B7	DN2	USB-DM
B8	SBU2	SBU2
B9	VBUS_B	+VBUS
B12	GND_B	GND
S1	SHIELD	GND
S2	SHIELD	GND
S3	SHIELD	GND
S4	SHIELD	GND

6 Indicator Documentation

No indicator devices (LED*, LD*, D* LEDs) found in design.

7 Switch Documentation

No switches or push buttons found in design.

8 Low-Speed Serial Interfaces (LSSI)

Detected: 1 I2C, 2 SPI, 1 SWD | 1 partial

8.1 I2C

I2C: U1
Topology: U1 » Targets (J1)
Signal	Net Name	Connector	Test Point	Target Pin
SCL (needs pull-up)	SBU2	J1_B8	(none)	U1_C2 (P1_9/FREQME_CLK_IN1/LPUART1_TXD/LPI2C2_SCL/CT_INP9/CT0_MAT3/FLEXIO0_D17)
SDA (needs pull-up)	SBU1	J1_A8	(none)	U1_B2 (P1_8/FREQME_CLK_IN0/LPUART1_RXD/LPI2C2_SDA/CT_INP8/CT0_MAT2/FLEXIO0_D16)
Controller	Industry Type	Description
U1	MCXA156VMP	ARM Microcontrollers - MCU MCXA18, 1MB Flash, 128KB RAM, 64BGA

I2C Pull-up Check
Net	Component	Status
SBU1		Pull-up not found on SBU1. The bus driver could not be identified on this board, and pull-ups are conventionally placed at the driver. Review: confirm the SDA pull-up is provided by the driver (internal to the driver IC or on the driving assembly).	✓
SBU2		Pull-up not found on SBU2. The bus driver could not be identified on this board, and pull-ups are conventionally placed at the driver. Review: confirm the SCL pull-up is provided by the driver (internal to the driver IC or on the driving assembly).	✓

8.2 SPI

SPI [ACCEL]: U1 -> U3
Topology: U1 » Targets (U3)
Signal	Net Name	Connector	Test Point	Target Pin
MOSI	ACCEL-MOSI	(none)	(none)	U3_14 (AP-SDA/AP-SDIO/AP-SDI)
MISO	ACCEL-MISO	(none)	(none)	U3_1 (AP-SDO/AP-AD0)
SCK	ACCEL-SCK	(none)	(none)	U3_13 (AP-SCL/AP-SCLK)
CS	ACCEL-CS	(none)	(none)	U3_12 (AP-CS)
Target	CS Net	Industry Type	Description
U3	ACCEL-CS (12 AP-CS)	IIM-42352	COMPACT, LOW POWER 3-AXIS INDUST
Controller	Industry Type	Description
U1	MCXA156VMP	ARM Microcontrollers - MCU MCXA18, 1MB Flash, 128KB RAM, 64BGA

SPI [FLASH]: U1
Topology: U1 » Targets ()
Signal	Net Name	Connector	Test Point
MOSI	FLASH-MOSI	(none)	(none)
MISO	FLASH-MISO	(none)	(none)
SCK	FLASH-SCLK	(none)	(none)
CS	FLASH-CS	(none)	(none)
Controller	Industry Type	Description
U1	MCXA156VMP	ARM Microcontrollers - MCU MCXA18, 1MB Flash, 128KB RAM, 64BGA

8.3 SWD

SWD -> U1
Topology: Access (TP1, TP2) » Targets (U1)
Signal	Net Name	Connector	Test Point	Target Pin
SWCLK	Net-(U1B-SWCLK/P0_1)	(none)	TP1_1	U1_B7 (SWCLK/P0_1)
SWDIO	Net-(U1B-SWDIO/P0_0)	(none)	TP2_1	U1_B8 (SWDIO/P0_0)
NRST	Net-(U1B-P1_29/RESET_B/SPC_LPREQ)	(none)	TP3_1	U1_E1 (P1_29/RESET_B/SPC_LPREQ)
Target	Industry Type	Description
U1	MCXA156VMP	ARM Microcontrollers - MCU MCXA18, 1MB Flash, 128KB RAM, 64BGA

8.4 LSSI DFT Analysis

10 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
SCL	SBU2	J1_B8	I2C
SDA	SBU1	J1_A8	I2C
CS	ACCEL-CS	(none)	SPI -> U3
MISO	ACCEL-MISO	(none)	SPI -> U3
MOSI	ACCEL-MOSI	(none)	SPI -> U3
SCK	ACCEL-SCK	(none)	SPI -> U3
CS	FLASH-CS	(none)	SPI
MISO	FLASH-MISO	(none)	SPI
MOSI	FLASH-MOSI	(none)	SPI
SCK	FLASH-SCLK	(none)	SPI

9 High-Speed Serial Interfaces (HSSI)

2 differential pair(s)

Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.

1 USB differential pair(s) have no controlled-impedance net class assigned. Assign a 90 Ohm differential net class so the impedance intent carries into PCB layout and length tuning.

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 2 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
USB-DM	USB
USB-DP	USB

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Interface on the Type-C Receptacle J1

AI-Assisted — The only high-speed serial interface on the board is a single USB 2.0 link between the MCXA156 (U1) on-die USB transceiver and the GCT USB4145-03-0230-C Type-C receptacle J1. The pair runs U1 pin J7 (USB0_DP) through R4 (33 ohm) to net USB-DP and J1 pins A6/DP1 and B6/DP2, and U1 pin H7 (USB0_DM) through R3 (33 ohm) to net USB-DM and J1 pins A7/DN1 and B7/DN2. Tying the A- and B-side D+/D- contacts together at the receptacle is the required arrangement for a USB 2.0-only Type-C receptacle and gives correct cable-flip operation. J1 exposes only the 16 contacts of a USB 2.0 Type-C receptacle - no SSTX/SSRX contacts appear in the design - so there are no SuperSpeed lanes to evaluate and no 5 Gbit/s connector-launch concerns. USB 2.0 is a DC-coupled interface per USB 2.0 specification revision 2.0, chapter 7; the absence of series AC-coupling capacitors on USB-DP/USB-DM is correct and required. The USB 2.0 specification calls for 90 ohm differential characteristic impedance on the D+/D- pair; no impedance net class is assigned to USB-DP, USB-DM, Net-(U1B-USB0_DP) or Net-(U1B-USB0_DM) in the schematic. Assign a 90 ohm differential class to these four nets in the schematic net-class editor so the constraint reaches layout as data rather than as a drawing note. R3 and R4 at 33 ohm are series damping in the classic USB 2.0 full-speed position between the transceiver and the connector; USB 2.0 termination is on-die in the transceiver, and no external pull-up or pull-down is required or present on the data pair.

9.2.2 ESD Protection and Its Position in the Pair

AI-Assisted — U5, a Nexperia PRTR5V0U2X in SOT143B, protects the pair. Its I/O pins 2 and 3 sit on USB-DP and USB-DM on the connector side of R3/R4, so the transient is clamped before it meets the series resistors and the transceiver - the correct order. U5 pin 4 (VCC) returns to +VBUS at 5.00 V and pin 1 (GND) to GND; the device's standoff voltage is 5.5 V maximum and its breakdown window is 6 V to 9 V, so it does not conduct at the 5 V VBUS rail it references. Line capacitance is 1 pF typical, 1.5 pF maximum per I/O to ground and 0.6 pF typical I/O to I/O (Nexperia PRTR5V0U2X datasheet, https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf), which is negligible against the USB 2.0 full-/high-speed eye and well inside the specification's allowance for connector-side capacitance. The datasheet states no external capacitor on VCC is required to reach the maximum ESD level, and none is fitted - consistent. The clamping voltage is 17 V typical at 2.5 A with an 8/20 us waveform; no transient withstand figure for the same waveform is available for the MCXA156 USB pins, so the clamp-to-victim margin cannot be closed from the data at hand, and this is recorded as a note rather than a defect. No ESD device is fitted on CC1, CC2, SBU1 or SBU2, all of which are user-accessible contacts on J1.

9.3 Observations

AI-Assisted — The design carries no multi-gigabit lanes, no reference-clock distribution and no SerDes, so there is no AC coupling, no receiver bias network and no equalisation to assess. The transceiver supply pin VDD_USB (U1 pin H6) sits on the +3v3 rail, which carries 6 uF of bypass in total across nine capacitors - two 2.2 uF, one 1 uF and six 0.1 uF - distributed across the MCU, flash and sensor supply pins; there is no dedicated ferrite or separate filter between the digital 3.3 V rail and the USB transceiver supply, which is acceptable for full-speed signalling but leaves the transceiver referenced to the same rail as the SPI flash switching currents. The MCXA156 device documentation was not available for this review, so the transceiver's own recommended series-resistor value, USB signalling speed and any dedicated VDD_USB filtering requirement could not be checked against the manufacturer's figures - the 33 ohm value and the shared rail are reported as-drawn, not as verified against NXP's recommendation. U2 (ADXL355) is marked do-not-install, so no interface of that device is live in this build.

9.4 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.4.1	USB-DP / USB-DM	USB 2.0	No 90 ohm differential impedance class assigned to USB-DP, USB-DM, Net-(U1B-USB0_DP) or Net-(U1B-USB0_DM); set the net class in the schematic so the constraint carries into layout (USB 2.0 specification rev 2.0)	Medium
9.4.2	CC1 / CC2 / SBU1 / SBU2	USB Type-C	No ESD device on the user-accessible CC and SBU contacts of J1; only the D+/D- pair is protected	Medium
9.4.3	SBU1 / SBU2	USB Type-C sideband	Each SBU net lands on two MCU pins (SBU1 to U1 B2 and D1; SBU2 to U1 C2 and D2) - driver contention risk if both are ever configured as outputs	Low
9.4.4	USB-DP / USB-DM	USB 2.0	R3 and R4, 33 ohm, series damping between transceiver and connector; USB 2.0 termination is on-die, no external termination required. Transceiver datasheet for MCXA156 not available, so the value is not checked against NXP's recommendation	Review
9.4.5	USB-DP / USB-DM	ESD protection	U5 clamps at 17 V typ at 2.5 A, 8/20 us; no matching transient withstand figure is published for the MCXA156 USB pins, so the clamp-to-victim margin cannot be closed - waveform/condition mismatch	Review
9.4.6	U1 VDD_USB	Transceiver supply	VDD_USB (U1 H6) fed from the shared +3v3 rail with 6 uF total bypass across the rail; no dedicated ferrite or filter separates the transceiver supply from the digital rail	Review
9.4.7	USB-DP / USB-DM	USB 2.0	Pair runs U1 J7/H7 to J1 A6+B6 / A7+B7; A- and B-side contacts paralleled as required for a USB 2.0-only Type-C receptacle (USB Type-C Cable and Connector Specification)	✓
9.4.8	USB-DP / USB-DM	USB 2.0	No series AC-coupling capacitors - USB 2.0 is DC-coupled per USB 2.0 specification rev 2.0 ch.7; correct as drawn	✓
9.4.9	USB-DP / USB-DM	ESD protection	U5 (PRTR5V0U2X) placed on the connector side of R3/R4 - transient clamped ahead of the series resistors and the transceiver	✓
9.4.10	USB-DP / USB-DM	ESD protection	U5 line capacitance 1 pF typ / 1.5 pF max per I/O and 0.6 pF I/O-to-I/O; negligible loading of the USB 2.0 eye (Nexperia PRTR5V0U2X datasheet, https://assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf)	✓
9.4.11	USB-DP / USB-DM	ESD protection	U5 VCC on +VBUS (5.00 V), GND on GND; standoff 5.5 V max and breakdown 6-9 V, so no conduction at the working rail (Nexperia PRTR5V0U2X datasheet)	✓
9.4.12	USB-DP / USB-DM	ESD protection	No external VCC capacitor fitted on U5; datasheet states none is required for the maximum ESD level (Nexperia PRTR5V0U2X datasheet)	✓
9.4.13	CC1 / CC2	USB Type-C	R2 (5.1 kOhm) CC1-to-GND and R1 (5.1 kOhm) CC2-to-GND: correct single-Rd-per-line sink presentation (USB Type-C Cable and Connector Specification)	✓
9.4.14	VBUS	USB Type-C sink	C4 (1 uF, 16 V from the part number) on +VBUS is within the 1-10 uF sink bypass window of the USB Type-C Cable and Connector Specification; VBUS also drives U9 EN so the 3.3 V rail follows VBUS presence	✓
9.4.15	J1 connector	USB 2.0 Type-C	Receptacle exposes only the 16 USB 2.0 contacts - no SuperSpeed lanes present, so no 5 Gbit/s launch or connector-bandwidth concern applies	✓

9.5 Citations

AI-Assisted —

References
PRTR5V0U2X (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 U6 QSPI

U6 (W25Q128JVPIQ) - QSPI [4-bit data]
Signal	Pin Name	Pin #	Net Name	Test Point
CLOCK	SCK	6	FLASH-SCLK	-
DATA_0	HOLD_(IO3)	7	+3v3	TP4_1
DATA_1	SI_(IO0)	5	FLASH-MOSI	-
DATA_2	SO_(IO1)	2	FLASH-MISO	-
DATA_3	WP_(IO2)	3	+3v3	TP4_1
SELECT	CE	1	FLASH-CS	-
DESIGN_WARNING: Test points needed on FLASH-CS, FLASH-MISO, FLASH-MOSI and FLASH-SCLK for direct on-board programming
U6 is in-system programmable via U1 (MCXA156VMP) over SWD. A debug probe on the SWD port loads a programming routine into U1, which then drives the memory bus
This device may be testable or programmable via boundary-scan however analysis to verify each net is controllable could not be done because a BSDL file for the attached device was not provided

10.2 Programming Access Verification

Verifies that ICs sharing the QSPI bus can be disabled during non-volatile memory programming.

U6 (W25Q128JVPIQ)
Adjacent IC	Type	Can Disable	Control Path
U1	MCXA156VMP	[FAIL]	No disable pins (RESET, CE#, OE#) found on component
U2	ADXL355BEZ-RL7	[FAIL]	No disable pins (RESET, CE#, OE#) found on component
U3	IIM-42352	[FAIL]	No disable pins (RESET, CE#, OE#) found on component
U9	TPS7A2033DQNR	[OK]	via J1 -> U9.EN
DESIGN_WARNING:U1 (MCXA156VMP): No disable pins (RESET, CE#, OE#) found on component
DESIGN_WARNING:U2 (ADXL355BEZ-RL7): No disable pins (RESET, CE#, OE#) found on component
DESIGN_WARNING:U3 (IIM-42352): No disable pins (RESET, CE#, OE#) found on component

10.3 AI-Assisted Analysis

10.3.1 Serial NOR Flash U6 (W25Q128JVPIQ) — interface and topology

AI-Assisted — U6 is a 128 Mbit Winbond serial NOR flash in the 8-pad WSON package, wired point-to-point to the MCXA156VMP (U1) LPSPI0 port: FLASH-SCLK to the clock input, FLASH-MOSI to SI/IO0, FLASH-MISO to SO/IO1, and FLASH-CS to the chip-select input. No other device shares these four nets, so there is no multi-slave direction conflict and no bus contention on the data lines. The flash VCC pin sits on +3v3 (3.30 V from U9) and GND is tied to the board ground, both DC-connected. Per the Winbond datasheet the 3.0-3.6 V supply window supports the full 133 MHz clock for all instructions except Read Data (03h), which is limited to 50 MHz; the MCXA156 LPSPI cannot exceed that ceiling, so no clock-rate violation exists.

The interface is wired as single-bit SPI only: IO2 (/WP) and IO3 (/HOLD) are hard-tied to +3v3 rather than routed to the controller. Dual and quad read modes are therefore unavailable, and read throughput is limited to one bit per clock. If a wider interface is intended later, IO2/IO3 must be brought to LPSPI0 pins; the MCXA156 provides them on the same port group.

No series damping resistors are fitted on FLASH-SCLK or the data lines. At the short trace lengths implied by a single 64-ball MCU and one flash on a compact board this is acceptable, but a footprint for a 22-33 ohm series element in the clock line is cheap insurance before layout, given the 0.1 V/ns typical edge rate quoted in the Winbond datasheet.

10.3.2 Flash configuration pins, reset and chip-select biasing

AI-Assisted — The fitted ordering option is the IQ suffix. Per the Winbond datasheet this variant ships with the Quad Enable bit fixed at QE=1 and 25% default output drive strength. With QE=1 the /WP and /HOLD functions are permanently disabled and those two pads act as IO2 and IO3. Because both are hard-tied to +3v3 through no series resistance, any quad-mode instruction issued by firmware would drive the flash outputs directly into the 3.3 V rail. Firmware must never issue a quad instruction to this part as wired; a safer arrangement is a series resistor (typically 1 kOhm) or a pull-up to +3v3 at each of IO2 and IO3 so a mis-issued quad command cannot produce a low-impedance fight.

FLASH-CS carries only the MCU pin and the flash input, with no pull-up to +3v3. The Winbond datasheet recommends (does not require) a /CS pull-up so the chip select tracks VCC during power-up and power-down sequencing; without it, /CS floats while the MCU I/O is in its high-impedance reset state, and the flash could see a spurious selection during the power ramp. A 10 kOhm pull-up to +3v3 closes this.

The 8-pad WSON package carries no dedicated hardware /RESET pin, so the software reset sequence (66h followed by 99h, approximately 30 us per the datasheet) is the only recovery path. The datasheet's 5 ms power-up delay before a write instruction and the 20 us VCC-valid-to-/CS-low time must be respected by the boot code.

10.3.3 Flash supply decoupling and rail ratings

AI-Assisted — The +3v3 rail carries 6 uF total local capacitance across nine parts (2x2.2 uF, 1x1 uF, 6x0.1 uF) shared between U1, U3, U6 and the fitted DNI-optional U2. At least one 0.1 uF X7R part must sit adjacent to the U6 VCC pad at layout; peak flash demand is the 25 mA maximum erase/program current from the Winbond datasheet, which the rail's bulk capacitance covers comfortably.

Rail rating check: the 2.2 uF parts on +3v3 are 6.3 V devices known from the part number; derated 20% they permit 5.04 V against 3.30 V applied - correctly sized. The 1 uF and 0.1 uF parts are 16 V devices, giving 12.8 V permitted after the same derating against 3.30 V applied - ample, and a 6.3 V or 10 V part would serve the same position. The 16 V ratings of C1, C2, C5, C6, C7 and C9 appear only in the part description; they should be carried in a named Voltage property so BOM and AOI tooling reads them.

10.3.4 Test access and in-system programming

AI-Assisted — None of the four flash bus signals is brought to a test point. The only accessible node associated with U6 is the +3v3 rail at TP4, which is where IO2 and IO3 terminate. In-system programming of U6 by a bench fixture is therefore not possible without lifting the part or driving the bus through U1, and U1 offers no chip-disable pin that would tri-state its LPSPI0 outputs. TP3 does land on the MCU reset line, which allows the MCU to be held in reset; combined with test pads on FLASH-SCLK, FLASH-MOSI, FLASH-MISO and FLASH-CS this would give direct flash access for production programming and for functional verification of the bus. Adding those four pads is the single highest-value change for testability before layout is committed. SWD access is provided at TP1 and TP2, so programming through the MCU remains available.

10.4 Observations

AI-Assisted — The memory subsystem is a single serial NOR flash; there is no DDR, SDRAM, SRAM or NVRAM on this board, and no memory module socket. Consequently topology classification, termination, VREF/ZQ and byte-lane organisation checks do not apply.

The accelerometer interface (U3 IIM-42352, with U2 ADXL355 marked do-not-install) runs on a separate LPSPI1 bus with its own chip select and does not share any net with the flash, so flash timing is unaffected by sensor traffic. The two sensors share ACCEL-CS; with U2 not installed this is a single-slave bus as built, but if U2 is ever populated both parts would be selected simultaneously and their outputs would collide on ACCEL-MISO. A separate chip select for U2 should be allocated before that build option is exercised.

No lifecycle issue applies to the fitted flash: the Winbond datasheet for the W25Q128JV family states no NRND or end-of-life status.

10.5 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.5.1	U6 W25Q128JVPIQ	Configuration pins	IQ suffix fixes QE=1, so IO2/IO3 are data pins; hard tie to the rail risks output contention if a quad instruction is issued - use series resistors or pull-ups (Winbond datasheet, ordering options and Status Register sections)	Medium
10.5.2	U6 W25Q128JVPIQ	Interface width	IO2 and IO3 hard-tied to +3v3: interface limited to 1-bit SPI, dual/quad read unavailable	Low
10.5.3	U6 W25Q128JVPIQ	Test access / programming	No test points on clock, data or chip select; U1 has no chip-disable, so in-system flash programming is not possible from a fixture - add four pads	Low
10.5.4	U2 / U3 sensor bus	SPI (non-memory)	ACCEL-CS shared by U3 and the do-not-install U2; if U2 is populated both slaves select together and collide on ACCEL-MISO - allocate a separate chip select	Low
10.5.5	U6 W25Q128JVPIQ	Chip select bias	No pull-up on FLASH-CS; datasheet recommends one so /CS tracks VCC during power sequencing - 10 kOhm to +3v3 suggested (recommendation, not a requirement)	Review
10.5.6	U6 W25Q128JVPIQ	Reset	8-pad WSON has no hardware /RESET pin; software reset 66h+99h (approx. 30 us) is the only recovery path - boot code dependency (Winbond datasheet)	Review
10.5.7	U6 W25Q128JVPIQ	Signal integrity	No series damping on FLASH-SCLK or data lines; 0.1 V/ns typical edge rate - recommend a series resistor footprint in the clock line before layout	Review
10.5.8	+3v3 rail	Capacitor ratings	6.3 V parts derated 20% permit 5.04 V, 16 V parts permit 12.8 V, 3.30 V applied - correctly sized; the 16 V ratings should be carried in a named Voltage property rather than only in the description	Review
10.5.9	U6 W25Q128JVPIQ	Serial NOR flash	Point-to-point SPI to U1 LPSPI0; clock, both data lines and chip select correctly wired, no shared slaves, no direction conflict (Winbond W25Q128JV datasheet)	✓
10.5.10	U6 W25Q128JVPIQ	Power / ground	VCC on +3v3 (3.30 V) within the 3.0-3.6 V window for full 133 MHz operation; GND DC-connected to board ground (Winbond datasheet)	✓
10.5.11	U6 W25Q128JVPIQ	Decoupling	+3v3 carries 6 uF total (2x2.2 uF + 1x1 uF + 6x0.1 uF); adequate for the 25 mA maximum erase/program current (Winbond datasheet)	✓
10.5.12	U6 W25Q128JVPIQ	Timing	133 MHz maximum clock (50 MHz for Read Data 03h) at 3.0-3.6 V is above any LPSPI0 rate the MCXA156 can generate (Winbond datasheet)	✓
10.5.13	U6 W25Q128JVPIQ	Lifecycle	No NRND or end-of-life status stated for the W25Q128JV family (Winbond datasheet)	✓

10.6 Citations

AI-Assisted —

References
W25Q128JV-IQ (Winbond) — datasheet W25Q128JVSIQ.pdf

11 Functional Analysis

3 device(s) to review across 2 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
U1	DEVICE	MCXA156VMP	ARM Microcontrollers - MCU MCXA18,1MB Flash, 128KB RAM, 64BGA	I2C, SPI [ACCEL], SPI [FLASH], SWD, SWD [Net-(U1B] (partial)	-
U3	DEVICE	IIM-42352	COMPACT, LOW POWER 3-AXIS INDUST	SPI [ACCEL]	-
U5	Prot.	PRTR5V0U2X,215	6V Unidirectional 5.5V SOT-143 ESD and Surge Protection (TVS/ESD) ROHS	-	-

11.1 Functional Analysis

11.1.1 MCXA156VMP microcontroller (U1) — supplies, boot strap and interfaces

AI-Assisted — All five supply pins (VDD, VDD_P3, VDD_ANA, VDD_USB, VREFH) sit on +3v3. Per the NXP MCXA156 datasheet (p.13) VDD is specified 1.71–3.6 V, VDD_P3 1.71–3.6 V in normal condition, VDD_ANA within VDD ±0.1 V and VDD_USB 3.0–3.6 V; a single 3.3 V rail satisfies every one of them simultaneously, including the narrow USB window that would fail on a 3.0 V or lower rail. VREFL is tied to GND and the VSS pins D4, D5, D6, E6, F5, F6 are on GND, so every return has a true DC ground path. The rail carries 6 µF of local ceramic bypass across the five supply pins.
The ISP boot strap P0_6/ISPMODE_N is defined by R5 (5,1 kΩ) from that net to +3v3, with TP8 on the same net — the strap is held at a valid inactive level at reset rather than floating, and remains overridable at the test point. USB0_DP and USB0_DM leave through R4 and R3 (33 Ω each) to the connector D+/D- pairs, the conventional series termination for the full-speed driver; both connector rows (A6/B6 and A7/B7) are tied together, giving flip-agnostic operation. USB0_VBUS_DET is on +3v3 rather than a divided VBUS sense, so the port is permanently reported as attached — acceptable for a self-contained bus-powered board but it removes VBUS-presence detection.
CC1 and CC2 each carry a 5,1 kΩ resistor (R2, R1) to GND, which is the correct Rd sink advertisement for a USB Type-C device, and both nets are also brought to MCU pins for CC sensing. SWDIO, SWCLK and RESET_B each reach a test point, giving full debug and reset access.
The unused port pins are left open, which is permitted for this family.

11.1.2 IIM-42352 inertial sensor (U3)

AI-Assisted — VDD (pin 8) and VDDIO (pin 5) are both on +3v3; the TDK datasheet (p.11) specifies VDD 1,71–3,6 V and VDDIO 1,71–3,6 V, so 3,3 V is inside both windows and no level shifting is needed between the sensor and the MCU, whose VIH is 0,7 × VDD against the sensor's VOH of 0,9 × VDDIO. GND (pin 6) is on GND, as are the reserved pins 2, 3 and 7; pins 10 and 11 are deliberately left open. Bypassing asked by the datasheet (0,1 µF and 2,2 µF at VDD, 10 nF at VDDIO) is met in kind by the 0,1 µF and 2,2 µF ceramics fitted on the +3v3 rail.
The device is wired as a 4-wire SPI slave: AP-CS from ACCEL-CS, AP-SCL/AP-SCLK from ACCEL-SCK, AP-SDA/AP-SDI from ACCEL-MOSI and AP-SDO to ACCEL-MISO, all reaching LPSPI1 pins on U1 (PCS0, SCK, SDO, SDI). Directions agree on every wire. The datasheet states pin 12 (AP-CS) has its internal pull-up enabled by default (PIN12_PU_EN, register 0x0Eh Bank 3), so the select is held deselected before firmware drives it — no external pull-up is required here. The same net also lands on the do-not-install ADXL355 (U2), so no second driver is present as built.
Both interrupts are routed: INT1 to P3_6 and INT2/FSYNC/CLKIN to P3_7, both GPIO-capable, with polarity and push-pull/open-drain selectable in register 0x14h. Note that tying INT2/FSYNC/CLKIN to a live MCU pin means FSYNC and external-CLKIN use remain available in firmware. The LPSPI1 clock must be kept at or below the 24 MHz SPI limit.

11.1.3 PRTR5V0U2X ESD protection array (U5)

AI-Assisted — U5 is connected as intended for a rail-referenced dual-channel array: VCC (pin 4) to +VBUS, GND (pin 1) to GND, IO1 (pin 2) to USB-DP and IO2 (pin 3) to USB-DM. The Nexperia datasheet confirms the internal diode network is symmetric — clamping is specified for both +2,5 A and −2,2 A pulses — so no orientation constraint applies to the I/O pins and none is violated here.
Electrically the placement is correct: the array sits on the connector side of the 33 Ω series resistors R3 and R4, so a strike at J1 is diverted before it reaches the series elements and the MCU USB pins, rather than after them. Line capacitance of 1 pF typical (max 1,5 pF I/O to ground, 0,6 pF I/O to I/O) is negligible against the USB full-speed eye the MCXA156 transceiver drives.
The datasheet states no external capacitor at VCC is needed to reach the rated protection level, and +VBUS carries a 1 µF ceramic (C4) in any case. SBU1 and SBU2 are taken directly to MCU pins with no protection device on those two lines; they are exposed at the connector and, unlike D+/D-, have no clamp between the plug and the port pins. If those pins are to be retained as usable sideband signals, extend ESD protection to cover them.

11.1.4 Type-C Configuration Channel, SBU and VBUS

AI-Assisted — R2 (5.1 kOhm) connects CC1 (J1 pin A5) to GND and R1 (5.1 kOhm) connects CC2 (J1 pin B5) to GND. One Rd per CC line at 5.1 kOhm is the sink (UFP) presentation defined by the USB Type-C Cable and Connector Specification, and the board therefore advertises itself correctly as a power sink with no alternate-mode or DFP capability. Both CC nets also reach MCU inputs - CC1 to U1 pin A1 and CC2 to U1 pin B1 - allowing plug-orientation and Rp advertisement to be read in firmware; those pins must stay configured as inputs, since driving either would corrupt the Rd presentation. The SBU contacts are wired to two MCU pins each: SBU1 (J1 pin A8) to U1 pins B2 and D1, and SBU2 (J1 pin B8) to U1 pins C2 and D2. Doubling up two GPIO on one net gives pin-mux flexibility but creates a contention path if firmware ever enables both as outputs; it also loads each SBU line with two pin capacitances. VBUS from J1 pins A4/A9/B4/B9 is bypassed by C4 (1 uF, 16 V from the part number) and feeds U9 (TPS7A2033DQNR) at both IN and EN, so the 3.3 V rail follows VBUS presence directly. A sink VBUS bypass of 1 uF sits inside the 1 uF to 10 uF window the Type-C specification allows for a sink.

11.2 Findings

AI-Assisted —

#	Device	Finding	Severity
11.2.1	J1 (USB4145-03-0230-C) / U1	SBU1 and SBU2 run from the connector directly to MCU pins with no ESD clamp on those lines, while D+/D- are protected — extend protection to the sideband pair if it is to be used.	Medium
11.2.2	U1 (MCXA156VMP)	USB0_VBUS_DET tied to +3v3 rather than a VBUS-derived sense: the port is always reported attached, removing VBUS-presence detection.	Review
11.2.3	U6 (W25Q128JVPIQ) select, via U1 LPSPI0	FLASH-CS is driven only by U1 pin B3 with no external pull-up and no slave-side pull-up in evidence; what holds the flash deselected before firmware configures LPSPI0 rests on the MCXA156 reset state of that pin, which is not established from the data supplied.	Review
11.2.4	U3 (IIM-42352)	SPI clock limit 24 MHz (TDK datasheet p.14); LPSPI1 must be configured at or below this.	Review
11.2.5	U1 (MCXA156VMP)	VDD, VDD_P3, VDD_ANA, VREFH on +3v3 — inside 1,71–3,6 V and VDD_ANA within VDD ±0,1 V (NXP datasheet p.13). VSS pins and VREFL on GND, true DC ground path.	✓
11.2.6	U1 (MCXA156VMP)	VDD_USB on +3v3 — datasheet window 3,0–3,6 V (p.13); the single 3,3 V rail is the only one of the supplies with this narrow limit and it is met.	✓
11.2.7	U1 (MCXA156VMP)	Boot strap P0_6/ISPMODE_N defined by R5 5,1 kΩ from that net to +3v3, with TP8 for override — no floating strap at reset.	✓
11.2.8	U1 (MCXA156VMP)	USB0_DP / USB0_DM via R4 / R3 (33 Ω) to J1 D+/D- of both rows — conventional full-speed series termination, flip-agnostic.	✓
11.2.9	U1 (MCXA156VMP)	CC1 / CC2 each with 5,1 kΩ (R2 / R1) to GND — correct Rd sink advertisement for USB Type-C; both nets also sensed by MCU pins.	✓
11.2.10	U1 (MCXA156VMP)	SWDIO, SWCLK and RESET_B each brought to a test point (TP2, TP1, TP3) — debug and reset accessible.	✓
11.2.11	U3 (IIM-42352)	VDD and VDDIO on +3v3 — TDK datasheet p.11 gives 1,71–3,6 V for both; GND and reserved pins 2, 3, 7 on GND.	✓
11.2.12	U3 (IIM-42352)	Required bypass (0,1 µF + 2,2 µF at VDD, 10 nF at VDDIO, TDK datasheet p.1) met in kind by the 0,1 µF and 2,2 µF ceramics on +3v3.	✓
11.2.13	U3 (IIM-42352)	4-wire SPI to U1 LPSPI1: CS/SCLK/SDI/SDO directions agree on every net; no conflicting driver, the shared ADXL355 (U2) is do-not-install.	✓
11.2.14	U3 (IIM-42352)	AP-CS internal pull-up enabled by default (PIN12_PU_EN, reg. 0x0Eh Bank 3, TDK datasheet) holds the select deselected before firmware runs — no external pull-up needed.	✓
11.2.15	U3 (IIM-42352)	INT1 to U1 P3_6 and INT2/FSYNC/CLKIN to U1 P3_7 — both routed to GPIO-capable pins; drive mode and polarity configurable in reg. 0x14h.	✓
11.2.16	U3 (IIM-42352)	VIH 0,7 × VDDIO / VOH 0,9 × VDDIO against MCXA156 VIH 0,7 × VDD on a common 3,3 V rail — logic levels compatible, no translation required.	✓
11.2.17	U5 (PRTR5V0U2X,215)	VCC on +VBUS, GND on GND, IO1 on USB-DP, IO2 on USB-DM — correct rail-referenced array wiring; topology confirmed bidirectional by the Nexperia datasheet, no orientation constraint.	✓
11.2.18	U5 (PRTR5V0U2X,215)	Fitted on the connector side of R3 / R4, so transients at J1 are diverted ahead of the series resistors and the MCU USB pins.	✓
11.2.19	U5 (PRTR5V0U2X,215)	Line capacitance 1 pF typ (max 1,5 pF to GND, Nexperia datasheet p.4) — negligible loading for USB full speed.	✓

11.3 Citations

AI-Assisted —

References
IIM-42352 (InvenSense, a TDK Group Company) — datasheet, cited pages 1,18 product.tdk.com/system/files/dam/doc/product/sensor/morti...
MCXA156 (NXP) — datasheet, cited pages 2,60 MCXA156VMP.PDF
PRTR5V0U2X (Nexperia) — datasheet assets.nexperia.com/documents/data-sheet/PRTR5V0U2X.pdf
TPS7A2033 (Texas Instruments) — datasheet, cited pages 1,3,4,5,46 www.ti.com/lit/ds/symlink/tps7a20.pdf

12 Designer Annotated Nets

No designer-annotated nets found.

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J1	USB4145-03-0230-C	J1 (USB4145-03-0230-C) [USB4145-03-0230-C]: Shield pins SHIELD, SHIELD, SHIELD, SHIELD connected directly to logic GND which masks design intent for layout.	Place shell/shield tabs on a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD). This net represents the copper pour under the shielded connector. For plastic enclosed products with no earth ground, add a schematic note for dense via stitching of the shield copper pours to the ground plane with no isolation network. For earth ground connected products, review if the product requires R\|\|C isolation of shields from logic GND to meet ESD compliance (IEC 61000-4-2).

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed:6 connector-facing signal(s). 0 protected, 6 unprotected, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
USB-DP	J1	No ESD Protection
USB-DM	J1	No ESD Protection
SBU2	J1	No ESD Protection
SBU1	J1	No ESD Protection
CC2	J1	No ESD Protection
CC1	J1	No ESD Protection

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture — Grounding, Filtering and Shielding

AI-Assisted — The board is a single-domain design: one GND net serves the USB Type-C receptacle J1 (contacts A1, A12, B1, B12), all four shell tabs S1–S4, the decoupling of U1, U2, U3, U6, the LDO U9 return, and the ESD device U5 ground pin. No separate chassis or shield domain is drawn, so the shield bonding strategy is not captured as design intent — the layout engineer receives no net-level guidance for a dedicated shield copper pour under J1, nor any explicit bond component between shell and logic ground. The recommendation is a dedicated net (e.g. SHIELD_GND_TYPE_C) carrying S1–S4, with the bond element drawn on the sheet. Scenario A, plastic enclosure: no earth exists, the logic plane is the only ESD sink; bond the shield pour directly to logic GND with dense via stitching so the plane and shell rise together during a strike, keeping differential stress across the contacts near zero, and add a schematic note recording that intent. Scenario B, metal chassis with earth: review whether shield-to-logic isolation is required; if so bridge the pour to logic GND with 1 MΩ || 4.7 nF rated ≥2 kV and bond the pour mechanically to chassis at the panel opening. Line filtering entering the enclosure is limited to R3/R4 33 Ω in the D+/D− pair; CC, SBU and VBUS carry no filter element. For an industrial product the applicable immunity and emission frames are IEC 61000-6-2 and IEC 61000-6-4, with ESD per IEC 61000-4-2 (±4 kV contact, ±8 kV air).

13.3.2 J1 — USB Type-C Receptacle, High-Speed Pair and Power

AI-Assisted — J1 is a 24-position USB Type-C receptacle, by definition external and user-pluggable, so IEC 61000-4-2 contact discharge applies to every exposed contact and to the shell. The USB 2.0 pair is protected: U5 (PRTR5V0U2X) sits on USB-DP/USB-DM at the connector side of the 33 Ω series resistors R3/R4, which is the correct topology — the clamp intercepts the strike first and the series resistance then limits residual current into the MCU USB pads (U1 pins J7 and H7). U5 is a rail-referenced dual channel array with its ground pin on GND and its supply pin on +VBUS, giving the intended clamp orientation toward both rails; its 5.5 V working voltage matches the 3.3 V-signalling USB 2.0 lines with margin, and its sub-pF line capacitance is transparent at full-speed and high-speed data rates (NXP PRTR5V0U2X datasheet). The CC pins present Rd = 5.1 kΩ to GND through R2 (CC1) and R1 (CC2), the pull-downs running from J1 A5 and B5 to GND, which declares the board a sink/UFP per USB Type-C Specification R2.5 §4.5.1.2.1 — the value and tolerance class (1 %) are compliant. Both CC lines and both SBU lines run from the receptacle straight to MCU pins with no clamp and no series element, leaving four externally exposed contacts with only the MCU's internal pad protection between the cable and the die. TP6/TP7 tap the data pair at the receptacle; stub length is a layout matter to keep minimal.

13.3.3 J1 — VBUS and Sink Power Entry

AI-Assisted — +VBUS arrives on J1 contacts A4, A9, B4, B9 and is decoupled by C4 (1 µF), feeding the supply pin of U5 and the input of the LDO U9 (TPS7A2033DQNR), which generates the +3v3 rail for U1, U2, U3 and U6. Sink bypass capacitance of 1 µF is inside the 1–10 µF window required of a sink by USB Type-C Specification R2.5 §4.4.1. No transient clamp is fitted at the VBUS entry contacts of J1: cable insertion into a live source produces an inrush/hot-plug overshoot on VBUS, and a Type-C receptacle is also exposed to a CC-to-VBUS short in a non-compliant cable. The exposed part behind that entry is the LDO input; a 5.5–6 V standoff unidirectional TVS across the VBUS contacts to GND would clamp below the input rating of U9 and of U5's supply pin, and is the conventional treatment for an externally cabled 5 V entry under IEC 61000-4-5 surge and IEC 61000-4-2. This is offered as an investigation item, not an error — the design may rely on the source's own current limit and on cable length being short. Note that the clamp fitted on the data pair covers the two data lines it is wired across and nothing else; that is not a shortcoming of that device.

13.4 Observations

AI-Assisted — Radiated-emission risk on this board is dominated by the common-mode path from the logic plane out along the USB cable: with shell tabs sharing the logic GND net and no explicit bond element on the sheet, the return strategy is decided implicitly in layout, and a high-inductance or long shield-to-plane connection converts cable-borne common-mode current into radiation at the harmonics of the 12 Mbit/s and 480 Mbit/s USB clocks — the failure mode is a radiated-emission excursion at IEC 61000-6-4 and a shell-discharge upset at IEC 61000-4-2 level 2 rather than a hard failure. The likely in-field ESD failure mode for the unclamped CC and SBU contacts is direct injection into the MCU pads: an air discharge to an exposed receptacle contact couples into U1 with only the 5.1 kΩ Rd resistors offering any impedance on CC, and nothing at all on SBU1/SBU2, giving latch-up or pad damage rather than recoverable upset. Ground bounce is not a structural concern here — the ground is a single low-impedance domain with a large distributed decoupling bank on the +3v3 rail — but that same single domain means all ESD energy entering the shell transits the logic plane, which is precisely why the shield bond geometry needs to be stated on the schematic rather than left to the layout stage.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J1	Shell tabs S1–S4 share the logic GND net; the shield bonding strategy is not captured as design intent. Assign a dedicated net (e.g. SHIELD_GND_TYPE_C) and draw the bond element, so the layout engineer receives an explicit shield pour and bond. Source: USB Type-C Specification R2.5 §3.2.1, IEC 61000-4-2.	Medium
13.5.2	J1	CC1 and CC2 run from contacts A5/B5 directly to MCU pins U1 A1/B1 with only the Rd resistors present; the exposed CC contacts have no transient clamp. Investigate a low-capacitance clamp on CC1/CC2. Source: IEC 61000-4-2, USB Type-C Specification R2.5.	Medium
13.5.3	J1	SBU1 and SBU2 run from contacts A8/B8 directly to MCU pins with no clamp and no series element; externally exposed contacts rely on MCU pad protection alone. Investigate adding an ESD clamp on the SBU pair. Source: IEC 61000-4-2.	Medium
13.5.4	J1	VBUS entry contacts A4/A9/B4/B9 carry no transient clamp to GND ahead of the LDO input of U9 and the supply pin of U5. Investigate a 5.5–6 V standoff unidirectional TVS at the entry. Source: IEC 61000-4-5, IEC 61000-4-2.	Low
13.5.5	J1	TP6/TP7 tap USB-DM/USB-DP at the receptacle; keep the test-point stubs short at layout to avoid impedance discontinuity on the pair. Source: USB 2.0 Specification, Chapter 7.	Review
13.5.6	J1	Series resistors R3/R4 (33 Ω) provide both edge damping for radiated emissions and residual ESD current limiting into the MCU USB pads; combined value against the MCU driver output impedance was not computed from the loads on the net. Source: NXP MCXA156 datasheet, IEC 61000-6-4.	Review
13.5.7	J1	USB 2.0 pair USB-DP/USB-DM protected by U5 (PRTR5V0U2X) placed at the receptacle side of series resistors R3/R4 (33 Ω) — correct clamp-then-limit ordering toward MCU pins U1 J7/H7. Source: NXP PRTR5V0U2X datasheet.	✓
13.5.8	J1	U5 orientation correct: ground pin on GND, supply pin on +VBUS, 5.5 V working voltage above the 3.3 V USB signalling level; low line capacitance does not load the data pair. Source: NXP PRTR5V0U2X datasheet.	✓
13.5.9	J1	Rd pull-downs R1 (CC2 to GND) and R2 (CC1 to GND) at 5.1 kΩ 1 % correctly declare the board a sink/UFP. Source: USB Type-C Specification R2.5 §4.5.1.2.1.	✓
13.5.10	J1	Sink bypass capacitance on +VBUS is C4 = 1 µF, inside the 1–10 µF sink window. Source: USB Type-C Specification R2.5 §4.4.1.	✓
13.5.11	J1	Single-domain ground: connector returns, shell tabs, ESD device return, LDO return and all decoupling share one GND net — low-impedance and consistent, with no split-plane discontinuity. Source: IEC 61000-6-2, IEC 61000-6-4.	✓

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	3
Rails with TPs	2
Rails without TPs	1

1 power rail(s) need test points in the submitted design.

7 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+3v3		TP4	✓
+VBUS		-	NEEDS TP
GND		TP5	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP9	+VBUS	11-10080__yoshi-mainboard__A.kicad_sch
TP10	GND	11-10080__yoshi-mainboard__A.kicad_sch
TP11	GND	11-10080__yoshi-mainboard__A.kicad_sch
TP12	GND	11-10080__yoshi-mainboard__A.kicad_sch
TP13	GND	11-10080__yoshi-mainboard__A.kicad_sch
TP14	GND	11-10080__yoshi-mainboard__A.kicad_sch
TP15	GND	11-10080__yoshi-mainboard__A.kicad_sch

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U9	TPS7A2033DQNR	EN	3	tied to VCC - recommend pull-up resistor and test point

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.5 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
SMT_TP-1MM	SMT Testpoint 35mil	8

14.5.1 By Sheet

Test Point	Net Name	Footprint
11-10080__yoshi-mainboard__A (8 test points)
TP1	Net-(U1B-SWCLK/P0_1)	SMT_TP-1MM
TP2	Net-(U1B-SWDIO/P0_0)	SMT_TP-1MM
TP3	Net-(U1B-P1_29/RESET_B/SPC_LPREQ)	SMT_TP-1MM
TP4	+3v3	SMT_TP-1MM
TP5	GND	SMT_TP-1MM
TP6	USB-DM	SMT_TP-1MM
TP7	USB-DP	SMT_TP-1MM
TP8	Net-(U1B-P0_6/ISPMODE_N)	SMT_TP-1MM

14.5.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP1	Net-(U1B-SWCLK/P0_1)	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP2	Net-(U1B-SWDIO/P0_0)	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP3	Net-(U1B-P1_29/RESET_B/SPC_LPREQ)	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP4	+3v3	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP5	GND	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP6	USB-DM	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP7	USB-DP	11-10080__yoshi-mainboard__A	SMT_TP-1MM
TP8	Net-(U1B-P0_6/ISPMODE_N)	11-10080__yoshi-mainboard__A	SMT_TP-1MM

14.6 Powered-off Testing

8 nets with test points: 9 pins with opens coverage, 0 pins with partial opens, 80 pins with shorts coverage.

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
C1_2	+3v3	Capacitor	-	●
C2_2	+3v3	Capacitor	-	●
C3_2	+3v3	Capacitor	-	●
C5_2	+3v3	Capacitor	-	●
C6_2	+3v3	Capacitor	-	●
C7_2	+3v3	Capacitor	-	●
C9_2	+3v3	Capacitor	-	●
C14_2	+3v3	Capacitor	-	●
C16_2	+3v3	Capacitor	-	●
R5_2	+3v3	Passive	●	●
U1_E3	+3v3	IC	-	●
U1_F4	+3v3	IC	-	●
U1_G3	+3v3	IC	-	●
U1_G5	+3v3	IC	-	●
U1_H6	+3v3	IC	-	●
U1_J4	+3v3	IC	-	●
U2_5	+3v3	IC	-	●
U2_11	+3v3	IC	-	●
U3_5	+3v3	IC	-	●
U3_8	+3v3	IC	-	●
U6_3	+3v3	IC	-	●
U6_7	+3v3	IC	-	●
U6_8	+3v3	IC	-	●
U9_1	+3v3	IC	-	●
C1_1	GND	Capacitor	-	●
C2_1	GND	Capacitor	-	●
C3_1	GND	Capacitor	-	●
C4_1	GND	Capacitor	-	●
C5_1	GND	Capacitor	-	●
C6_1	GND	Capacitor	-	●
C7_1	GND	Capacitor	-	●
C9_1	GND	Capacitor	-	●
C10_1	GND	Capacitor	-	●
C11_1	GND	Capacitor	-	●
C12_1	GND	Capacitor	-	●
C13_1	GND	Capacitor	-	●
C14_1	GND	Capacitor	-	●
C16_1	GND	Capacitor	-	●
J1_A1	GND	Connector	-	●
J1_A12	GND	Connector	-	●
J1_B1	GND	Connector	-	●
J1_B12	GND	Connector	-	●
J1_S1	GND	Connector	-	●
J1_S2	GND	Connector	-	●
J1_S3	GND	Connector	-	●
J1_S4	GND	Connector	-	●
M1_1	GND	Passive	●	●
R1_1	GND	Passive	-	●
R2_1	GND	Passive	-	●
U1_D4	GND	IC	-	●
U1_D5	GND	IC	-	●
U1_D6	GND	IC	-	●
U1_E4	GND	IC	-	●
U1_E6	GND	IC	-	●
U1_F5	GND	IC	-	●
U1_F6	GND	IC	-	●
U2_6	GND	IC	-	●
U2_7	GND	IC	-	●
U2_9	GND	IC	-	●
U3_2	GND	IC	-	●
U3_3	GND	IC	-	●
U3_6	GND	IC	-	●
U3_7	GND	IC	-	●
U5_1	GND	IC	-	●
U6_4	GND	IC	-	●
U9_2	GND	IC	-	●
U9_5	GND	IC	-	●
R5_1	Net-(U1B-P0_6/ISPMODE_N)	Passive	●	●
U1_C7	Net-(U1B-P0_6/ISPMODE_N)	IC	●	●
U1_E1	Net-(U1B-P1_29/RESET_B/SPC_LPREQ)	IC	●	●
U1_B7	Net-(U1B-SWCLK/P0_1)	IC	●	●
U1_B8	Net-(U1B-SWDIO/P0_0)	IC	●	●
J1_A7	USB-DM	Connector	-	●
J1_B7	USB-DM	Connector	-	●
R3_2	USB-DM	Passive	-	●
U5_3	USB-DM	IC	●	●
J1_A6	USB-DP	Connector	-	●
J1_B6	USB-DP	Connector	-	●
R4_2	USB-DP	Passive	-	●
U5_2	USB-DP	IC	●	●

14.7 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

2 power rail nets with test points: 24 source-path pins (opens + shorts), 45 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
C1_2	+3v3	Sink	-	●
C2_2	+3v3	Sink	-	●
C3_2	+3v3	Sink	-	●
C5_2	+3v3	Sink	-	●
C6_2	+3v3	Sink	-	●
C7_2	+3v3	Sink	-	●
C9_2	+3v3	Sink	-	●
C14_2	+3v3	Sink	-	●
C16_2	+3v3	Sink	-	●
R5_2	+3v3	Series (U1 → R5)	●	●
TP4_1	+3v3	Sink	-	●
U1_E3	+3v3	Series path	●	●
U1_F4	+3v3	Series path	●	●
U1_G3	+3v3	Series path	●	●
U1_G5	+3v3	Series path	●	●
U1_H6	+3v3	Series path	●	●
U1_J4	+3v3	Series path	●	●
U2_5	+3v3	Sink	-	●
U2_11	+3v3	Sink	-	●
U3_5	+3v3	Sink	-	●
U3_8	+3v3	Sink	-	●
U6_3	+3v3	Sink	-	●
U6_7	+3v3	Sink	-	●
U6_8	+3v3	Sink	-	●
U9_1	+3v3	Source (OUT)	●	●
C1_1	GND	Sink	-	●
C2_1	GND	Sink	-	●
C3_1	GND	Sink	-	●
C4_1	GND	Sink	-	●
C5_1	GND	Sink	-	●
C6_1	GND	Sink	-	●
C7_1	GND	Sink	-	●
C9_1	GND	Sink	-	●
C10_1	GND	Series (U2 → C10)	●	●
C11_1	GND	Series (U2 → C11)	●	●
C12_1	GND	Series (U2 → C12)	●	●
C13_1	GND	Series (U2 → C13)	●	●
C14_1	GND	Sink	-	●
C16_1	GND	Sink	-	●
J1_A1	GND	Sink	-	●
J1_A12	GND	Sink	-	●
J1_B1	GND	Sink	-	●
J1_B12	GND	Sink	-	●
J1_S1	GND	Sink	-	●
J1_S2	GND	Sink	-	●
J1_S3	GND	Sink	-	●
J1_S4	GND	Sink	-	●
M1_1	GND	Sink	-	●
R1_1	GND	Series (U1 → R1)	●	●
R2_1	GND	Series (U1 → R2)	●	●
TP5_1	GND	Sink	-	●
U1_D4	GND	Series path	●	●
U1_D5	GND	Series path	●	●
U1_D6	GND	Series path	●	●
U1_E4	GND	Series path	●	●
U1_E6	GND	Series path	●	●
U1_F5	GND	Series path	●	●
U1_F6	GND	Series path	●	●
U2_6	GND	Series path	●	●
U2_7	GND	Series path	●	●
U2_9	GND	Series path	●	●
U3_2	GND	Sink	-	●
U3_3	GND	Sink	-	●
U3_6	GND	Sink	-	●
U3_7	GND	Sink	-	●
U5_1	GND	Sink	-	●
U6_4	GND	Sink	-	●
U9_2	GND	Sink	-	●
U9_5	GND	Sink	-	●

14.8 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.9 Inspection

Total: 29 components, 153 of 154 pins with inspection coverage.

14.9.1 AOI

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
C0402_0.55MM_MD
C0402_0.55MM_MD			Chip Passive	Designator	8	16	C1, C10, C12, C2, C5, C6, C7, C9
C0603_0.90MM_MD
C0603_0.90MM_MD			Chip Passive	Designator	6	12	C11, C13, C14, C16, C3, C4
R0402_0.40MM_HD
R0402_0.40MM_HD			Chip Passive	Designator	5	10	R1, R2, R3, R4, R5
Subtotal: 19 components, 38 pins
Opens only (leads visible, shorts unreliable)
SOT143B
SOT143B			SOIC/SOP	Designator	1	4	U5
X2SON
X2SON			SOIC/SOP	Designator	1	5	U9
Subtotal: 2 components, 9 pins
Presence check (manual verification)
USB4145-03-0230-C
USB4145-03-0230-C			Connector	Designator	1	20	J1
Subtotal: 1 components, 20 pins

14.9.2 AXI

IPC Compliant Footprints (Hidden Joints)
Components with IPC compliant footprints and solder joints hidden under the package body.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
SON127P600X80_HS-9N
SON127P600X80_HS-9N			QFN/DFN (No-Lead)	IPC-7351B	1	8	U6
Subtotal: 1 components, 8 pins

Assumed Classification (Non-IPC Footprints)
Hidden-joint classification inferred from Pkg Type property or designator prefix. Footprint names are not IPC-7351B or IPC-7251.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
LFBGA64
LFBGA64			BGA (Ball Grid Array)	Footprint	4	64	U1, U1, U1, U1
PQFN50P250X300X97-14N
PQFN50P250X300X97-14N			QFN/DFN (No-Lead)	Footprint	1	14	U3
Subtotal: 5 components, 78 pins

14.9.3 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
M2.2
M2.2	Unclassified	Unknown	1	1	M1
Subtotal: 1 components, 1 pins

14.10 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.10.1 Fault Coverage Summary

Fault Coverage Summary (168 pins)
Test Method	Opens	Shorts
X-ray (AXI)	8 (4.8%)	8 (4.8%)
Optical (AOI)	0 (0.0%)	0 (0.0%)
Electrical
Powered-off Testing	32 (19.0%)	80 (47.6%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	9 (5.4%)	9 (5.4%)
Total	38 (22.6%)	94 (56.0%)
Total Fault Coverage	46 (27.4%)	98 (58.3%)
No coverage	122 (72.6%)	70 (41.7%)

14.10.2 Uncovered Pins (70)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
R1_2	CC2
R4_1	Net-(U1B-USB0_DP)
U2_2	ACCEL-SCK
U2_1	ACCEL-CS
U2_10	Net-(U2-V1P8ANA)
U2_13	INT2/CLKIN
U2_14	DRDY
U2_8	Net-(U2-V1P8DIG)
U2_3	ACCEL-MOSI
U2_4	ACCEL-MISO
U2_12	INT1
R2_2	CC1
C13_2	Net-(U2-V1P8DIG)
R3_1	Net-(U1B-USB0_DM)
U1_A2	Net-(U1C-P1_5/FREQME_CLK_IN1/LPSPI0_PCS2/LPUART2_TXD/CT1_MAT3/FLEXIO0_D13/A0_21)
U1_C3	Net-(U1C-P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1)
U1_B4	FLASH-MISO
U1_A6	Net-(U1C-P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT/A0_14)
U1_A5	FLASH-MOSI
U1_C5	Net-(U1C-P0_16/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0)
U1_B5	FLASH-SCLK
U1_B6	Net-(U1C-P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2)
U1_B3	FLASH-CS
U1_A3	Net-(U1C-P1_4/FREQME_CLK_IN0/LPSPI0_PCS3/LPUART2_RXD/CT1_MAT2/FLEXIO0_D12/A0_20)
U1_J5
U1_H5
U1_A1	CC1
U1_E2
U1_F2
U1_G2
U1_H1
U1_J1
U1_H2
U1_G1
U1_B1	CC2
U1_H3
U1_J2
U1_H4
C12_2	Net-(U2-V1P8DIG)
U3_9	INT2/CLKIN
U3_12	ACCEL-CS
U3_14	ACCEL-MOSI
U3_1	ACCEL-MISO
U3_13	ACCEL-SCK
U3_4	INT1
U3_11
U3_10
U1_C8	ACCEL-MOSI
U1_D8	ACCEL-MISO
U1_A8	DRDY
U1_C9	INT2/CLKIN
U1_H9
U1_G7
U1_A9	Net-(U1D-P3_1/TRIG_IN1/LPUART3_TXD/CT_INP17/PWM0_B0/FLEXIO0_D9/PWM1_X1)
U1_B9	INT1
U1_F8
U1_E8	ACCEL-SCK
U1_G8
U1_F9
U1_H8
U1_E9	ACCEL-CS
U1_E7
U1_J9
U1_J8
U1_J7	Net-(U1B-USB0_DP)
U1_H7	Net-(U1B-USB0_DM)
C10_2	Net-(U2-V1P8ANA)
C11_2	Net-(U2-V1P8ANA)
J1_A5	CC1
J1_B5	CC2

14.10.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
C7_1	GND	-	●	-	-	-	-
C7_2	+3v3	-	●	-	-	-	-
C9_1	GND	-	●	-	-	-	-
C9_2	+3v3	-	●	-	-	-	-
R1_1	GND	●	●	-	-	-	-
R1_2	CC2	-	-	-	-	-	-
C1_1	GND	-	●	-	-	-	-
C1_2	+3v3	-	●	-	-	-	-
U9_1	+3v3	●	●	-	-	-	-
U9_3	+VBUS	-	●	-	-	-	-
U9_2	GND	-	●	-	-	-	-
U9_4	+VBUS	-	●	-	-	-	-
U9_5	GND	-	●	-	-	-	-
C2_1	GND	-	●	-	-	-	-
C2_2	+3v3	-	●	-	-	-	-
R4_1	Net-(U1B-USB0_DP)	-	-	-	-	-	-
R4_2	USB-DP	-	●	-	-	-	-
U2_11	+3v3	-	●	-	-	-	-
U2_7	GND	●	●	-	-	-	-
U2_5	+3v3	-	●	-	-	-	-
U2_2	ACCEL-SCK	-	-	-	-	-	-
U2_6	GND	●	●	-	-	-	-
U2_1	ACCEL-CS	-	-	-	-	-	-
U2_10	Net-(U2-V1P8ANA)	-	-	-	-	-	-
U2_13	INT2/CLKIN	-	-	-	-	-	-
U2_14	DRDY	-	-	-	-	-	-
U2_8	Net-(U2-V1P8DIG)	-	-	-	-	-	-
U2_3	ACCEL-MOSI	-	-	-	-	-	-
U2_9	GND	●	●	-	-	-	-
U2_4	ACCEL-MISO	-	-	-	-	-	-
U2_12	INT1	-	-	-	-	-	-
C3_2	+3v3	-	●	-	-	-	-
C3_1	GND	-	●	-	-	-	-
R2_1	GND	●	●	-	-	-	-
R2_2	CC1	-	-	-	-	-	-
C4_2	+VBUS	-	●	-	-	-	-
C4_1	GND	-	●	-	-	-	-
C13_2	Net-(U2-V1P8DIG)	-	-	-	-	-	-
C13_1	GND	●	●	-	-	-	-
U5_1	GND	-	●	-	-	-	-
U5_4	+VBUS	-	●	-	-	-	-
U5_3	USB-DM	●	●	-	-	-	-
U5_2	USB-DP	●	●	-	-	-	-
R3_1	Net-(U1B-USB0_DM)	-	-	-	-	-	-
R3_2	USB-DM	-	●	-	-	-	-
U1_E4	GND	●	●	-	-	-	-
U1_E3	+3v3	●	●	-	-	-	-
U1_F4	+3v3	●	●	-	-	-	-
U1_G5	+3v3	●	●	-	-	-	-
U1_D4	GND	●	●	-	-	-	-
U1_G3	+3v3	●	●	-	-	-	-
U1_F5	GND	●	●	-	-	-	-
U1_F6	GND	●	●	-	-	-	-
U1_D5	GND	●	●	-	-	-	-
U1_D6	GND	●	●	-	-	-	-
U1_E6	GND	●	●	-	-	-	-
C16_2	+3v3	-	●	-	-	-	-
C16_1	GND	-	●	-	-	-	-
U1_A2	Net-(U1C-P1_5/FREQME_CLK_IN1/LPSPI0_PCS2/LPUART2_TXD/CT1_MAT3/FLEXIO0_D13/A0_21)	-	-	-	-	-	-
U1_C3	Net-(U1C-P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1)	-	-	-	-	-	-
U1_B4	FLASH-MISO	-	-	-	-	-	-
U1_A6	Net-(U1C-P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT/A0_14)	-	-	-	-	-	-
U1_A5	FLASH-MOSI	-	-	-	-	-	-
U1_C5	Net-(U1C-P0_16/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0)	-	-	-	-	-	-
U1_B5	FLASH-SCLK	-	-	-	-	-	-
U1_B6	Net-(U1C-P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2)	-	-	-	-	-	-
U1_B3	FLASH-CS	-	-	-	-	-	-
U1_A3	Net-(U1C-P1_4/FREQME_CLK_IN0/LPSPI0_PCS3/LPUART2_RXD/CT1_MAT2/FLEXIO0_D12/A0_20)	-	-	-	-	-	-
U1_J5		-	-	-	-	-	-
U1_D2	SBU2	●	◐	-	-	-	-
U1_H5		-	-	-	-	-	-
U1_D1	SBU1	●	◐	-	-	-	-
U1_A1	CC1	-	-	-	-	-	-
U1_E2		-	-	-	-	-	-
U1_F2		-	-	-	-	-	-
U1_C2	SBU2	●	◐	-	-	-	-
U1_G2		-	-	-	-	-	-
U1_H1		-	-	-	-	-	-
U1_J1		-	-	-	-	-	-
U1_H2		-	-	-	-	-	-
U1_B2	SBU1	●	◐	-	-	-	-
U1_G1		-	-	-	-	-	-
U1_B1	CC2	-	-	-	-	-	-
U1_H3		-	-	-	-	-	-
U1_J2		-	-	-	-	-	-
U1_H4		-	-	-	-	-	-
C14_2	+3v3	-	●	-	-	-	-
C14_1	GND	-	●	-	-	-	-
M1_1	GND	●	●	-	-	-	-
U6_1	FLASH-CS	-	-	-	-	●	◐
U6_6	FLASH-SCLK	-	-	-	-	●	◐
U6_4	GND	-	●	-	-	●	◐
U6_7	+3v3	-	●	-	-	●	◐
U6_5	FLASH-MOSI	-	-	-	-	●	◐
U6_8	+3v3	-	●	-	-	●	◐
U6_2	FLASH-MISO	-	-	-	-	●	◐
U6_3	+3v3	-	●	-	-	●	◐
C12_1	GND	●	●	-	-	-	-
C12_2	Net-(U2-V1P8DIG)	-	-	-	-	-	-
U3_9	INT2/CLKIN	-	-	-	-	-	-
U3_5	+3v3	-	●	-	-	-	-
U3_12	ACCEL-CS	-	-	-	-	-	-
U3_14	ACCEL-MOSI	-	-	-	-	-	-
U3_1	ACCEL-MISO	-	-	-	-	-	-
U3_13	ACCEL-SCK	-	-	-	-	-	-
U3_4	INT1	-	-	-	-	-	-
U3_8	+3v3	-	●	-	-	-	-
U3_2	GND	-	●	-	-	-	-
U3_6	GND	-	●	-	-	-	-
U3_3	GND	-	●	-	-	-	-
U3_7	GND	-	●	-	-	-	-
U3_11		-	-	-	-	-	-
U3_10		-	-	-	-	-	-
C6_1	GND	-	●	-	-	-	-
C6_2	+3v3	-	●	-	-	-	-
C5_1	GND	-	●	-	-	-	-
C5_2	+3v3	-	●	-	-	-	-
U1_C8	ACCEL-MOSI	-	-	-	-	-	-
U1_D8	ACCEL-MISO	-	-	-	-	-	-
U1_A8	DRDY	-	-	-	-	-	-
U1_C9	INT2/CLKIN	-	-	-	-	-	-
U1_H9		-	-	-	-	-	-
U1_G7		-	-	-	-	-	-
U1_A9	Net-(U1D-P3_1/TRIG_IN1/LPUART3_TXD/CT_INP17/PWM0_B0/FLEXIO0_D9/PWM1_X1)	-	-	-	-	-	-
U1_B9	INT1	-	-	-	-	-	-
U1_F8		-	-	-	-	-	-
U1_E8	ACCEL-SCK	-	-	-	-	-	-
U1_G8		-	-	-	-	-	-
U1_F9		-	-	-	-	-	-
U1_H8		-	-	-	-	-	-
U1_E9	ACCEL-CS	-	-	-	-	-	-
U1_E7		-	-	-	-	-	-
U1_J9		-	-	-	-	-	-
U1_J8		-	-	-	-	-	-
U1_H6	+3v3	●	●	-	-	-	-
U1_J7	Net-(U1B-USB0_DP)	-	-	-	-	-	-
U1_E1	Net-(U1B-P1_29/RESET_B/SPC_LPREQ)	●	●	-	-	-	-
U1_H7	Net-(U1B-USB0_DM)	-	-	-	-	-	-
U1_B7	Net-(U1B-SWCLK/P0_1)	●	●	-	-	-	-
U1_B8	Net-(U1B-SWDIO/P0_0)	●	●	-	-	-	-
U1_C7	Net-(U1B-P0_6/ISPMODE_N)	●	●	-	-	-	-
U1_J4	+3v3	●	●	-	-	-	-
C10_1	GND	●	●	-	-	-	-
C10_2	Net-(U2-V1P8ANA)	-	-	-	-	-	-
R5_1	Net-(U1B-P0_6/ISPMODE_N)	●	●	-	-	-	-
R5_2	+3v3	●	●	-	-	-	-
C11_2	Net-(U2-V1P8ANA)	-	-	-	-	-	-
C11_1	GND	●	●	-	-	-	-
J1_A4	+VBUS	-	●	-	-	-	-
J1_A9	+VBUS	-	●	-	-	-	-
J1_B4	+VBUS	-	●	-	-	-	-
J1_S4	GND	-	●	-	-	-	-
J1_B9	+VBUS	-	●	-	-	-	-
J1_S2	GND	-	●	-	-	-	-
J1_A1	GND	-	●	-	-	-	-
J1_A12	GND	-	●	-	-	-	-
J1_B1	GND	-	●	-	-	-	-
J1_S1	GND	-	●	-	-	-	-
J1_S3	GND	-	●	-	-	-	-
J1_A5	CC1	-	-	-	-	-	-
J1_A7	USB-DM	-	●	-	-	-	-
J1_B12	GND	-	●	-	-	-	-
J1_B5	CC2	-	-	-	-	-	-
J1_A6	USB-DP	-	●	-	-	-	-
J1_B8	SBU2	●	◐	-	-	-	-
J1_B6	USB-DP	-	●	-	-	-	-
J1_B7	USB-DM	-	●	-	-	-	-
J1_A8	SBU1	●	◐	-	-	-	-

14.11 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.11.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	69.2%	38.5%	0.0%	8.3%	0.0%	28.9%	22.7%	0.0%
Optical Inspection (AOI)	3.8%	3.8%	3.8%	0.0%	0.0%	0.0%	0.0%	0.0%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	1.9%	2.6%	2.6%	2.6%
Combined	71.2%	42.3%	3.8%	8.3%	1.9%	30.2%	25.3%	2.6%

14.11.2 PCB Device/Pin Count

Devices (PCOLA): 26
Pins (SOQ): 154

14.11.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	25513 / 100,000	25.5%
SOQ	19372 / 100,000	19.4%
Combined	22443 / 100,000	22.4%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	23205 / 100,000	17208 / 100,000
Optical/X-ray Inspection	2692 / 100,000	2597 / 100,000
Combined (max)	25513 / 100,000	19372 / 100,000

14.11.4 PCOLA (26 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
70%	U6	W25Q128JVPIQ / SON127P600X80_HS-9N	IC	●	●	●	○	◐	AOI, AXI, Powered_Off
40%	C7	0.1µF / C0402_0.55MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C9	0.1µF / C0402_0.55MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C1	0.1µF / C0402_0.55MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C2	0.1µF / C0402_0.55MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C3	1µF / C0603_0.90MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C16	2.2µF / C0603_0.90MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C14	2.2µF / C0603_0.90MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C6	0.1µF / C0402_0.55MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	C5	0.1µF / C0402_0.55MM_MD *	Capacitor	●	●	○	—	○	Passive_Meas, Powered_Off
40%	R5	5.1kΩ / R0402_0.40MM_HD *	Resistor	●	●	○	—	○	Passive_Meas, Powered_Off
20%	U1	MCXA156VMP / LFBGA64 *	IC	◐	○	○	◐	○	LSSI, Powered_Off
10%	R1	5.1kΩ / R0402_0.40MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	U9	TPS7A2033DQNR / X2SON *	IC	◐	○	○	○	○	Powered_Off
10%	R4	33Ω / R0402_0.40MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	R2	5.1kΩ / R0402_0.40MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	C4	1µF / C0603_0.90MM_MD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C13	2.2µF / C0603_0.90MM_MD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U5	PRTR5V0U2X,215 / SOT143B *	IC	◐	○	○	○	○	Powered_Off
10%	R3	33Ω / R0402_0.40MM_HD *	Resistor	◐	○	○	—	○	Powered_Off
10%	M1	M2.2 / M2.2 *	Other	◐	○	○	○	○	Powered_Off
10%	C12	0.1µF / C0402_0.55MM_MD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U3	IIM-42352 / PQFN50P250X300X97-14N *	IC	◐	○	○	○	○	Powered_Off
10%	C10	0.1µF / C0402_0.55MM_MD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C11	2.2µF / C0603_0.90MM_MD *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J1	USB4145-03-0230-C / USB4145-03-0230-C *	Connector	◐	○	○	—	○	Powered_Off

14.11.5 SOQ (154 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
50%	R2_1	GND	◐	●	○
50%	U6_8	+3v3	◐	◐	◐
50%	U6_5	FLASH-MOSI	◐	◐	◐
50%	U6_7	+3v3	◐	◐	◐
50%	R1_1	GND	◐	●	○
50%	U6_1	FLASH-CS	◐	◐	◐
50%	U6_6	FLASH-SCLK	◐	◐	◐
50%	M1_1	GND	◐	●	○
50%	U9_1	+3v3	◐	●	○
50%	J1_B8	SBU2	◐	●	○
50%	C11_1	GND	◐	●	○
50%	R5_2	+3v3	◐	●	○
50%	R5_1	Net-(U1B-P0_6/ISPMODE_N)	◐	●	○
50%	C10_1	GND	◐	●	○
50%	U1_J4	+3v3	◐	●	○
50%	U1_D2	SBU2	◐	●	○
50%	U1_C7	Net-(U1B-P0_6/ISPMODE_N)	◐	●	○
50%	U1_D1	SBU1	◐	●	○
50%	U6_4	GND	◐	◐	◐
50%	U1_F6	GND	◐	●	○
50%	U1_B8	Net-(U1B-SWDIO/P0_0)	◐	●	○
50%	U1_B7	Net-(U1B-SWCLK/P0_1)	◐	●	○
50%	U1_C2	SBU2	◐	●	○
50%	U1_E1	Net-(U1B-P1_29/RESET_B/SPC_LPREQ)	◐	●	○
50%	C13_1	GND	◐	●	○
50%	U1_H6	+3v3	◐	●	○
50%	J1_A8	SBU1	◐	●	○
50%	U5_3	USB-DM	◐	●	○
50%	U5_2	USB-DP	◐	●	○
50%	C12_1	GND	◐	●	○
50%	U1_B2	SBU1	◐	●	○
50%	U1_E4	GND	◐	●	○
50%	U1_E3	+3v3	◐	●	○
50%	U1_F4	+3v3	◐	●	○
50%	U1_G5	+3v3	◐	●	○
50%	U1_D4	GND	◐	●	○
50%	U1_G3	+3v3	◐	●	○
50%	U1_F5	GND	◐	●	○
50%	U6_3	+3v3	◐	◐	◐
50%	U1_D5	GND	◐	●	○
50%	U1_D6	GND	◐	●	○
50%	U1_E6	GND	◐	●	○
50%	U6_2	FLASH-MISO	◐	◐	◐
17%	C7_2	+3v3	◐	○	○
17%	C9_1	GND	◐	○	○
17%	C9_2	+3v3	◐	○	○
17%	J1_A1	GND	◐	○	○
17%	C1_1	GND	◐	○	○
17%	C1_2	+3v3	◐	○	○
17%	U9_3	+VBUS	◐	○	○
17%	U9_2	GND	◐	○	○
17%	U9_4	+VBUS	◐	○	○
17%	U9_5	GND	◐	○	○
17%	C2_1	GND	◐	○	○
17%	C2_2	+3v3	◐	○	○
17%	J1_A12	GND	◐	○	○
17%	R4_2	USB-DP	◐	○	○
17%	C3_2	+3v3	◐	○	○
17%	C3_1	GND	◐	○	○
17%	J1_B1	GND	◐	○	○
17%	C4_2	+VBUS	◐	○	○
17%	C4_1	GND	◐	○	○
17%	J1_S1	GND	◐	○	○
17%	U5_1	GND	◐	○	○
17%	U5_4	+VBUS	◐	○	○
17%	J1_S3	GND	◐	○	○
17%	R3_2	USB-DM	◐	○	○
17%	C7_1	GND	◐	○	○
17%	C16_2	+3v3	◐	○	○
17%	C16_1	GND	◐	○	○
17%	J1_A7	USB-DM	◐	○	○
17%	J1_B12	GND	◐	○	○
17%	J1_A6	USB-DP	◐	○	○
17%	J1_B6	USB-DP	◐	○	○
17%	J1_B7	USB-DM	◐	○	○
17%	C14_2	+3v3	◐	○	○
17%	C14_1	GND	◐	○	○
17%	U3_7	GND	◐	○	○
17%	U3_5	+3v3	◐	○	○
17%	U3_8	+3v3	◐	○	○
17%	U3_2	GND	◐	○	○
17%	U3_6	GND	◐	○	○
17%	U3_3	GND	◐	○	○
17%	C6_1	GND	◐	○	○
17%	C6_2	+3v3	◐	○	○
17%	C5_1	GND	◐	○	○
17%	C5_2	+3v3	◐	○	○
17%	J1_A4	+VBUS	◐	○	○
17%	J1_A9	+VBUS	◐	○	○
17%	J1_B4	+VBUS	◐	○	○
17%	J1_S4	GND	◐	○	○
17%	J1_B9	+VBUS	◐	○	○
17%	J1_S2	GND	◐	○	○
0%	R1_2	CC2	○	○	○
0%	R4_1	Net-(U1B-USB0_DP)	○	○	○
0%	R2_2	CC1	○	○	○
0%	C13_2	Net-(U2-V1P8DIG)	○	○	○
0%	R3_1	Net-(U1B-USB0_DM)	○	○	○
0%	U1_A2	Net-(U1C-P1_5/FREQME_CLK_IN1/LPSPI0_PCS2/LPUART2_TXD/CT1_MAT3/FLEXIO0_D13/A0_21)	○	○	○
0%	U1_C3	Net-(U1C-P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1)	○	○	○
0%	U1_B4	FLASH-MISO	○	○	○
0%	U1_A6	Net-(U1C-P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT/A0_14)	○	○	○
0%	U1_A5	FLASH-MOSI	○	○	○
0%	U1_C8	ACCEL-MOSI	○	○	○
0%	U1_D8	ACCEL-MISO	○	○	○
0%	U1_A8	DRDY	○	○	○
0%	U1_C9	INT2/CLKIN	○	○	○
0%	U1_H9		○	○	○
0%	U1_G7		○	○	○
0%	U1_A9	Net-(U1D-P3_1/TRIG_IN1/LPUART3_TXD/CT_INP17/PWM0_B0/FLEXIO0_D9/PWM1_X1)	○	○	○
0%	U1_B9	INT1	○	○	○
0%	U1_F8		○	○	○
0%	U1_E8	ACCEL-SCK	○	○	○
0%	U1_G8		○	○	○
0%	U1_F9		○	○	○
0%	U1_J1		○	○	○
0%	U1_E9	ACCEL-CS	○	○	○
0%	U1_E7		○	○	○
0%	U1_J9		○	○	○
0%	U1_J8		○	○	○
0%	U1_H1		○	○	○
0%	U1_J7	Net-(U1B-USB0_DP)	○	○	○
0%	U1_G2		○	○	○
0%	U1_H7	Net-(U1B-USB0_DM)	○	○	○
0%	U1_F2		○	○	○
0%	U1_E2		○	○	○
0%	U1_H5		○	○	○
0%	U1_J5		○	○	○
0%	U1_A3	Net-(U1C-P1_4/FREQME_CLK_IN0/LPSPI0_PCS3/LPUART2_RXD/CT1_MAT2/FLEXIO0_D12/A0_20)	○	○	○
0%	C10_2	Net-(U2-V1P8ANA)	○	○	○
0%	U1_B3	FLASH-CS	○	○	○
0%	U1_B6	Net-(U1C-P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2)	○	○	○
0%	C11_2	Net-(U2-V1P8ANA)	○	○	○
0%	U1_B5	FLASH-SCLK	○	○	○
0%	U3_12	ACCEL-CS	○	○	○
0%	U3_14	ACCEL-MOSI	○	○	○
0%	U3_1	ACCEL-MISO	○	○	○
0%	U3_13	ACCEL-SCK	○	○	○
0%	U3_4	INT1	○	○	○
0%	U1_J2		○	○	○
0%	U1_H3		○	○	○
0%	U1_B1	CC2	○	○	○
0%	U1_G1		○	○	○
0%	U1_A1	CC1	○	○	○
0%	U3_11		○	○	○
0%	J1_A5	CC1	○	○	○
0%	U3_10		○	○	○
0%	U1_H2		○	○	○
0%	J1_B5	CC2	○	○	○
0%	C12_2	Net-(U2-V1P8DIG)	○	○	○
0%	U1_C5	Net-(U1C-P0_16/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0)	○	○	○
0%	U3_9	INT2/CLKIN	○	○	○
0%	U1_H4		○	○	○
0%	U1_H8		○	○	○

14.11.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Component Properties

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Model Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U1	F	64	0	0	0	0	0	0	0	64	MCXA156VMP
U2	F	14	0	0	0	0	0	0	0	14	ADXL355BEZ-RL7
U6	F	8	0	0	0	0	0	0	0	8	W25Q128JVPIQ
U9	F	5	0	0	0	0	0	0	0	5	TPS7A2033DQNR
U5	C	4	0	0	0	4	0	0	0	0	PRTR5V0U2X,215
U3	B	14	3	2	1	3	0	0	0	5	IIM-42352

15.1.1 Library Quality Summary

Total ICs evaluated	6
Grade A (excellent)	0 (0.0%)
Grade B (good)	1 (16.7%)
Grade C (fair)	1 (16.7%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	4 (66.7%)
OVERALL LIBRARY QUALITY	D (0.98/4.00)

15.2 Component Library Validation

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (5 models)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
ADXL355BEZ-RL7	ADXL355BEZ-RL7	ADXL355BEZ-RL7	U2	14	P:14	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [VSUPPLY=Passive, VDDIO=Passive, VSSIO=Passive, VSS=Passive]
MCXA156VMP	MCXA156VMP	MCXA156VMP	U1	64	P:64	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [VREFL=Passive, VDD_ANA=Passive, VREFH=Passive, VDD_P3=Passive, VSS=Passive, +7 more]
PRTR5V0U2X,215	PRTR5V0U2X,215	PRTR5V0U2X,215	U5	4	Bi:4	Power-named pins not typed as Power - library pin types incomplete [GND=Bidirectional, VCC=Bidirectional]
TPS7A2033DQNR	TPS7A2033DQNR	TPS7A2033DQNR	U9	5	P:5	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [OUT=Passive, GND=Passive, IN=Passive, GND=Passive]
W25Q128JVPIQ	W25Q128JVPIQ	W25Q128JVPIQ	U6	8	P:8	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete [GND=Passive, VCC=Passive]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Shielded Connector Model Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.4 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
J1	USB4145-03-0230-C	20	Footprint	USB4145-03-0230-C:USB4145-03-0230-C
M1	M2.2	1	Footprint	M2.2:M2.2
U1	MCXA156VMP	64	Footprint	LFBGA64:LFBGA64
U2	ADXL355BEZ-RL7	14	Footprint	LCC14P127_600X600X225L91X50N:LCC14P127_600X600X225L91X50N
U3	IIM-42352	14	Footprint	PQFN50P250X300X97-14N:PQFN50P250X300X97-14N
U5	PRTR5V0U2X,215	4	Footprint	SOT143B:SOT143B
U6	W25Q128JVPIQ	8	Footprint	SON127P600X80_HS-9N:SON127P600X80_HS-9N
			(IPC-7351B)	Small Outline No-lead, 127 pins, 6.00mm pitch
U9	TPS7A2033DQNR	5	Footprint	X2SON:X2SON

15.5 IC Pin Electrical Properties

Unique IC models	6
Total IC instances	6

IC Library Models
Industry Name	Library Name	RefDes	Notes
ADXL355BEZ-RL7	ADXL355BEZ-RL7	U2
IIM-42352	IIM-42352	U3
MCXA156VMP	MCXA156VMP	U1
PRTR5V0U2X,215	PRTR5V0U2X,215	U5
TPS7A2033DQNR	TPS7A2033DQNR	U9
W25Q128JVPIQ	W25Q128JVPIQ	U6

15.5.1 ADXL355BEZ-RL7 (ADXL355BEZ-RL7)

Pin	Pin Name	Electrical
1	CS/SCL	Passive
2	SCLK/VSSIO	Passive
3	MOSI/SDA	Passive
4	MISO/ASEL	Passive
5	VDDIO	Passive
6	VSSIO	Passive
7	RSV	Passive
8	V1P8DIG	Passive
9	VSS	Passive
10	V1P8ANA	Passive
11	VSUPPLY	Passive
12	INT1	Passive
13	INT2	Passive
14	DRDY	Passive

15.5.2 IIM-42352 (IIM-42352)

Pin	Pin Name	Electrical
1	AP-SDO/AP-AD0	Bidirectional
2	RESV	Passive
3	RESV	Passive
4	INT1/INT	Output
5	VDDIO	Power In
6	GND	Power In
7	RESV	Passive
8	VDD	Power In
9	INT2/FSYNC/CLKIN	Bidirectional
10	RESV	Passive
11	RESV	Passive
12	AP-CS	Input
13	AP-SCL/AP-SCLK	Input
14	AP-SDA/AP-SDIO/AP-SDI	Bidirectional

15.5.3 MCXA156VMP (MCXA156VMP)

Pin	Pin Name	Electrical
A1	P1_6/TRIG_IN2/LPSPI0_PCS1/LPUART2_RTS_B/CT_INP6/CT4_MAT0/FLEXIO0_D14/CAN0-TX/A0_22	Passive
A2	P1_5/FREQME_CLK_IN1/LPSPI0_PCS2/LPUART2_TXD/CT1_MAT3/FLEXIO0_D13/A0_21	Passive
A3	P1_4/FREQME_CLK_IN0/LPSPI0_PCS3/LPUART2_RXD/CT1_MAT2/FLEXIO0_D12/A0_20	Passive
A5	P1_0/TRIG_IN0/LPSPI0_SDO/LPI2C1_SDA/CT_INP4/CT0_MAT2/FLEXIO0_D8/A0_16	Passive
A6	P0_3/TDI/LPUART0_TXD/LPSPI0_SDO/CT0_MAT1/UTICK_CAP1/FLEXIO0_D3/CMP0_OUT/A0_14	Passive
A8	P3_0/TRIG_IN0/LPUART3_RXD/CT_INP16/PWM0_A0/FLEXIO0_D8/PWM1_X0	Passive
A9	P3_1/TRIG_IN1/LPUART3_TXD/CT_INP17/PWM0_B0/FLEXIO0_D9/PWM1_X1	Passive
B1	P1_7/TRIG_OUT2/LPUART2_CTS_B/CT_INP7/CT4_MAT1/FLEXIO0_D15/CAN0-RX/A0_23	Passive
B2	P1_8/FREQME_CLK_IN0/LPUART1_RXD/LPI2C2_SDA/CT_INP8/CT0_MAT2/FLEXIO0_D16	Passive
B3	P1_3/TRIG_OUT1/LPSPI0_PCS0/LPI2C1_SCLS/CT1_MAT1/CT_INP1/FLEXIO0_D11/CAN0-RX/A0_19	Passive
B4	P1_2/TRIG_OUT0/LPSPI0_SDI/LPI2C1_SDAS/CT1_MAT0/CT_INP0/FLEXIO0_D10/CAN0-TX/A0_18	Passive
B5	P1_1/TRIG_IN1/LPSPI0_SCK/LPI2C1_SCL/CT_INP5/CT0_MAT3/FLEXIO0_D9/A0_17	Passive
B6	P0_2/TDO/SWO/LPUART0_RXD/LPSPI0_SCK/CT0_MAT0/UTICK_CAP0/FLEXIO0_D2	Passive
B7	SWCLK/P0_1	Passive
B8	SWDIO/P0_0	Passive
B9	P3_6/CLKOUT/LPSPI1_PCS3/LPUART3_RTS_B/CT4_MAT2/PWM0_A0/FLEXIO0_D14/PWM1_A0	Passive
C2	P1_9/FREQME_CLK_IN1/LPUART1_TXD/LPI2C2_SCL/CT_INP9/CT0_MAT3/FLEXIO0_D17	Passive
C3	P0_17/LPI2C0_SCL/LPSPI0_PCS3/CT0_MAT1/UTICK_CAP3/FLEXIO0_D1	Passive
C5	P0_16/LPI2C0_SDA/LPSPI0_PCS2/CT0_MAT0/UTICK_CAP2/FLEXIO0_D0	Passive
C7	P0_6/ISPMODE_N	Passive
C8	P3_8/TRIG_IN3/LPSPI1_SDO/LPUART1_RXD/CT_INP4/PWM0_A1/FLEXIO0_D16	Passive
C9	P3_7/TRIG_IN2/LPSPI1_PCS2/LPUART3_CTS_B/CT4_MAT3/PWM0_B0/FLEXIO0_D15/PWM1_B0	Passive
D1	P1_11/TRIG_OUT2/LPUART1_CTS_B/LPI2C2_SCLS/CT2_MAT1/FLEXIO0_D19/CAN0-RX/A1_A9	Passive
D2	P1_10/LPUART1_RTS_B/LPI2C2_SDAS/CT2_MAT0/FLEXIO0_D18/CAN0-TX/A1_A8	Passive
D4	VSS	Passive
D5	VSS	Passive
D6	VSS	Passive
D8	P3_9/TRIG_IN4/LPSPI1_SDI/LPUART1_TXD/CT_INP5/PWM0_B1/FLEXIO0_D17	Passive
E1	P1_29/RESET_B/SPC_LPREQ	Passive
E2	P1_30/TRIG_OUT3/LPI2C0_SDA/CT_INP16/FLEXIO0_D30	Passive
E3	VDD_ANA	Passive
E4	VREFL	Passive
E6	VSS	Passive
E7	P3_27/TRIG_OUT7/LPI2C3_SCL/LPUART4_TXD/CT_INP13/CT3_MAT1/FLEXIO0_D27	Passive
E8	P3_10/TRIG_IN5/LPSPI1_SCK/LPUART1_RTS_B/CT1_MAT0/PWM0_A2/FLEXIO0_D18	Passive
E9	P3_11/TRIG_IN6/LPSPI1_PCS0/LPUART1_CTS_B/CT1_MAT1/PWM0_B2/FLEXIO0_D19	Passive
F2	P1_31/TRIG_IN4/LPI2C0_SCL/CT_INP17/FLEXIO0_D31	Passive
F4	VREFH	Passive
F5	VSS	Passive
F6	VSS	Passive
F8	P3_13/LPUART2_CTS_B/LPUART3_RXD/CT1_MAT3/PWM0_X1/FLEXIO0_D21/PWM1_B2	Passive
F9	P3_12/LPUART2_RTS_B/LPUART3_TXD/CT1_MAT2/PWM0_X0/FLEXIO0_D20/PWM1_A2	Passive
G1	P2_1/TRIG_IN7/LPUART0_TXD/LPUART4_RTS_B/CT_INP17/CT2_MAT1/FLEXIO0_D9/A0_A1	Passive
G2	P2_0/TRIG_IN6/LPUART0_RXD/LPUART4_CTS_B/CT_INP16/CT2_MAT0/FLEXIO0_D8/A0_A0	Passive
G3	VDD	Passive
G5	VDD_P3	Passive
G7	P3_28/TRIG_IN11/LPI2C3_SDA/LPUART4_RXD/CT_INP12/CT3_MAT2/FLEXIO0_D28	Passive
G8	P3_14/LPUART2_RXD/LPUART3_CTS_B/CT_INP6/PWM0_X2/FLEXIO0_D22/PWM1_A1	Passive
H1	P2_2/TRIG_IN6/LPUART0_RTS_B/LPUART2_TXD/CT_INP12/CT2_MAT2/FLEXIO0_D10/A0_A4/DAC0	Passive
H2	P2_5/LPUART2_RTS_B/CT_INP15/CT1_MAT1/FLEXIO0_D13/A1_A1	Passive
H3	P2_6/TRIG_OUT4/LPSPI1_PCS1/LPUART4_RXD/CT_INP18/CT1_MAT2/FLEXIO0_D14/A1_A3	Passive
H4	P2_7/TRIG_IN5/LPUART4_TXD/CT_INP19/CT1_MAT3/FLEXIO0_D15/A0_A7	Passive
H5	P2_15/TRIG_OUT4/LPSPI1_SDI/LPUART1_RTS_B/CT4_MAT3/CT0_MAT2/FLEXIO0_D23/A0_A2	Passive
H6	VDD_USB	Passive
H7	USB0_DM	Passive
H8	P3_15/LPUART2_TXD/LPUART3_RTS_B/CT_INP7/FLEXIO0_D23/PWM1_B1	Passive
H9	P3_29/ISPMODE_N/LPI2C3_HREQ/CT_INP3/CT3_MAT3/FLEXIO0_D29/A1_22	Passive
J1	P2_3/TRIG_IN7/LPUART0_CTS_B/LPUART2_RXD/CT_INP13/CT2_MAT3/FLEXIO0_D11/A1_A4	Passive
J2	P2_4/LPUART2_CTS_B/CT_INP14/CT1_MAT0/FLEXIO0_D12/A1_A0	Passive
J4	P2_12/USB0_VBUS_DET	Passive
J5	P2_13/TRIG_IN8/LPSPI1_SDO/LPUART1_TXD/CT4_MAT1/CT0_MAT1/FLEXIO0_D21/CAN0-TX/A1_A5	Passive
J7	USB0_DP	Passive
J8	P3_31/TRIG_IN10/LPI2C3_SDAS/LPUART4_CTS_B/CT0_MAT3/FLEXIO0_D31/A1_20	Passive
J9	P3_30/TRIG_OUT6/LPI2C3_SCLS/LPUART4_RTS_B/CT0_MAT2/FLEXIO0_D30/A1_21	Passive

15.5.4 PRTR5V0U2X,215 (PRTR5V0U2X,215)

Pin	Pin Name	Electrical
1	GND	Bidirectional
2	IO1	Bidirectional
3	IO2	Bidirectional
4	VCC	Bidirectional

15.5.5 TPS7A2033DQNR (TPS7A2033DQNR)

Pin	Pin Name	Electrical
1	OUT	Passive
2	GND	Passive
3	EN	Passive
4	IN	Passive
5	GND	Passive

15.5.6 W25Q128JVPIQ (W25Q128JVPIQ)

Pin	Pin Name	Electrical
1	CE	Passive
2	SO_(IO1)	Passive
3	WP_(IO2)	Passive
4	GND	Passive
5	SI_(IO0)	Passive
6	SCK	Passive
7	HOLD_(IO3)	Passive
8	VCC	Passive

11-10080__yoshi-mainboard__A Design Analysis

1 Design Summary

1.1 Design Overview

1.2 Processed Sheets

1.3 Structured DNP (Not Fitted)

1.4 Footprint Compliance

2 Component Value Properties

2.1 Part Number vs Stated Values

2.2 Derating Check

3 Pin Connectivity Report

3.1 Unconnected Pins

3.2 Implied/Hidden Net Connections

3.3 Open-Collector Pull-up Audit

3.4 Summary

4 Power Overview

4.1 Power Rail Analysis

4.2 AI-Assisted Analysis

4.2.1 Power Tree Overview

4.2.2 TPS7A2033DQNR LDO (U9)

4.2.3 Load Current and Thermal Headroom

4.2.4 USB Port Protection and Rail Derating

4.3 Observations

4.4 Findings

4.5 Citations

5 Connector Pinouts

5.1 J1 USB4145-03-0230-C

6 Indicator Documentation

7 Switch Documentation

8 Low-Speed Serial Interfaces (LSSI)

8.1 I2C

8.2 SPI

8.3 SWD

8.4 LSSI DFT Analysis

9 High-Speed Serial Interfaces (HSSI)

9.1 Differential Pairs

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Interface on the Type-C Receptacle J1

9.2.2 ESD Protection and Its Position in the Pair

9.3 Observations

9.4 Findings

9.5 Citations

10 Memory Interface Analysis

10.1 U6 QSPI

10.2 Programming Access Verification

10.3 AI-Assisted Analysis

10.3.1 Serial NOR Flash U6 (W25Q128JVPIQ) — interface and topology

10.3.2 Flash configuration pins, reset and chip-select biasing

10.3.3 Flash supply decoupling and rail ratings

10.3.4 Test access and in-system programming

10.4 Observations

10.5 Findings

10.6 Citations

11 Functional Analysis

11.1 Functional Analysis

11.1.1 MCXA156VMP microcontroller (U1) — supplies, boot strap and interfaces

11.1.2 IIM-42352 inertial sensor (U3)

11.1.3 PRTR5V0U2X ESD protection array (U5)

11.1.4 Type-C Configuration Channel, SBU and VBUS

11.2 Findings

11.3 Citations

12 Designer Annotated Nets

13 EMC & ESD Protection Checks

13.1 Connector Shell Grounding

13.2 ESD/TVS Protection Audit

13.2.1 Unprotected Signal Nets

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture — Grounding, Filtering and Shielding

13.3.2 J1 — USB Type-C Receptacle, High-Speed Pair and Power

13.3.3 J1 — VBUS and Sink Power Entry

13.4 Observations

13.5 Findings

14 Design-for-Test

14.1 DFx Options Selected

14.2 Power Rail Test Point Check

14.3 IC Enable Test Point Check

14.4 Kelvin Test Points Check

14.5 Current Test Points

14.5.1 By Sheet

14.5.2 All Test Points

14.6 Powered-off Testing

11-10080yoshi-mainboardA Design Analysis