PCB Design Analysis

1 Design Summary

out of 100

Design Type	Flat (1 sheets)
Total Components	71
Total Pins	374
Total Nets	67
Total Test Points	0

Improve your score:

Improve fault coverage (opens/shorts) +13
Improve JTAG/I2C/SPI bus accessibility +4
Add I2C pull-up resistors +4
Add test points on power rails +1
Add test points on indicator signals +1
Add test points on switch signals +1
Move component values to VALUE property +1
Use IPC-compliant footprint names +1

AI findings to review:

Power findings — 4 Medium, 1 Low
HSSI findings — 2 Low
Memory findings — 1 Low
Functional findings — 2 High, 1 Medium, 2 Low
EMC/ESD findings — 3 Medium, 2 Low
Devices without datasheet data

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. Rate any finding's accuracy with the thumbs in the table toolbar (select rows first); click a severity badge to mark a finding resolved or invalid — your team sees the same status.

Based on user-selected TP insertion settings, 8 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

The test point count is unusually high because Optical (AOI) and X-ray (AXI) inspection contributes no coverage — none of the footprint names are recognized as IPC-7351B or IPC-7251 compliant. Repair the library footprint names to follow IPC naming and resubmit; the test point count will drop to typical levels.

1.1 Design Overview

AI-Assisted — This board is a single-sheet, battery- and supercapacitor-powered sub-GHz wireless sensor node built around an STMicroelectronics STM32L052C8Tx Arm Cortex-M0+ microcontroller (64 KB Flash, 8 KB RAM, LQFP-48) and a Semtech SX1262 150–960 MHz long-range LoRa transceiver capable of +22 dBm output.

Processing and memory. The STM32L052 acts as system host and communicates with the SX1262 over a 4-wire SPI link (CLK/MOSI/MISO with NSS), and with a Winbond W25Q32JV 32-Mbit (4 MiB) serial Flash over the same SPI bus using a dedicated chip select. A 24.000 MHz AT-cut crystal (Y1, Vectron VXM7A-9001 family) provides the transceiver reference; pins 2 and 4 of that package are the grounded cover.

Radio front end. The SX1262 transmit and receive paths run through a Johanson 0900FM15K0039 868/915 MHz impedance-matched filter (FL1) and a Peregrine PE4259 SPDT DC–9 GHz RF switch (U9) to the antenna terminal AE1, with the receive path using the differential RFI_P/RFI_N port. The DC-DC switcher and PA regulator nodes use external inductors as required by the SX1262.

Sensing and host I/O. Two environmental sensors share an I²C bus to the MCU: a Sensirion SHT4x humidity/temperature sensor (±1.8 %RH, ±0.2 °C typ) and an ST LPS25HB 260–1260 hPa absolute pressure sensor. Additional analog inputs include a light-dependent resistor (R15) and an NTC thermistor (TH1). General-purpose I/O and a 4-pin SWD debug interface (J2) are broken out on pin headers J2–J4.

USB and protection. A 16-pin USB 2.0 Type-C receptacle (J1) provides the VBUS input and the USB D+/D- data pair to the MCU; an ST USBLC6-2P6 (U3) provides IEC 61000-4-2 Level 4 ESD protection on the data lines, rated to 15 kV contact/air discharge per its datasheet.

Power tree. VBUS (5 V) from the Type-C connector feeds two regulators. A Diodes AP2112K-3.3 LDO (U4) generates the +3V3 system rail from VBUS, with 250 mV typical dropout at 600 mA and ±1.5 % output accuracy. A Texas Instruments BQ25176J (BQ25173) 800-mA linear supercapacitor/cell charger (U5) takes the +5V input and produces the +BATT rail at its OUT pin, with a Keystone 18650 holder (BT1) on the same node and charge current set by the ISET resistor. A 3-pin header (J5) selects the power source. The resolved rails are +3V3 (sourced by U4 VOUT), +BATT (sourced by U5 OUT), +5V, VBUS and GND. Rail-level voltage monitoring is provided by a divider (R10/R9, ratio 0.248) from +BATT into a STM32L052 ADC input.

Temperature. The narrowest device operating ranges set the system envelope: the USB-C receptacle (-30 to +85 °C) and the SX1262, PE4259, AP2112K and W25Q32JV (each to +85 °C) bound a practical operating window of approximately -30 °C to +85 °C; the sensors and charger extend higher.

Boundary scan. The host MCU uses a 2-wire SWD interface rather than an IEEE 1149.1 TAP, and no boundary-scan models were supplied for any device on this board; device-level boundary-scan testability is therefore addressed in the dedicated Design-for-Test section.

1.2 Processed Sheets

#	Sheet Name
1	PCB.kicad_sch

1.3 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
16 SMT footprints do not follow IPC-7351B naming
4 footprints (connectors, specialty) — compliance unknown
4 footprints could not be classified for inspection

1.4 Incorrect BOM Settings

The following components have part types associated with non-BOM items (fiducials, mounting holes, test pads) but are not marked as excluded from the BOM in the schematic library. The default is parts with reference designators are BOM parts to populate on the PCB, so the "Include in BOM" setting needs to be false either in the component library or overriding within the schematic instance. This affects downstream processes that rely on the BOM or check for populated parts.

RefDes	Part Type	Issue
TP1	TestPoint	Missing BOM exclusion flag
TP2	TestPoint	Missing BOM exclusion flag

1.5 Missing Datasheets

No public datasheet with the required data was found for the following devices. Verify each is a valid manufacturer part number (MPN) — a typo or an internal house number will not match a public datasheet — then re-submit, or include the PDF in the "datasheets" subfolder of the project.

LED

Thermistor_NTC

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	25	C11, C12, C3, C23, C16, C13, C25, C10 (+17 more)	✓
Resistors	Values in VALUE or Resistance	17	R5, R9, R10, R4, R7, R13, R16, R8 (+9 more)	✓
Inductors	Values in VALUE or Inductance	4	L4, L1, L3, L2	✓
Ferrite Beads	Values in VALUE or Impedance	1	FL1	✓
Ferrite Beads	VALUE has no numeric value — it is blank or a placeholder such as the symbol letter ("C", "R"). No electrical value is specified, so BOM queries, value parsing, and AI analysis cannot use it. Set VALUE to a number with units (e.g. 100nF, 10k, 10uH) or a =Property formula pointing at the typed value. (e.g. FB1 VALUE="FerriteBead")	1	FB1
Crystals	Values in VALUE or Frequency	1	Y1	✓

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

4 unconnected pin(s) found:

4 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
U1_19	PB1	Bidirectional	STM32L052C8Tx	-	No net
U1_20	PB2	Bidirectional	STM32L052C8Tx	-	No net
U2_6	DIO3	Bidirectional	SX1262IMLTRT	SX_DIO3
U4_4	NC	Unknown	AP2112K-3.3	-	No net

3.2 Implied/Hidden Net Connections

No components with implied/hidden net connections found.

3.3 Summary

Total NO_ERC markers in design	8
Pins needing attention (warnings)	4
Pins for information only	0

4 Power Overview

Power rails	5
Power management sources identified	2

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
Rail	Voltage	Source	Consumers
+5V	5.00V	J1 External	U3 (USBLC6-2P6), U5 (BQ25176J)
VBUS	5.00V	J5 External	U4 (AP2112K-3.3)
+3V3	3.30V	U4 AP2112K-3.3	U1 (STM32L052C8Tx), U6 (SHT4x), U7 (LPS25HB), U8 (W25Q32JVSS)
+BATT	-	U5 BQ25176J	-
GND	-	J1 External	-

4.1.1 Open-Collector Pull-up Audit

Examined 2 candidate pin(s) on 2 net(s). 2 to verify with destination IC.

Finding	Recommended Action	Severity
Open-collector / open-drain outputs need an external pull-up resistor to a power rail to function. This audit lists pins where a pull-up appears to be missing or where the pin type may not match the schematic library.
U5_5 (STAT) on Net-(D2-K) U5 (BQ25176J) 800-mA Linear Charger for 1- to 4-Cell Supercapacitor, input 3 to 18v, WSON-8 on-board only · library: Open Collector	Information: this net may be missing a pull-up. The destination IC (MCU/FPGA/other) may enable a configurable internal pull-up — verify its datasheet/BSDL. If none, add an external pull-up to a power rail.	Information
U5_6 (PG) on Net-(D1-K) U5 (BQ25176J) 800-mA Linear Charger for 1- to 4-Cell Supercapacitor, input 3 to 18v, WSON-8 on-board only · library: Open Collector	Information: this net may be missing a pull-up. The destination IC (MCU/FPGA/other) may enable a configurable internal pull-up — verify its datasheet/BSDL. If none, add an external pull-up to a power rail.	Information

4.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections.

4.2.1 Power Tree Overview

AI-Assisted — The board draws 5 V from the USB Type-C receptacle J1 (VBUS pins), forming the +5V rail. The 3-pin header J5 ("Power select") selects the input to the VBUS node that feeds the LDO: pin 1 is +5V, pin 3 is +BATT, and the common pin 2 (VBUS) routes the chosen source to U4. U4 (AP2112K-3.3) regulates that input down to the +3V3 system rail, which powers the STM32L052 (U1), the SX1262 transceiver (U2), the SHT4x (U6), LPS25HB (U7), W25Q32 flash (U8) and the PE4259 switch (U9). Separately, +5V feeds U5 (BQ25176J) IN; U5 charges the cell in holder BT1 and forms the +BATT rail. Sequencing is jumper-defined: with USB present, U5 charges the cell and J5 can route either USB or battery to U4; with USB removed, J5 must be on +BATT to keep +3V3 alive. TP1 probes VBUS and TP2 probes +BATT. All supply and ground pins of both power devices have verified DC paths to their named rails and to GND.

4.2.2 AP2112K-3.3 LDO (U4)

AI-Assisted — U4 input sits on VBUS at a nominal 5 V, inside the AP2112 recommended operating range of 2.5–6.0 V (abs max 6.5 V, datasheet page 3). EN is tied to VBUS, so the regulator enables whenever input is present (VEN high threshold 1.5 V, page 4). The typical dropout is 250 mV at 600 mA (page 8), giving ample headroom from 5 V to 3.3 V. The +3V3 rail carries 20.7 µF of ceramic decoupling (4×4.7µF + 1×1µF + 9×100nF), well above the 1.0 µF COUT minimum required for stability (page 2); the input is bypassed by C1 1µF on VBUS, meeting the 1.0 µF CIN recommendation. Pin 4 (NC) is unconnected, matching the datasheet instruction "No connection — do not connect."

4.2.3 BQ25176J Cell Charger (U5)

AI-Assisted — U5 (orderable BQ25176J, BQ2517x linear charger family) runs from +5V into IN, within the 3.0–18 V operating range (datasheet page 4); OUT forms +BATT with C13 1µF, meeting the 1 µF COUT minimum, and IN is bypassed by C12 1µF meeting the 1 µF CIN minimum (page 4). ISET resistor R7 600Ω programs the fast-charge current: ICHG = KISET/RISET = 300 AΩ / 600 Ω = 500 mA (KISET typ, page 6), inside the 375 Ω–30 kΩ range and above the 350 Ω short threshold. The datasheet recommends a ±1% ISET resistor to bound charge-current error. The regulation voltage is set by R8 35.7k on the ~VSET pin per the device's VSET-resistor table, which is not in the verified data, so the configured target voltage cannot be computed here. Both open-collector outputs are pulled to the charger's own +BATT output through 10 kΩ series resistors and indicator LEDs — STAT through R6/D2 and ~PG through R5/D1 — which is the correct pull-up arrangement for an OC status output (the sink transistor drives low on fault regardless of rail level). STAT/~PG VOL is 0.4 V at 5 mA sink (page 7), and 10 kΩ keeps sink current well under the 5 mA limit.

4.3 Observations

AI-Assisted — The STM32 VDDA pin is fed through L1 3.3µH from +3V3 but its net contains no capacitor to GND, so the LC filter is incomplete and the analog supply has no local bypass — add a 100 nF (and ideally 1 µF) capacitor at the VDDA node. The BQ25176J is a supercapacitor charger (constant-current then constant-voltage to VREG with no current-termination threshold); if BT1 holds a Li-ion 18650 rather than a supercapacitor, the absence of termination should be weighed against the cell's charge profile. The +BATT battery voltage was not specified; passive ratings on that rail (C13, R10) should be checked against the actual cell voltage. The +BATT monitor divider R10 100k / R9 33k (ratio 0.248) presents 1.04 V to PA0 at a 4.2 V cell, well within the STM32 ADC input range. The SX1262 supply pins sit on +3V3, inside the 1.8–3.7 V operating window (abs max 3.9 V), with its DC-DC node decoupled by C17 470nF through L2 15µH. All capacitors on the power rails are ceramic; no polarized parts are present, so there are no orientation risks.

4.4 Findings

AI-Assisted —

Device	Rail	Observation	Severity
U5 (BQ25176J)	+BATT	Regulation voltage set by ~VSET R8 35.7k per device table not in verified data; configured output cannot be computed	Medium
U5 (BQ25176J)	+BATT	Supercapacitor charger with no charge-current termination feeding a single-cell 18650 holder; weigh against cell charge profile (BQ2517x datasheet device description)	Medium
U1 (STM32L052)	Net-(U1-VDDA)	VDDA fed through L1 3.3µH with no capacitor to GND at the pin; LC filter incomplete, no local bypass	Medium
BT1 / +BATT	+BATT	Battery voltage not specified; verify C13/R10 voltage ratings against actual cell voltage	Medium
U5 (BQ25176J)	+BATT	ISET R7 600Ω programs ICHG = 300/600 = 500 mA; ±1% resistor recommended (BQ2517x datasheet p.6/p.12)	Low
U4 (AP2112K-3.3)	VBUS/+3V3	Input on VBUS ~5 V within 2.5–6.0 V operating range; EN tied to VBUS enables device (AP2112 datasheet p.3/p.4)	✓
U4 (AP2112K-3.3)	+3V3	Output decoupling 20.7 µF ceramic exceeds 1.0 µF COUT minimum (AP2112 datasheet p.2)	✓
U4 (AP2112K-3.3)	VBUS	Input cap C1 1µF meets 1.0 µF CIN recommendation (AP2112 datasheet p.2)	✓
U4 (AP2112K-3.3)	+3V3	Dropout 250 mV typ at 600 mA; 5 V→3.3 V headroom adequate (AP2112 datasheet p.8)	✓
U4 (AP2112K-3.3)	—	Pin 4 (NC) left unconnected per datasheet "do not connect" (AP2112 datasheet pin table)	✓
U5 (BQ25176J)	+5V	IN ~5 V within 3.0–18 V operating range (BQ2517x datasheet p.4)	✓
U5 (BQ25176J)	+BATT	Output cap C13 1µF meets 1 µF COUT minimum (BQ2517x datasheet p.4)	✓
U5 (BQ25176J)	+5V	Input cap C12 1µF meets 1 µF CIN minimum (BQ2517x datasheet p.4)	✓
U5 (BQ25176J)	+BATT	STAT OC output pulled to +BATT via R6 10k and LED D2; valid pull-up to output rail (BQ2517x datasheet p.3/p.7)	✓
U5 (BQ25176J)	+BATT	~PG OC output pulled to +BATT via R5 10k and LED D1; valid pull-up to output rail (BQ2517x datasheet p.3/p.7)	✓
U1 (STM32L052)	+BATT	Monitor divider R10 100k / R9 33k ratio 0.248 gives 1.04 V at 4.2 V cell, within STM32 ADC range	✓
U2 (SX1262)	+3V3	Supply pins 3.3 V within 1.8–3.7 V operating range (abs max 3.9 V); DC-DC node C17 470nF + L2 15µH (SX1262 datasheet p.14/p.35)	✓

4.5 Citations

AI-Assisted —

References
AP2112-3.3 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/AP2112.pdf
BQ25173 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/bq25173.pdf

5 Connector Pinouts

Total connectors

5.1 J1 USB_C_Receptacle_USB2.0_16P

J1 - USB_C_Receptacle_USB2.0_16P
Pin	Pin Name	Net	Notes
A1	GND	GND
A4	VBUS	+5V
A5	CC1	Net-(J1-CC1)
A6	D+	DI+
A7	D-	DI-
A8	SBU1	NC
A9	VBUS	+5V
A12	GND	GND
B1	GND	GND
B4	VBUS	+5V
B5	CC2	Net-(J1-CC2)
B6	D+	DI+
B7	D-	DI-
B8	SBU2	NC
B9	VBUS	+5V
B12	GND	GND
SH	SHIELD	Net-(J1-SHIELD)

5.2 J2 Conn_01x04_Pin (SWD)

J2 - Conn_01x04_Pin (SWD)
Pin	Pin Name	Net	Notes
1	Pin_1	SWDIO
2	Pin_2	SWCLK
3	Pin_3	NRST
4	Pin_4	GND

5.3 J3 Conn_01x12_Pin

J3 - Conn_01x12_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	PA2
2	Pin_2	PA3
3	Pin_3	GND
4	Pin_4	GND
5	Pin_5	GND
6	Pin_6	GND
7	Pin_7	+5V
8	Pin_8	+3V3
9	Pin_9	PB3
10	Pin_10	PB4
11	Pin_11	+5V
12	Pin_12	+3V3

5.4 J4 Conn_01x12_Pin

J4 - Conn_01x12_Pin
Pin	Pin Name	Net	Notes
1	Pin_1	PB5
2	Pin_2	+3V3
3	Pin_3	PB8
4	Pin_4	PB9
5	Pin_5	PB10
6	Pin_6	PB11
7	Pin_7	PB12
8	Pin_8	PB13
9	Pin_9	PB14
10	Pin_10	PB15
11	Pin_11	GND
12	Pin_12	GND

5.5 J5 Power select

J5 - Power select
Pin	Pin Name	Net	Notes
1	Pin_1	+5V
2	Pin_2	VBUS
3	Pin_3	+BATT

6 Indicator Documentation

2 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D1	LED	-	Net-(D1-K)	PCB.kicad_sch	LOW = On; R5 (10k); A:Net-(D1-A) K:Net-(D1-K)
D2	LED	-	Net-(D2-K)	PCB.kicad_sch	LOW = On; R6 (10k); A:Net-(D2-A) K:Net-(D2-K)

6.2 Indicator Testability

0 of 2 indicators have test coverage.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D1	Direct	Net-(D1-K)	Design Warning: Test point needed on Net-(D1-K). Drive HIGH to turn on LED D1.
D2	Direct	Net-(D2-K)	Design Warning: Test point needed on Net-(D2-K). Drive HIGH to turn on LED D2.

7 Switch Documentation

1 switch(es) found in design.

7.1 Switch Configurations

SW1 Contact Pairs (SW_Push)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Net-(C11-Pad2)	1	GND	SIGNAL	LOW

SW1 All Pins
Pin #	Pin Name	Net	Paired With	Type
1	1	GND	-	-
2	2	Net-(C11-Pad2)	1	CONTACT

7.2 Switch DFT Analysis

Switches for mode selection are useful for development and manual debug, but production test environments require electrical override capability. Latching switches (DIP) that hold a signal to GND need isolation resistors so ATE can override. Momentary switches (push buttons) don't hold the signal, but ATE still needs test point access to stimulate the signal.

Testpoint and Rs isolation resistor placement

Design Rationale: Switches for mode selection are valuable for engineering development and bench debug. However, production test and field returns require electrical override capability without manual intervention. Adding test points and isolation resistors creates a lifecycle-robust design that works across development, production test, and field returns without requiring procedure documentation or specialized knowledge of switch positions. The goal is a self-documenting, procedure-proof test interface. BOM impact: One 0201/0402 resistor per controlled signal.

Switch	Signal	Function	Pullup	Rail	Issue	Test Point?
SW1	Net-(C11-Pad2)	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access

8 Low-Speed Serial Interfaces (LSSI)

Detected: 1 I2C, 1 SPI | 1 partial

8.1 I2C

I2C: U1 -> U6, U7
Topology: U1 » Targets (U6, U7)
Signal	Net Name	Connector	Test Point	Target Pin
SCL	SCK	(none)	(none)	U1_42 (PB6), U6_2 (SCL), U7_2 (SCL)
SDA	SDA	(none)	(none)	U1_43 (PB7), U6_1 (SDA), U7_4 (SDA)
Address	Target	Industry Type	Description
	U6	SHT4x	Digital Humidity and Temperature Sensor, ±1%RH, ±0.1°C, I2C, 1.08-3.6V, 16bit, DFN-4
	U7	LPS25HB	MEMS nano pressure sensor, 260-1260 hPa, absolute digital output baromeeter, 24 bit, SPI, I2C, 0.01 hPa noise rms, ST_HLGA-10L
Controller	Industry Type	Description
U1	STM32L052C8Tx	STMicroelectronics Arm Cortex-M0+ MCU, 64KB flash, 8KB RAM, 32 MHz, 1.65-3.6V, 37 GPIO, LQFP48

I2C Pull-up Check
Net	Component	Status
SDA	R12, R13	Multiple pull-up resistors found on SDA (R12, R13)
SCK	R11, R14	Multiple pull-up resistors found on SCL (R11, R14)

8.2 SPI

SPI [SX]: U1 -> U2, U8
Topology: U1 » Targets (U2, U8)
Signal	Net Name	Connector	Test Point	Target Pin
MOSI	SX_MOSI	(none)	(none)	U2_17 (MOSI), U8_5 (DI/IO_{0})
MISO	SX_MISO	(none)	(none)	U2_16 (MISO), U8_2 (DO/IO_{1})
SCK	CLK	(none)	(none)	-
Target	Industry Type	Description
U2	SX1262IMLTRT	150 MHz to 960 MHz Low Power Long Range Transceiver, 22dBm output power, spreading factor from 5 to 12, LoRA, QFN-24
U8	W25Q32JVSS	32Mbit / 4MiB Serial Flash Memory, Standard/Dual/Quad SPI, 2.7-3.6V, SOIC-8 (208 mil)
Controller	Industry Type	Description
U1	STM32L052C8Tx	STMicroelectronics Arm Cortex-M0+ MCU, 64KB flash, 8KB RAM, 32 MHz, 1.65-3.6V, 37 GPIO, LQFP48

8.3 Signals That Failed to Trace

These signals appear to be part of LSSI interfaces based on naming patterns, but their endpoints could not be fully traced. The signals were found on test points or connectors but the target IC could not be determined. This may indicate daisy-chained connections (TDO->TDI), signals through resistors, or non-standard naming.

Failed Interface Trace Details
Interface	Target	Found Signals	Trace Path	Missing Signals	Connector	Test Point
SWD	U1	NRST, SWDIO, TCK	NRST: NRST SWDIO: SWDIO TCK: SWCLK	SWCLK	J2_1, J2_2, J2_3	(none)

8.4 LSSI DFT Analysis

8 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
SCL	SCK	(none)	I2C -> U6, U7
SDA	SDA	(none)	I2C -> U6, U7
MISO	SX_MISO	(none)	SPI -> U2, U8
MOSI	SX_MOSI	(none)	SPI -> U2, U8
SCK	CLK	(none)	SPI -> U2, U8
NRST	NRST	J2_3	SWD -> U1
SWDIO	SWDIO	J2_1	SWD -> U1
TCK	SWCLK	J2_2	SWD -> U1

9 High-Speed Serial Interfaces (HSSI)

2 differential pair(s)

Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 1 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
SX_RFI_P/N	DIFF_PAIR

9.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections.

9.2.1 USB 2.0 Full-Speed Interface (J1)

AI-Assisted — J1 is a 16-pin USB 2.0-only Type-C receptacle. The data pair runs from the STM32L052 USB peripheral PA11 (pin 32, USB_DM) and PA12 (pin 33, USB_DP) through the USBLC6-2P6 ESD array U3 (I/O1/I/O2 on both faces) to the connector D+/D- contacts (J1 A6/B6 and A7/B7, with the two A/B pairs strapped for cable-flip support). The STM32L052 integrates a USB full-speed (12 Mbps) device controller, so this is a USB 2.0 full-speed link governed by the USB 2.0 specification: 90 ohm differential, DC-coupled with no series AC-coupling capacitors — none are present, which is correct. Device attach is signalled by the internal 1.5 k pull-up on D+ inside the STM32, so no external pull-up is required. U3 is a low-capacitance ESD protector appropriate for the pair. The Type-C receptacle is an impedance-controlled connector suited to this speed. CC1 (J1 A5) and CC2 (J1 B5) each carry a 5.1 k pull-down to GND (R3, R4), the correct Rd value to advertise this board as a USB Type-C sink/UFP. SBU1/SBU2 (J1 A8/B8) are left unconnected, consistent with a USB 2.0-only port. Neither the STM32L052 nor the USBLC6-2P6 appears in the verified device parameters, so their detailed AC limits were not independently sourced; the topology nonetheless matches standard USB 2.0 full-speed practice. A 90 ohm differential net class on D+/D- is not visible in the provided schematic and should be assigned.

9.2.2 Sub-GHz Radio Front End (SX1262, AE1)

AI-Assisted — The SX1262 transceiver U2 drives a 868/915 MHz sub-GHz RF front end. Its differential receive inputs RFI_P (pin 21) and RFI_N (pin 22) connect to the Johanson 0900FM15K0039 integrated balun/filter FL1, which is the manufacturer-matched part for the SX1261/SX1262 RFI port; the transmit output RFO (pin 23) reaches FL1 through series inductor L3 (47uH net node), with PA supply VR_PA (pin 24) decoupled by C20 and C21 (47nF each). FL1 provides the impedance match plus the harmonic low-pass filter the SX1262 datasheet requires on both RX and TX paths, with typical insertion loss of 1.5 dB RX and 1.1 dB TX. FL1's switched ports SW_RFI and SW_RFO route to the PE4259 SPDT switch U9 (RF2/RF1), whose RFIN feeds the antenna matching network (C22 39pF series, C23/C24 3.3pF shunt, L4) to antenna header AE1. U9 is steered by SX1262 DIO2 (pin 12) through series R17 with C25 1nF on the control node, consistent with SetDIO2AsRfSwitchCtrl operation (DIO2=1 in TX). This is a 50 ohm single-ended RF chain, not an AC-coupled SerDes lane; C22 is part of the match, not a coupling cap. Per the Johanson datasheet, GND-via placement around FL1 is crucial to achieving rated harmonic attenuation — a layout-stage handoff item. The 32 MHz reference crystal Y1 on XTA/XTB supplies the radio clock, using the SX1262 internal trimming capacitors.

9.3 Observations

AI-Assisted — The SX1262 DC-DC mode is wired correctly: DCC_SW (pin 9) drives L2 (15uH) into the VREG node with C17 (470nF) decoupling, matching the datasheet DC-DC distribution option. SX1262 supplies VDD_IN, VBAT and VBAT_IO sit on +3V3, within the 1.8-3.7 V operating window and below the 3.9 V absolute maximum, sharing the bulk +3V3 decoupling bank. Both high-speed paths in this design are low-speed by SerDes standards — a USB 2.0 full-speed link and a sub-GHz RF front end — so no multi-gigabit AC-coupling or equalization concerns apply. The two genuine signal-integrity handoffs are: assign a 90 ohm differential net class to the USB D+/D- pair, and assign 50 ohm controlled impedance with the prescribed ground-via stitching to the RF traces around FL1 and U9, as the Johanson filter's harmonic rejection depends on it.

9.4 Findings

AI-Assisted —

Interface	Protocol	Finding	Severity
USB D+/D- (J1)	USB 2.0 Full-Speed	90 ohm differential controlled-impedance net class for D+/D- is not visible in the provided schematic; assign it before layout per USB 2.0 specification.	Low
RF front-end grounding (FL1)	50 ohm RF chain	Per Johanson 0900FM15K0039 datasheet (page 4), GND-via placement around FL1 is crucial to rated harmonic attenuation and to 50 ohm RF trace impedance; assign at layout.	Low
USB D+/D- (J1)	USB 2.0 Full-Speed	STM32L052 PA11/PA12 route through USBLC6-2P6 U3 to J1 A6/B6, A7/B7; DC-coupled with no series caps, correct per USB 2.0 (no AC coupling at full speed). Internal 1.5k D+ pull-up handles attach. Topology correct.	✓
USB-C CC1/CC2 (J1)	USB Type-C sink	R3, R4 (5.1k) pull-downs to GND on CC1/CC2 provide the correct Rd value advertising a UFP/sink, per USB Type-C specification.	✓
USB ESD (U3)	USB 2.0 Full-Speed	USBLC6-2P6 low-capacitance ESD array placed in-line on the data pair, appropriate for full-speed signalling.	✓
SX1262 RFI_P/RFI_N (U2-FL1)	Sub-GHz LoRa/FSK	Differential receive inputs connect to Johanson 0900FM15K0039 FL1, the manufacturer-matched balun/filter for the SX1261/SX1262 RFI port (datasheet 0900FM15K0039). Correct.	✓
SX1262 RFO (U2-FL1)	Sub-GHz LoRa/FSK	RFO transmit output reaches FL1 via L3 with VR_PA decoupled by C20/C21 (47nF); FL1 provides the required match and harmonic LPF per SX1262 datasheet Rev 1.2. Correct.	✓
RF switch / antenna (U9, AE1)	50 ohm RF chain	PE4259 SPDT U9 selects TX/RX between FL1 SW_RFO/SW_RFI and the antenna matching network (C22 39pF, C23/C24 3.3pF, L4) to AE1; controlled by SX1262 DIO2 via R17, consistent with SetDIO2AsRfSwitchCtrl per SX1262 datasheet.	✓
SX1262 DC-DC (U2)	Power	DCC_SW drives L2 (15uH) into VREG with C17 (470nF) decoupling, matching the SX1262 DC-DC distribution option (datasheet Section 5.1.5).	✓
SX1262 supply (U2)	Power	VDD_IN/VBAT/VBAT_IO on +3V3, within the 1.8-3.7 V operating range and below the 3.9 V absolute maximum per SX1262 datasheet Rev 1.2.	✓
SX1262 reference clock (Y1)	Clock	32 MHz crystal Y1 on XTA/XTB provides the radio reference using the SX1262 internal trimming capacitors per datasheet Rev 1.2.	✓

9.5 Citations

AI-Assisted —

References
0900FM15K0039 (Johanson Technology) — datasheet www.johansontechnology.com/datasheets/0900FM15K0039/0900F...
SX1262 (Semtech) — datasheet cdn.sparkfun.com/assets/6/b/5/1/4/SX1262_datasheet.pdf

10 Memory Interface Analysis

Found 1 complete memory interface(s)

10.1 U8 MICROWIRE

U8 (W25Q32JVSS) - MICROWIRE
Signal	Pin Name	Pin #	Net Name	Test Point
CLOCK	CLK	6	CLK	-
DATA_IN	DI/IO_{0}	5	SX_MOSI	-
DATA_OUT	DO/IO_{1}	2	SX_MISO	-
SELECT	CS	1	SCS	-
DESIGN_WARNING: Test points needed on CLK, SCS, SX_MISO and SX_MOSI for direct on-board programming
This device may be testable or programmable via boundary-scan however analysis to verify each net is controllable could not be done because a BSDL file for the attached device was not provided

10.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections.

10.2.1 Serial Flash Memory (U8, W25Q32JVSS)

AI-Assisted — U8 is a Winbond W25Q32JV 32-Mbit serial flash on the +3V3 rail (3.3 V from the AP2112K-3.3 LDO U4), within the 3.0–3.6 V window that supports the device's full 133 MHz clock rating per the Winbond W25Q32JV datasheet (Rev G). It is wired as a single SPI (1x) slave: CLK, SX_MOSI and SX_MISO are shared with the STM32L052 (U1) and the SX1262 transceiver (U2), while chip select SCS (U1 PA4) is dedicated to U8 and is separate from the transceiver's NSS, so bus arbitration is by chip select as required. IO2 (/WP) and IO3 (/HOLD/RESET) are tied to +3V3, which disables write protect and hold and keeps the device in standard single-bit mode; quad operation is not used. The /CS line SCS has no external pull-up to +3V3; the Winbond datasheet notes /CS must be high to deselect the device, and during MCU reset or boot the PA4 pin floats, so a weak pull-up on SCS is recommended to prevent spurious selection. CLK, SX_MOSI and SX_MISO carry no series source-termination resistors; at the STM32L052 SPI master clock rates this is acceptable for signal integrity. VCC (pin 8) is on +3V3 and GND (pin 4) is on GND, both with valid DC paths. No on-chip DDR test enable pin exists on this device, so no DFT test-enable handling applies.

10.3 Findings

AI-Assisted —

Memory	Interface	Finding	Severity
W25Q32JVSS (U8)	SPI Flash	No pull-up on /CS (SCS) to +3V3; the line floats while the MCU is held in reset or boot, risking spurious device selection. Winbond datasheet requires /CS high to deselect — add a weak pull-up.	Low
W25Q32JVSS (U8)	SPI Flash	VCC supplied from +3V3 (3.3 V, U4 AP2112K-3.3), within the 3.0–3.6 V range that supports 133 MHz operation per Winbond W25Q32JV datasheet Rev G.	✓
W25Q32JVSS (U8)	SPI Flash	Configured for single (1x) SPI: /WP (IO2) and /HOLD/RESET (IO3) tied to +3V3, disabling write protect and hold and preventing dual/quad use — correct for standard SPI per Winbond datasheet.	✓
W25Q32JVSS (U8)	SPI Flash	Chip select SCS (U1 PA4 to U8 /CS) is dedicated and distinct from the SX1262 NSS, giving clean per-slave selection on the shared CLK/MOSI/MISO bus.	✓
W25Q32JVSS (U8)	SPI Flash	No series termination on CLK, SX_MOSI or SX_MISO; acceptable at the STM32L052 SPI master clock rates for this 1x bus.	✓
W25Q32JVSS (U8)	SPI Flash	VCC (pin 8) on +3V3 and GND (pin 4) on GND both have valid DC paths.	✓
W25Q32JVSS (U8)	SPI Flash	Device has no DDR connectivity test-enable pin; no boundary-scan TEN handling applies.	✓

10.4 Citations

AI-Assisted —

References
W25Q32JV (Winbond Electronics Corporation) — datasheet www.winbond.com/resource-files/w25q32jv%20revg%2003272018...

11 Functional Analysis

11 device(s) to review across 5 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
Y1	CRYSTAL	Crystal_GND24	Four pin crystal, GND on pins 2 and 4	-	-
BT1	DEVICE	V	Single-cell battery	-	-
TH1	DEVICE	Thermistor_NTC	Temperature dependent resistor, negative temperature coefficient	-	-
U1	DEVICE	STM32L052C8Tx	STMicroelectronics Arm Cortex-M0+ MCU, 64KB flash, 8KB RAM, 32 MHz, 1.65-3.6V, 37 GPIO, LQFP48	I2C, SPI [SX], SWD (partial)	-
U3	DEVICE	USBLC6-2P6	Very low capacitance ESD protection diode, 2 data-line, SOT-666	-	-
U9	DEVICE	PE4259	SPDT DC-9GHz switch	-	-
D1	DIODE	LED	Light emitting diode	-	-
D2	DIODE	LED	Light emitting diode	-	-
U6	SENSOR	SHT4x	Digital Humidity and Temperature Sensor, ±1%RH, ±0.1°C, I2C, 1.08-3.6V, 16bit, DFN-4	I2C	-
U7	SENSOR	LPS25HB	MEMS nano pressure sensor, 260-1260 hPa, absolute digital output baromeeter, 24 bit, SPI, I2C, 0.01 hPa noise rms, ST_HLGA-10L	I2C	-
U2	WIRELESS	SX1262IMLTRT	150 MHz to 960 MHz Low Power Long Range Transceiver, 22dBm output power, spreading factor from 5 to 12, LoRA, QFN-24	SPI [SX]	-

11.1 Functional Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections.

11.1.1 Reference Crystal Y1 and SX1262 Oscillator

AI-Assisted — Y1 is the resolved Vectron VXM7A-9001-24M0000000, a 24.000 MHz fundamental AT-cut crystal, wired to the SX1262 oscillator: pin 1 to XTB and pin 3 to XTA, with the cover pins 2 and 4 grounded as the datasheet requires. The frequency is the problem. The SX1262 datasheet specifies a 32 MHz crystal on XTA/XTB (load caps trimmed internally via the XTA/XTB trim registers). Driving the radio with a 24 MHz reference shifts the synthesizer and all derived RF/timing constants; the part will not tune to the intended sub-GHz channels. A 32 MHz part must be fitted. No external load capacitors are present, which is correct because the SX1262 provides internal trimming caps for its 32 MHz reference; the crystal's 8 pF load and 100 ohm max ESR are compatible with that arrangement once the frequency is corrected.

11.1.2 MCU STM32L052C8Tx (U1)

AI-Assisted — U1 runs from +3V3, well inside its 1.65-3.6 V range, with the four VDD/VDD_USB pins decoupled by the shared 20.7uF on +3V3. BOOT0 is pulled to GND through R1 (10k), selecting main-flash boot, and NRST carries R2 (10k) plus a 100nF cap and the SW1 reset button. The analog supply VDDA reaches the pin only through the series filter inductor L1 (3.3uH) from +3V3; its net carries no local bypass capacitor to ground, so the recommended VDDA decoupling is absent and the LC input lacks the shunt element that makes it effective — add 100nF (and a 1uF) at the VDDA pin. The sensor I2C bus (nets labelled SDA and SCK) and SPI to U2/U8 are wired conventionally; OSC pins PH0/PH1 are left unconnected as intended for internal-clock operation.

11.1.3 USB ESD Protection U3 (USBLC6-2P6)

AI-Assisted — U3 is correctly placed as a series 2-line ESD clamp between the Type-C receptacle and the MCU USB pins: the I/O1 pair (pins 1,6) sits on the D-/DI- line and the I/O2 pair (pins 3,4) on the D+/DI+ line, with GND (pin 2) to GND and VBUS (pin 5) to the +5V VBUS supply. The device is bidirectional, so no orientation concern applies. Its 3.5 pF max capacitance and VRM of 5 V suit USB 2.0 full/high-speed signalling on this rail.

11.1.4 RF Switch U9 (PE4259)

AI-Assisted — U9 supplies from +3V3, at the top of its 1.8-3.3 V operating range and within the 4.0 V absolute max. Pin 6 is tied to VDD, selecting single-pin control mode, so the switch is steered solely by CTRL (pin 4), which is driven from the SX1262 DIO2 RF-switch control output through series R17 (100) and shunt C25 (1nF) — a benign RC well inside the 25 kHz max switching rate, with DIO2 logic levels meeting the 0.7xVDD high threshold. The RF common port RFIN (pin 5) is DC-blocked by series C22 (39pF), and RF1/RF2 route to the FL1 matched balun, satisfying the requirement that all RF ports be DC-blocked. Wiring is consistent with the datasheet.

11.1.5 Status LEDs D1 and D2

AI-Assisted — D1 and D2 are indicator LEDs driven by the BQ25173 charger open-drain outputs: D1 cathode to the /PG pin and D2 cathode to STAT, each anode fed from +BATT through a 10k resistor (R5, R6). The polarity is correct for an open-drain sink — the output pulls the cathode low to illuminate. With a 10k series resistor the drive current is only a few tenths of a milliamp, so the LEDs will be very dim; reduce the resistor if visible indication is needed.

11.1.6 Humidity/Temperature Sensor U6 (SHT4x)

AI-Assisted — U6 powers from +3V3, inside its 1.08-3.6 V range, with VSS to GND. The I2C lines (SDA on pin 1, SCL on pin 2) join the shared sensor bus, which carries pull-ups to +3V3 (R12/R13 on data, R11/R14 on clock). The SHT40-AD1B I2C address is fixed at 0x44 and does not conflict with the LPS25HB. The datasheet 100 nF VDD decoupling is provided by the +3V3 ceramic pool. Connection is correct.

11.1.7 Pressure Sensor U7 (LPS25HB)

AI-Assisted — U7 takes VDD and Vdd_IO from +3V3, within its 1.7-3.6 V range, with all GND/return pins (3, 8, 9) grounded. /CS (pin 6) is tied to +3V3, selecting the I2C interface, and SA0 (pin 5) is tied to GND, fixing the I2C address at 0x5C — distinct from the SHT4x at 0x44, so the two share the bus without contention. SDA (pin 4) and SCL (pin 2) join the pulled-up sensor bus. INT_DRDY (pin 7) is left unconnected; the data-ready interrupt is optional and the host can poll, so no fault. The datasheet 100 nF VDD decoupling is supplied from the +3V3 rail.

11.1.8 Battery BT1 and Thermistor TH1

AI-Assisted — BT1, a single-cell 18650 holder, connects its positive terminal to the +BATT rail (the BQ25173 charger OUT) and its negative terminal to GND, so it is the charge target with a 1uF bypass on the rail. TH1, the NTC thermistor, connects pin 1 to the charger TS sense input and pin 2 to GND, providing the temperature-qualification feedback the BQ25173 TS pin expects. Both connections are consistent with the charger's intended topology.

11.1.9 Sub-GHz Transceiver U2 (SX1262IMLTRT)

AI-Assisted — U2 powers VDD_IN (pin 1), VBAT (pin 10) and VBAT_IO (pin 11) from +3V3, inside the 1.8-3.7 V operating range and under the 3.9 V absolute max, with all GND returns (pins 2, 5, 8, 20, 25) grounded; the shared 20.7uF on +3V3 plus the dedicated 470nF on VREG provide decoupling. The DC-DC regulator is implemented per the datasheet: DCC_SW (pin 9) feeds L2 (15uH) into VREG (pin 7), a valid switcher configuration. The crystal reference is the one hard error — XTA (pin 3) and XTB (pin 4) connect to Y1, but Y1 is a 24 MHz part while the SX1262 datasheet mandates a 32 MHz reference; this prevents correct synthesizer tuning and must be corrected (also flagged under Y1). The RF front end is properly built: RFI_P/RFI_N (pins 21/22) drive the FL1 Johanson 0900FM15K0039 matched balun/LPF, and the PA output RFO (pin 23) with PA supply VR_PA (pin 24, bypassed by C20/C21 47nF and choked through L3 47uH) feeds the same matching network onward to the PE4259 antenna switch — matching the reference design. The 4-wire SPI is wired conventionally (NSS, MOSI, MISO, SCK on the labelled buses) with BUSY (pin 14) and NRESET (pin 15) routed to MCU GPIO. DIO2 (pin 12) drives the U9 RF-switch control through R17, the intended SetDIO2AsRfSwitchCtrl use; DIO3 (pin 6) is unused, acceptable since a plain crystal (not a TCXO) is fitted.

11.2 Findings

AI-Assisted —

Device	Finding	Severity
Y1 (Crystal_GND24)	Fitted crystal is 24.000 MHz (Vectron VXM7A 24M datasheet); the SX1262 datasheet requires a 32 MHz reference on XTA/XTB — the radio will not tune correctly. Replace with a 32 MHz part.	High
U2 (SX1262IMLTRT)	XTA/XTB connect to Y1, a 24 MHz crystal, but the Semtech SX1262 datasheet requires a 32 MHz reference — synthesizer cannot tune correctly. Replace Y1 with a 32 MHz part.	High
U1 (STM32L052C8Tx)	VDDA reaches the pin only through series L1 (3.3uH) with no local bypass capacitor to ground on its net; recommended VDDA 100nF/1uF decoupling is absent (ST STM32L052 datasheet).	Medium
D1 (LED)	Cathode to BQ25173 /PG open-drain, anode to +BATT via R5 10k — correct polarity; ~0.2 mA drive gives very dim indication, lower R for brightness.	Low
D2 (LED)	Cathode to BQ25173 STAT open-drain, anode to +BATT via R6 10k — correct polarity; ~0.2 mA drive gives very dim indication, lower R for brightness.	Low
Y1 (Crystal_GND24)	Cover/GND pins 2 and 4 tied to GND, no external load caps needed (SX1262 internal trim caps); load 8 pF / ESR 100 ohm compatible once frequency corrected.	✓
U1 (STM32L052C8Tx)	+3V3 supply within 1.65-3.6 V, BOOT0 pulled low (R1 10k) for flash boot, NRST RC+button correct, bulk decoupling 20.7uF present (ST datasheet).	✓
U3 (USBLC6-2P6)	Series 2-line ESD array correctly placed between Type-C D+/D- and MCU; GND grounded, VBUS on +5V, bidirectional so no orientation issue (ST USBLC6-2 datasheet).	✓
U9 (PE4259)	+3V3 within 1.8-3.3 V range; pin 6 to VDD = single-pin control mode; CTRL from DIO2 via R17/C25; all RF ports DC-blocked (C22 39pF on RFC). Wiring per Peregrine datasheet.	✓
U6 (SHT4x)	+3V3 supply within 1.08-3.6 V, I2C on pulled-up bus, fixed address 0x44 (no conflict), 100nF decoupling present (Sensirion SHT40 datasheet).	✓
U7 (LPS25HB)	+3V3 within 1.7-3.6 V; /CS high selects I2C, SA0 low sets address 0x5C (no conflict with 0x44); INT_DRDY optional/unconnected; decoupling present (ST LPS25HB datasheet).	✓
BT1 (Battery)	18650 cell positive on +BATT (charger OUT), negative to GND with 1uF rail bypass — consistent with BQ25173 charge target.	✓
TH1 (NTC)	Thermistor between charger TS sense input and GND, providing temperature qualification per BQ25173 TS pin.	✓
U2 (SX1262IMLTRT)	VDD_IN/VBAT/VBAT_IO on +3V3 within 1.8-3.7 V operating range (abs max 3.9 V); all GND pins grounded; bulk 20.7uF + 470nF VREG decoupling present (Semtech datasheet).	✓
U2 (SX1262IMLTRT)	DC-DC regulator correctly formed: DCC_SW through L2 15uH to VREG with 470nF — valid SX1262-with-DC-DC option (Semtech datasheet sec 5.1.5).	✓
U2 (SX1262IMLTRT)	RF path uses FL1 (Johanson 0900FM15K0039) matched balun/LPF on RFI_P/N and RFO; VR_PA bypassed by C20/C21 47nF and L3 47uH choke — consistent with reference design.	✓
U2 (SX1262IMLTRT)	4-wire SPI (NSS/MOSI/MISO/SCK) plus BUSY and NRESET routed to MCU GPIO; DIO2 drives PE4259 via R17 (SetDIO2AsRfSwitchCtrl), DIO3 unused with crystal — all per datasheet.	✓

11.3 Citations

AI-Assisted —

References
AP2112-3.3 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/AP2112.pdf
BQ25173 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/bq25173.pdf
VXM7A-9001-24M0000000 (Vectron (a Microchip company)) — datasheet ww1.microchip.com/downloads/aemDocuments/documents/WSG/Pr...
LPS25HB (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/b576f690817a4b33c31ecedd...
PE4259 (Peregrine Semiconductor) — datasheet datasheet.lcsc.com/datasheet/pdf/0ab426dc96a0f17099b51f2f...
SHT40-AD1B (Sensirion) — datasheet download.mikroe.com/documents/datasheets/SHT40%20Datashee...
SX1262 (Semtech) — datasheet cdn.sparkfun.com/assets/6/b/5/1/4/SX1262_datasheet.pdf
USBLC6-2P6 (STMicroelectronics) — datasheet www.st.com/resource/en/datasheet/usblc6-2.pdf
W25Q32JV (Winbond Electronics Corporation) — datasheet www.winbond.com/resource-files/w25q32jv%20revg%2003272018...

12 Designer Annotated Nets

Annotated signals

Designer-placed annotation markers on nets that are not already analyzed as HSSI differential pairs or Memory Bus signals.

Designer Annotations
Net Name	Annotation	Impedance	Notes
D+	Dataline
D-	Dataline

13 EMC & ESD Protection Checks

Checks run	1
Passed	1
Issues found	0

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	0	✓

13.1 EMC & ESD Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections.

13.1.1 EMC Architecture — Grounding, Filtering and Shielding

AI-Assisted — The board uses a single logic ground net (GND) as the common return for the MCU U1, the SX1262 sub-GHz transceiver U2, sensors, flash and the two regulators. A distinct net Net-(J1-SHIELD), annotated CHASSIS_GND, carries the USB-C shell pin SH and bonds to logic GND through ferrite bead FB1 (FB1 pin 1 on the shield net, pin 2 on GND). This is the only place the shield/chassis domain meets logic GND, giving a single-point bond and capturing the shield-bond design intent as a separate net — favourable for EN 61000-6-4/CISPR 11 radiated-emission control because it discourages the layout tool from merging the shell pour into the main plane. The only off-enclosure high-current path is USB VBUS (+5V), filtered locally only by C1 (1µF) at U4 VIN; there is no series common-mode choke or pi-filter on VBUS, so conducted-emission energy from the +3V3 switching loads can couple back onto the cable (assess against EN 61000-6-4). The D+/D- pair passes through ESD device U3 before reaching U1; no series resistors or common-mode choke are present on the differential pair, acceptable for USB 2.0 full-/low-speed but worth review if high-speed signalling is used. The RF chain (U2/FL1/U9/AE1) keeps its return on GND with local RF bypass (C20/C21 47nF on VR_PA), consistent with the SX1261/SX1262 reference.

13.1.2 J1 USB-C Receptacle — External Port ESD

AI-Assisted — J1 is a 16-pin USB 2.0-only Type-C receptacle, a user-accessible external port that must withstand IEC 61000-4-2 contact/air discharge. The differential pair is protected: D+/D- (DI+/DI-) route through U3 (USBLC6-2P6), whose datasheet rates ±15 kV air / ±8 kV contact (IEC 61000-4-2) with low line capacitance suited to USB 2.0. U3 is correctly placed between the connector and the MCU pins PA11/PA12, with its VBUS reference pin on +5V and GND pin on GND; the device is symmetric so no orientation constraint applies. CC1/CC2 carry 5.1k pull-downs (R3, R4 to GND), the correct Rd values presenting the board as a UFP sink per USB Type-C R2.5. SBU1/SBU2 (A8/B8) are unused, consistent with a USB 2.0-only design. VBUS (+5V) is decoupled by C1 (1µF) but has no dedicated VBUS transient clamp; for a consumer-facing port a VBUS TVS warrants investigation, since hot-plug inrush and ESD reach the +5V net and U4/U5 inputs. The shell pin SH is on the dedicated CHASSIS_GND net through ferrite bead FB1 to GND. The schematic captures the shield bond as a separate net; in a plastic enclosure (battery device) the logic GND plane is the only ESD sink and a direct, densely-stitched bond keeps common-mode rise uniform, whereas in a metal/earthed chassis an R||C (1 MΩ || 4.7 nF, ≥2 kV) isolation may be required — enclosure type is not shown.

13.1.3 J2 Debug and J3/J4 GPIO Headers — Internal Interfaces

AI-Assisted — J2 (1x04) carries SWDIO, SWCLK, NRST and GND — an internal debug/programming header, not a user-facing port, so on-board ESD clamps are not expected; NRST is held by R2 with C-network and is not exposed beyond the header. J3 and J4 (1x12 each) break out MCU GPIO, +3V3, +5V and GND to a board-to-board/expansion interface. These are internal pin headers; if any of these signals leave the enclosure, IEC 61000-4-2 immunity should be assessed at the destination, but as internal headers no TVS is mandated. No filtering is present on these lines, which is acceptable for short internal interconnect; long external cabling on J3/J4 would raise radiated-emission and ESD-coupling exposure (EN 61000-6-2/6-4).

13.1.4 J5 Power-Select Header and AE1 Antenna Port

AI-Assisted — J5 (1x03, "Power select") jumpers among +5V (pin 1), VBUS (pin 2) and +BATT (pin 3), selecting the source feeding U4 VIN on VBUS. It is an internal configuration header with no signal lines requiring ESD clamps. AE1 is a sub-GHz antenna terminal driven through balun FL1 (0900FM15K0039) and SPDT switch U9 (PE4259) from SX1262 U2. The antenna node Net-(AE1-A) carries an impedance-matching network (C24 3.3pF to GND, L4) but no DC discharge path or RF ESD clamp; an exposed external antenna is subject to IEC 61000-4-2, so a low-capacitance RF TVS or DC-ground bleed is worth investigation to avoid ESD energy reaching U2 RFI/RFO pins. The RF switch and PA bypassing (C20/C21 47nF, C25 1nF) follow the transceiver reference design.

13.2 Observations

AI-Assisted — The shield-bond architecture is sound at schematic level: J1 shell is isolated on CHASSIS_GND and bonded through FB1, a common-mode ferrite that limits high-frequency shield current onto logic GND (EN 61000-6-4). The remaining cross-cutting risks are: absence of a VBUS transient clamp on the external +5V path; no DC bleed/ESD clamp at the antenna terminal AE1; and unfiltered GPIO breakout on J3/J4 should those leave the enclosure. None of these are wiring errors — they are protection observations under IEC 61000-4-2 and EN 61000-6-2. Capacitor voltage ratings on the +BATT rail (C13 1µF) and +5V rail (C12 1µF) are not stated; for an 18650 cell the bus reaches ~4.2 V, so the rated voltage of parts on +BATT should be checked against the actual cell voltage.

13.3 Findings

AI-Assisted —

Connector	Finding	Severity
J1	VBUS (+5V) decoupled by C1 (1µF) but has no dedicated transient clamp on this external port; investigate a VBUS TVS for hot-plug/ESD per IEC 61000-4-2.	Medium
AE1	External sub-GHz antenna terminal with matching network (C24 3.3pF, L4) but no DC bleed or RF ESD clamp to ground; investigate low-capacitance RF protection per IEC 61000-4-2. Not flagged as error.	Medium
—	Capacitor voltage ratings on +BATT (C13 1µF) and +5V (C12 1µF) not specified; check against 18650 cell voltage (~4.2 V max). Battery voltage not defined in schematic.	Medium
J1	No series common-mode choke or pi-filter on VBUS (+5V); conducted-emission coupling onto the cable possible — review against EN 61000-6-4 / CISPR 11.	Low
J3/J4	Internal GPIO/power breakout headers, unfiltered. Acceptable for short internal interconnect; if routed off-enclosure, assess ESD/emissions per EN 61000-6-2 / 6-4.	Low
J1	USB 2.0 D+/D- protected by U3 (USBLC6-2P6), placed between receptacle and U1 (PA11/PA12); ±8 kV contact / ±15 kV air per USBLC6-2P6 datasheet, IEC 61000-4-2. Symmetric device, no orientation constraint.	✓
J1	CC1/CC2 terminated with 5.1k pull-downs R3/R4 to GND — correct Rd for a UFP sink per USB Type-C R2.5.	✓
J1	Shell pin SH on dedicated CHASSIS_GND net bonded to logic GND via ferrite bead FB1 — single-point shield bond, design intent captured. Bond strategy (direct vs R\|\|C 1 MΩ\|\|4.7 nF ≥2 kV) depends on enclosure type, which is not shown. Ref: USB Type-C R2.5 §3.2.1, IEC 61000-4-2.	✓
J2	Internal SWD debug header (SWDIO/SWCLK/NRST/GND); not user-facing, on-board ESD clamps not required. IEC 61000-4-2 not applicable to internal debug interface.	✓
J5	Internal power-select header (+5V/VBUS/+BATT) feeding U4 VIN; configuration jumper, no signal-line ESD clamp required.	✓
—	Single logic GND with separate shield net via FB1 supports single-point chassis bond; ground architecture consistent with EN 61000-6-4.	✓

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	All_in_one	Powered-off tests, BSCAN, LSSI (I2C, UART, SPI), discrete digital, powered-on analog
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Bon	Bed-of-nails fixture access to PCB test points
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	Yes	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	Yes	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.x	IEEE 1149.1-2013 / 1149.6-2015 / 1149.10-2017 full boundary scan suite
LSSI	Yes	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	Yes	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	volume_production	Volume production: fixture-based, AOI/AXI, throughput-optimized

14.2 Power Rail Test Point Check

Power rails found	5
Rails with TPs	2
Rails without TPs	3

3 power rail(s) need test points in the submitted design.

8 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+3V3		-	NEEDS TP
+5V		-	NEEDS TP
+BATT		TP2	✓
GND		-	NEEDS TP
VBUS		TP1	✓

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP3	+3V3	PCB.kicad_sch
TP4	+5V	PCB.kicad_sch
TP5	GND	PCB.kicad_sch
TP6	GND	PCB.kicad_sch
TP7	GND	PCB.kicad_sch
TP8	GND	PCB.kicad_sch
TP9	GND	PCB.kicad_sch
TP10	GND	PCB.kicad_sch

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U4	AP2112K-3.3	EN	3	tied to VCC - recommend pull-up resistor and test point

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.5 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
TestPoint_Pad_D1.0mm	TestPoint	2

14.5.1 By Sheet

Test Point	Net Name	Footprint
PCB (2 test points)
TP1	VBUS	TestPoint_Pad_D1.0mm
TP2	+BATT	TestPoint_Pad_D1.0mm

14.5.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP1	VBUS	PCB	TestPoint_Pad_D1.0mm
TP2	+BATT	PCB	TestPoint_Pad_D1.0mm

14.6 Powered-off Testing

2 nets with test points: 0 pins with opens coverage, 0 pins with partial opens, 11 pins with shorts coverage.

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
BT1_1	+BATT	Passive	-	●
C13_2	+BATT	Capacitor	-	●
J5_3	+BATT	Connector	-	●
R5_1	+BATT	Passive	-	●
R6_1	+BATT	Passive	-	●
R10_2	+BATT	Passive	-	●
U5_8	+BATT	IC	-	●
C1_1	VBUS	Capacitor	-	●
J5_2	VBUS	Connector	-	●
U4_1	VBUS	IC	-	●
U4_3	VBUS	IC	-	●

14.7 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

2 power rail nets with test points: 2 source-path pins (opens + shorts), 11 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
BT1_1	+BATT	Sink	-	●
C13_2	+BATT	Sink	-	●
J5_3	+BATT	Sink	-	●
R5_1	+BATT	Sink	-	●
R6_1	+BATT	Sink	-	●
R10_2	+BATT	Series (U1 → R10)	●	●
TP2_1	+BATT	Sink	-	●
U5_8	+BATT	Source (OUT)	●	●
C1_1	VBUS	Sink	-	●
J5_2	VBUS	Sink	-	●
TP1_1	VBUS	Sink	-	●
U4_1	VBUS	Sink	-	●
U4_3	VBUS	Sink	-	●

14.8 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.8.1 Memory Interconnect

U8 QSPI Flash Interconnect
0/4 signals testable
Net Name	Device Leads	Testability
SX_MISO	U1_16, U2_16, U8_2	Not testable
SX_MOSI	U1_17, U2_17, U8_5	Not testable
SCS	U1_14, U8_1	Not testable
CLK	U1_15, U2_18, U8_6	Not testable

14.9 Inspection

Total: 69 components, 277 of 288 pins with inspection coverage.

14.9.1 AOI

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Package_QFP
LQFP-48_7x7mm_P0.5mm			QFP (Quad Flat Pack)	Footprint	1	48	U1
Package_TO_SOT_SMD
SOT-23-5			SOT (Small Outline Transistor)	Footprint	1	5	U4
Capacitor_SMD
C_0402_1005Metric			Chip Passive	Designator	25	50	C1, C10, C11, C12, C13, C14, C15, C16 ...+17 more
Inductor_SMD
L_0402_1005Metric			Chip Passive	Designator	5	10	FB1, L1, L2, L3, L4
OptoDevice
R_LDR_5.1x4.3mm_P3.4mm_Vertical			Chip Passive	Designator	1	2	R15
RF_Converter
Balun_Johanson_0900FM15K0039			Chip Passive	Designator	1	10	FL1
Resistor_SMD
R_0402_1005Metric			Chip Passive	Designator	16	32	R1, R10, R11, R12, R13, R14, R16, R17 ...+8 more
LED_SMD
LED_0402_1005Metric			SOD (Diode Package)	Designator	2	4	D1, D2
Subtotal: 52 components, 161 pins
Opens only (leads visible, shorts unreliable)
Package_SO
SOIC-8_5.3x5.3mm_P1.27mm			SOIC/SOP	Footprint	1	8	U8
Package_TO_SOT_SMD
SOT-363_SC-70-6			SOIC/SOP	Designator	1	6	U9
SOT-666			SOIC/SOP	Designator	1	6	U3
Subtotal: 3 components, 20 pins
Presence check (manual verification)
Connector_PinHeader_2.54mm
PinHeader_1x03_P2.54mm_Vertical			Connector	Designator	1	3	J5
PinHeader_1x04_P2.54mm_Vertical			Connector	Designator	1	4	J2
PinHeader_1x12_P2.54mm_Vertical			Connector	Designator	2	24	J3, J4
Connector_USB
USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal			Connector	Designator	1	17	J1
Subtotal: 5 components, 48 pins

14.9.2 AXI

Assumed Classification (Non-IPC Footprints)
Hidden-joint classification inferred from Pkg Type property or designator prefix. Footprint names are not IPC-7351B or IPC-7251.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Package_LGA
ST_HLGA-10_2.5x2.5mm_P0.6mm_LayoutBorder3x2y			LGA (Land Grid Array)	Footprint	1	10	U7
Package_DFN_QFN
QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm			QFN/DFN (No-Lead)	Footprint	1	25	U2
Package_SON
WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm			QFN/DFN (No-Lead)	Footprint	1	9	U5
Sensor_Humidity
Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad			QFN/DFN (No-Lead)	Footprint	1	4	U6
Subtotal: 4 components, 48 pins

14.9.3 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
Crystal
Crystal_SMD_3225-4Pin_3.2x2.5mm	Oscillator / Crystal	Designator	1	4	Y1
Battery
BatteryHolder_Keystone_1042_1x18650	Unclassified	Unknown	1	2	BT1
Button_Switch_SMD
SW_Push_SPST_NO_Alps_SKRK	Unclassified	Unknown	1	2	SW1
Connector_PinHeader_2.54mm
PinHeader_1x01_P2.54mm_Vertical	Unclassified	Unknown	1	1	AE1
Resistor_THT
R_Axial_DIN0204_L3.6mm_D1.6mm_P1.90mm_Vertical	Unclassified	Unknown	1	2	TH1
Subtotal: 5 components, 11 pins

14.10 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.10.1 Fault Coverage Summary

Fault Coverage Summary (288 pins)
Test Method	Opens	Shorts
X-ray (AXI)	0 (0.0%)	0 (0.0%)
Optical (AOI)	0 (0.0%)	0 (0.0%)
Electrical
Powered-off Testing	2 (0.7%)	11 (3.8%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	7 (2.4%)	7 (2.4%)
Total	46 (16.0%)	139 (48.3%)
Total Fault Coverage	46 (16.0%)	139 (48.3%)
No coverage	242 (84.0%)	149 (51.7%)

14.10.2 Uncovered Pins (149)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
R5_2	Net-(D1-A)
AE1_1	Net-(AE1-A)
C11_2	Net-(C11-Pad2)
D1_1	Net-(D1-K)
D1_2	Net-(D1-A)
J3_2	PA3
J3_1	PA2
J3_10	PB4
J3_9	PB3
L4_1	Net-(C22-Pad1)
L4_2	Net-(AE1-A)
R9_2	BS
C23_1	Net-(C22-Pad1)
R10_1	BS
R4_1	Net-(J1-CC2)
SW1_2	Net-(C11-Pad2)
U4_4
C25_1	Net-(U9-CTRL)
R7_2	Net-(U5-ISET)
U3_1	DI-
U3_4	D+
U3_3	DI+
U3_6	D-
J4_3	PB8
J4_8	PB13
J4_4	PB9
J4_1	PB5
J4_5	PB10
J4_6	PB11
J4_7	PB12
J4_10	PB15
J4_9	PB14
R13_2	SDA
R16_2	LDR
L1_1	Net-(U1-VDDA)
R8_2	Net-(U5-VSET)
R2_1	Net-(C11-Pad2)
D2_1	Net-(D2-K)
D2_2	Net-(D2-A)
R3_1	Net-(J1-CC1)
L3_1	SX_VR_PA
L3_2	SX_RFO
R14_1	SCK
R17_1	SX_DIO2
R17_2	Net-(U9-CTRL)
U7_2	SCK
U7_4	SDA
U7_7
TH1_1	TS
R12_1	SDA
C21_2	SX_VR_PA
U1_6
U1_12	PA2
U1_9	Net-(U1-VDDA)
U1_13	PA3
U1_14	SCS
U1_30	SX_DIO1
U1_3
U1_11	LDR
U1_5
U1_25	PB12
U1_15	CLK
U1_20
U1_10	BS
U1_29	SX_NSS
U1_2
U1_4
U1_16	SX_MISO
U1_17	SX_MOSI
U1_22	PB11
U1_18	LDR Pwr
U1_26	PB13
U1_21	PB10
U1_27	PB14
U1_28	PB15
U1_32	D-
U1_19
U1_43	SDA
U1_31	SX_BUSY
U1_41	PB5
U1_46	PB9
U1_44	Net-(U1-BOOT0)
U1_42	SCK
U1_33	D+
U1_45	PB8
U1_39	PB3
U1_38	SX_NRST
U1_40	PB4
R1_2	Net-(U1-BOOT0)
R15_2	LDR
R15_1	LDR Pwr
R6_2	Net-(D2-A)
J1_B8
J1_A8
J1_B5	Net-(J1-CC2)
J1_B7	DI-
J1_SH	Net-(J1-SHIELD)
J1_A6	DI+
J1_A7	DI-
J1_A5	Net-(J1-CC1)
J1_B6	DI+
U8_1	SCS
U8_2	SX_MISO
U8_6	CLK
U8_5	SX_MOSI
L2_1	Net-(U2-DCC_SW)
L2_2	Net-(U2-VREG)
Y1_1	SX_XTB
Y1_3	SX_XTA
C17_1	Net-(U2-VREG)
R11_2	SCK
C22_1	Net-(C22-Pad1)
C22_2	Net-(U9-RFIN)
C20_2	SX_VR_PA
C24_1	Net-(AE1-A)
U6_1	SDA
U6_2	SCK
U2_13	SX_DIO1
U2_21	SX_RFI_P
U2_3	SX_XTA
U2_19	SX_NSS
U2_4	SX_XTB
U2_7	Net-(U2-VREG)
U2_6	SX_DIO3
U2_9	Net-(U2-DCC_SW)
U2_12	SX_DIO2
U2_17	SX_MOSI
U2_14	SX_BUSY
U2_16	SX_MISO
U2_18	CLK
U2_15	SX_NRST
U2_22	SX_RFI_N
U2_23	SX_RFO
U2_24	SX_VR_PA
FL1_8	Net-(FL1-SW_RFO)
FL1_1	SX_RFO
FL1_3	SX_RFI_N
FL1_4	SX_RFI_P
FL1_6	Net-(FL1-SW_RFI)
U9_5	Net-(U9-RFIN)
U9_3	Net-(FL1-SW_RFI)
U9_4	Net-(U9-CTRL)
U9_1	Net-(FL1-SW_RFO)
FB1_1	Net-(J1-SHIELD)
U5_2	Net-(U5-ISET)
U5_5	Net-(D2-K)
U5_7	Net-(U5-VSET)
U5_6	Net-(D1-K)
U5_3	TS

14.10.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
R5_1	+BATT	-	●	-	-	-	-
R5_2	Net-(D1-A)	-	-	-	-	-	-
AE1_1	Net-(AE1-A)	-	-	-	-	-	-
C11_1	GND	●	●	-	-	-	-
C11_2	Net-(C11-Pad2)	-	-	-	-	-	-
D1_1	Net-(D1-K)	-	-	-	-	-	-
D1_2	Net-(D1-A)	-	-	-	-	-	-
J3_3	GND	-	●	-	-	-	-
J3_8	+3V3	-	●	-	-	-	-
J3_2	PA3	-	-	-	-	-	-
J3_4	GND	-	●	-	-	-	-
J3_1	PA2	-	-	-	-	-	-
J3_5	GND	-	●	-	-	-	-
J3_6	GND	-	●	-	-	-	-
J3_7	+5V	-	●	-	-	-	-
J3_11	+5V	-	●	-	-	-	-
J3_10	PB4	-	-	-	-	-	-
J3_12	+3V3	-	●	-	-	-	-
J3_9	PB3	-	-	-	-	-	-
L4_1	Net-(C22-Pad1)	-	-	-	-	-	-
L4_2	Net-(AE1-A)	-	-	-	-	-	-
C12_2	+5V	-	●	-	-	-	-
C12_1	GND	-	●	-	-	-	-
R9_1	GND	●	●	-	-	-	-
R9_2	BS	-	-	-	-	-	-
J5_3	+BATT	-	●	-	-	-	-
J5_2	VBUS	-	●	-	-	-	-
J5_1	+5V	-	●	-	-	-	-
C3_1	GND	-	●	-	-	-	-
C3_2	+3V3	-	●	-	-	-	-
C23_1	Net-(C22-Pad1)	-	-	-	-	-	-
C23_2	GND	●	●	-	-	-	-
R10_1	BS	-	-	-	-	-	-
R10_2	+BATT	●	●	-	-	-	-
R4_1	Net-(J1-CC2)	-	-	-	-	-	-
R4_2	GND	-	●	-	-	-	-
SW1_1	GND	-	●	-	-	-	-
SW1_2	Net-(C11-Pad2)	-	-	-	-	-	-
C16_1	GND	-	●	-	-	-	-
C16_2	+3V3	-	●	-	-	-	-
U4_5	+3V3	●	●	-	-	-	-
U4_4		-	-	-	-	-	-
U4_1	VBUS	-	●	-	-	-	-
U4_2	GND	-	●	-	-	-	-
U4_3	VBUS	-	●	-	-	-	-
C13_2	+BATT	-	●	-	-	-	-
C13_1	GND	-	●	-	-	-	-
C25_1	Net-(U9-CTRL)	-	-	-	-	-	-
C25_2	GND	●	●	-	-	-	-
C10_2	+3V3	-	●	-	-	-	-
C10_1	GND	-	●	-	-	-	-
R7_1	GND	●	●	-	-	-	-
R7_2	Net-(U5-ISET)	-	-	-	-	-	-
U3_5	+5V	-	●	-	-	-	-
U3_1	DI-	-	-	-	-	-	-
U3_2	GND	-	●	-	-	-	-
U3_4	D+	-	-	-	-	-	-
U3_3	DI+	-	-	-	-	-	-
U3_6	D-	-	-	-	-	-	-
J4_3	PB8	-	-	-	-	-	-
J4_8	PB13	-	-	-	-	-	-
J4_2	+3V3	-	●	-	-	-	-
J4_4	PB9	-	-	-	-	-	-
J4_1	PB5	-	-	-	-	-	-
J4_5	PB10	-	-	-	-	-	-
J4_6	PB11	-	-	-	-	-	-
J4_7	PB12	-	-	-	-	-	-
J4_11	GND	-	●	-	-	-	-
J4_10	PB15	-	-	-	-	-	-
J4_12	GND	-	●	-	-	-	-
J4_9	PB14	-	-	-	-	-	-
R13_1	+3V3	●	●	-	-	-	-
R13_2	SDA	-	-	-	-	-	-
R16_1	GND	●	●	-	-	-	-
R16_2	LDR	-	-	-	-	-	-
L1_1	Net-(U1-VDDA)	-	-	-	-	-	-
L1_2	+3V3	●	●	-	-	-	-
R8_1	GND	●	●	-	-	-	-
R8_2	Net-(U5-VSET)	-	-	-	-	-	-
J2_3	NRST	●	◐	-	-	-	-
J2_1	SWDIO	●	◐	-	-	-	-
J2_2	SWCLK	●	◐	-	-	-	-
J2_4	GND	-	●	-	-	-	-
R2_1	Net-(C11-Pad2)	-	-	-	-	-	-
R2_2	NRST	●	◐	-	-	-	-
D2_1	Net-(D2-K)	-	-	-	-	-	-
D2_2	Net-(D2-A)	-	-	-	-	-	-
R3_1	Net-(J1-CC1)	-	-	-	-	-	-
R3_2	GND	-	●	-	-	-	-
L3_1	SX_VR_PA	-	-	-	-	-	-
L3_2	SX_RFO	-	-	-	-	-	-
R14_1	SCK	-	-	-	-	-	-
R14_2	+3V3	●	●	-	-	-	-
C1_1	VBUS	-	●	-	-	-	-
C1_2	GND	-	●	-	-	-	-
C9_1	+3V3	-	●	-	-	-	-
C9_2	GND	-	●	-	-	-	-
R17_1	SX_DIO2	-	-	-	-	-	-
R17_2	Net-(U9-CTRL)	-	-	-	-	-	-
U7_9	GND	-	●	-	-	-	-
U7_1	+3V3	●	●	-	-	-	-
U7_3	GND	-	●	-	-	-	-
U7_10	+3V3	●	●	-	-	-	-
U7_5	GND	-	●	-	-	-	-
U7_6	+3V3	●	●	-	-	-	-
U7_8	GND	-	●	-	-	-	-
U7_2	SCK	-	-	-	-	-	-
U7_4	SDA	-	-	-	-	-	-
U7_7		-	-	-	-	-	-
C8_2	GND	-	●	-	-	-	-
C8_1	+3V3	-	●	-	-	-	-
TH1_2	GND	-	●	-	-	-	-
TH1_1	TS	-	-	-	-	-	-
R12_1	SDA	-	-	-	-	-	-
R12_2	+3V3	●	●	-	-	-	-
C19_1	GND	-	●	-	-	-	-
C19_2	+3V3	-	●	-	-	-	-
C21_1	GND	●	●	-	-	-	-
C21_2	SX_VR_PA	-	-	-	-	-	-
C15_1	GND	-	●	-	-	-	-
C15_2	+3V3	-	●	-	-	-	-
U1_6		-	-	-	-	-	-
U1_12	PA2	-	-	-	-	-	-
U1_9	Net-(U1-VDDA)	-	-	-	-	-	-
U1_7	NRST	●	◐	-	-	-	-
U1_8	GND	●	●	-	-	-	-
U1_13	PA3	-	-	-	-	-	-
U1_14	SCS	-	-	-	-	-	-
U1_30	SX_DIO1	-	-	-	-	-	-
U1_3		-	-	-	-	-	-
U1_11	LDR	-	-	-	-	-	-
U1_23	GND	●	●	-	-	-	-
U1_5		-	-	-	-	-	-
U1_25	PB12	-	-	-	-	-	-
U1_1	+3V3	●	●	-	-	-	-
U1_15	CLK	-	-	-	-	-	-
U1_20		-	-	-	-	-	-
U1_10	BS	-	-	-	-	-	-
U1_29	SX_NSS	-	-	-	-	-	-
U1_2		-	-	-	-	-	-
U1_4		-	-	-	-	-	-
U1_16	SX_MISO	-	-	-	-	-	-
U1_17	SX_MOSI	-	-	-	-	-	-
U1_22	PB11	-	-	-	-	-	-
U1_24	+3V3	●	●	-	-	-	-
U1_18	LDR Pwr	-	-	-	-	-	-
U1_26	PB13	-	-	-	-	-	-
U1_21	PB10	-	-	-	-	-	-
U1_27	PB14	-	-	-	-	-	-
U1_28	PB15	-	-	-	-	-	-
U1_32	D-	-	-	-	-	-	-
U1_19		-	-	-	-	-	-
U1_36	+3V3	●	●	-	-	-	-
U1_43	SDA	-	-	-	-	-	-
U1_35	GND	●	●	-	-	-	-
U1_37	SWCLK	●	◐	-	-	-	-
U1_31	SX_BUSY	-	-	-	-	-	-
U1_41	PB5	-	-	-	-	-	-
U1_46	PB9	-	-	-	-	-	-
U1_48	+3V3	●	●	-	-	-	-
U1_44	Net-(U1-BOOT0)	-	-	-	-	-	-
U1_42	SCK	-	-	-	-	-	-
U1_33	D+	-	-	-	-	-	-
U1_45	PB8	-	-	-	-	-	-
U1_34	SWDIO	●	◐	-	-	-	-
U1_39	PB3	-	-	-	-	-	-
U1_47	GND	●	●	-	-	-	-
U1_38	SX_NRST	-	-	-	-	-	-
U1_40	PB4	-	-	-	-	-	-
R1_1	GND	●	●	-	-	-	-
R1_2	Net-(U1-BOOT0)	-	-	-	-	-	-
R15_2	LDR	-	-	-	-	-	-
R15_1	LDR Pwr	-	-	-	-	-	-
R6_1	+BATT	-	●	-	-	-	-
R6_2	Net-(D2-A)	-	-	-	-	-	-
J1_B8		-	-	-	-	-	-
J1_A8		-	-	-	-	-	-
J1_B5	Net-(J1-CC2)	-	-	-	-	-	-
J1_B7	DI-	-	-	-	-	-	-
J1_SH	Net-(J1-SHIELD)	-	-	-	-	-	-
J1_B4	+5V	-	●	-	-	-	-
J1_A4	+5V	-	●	-	-	-	-
J1_A9	+5V	-	●	-	-	-	-
J1_B1	GND	-	●	-	-	-	-
J1_A6	DI+	-	-	-	-	-	-
J1_B12	GND	-	●	-	-	-	-
J1_B9	+5V	-	●	-	-	-	-
J1_A1	GND	-	●	-	-	-	-
J1_A7	DI-	-	-	-	-	-	-
J1_A12	GND	-	●	-	-	-	-
J1_A5	Net-(J1-CC1)	-	-	-	-	-	-
J1_B6	DI+	-	-	-	-	-	-
U8_1	SCS	-	-	-	-	-	-
U8_2	SX_MISO	-	-	-	-	-	-
U8_6	CLK	-	-	-	-	-	-
U8_5	SX_MOSI	-	-	-	-	-	-
U8_8	+3V3	-	●	-	-	-	-
U8_4	GND	-	●	-	-	-	-
U8_3	+3V3	-	●	-	-	-	-
U8_7	+3V3	-	●	-	-	-	-
L2_1	Net-(U2-DCC_SW)	-	-	-	-	-	-
L2_2	Net-(U2-VREG)	-	-	-	-	-	-
Y1_1	SX_XTB	-	-	-	-	-	-
Y1_2	GND	-	●	-	-	-	-
Y1_3	SX_XTA	-	-	-	-	-	-
Y1_4	GND	-	●	-	-	-	-
C14_1	+3V3	-	●	-	-	-	-
C14_2	GND	-	●	-	-	-	-
C6_2	+3V3	-	●	-	-	-	-
C6_1	GND	-	●	-	-	-	-
C17_1	Net-(U2-VREG)	-	-	-	-	-	-
C17_2	GND	●	●	-	-	-	-
C2_1	+3V3	-	●	-	-	-	-
C2_2	GND	-	●	-	-	-	-
R11_1	+3V3	●	●	-	-	-	-
R11_2	SCK	-	-	-	-	-	-
C22_1	Net-(C22-Pad1)	-	-	-	-	-	-
C22_2	Net-(U9-RFIN)	-	-	-	-	-	-
BT1_1	+BATT	-	●	-	-	-	-
BT1_2	GND	-	●	-	-	-	-
C18_1	+3V3	-	●	-	-	-	-
C18_2	GND	-	●	-	-	-	-
C20_1	GND	●	●	-	-	-	-
C20_2	SX_VR_PA	-	-	-	-	-	-
C24_1	Net-(AE1-A)	-	-	-	-	-	-
C24_2	GND	-	●	-	-	-	-
U6_1	SDA	-	-	-	-	-	-
U6_2	SCK	-	-	-	-	-	-
U6_3	+3V3	●	●	-	-	-	-
U6_4	GND	-	●	-	-	-	-
U2_13	SX_DIO1	-	-	-	-	-	-
U2_21	SX_RFI_P	-	-	-	-	-	-
U2_3	SX_XTA	-	-	-	-	-	-
U2_19	SX_NSS	-	-	-	-	-	-
U2_2	GND	●	●	-	-	-	-
U2_4	SX_XTB	-	-	-	-	-	-
U2_7	Net-(U2-VREG)	-	-	-	-	-	-
U2_6	SX_DIO3	-	-	-	-	-	-
U2_9	Net-(U2-DCC_SW)	-	-	-	-	-	-
U2_5	GND	●	●	-	-	-	-
U2_1	+3V3	-	●	-	-	-	-
U2_10	+3V3	-	●	-	-	-	-
U2_8	GND	●	●	-	-	-	-
U2_11	+3V3	-	●	-	-	-	-
U2_12	SX_DIO2	-	-	-	-	-	-
U2_17	SX_MOSI	-	-	-	-	-	-
U2_14	SX_BUSY	-	-	-	-	-	-
U2_16	SX_MISO	-	-	-	-	-	-
U2_18	CLK	-	-	-	-	-	-
U2_15	SX_NRST	-	-	-	-	-	-
U2_20	GND	●	●	-	-	-	-
U2_22	SX_RFI_N	-	-	-	-	-	-
U2_23	SX_RFO	-	-	-	-	-	-
U2_25	GND	●	●	-	-	-	-
U2_24	SX_VR_PA	-	-	-	-	-	-
FL1_2	GND	-	●	-	-	-	-
FL1_10	GND	-	●	-	-	-	-
FL1_5	GND	-	●	-	-	-	-
FL1_8	Net-(FL1-SW_RFO)	-	-	-	-	-	-
FL1_1	SX_RFO	-	-	-	-	-	-
FL1_3	SX_RFI_N	-	-	-	-	-	-
FL1_4	SX_RFI_P	-	-	-	-	-	-
FL1_6	Net-(FL1-SW_RFI)	-	-	-	-	-	-
FL1_7	GND	-	●	-	-	-	-
FL1_9	GND	-	●	-	-	-	-
U9_5	Net-(U9-RFIN)	-	-	-	-	-	-
U9_2	GND	●	●	-	-	-	-
U9_3	Net-(FL1-SW_RFI)	-	-	-	-	-	-
U9_4	Net-(U9-CTRL)	-	-	-	-	-	-
U9_1	Net-(FL1-SW_RFO)	-	-	-	-	-	-
U9_6	+3V3	-	●	-	-	-	-
C7_1	+3V3	-	●	-	-	-	-
C7_2	GND	-	●	-	-	-	-
C5_2	+3V3	-	●	-	-	-	-
C5_1	GND	-	●	-	-	-	-
FB1_1	Net-(J1-SHIELD)	-	-	-	-	-	-
FB1_2	GND	-	●	-	-	-	-
U5_1	+5V	-	●	-	-	-	-
U5_2	Net-(U5-ISET)	-	-	-	-	-	-
U5_4	GND	●	●	-	-	-	-
U5_5	Net-(D2-K)	-	-	-	-	-	-
U5_8	+BATT	●	●	-	-	-	-
U5_7	Net-(U5-VSET)	-	-	-	-	-	-
U5_6	Net-(D1-K)	-	-	-	-	-	-
U5_9	GND	●	●	-	-	-	-
U5_3	TS	-	-	-	-	-	-
C4_2	GND	-	●	-	-	-	-
C4_1	+3V3	-	●	-	-	-	-

14.11 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.11.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	43.5%	0.0%	0.0%	3.1%	0.0%	24.1%	16.0%	0.0%
Optical Inspection (AOI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
Combined	43.5%	0.0%	0.0%	3.1%	0.0%	24.1%	16.0%	0.0%

14.11.2 PCB Device/Pin Count

Devices (PCOLA): 69
Pins (SOQ): 288

14.11.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	9321 / 100,000	9.3%
SOQ	13368 / 100,000	13.4%
Combined	11344 / 100,000	11.3%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	9321 / 100,000	13368 / 100,000
Optical/X-ray Inspection	0 / 100,000	0 / 100,000
Combined (max)	9321 / 100,000	13368 / 100,000

14.11.4 PCOLA (69 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
20%	U1	STM32L052C8Tx / LQFP-48_7x7mm_P0.5mm *	IC	◐	○	○	◐	○	LSSI, Powered_Off
10%	R5	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C7	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C11	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C5	4.7uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J3	Conn_01x12_Pin / PinHeader_1x12_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	FB1	FerriteBead / L_0402_1005Metric *	Ferrite	◐	○	○	—	○	Powered_Off
10%	C12	1uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R9	33k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	J5	Power select / PinHeader_1x03_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	C3	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C23	3.3pF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R10	100k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R4	5.1k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	SW1	SW_Push / SW_Push_SPST_NO_Alps_SKRK *	Switch	◐	○	○	○	○	Powered_Off
10%	C16	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U4	AP2112K-3.3 / SOT-23-5 *	IC	◐	○	○	○	○	Powered_Off
10%	C13	1uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C25	1nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C10	4.7uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R7	600 / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	U3	USBLC6-2P6 / SOT-666 *	IC	◐	○	○	○	○	Powered_Off
10%	J4	Conn_01x12_Pin / PinHeader_1x12_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	R13	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R16	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	L1	3.3uH / L_0402_1005Metric *	Inductor	◐	○	○	—	○	Powered_Off
10%	R8	35.7k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R2	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	U5	BQ25176J / WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm *	IC	◐	○	○	○	○	Powered_Off
10%	R3	5.1k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C4	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R14	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C1	1uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C9	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J2	Conn_01x04_Pin / PinHeader_1x04_P2.54mm_Vertical *	Connector	◐	○	○	—	○	Powered_Off
10%	U7	LPS25HB / ST_HLGA-10_2.5x2.5mm_P0.6mm_LayoutBorder3x2y *	IC	◐	○	○	○	○	Powered_Off
10%	C8	4.7uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	TH1	Thermistor_NTC / R_Axial_DIN0204_L3.6mm_D1.6mm_P1.90mm_Vertical *	Other	◐	○	○	○	○	Powered_Off
10%	R12	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	C19	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C21	47nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C15	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R1	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	R6	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	J1	USB_C_Receptacle_USB2.0_16P / USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal *	Connector	◐	○	○	—	○	Powered_Off
10%	U8	W25Q32JVSS / SOIC-8_5.3x5.3mm_P1.27mm *	IC	◐	○	○	○	○	Powered_Off
10%	Y1	Crystal_GND24 / Crystal_SMD_3225-4Pin_3.2x2.5mm *	Other	◐	○	○	○	○	Powered_Off
10%	C14	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C6	4.7uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C17	470nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C2	1uF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R11	10k / R_0402_1005Metric *	Resistor	◐	○	○	—	○	Powered_Off
10%	BT1	Battery_Cell / BatteryHolder_Keystone_1042_1x18650 *	Other	◐	○	○	○	○	Powered_Off
10%	C18	100nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C20	47nF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C24	3.3pF / C_0402_1005Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U6	SHT4x / Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad *	IC	◐	○	○	○	○	Powered_Off
10%	U2	SX1262IMLTRT / QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm *	IC	◐	○	○	○	○	Powered_Off
10%	FL1	0900FM15K0039 / Balun_Johanson_0900FM15K0039 *	Ferrite	◐	○	○	—	○	Powered_Off
10%	U9	PE4259 / SOT-363_SC-70-6 *	IC	◐	○	○	○	○	Powered_Off
0%	AE1	Antenna / PinHeader_1x01_P2.54mm_Vertical *	Other	○	○	○	○	○
0%	D1	LED / LED_0402_1005Metric *	Diode	○	○	○	○	○
0%	L4	47uH / L_0402_1005Metric *	Inductor	○	○	○	—	○
0%	D2	LED / LED_0402_1005Metric *	Diode	○	○	○	○	○
0%	L3	47uH / L_0402_1005Metric *	Inductor	○	○	○	—	○
0%	R17	100 / R_0402_1005Metric *	Resistor	○	○	○	—	○
0%	L2	15uH / L_0402_1005Metric *	Inductor	○	○	○	—	○
0%	C22	39pF / C_0402_1005Metric *	Capacitor	○	○	○	—	○
0%	R15	LDR07 / R_LDR_5.1x4.3mm_P3.4mm_Vertical *	Resistor	○	○	○	—	○

14.11.5 SOQ (288 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
50%	U5_9	GND	◐	●	○
50%	U1_35	GND	◐	●	○
50%	C25_2	GND	◐	●	○
50%	C11_1	GND	◐	●	○
50%	U1_36	+3V3	◐	●	○
50%	U5_8	+BATT	◐	●	○
50%	R7_1	GND	◐	●	○
50%	U5_4	GND	◐	●	○
50%	R14_2	+3V3	◐	●	○
50%	U9_2	GND	◐	●	○
50%	U1_7	NRST	◐	●	○
50%	U1_8	GND	◐	●	○
50%	U2_25	GND	◐	●	○
50%	U2_20	GND	◐	●	○
50%	U2_8	GND	◐	●	○
50%	U2_5	GND	◐	●	○
50%	U7_1	+3V3	◐	●	○
50%	U2_2	GND	◐	●	○
50%	U7_10	+3V3	◐	●	○
50%	U1_23	GND	◐	●	○
50%	U7_6	+3V3	◐	●	○
50%	U6_3	+3V3	◐	●	○
50%	C20_1	GND	◐	●	○
50%	R9_1	GND	◐	●	○
50%	U1_1	+3V3	◐	●	○
50%	U1_24	+3V3	◐	●	○
50%	R11_1	+3V3	◐	●	○
50%	R13_1	+3V3	◐	●	○
50%	C17_2	GND	◐	●	○
50%	R16_1	GND	◐	●	○
50%	R1_1	GND	◐	●	○
50%	C23_2	GND	◐	●	○
50%	U1_47	GND	◐	●	○
50%	R10_2	+BATT	◐	●	○
50%	L1_2	+3V3	◐	●	○
50%	R8_1	GND	◐	●	○
50%	U1_34	SWDIO	◐	●	○
50%	J2_3	NRST	◐	●	○
50%	J2_1	SWDIO	◐	●	○
50%	J2_2	SWCLK	◐	●	○
50%	U4_5	+3V3	◐	●	○
50%	R12_2	+3V3	◐	●	○
50%	U1_48	+3V3	◐	●	○
50%	R2_2	NRST	◐	●	○
50%	U1_37	SWCLK	◐	●	○
50%	C21_1	GND	◐	●	○
17%	R5_1	+BATT	◐	○	○
17%	C4_2	GND	◐	○	○
17%	C19_1	GND	◐	○	○
17%	C19_2	+3V3	◐	○	○
17%	C15_1	GND	◐	○	○
17%	C15_2	+3V3	◐	○	○
17%	J3_3	GND	◐	○	○
17%	J3_8	+3V3	◐	○	○
17%	J1_B4	+5V	◐	○	○
17%	J3_4	GND	◐	○	○
17%	R6_1	+BATT	◐	○	○
17%	J3_5	GND	◐	○	○
17%	J3_6	GND	◐	○	○
17%	J3_7	+5V	◐	○	○
17%	J3_11	+5V	◐	○	○
17%	J1_A4	+5V	◐	○	○
17%	J3_12	+3V3	◐	○	○
17%	J1_A9	+5V	◐	○	○
17%	J1_B1	GND	◐	○	○
17%	J1_B12	GND	◐	○	○
17%	C12_2	+5V	◐	○	○
17%	C12_1	GND	◐	○	○
17%	J1_B9	+5V	◐	○	○
17%	J5_3	+BATT	◐	○	○
17%	J5_2	VBUS	◐	○	○
17%	J5_1	+5V	◐	○	○
17%	C3_1	GND	◐	○	○
17%	C3_2	+3V3	◐	○	○
17%	J1_A1	GND	◐	○	○
17%	J1_A12	GND	◐	○	○
17%	U8_8	+3V3	◐	○	○
17%	R4_2	GND	◐	○	○
17%	SW1_1	GND	◐	○	○
17%	U8_4	GND	◐	○	○
17%	C16_1	GND	◐	○	○
17%	C16_2	+3V3	◐	○	○
17%	U8_3	+3V3	◐	○	○
17%	U4_1	VBUS	◐	○	○
17%	U4_2	GND	◐	○	○
17%	U4_3	VBUS	◐	○	○
17%	C13_2	+BATT	◐	○	○
17%	C13_1	GND	◐	○	○
17%	U8_7	+3V3	◐	○	○
17%	C10_2	+3V3	◐	○	○
17%	C10_1	GND	◐	○	○
17%	Y1_2	GND	◐	○	○
17%	U3_5	+5V	◐	○	○
17%	Y1_4	GND	◐	○	○
17%	U3_2	GND	◐	○	○
17%	C14_1	+3V3	◐	○	○
17%	C14_2	GND	◐	○	○
17%	C6_2	+3V3	◐	○	○
17%	C6_1	GND	◐	○	○
17%	C2_1	+3V3	◐	○	○
17%	J4_2	+3V3	◐	○	○
17%	C2_2	GND	◐	○	○
17%	C4_1	+3V3	◐	○	○
17%	BT1_1	+BATT	◐	○	○
17%	BT1_2	GND	◐	○	○
17%	C18_1	+3V3	◐	○	○
17%	J4_11	GND	◐	○	○
17%	C18_2	GND	◐	○	○
17%	J4_12	GND	◐	○	○
17%	C24_2	GND	◐	○	○
17%	U6_4	GND	◐	○	○
17%	U2_1	+3V3	◐	○	○
17%	U2_10	+3V3	◐	○	○
17%	U2_11	+3V3	◐	○	○
17%	J2_4	GND	◐	○	○
17%	FL1_2	GND	◐	○	○
17%	FL1_10	GND	◐	○	○
17%	FL1_5	GND	◐	○	○
17%	FL1_7	GND	◐	○	○
17%	R3_2	GND	◐	○	○
17%	FL1_9	GND	◐	○	○
17%	U9_6	+3V3	◐	○	○
17%	C7_1	+3V3	◐	○	○
17%	C1_1	VBUS	◐	○	○
17%	C1_2	GND	◐	○	○
17%	C9_1	+3V3	◐	○	○
17%	C9_2	GND	◐	○	○
17%	C7_2	GND	◐	○	○
17%	C5_2	+3V3	◐	○	○
17%	U7_9	GND	◐	○	○
17%	U7_3	GND	◐	○	○
17%	U7_5	GND	◐	○	○
17%	U7_8	GND	◐	○	○
17%	C5_1	GND	◐	○	○
17%	FB1_2	GND	◐	○	○
17%	C8_2	GND	◐	○	○
17%	C8_1	+3V3	◐	○	○
17%	TH1_2	GND	◐	○	○
17%	U5_1	+5V	◐	○	○
0%	R5_2	Net-(D1-A)	○	○	○
0%	AE1_1	Net-(AE1-A)	○	○	○
0%	C11_2	Net-(C11-Pad2)	○	○	○
0%	D1_1	Net-(D1-K)	○	○	○
0%	D1_2	Net-(D1-A)	○	○	○
0%	J3_2	PA3	○	○	○
0%	J3_1	PA2	○	○	○
0%	J3_10	PB4	○	○	○
0%	J3_9	PB3	○	○	○
0%	L4_1	Net-(C22-Pad1)	○	○	○
0%	L4_2	Net-(AE1-A)	○	○	○
0%	R9_2	BS	○	○	○
0%	C23_1	Net-(C22-Pad1)	○	○	○
0%	R10_1	BS	○	○	○
0%	R4_1	Net-(J1-CC2)	○	○	○
0%	SW1_2	Net-(C11-Pad2)	○	○	○
0%	U4_4		○	○	○
0%	C25_1	Net-(U9-CTRL)	○	○	○
0%	R7_2	Net-(U5-ISET)	○	○	○
0%	U3_1	DI-	○	○	○
0%	U3_4	D+	○	○	○
0%	U3_3	DI+	○	○	○
0%	U3_6	D-	○	○	○
0%	J4_3	PB8	○	○	○
0%	J4_8	PB13	○	○	○
0%	J4_4	PB9	○	○	○
0%	J4_1	PB5	○	○	○
0%	J4_5	PB10	○	○	○
0%	J4_6	PB11	○	○	○
0%	J4_7	PB12	○	○	○
0%	J4_10	PB15	○	○	○
0%	J4_9	PB14	○	○	○
0%	R13_2	SDA	○	○	○
0%	R16_2	LDR	○	○	○
0%	L1_1	Net-(U1-VDDA)	○	○	○
0%	R8_2	Net-(U5-VSET)	○	○	○
0%	R2_1	Net-(C11-Pad2)	○	○	○
0%	D2_1	Net-(D2-K)	○	○	○
0%	D2_2	Net-(D2-A)	○	○	○
0%	R3_1	Net-(J1-CC1)	○	○	○
0%	L3_1	SX_VR_PA	○	○	○
0%	L3_2	SX_RFO	○	○	○
0%	R14_1	SCK	○	○	○
0%	R17_1	SX_DIO2	○	○	○
0%	R17_2	Net-(U9-CTRL)	○	○	○
0%	U7_2	SCK	○	○	○
0%	U7_4	SDA	○	○	○
0%	TH1_1	TS	○	○	○
0%	R12_1	SDA	○	○	○
0%	J1_A7	DI-	○	○	○
0%	U1_22	PB11	○	○	○
0%	J1_A5	Net-(J1-CC1)	○	○	○
0%	J1_B6	DI+	○	○	○
0%	U8_1	SCS	○	○	○
0%	U8_2	SX_MISO	○	○	○
0%	U8_6	CLK	○	○	○
0%	U8_5	SX_MOSI	○	○	○
0%	U1_43	SDA	○	○	○
0%	U1_17	SX_MOSI	○	○	○
0%	U1_16	SX_MISO	○	○	○
0%	U1_31	SX_BUSY	○	○	○
0%	L2_1	Net-(U2-DCC_SW)	○	○	○
0%	L2_2	Net-(U2-VREG)	○	○	○
0%	Y1_1	SX_XTB	○	○	○
0%	U1_41	PB5	○	○	○
0%	Y1_3	SX_XTA	○	○	○
0%	U1_46	PB9	○	○	○
0%	U1_4		○	○	○
0%	U1_44	Net-(U1-BOOT0)	○	○	○
0%	U1_42	SCK	○	○	○
0%	U1_33	D+	○	○	○
0%	C17_1	Net-(U2-VREG)	○	○	○
0%	U1_20		○	○	○
0%	U1_45	PB8	○	○	○
0%	U1_2		○	○	○
0%	U1_15	CLK	○	○	○
0%	U1_39	PB3	○	○	○
0%	C22_1	Net-(C22-Pad1)	○	○	○
0%	C22_2	Net-(U9-RFIN)	○	○	○
0%	U1_29	SX_NSS	○	○	○
0%	U1_38	SX_NRST	○	○	○
0%	U1_40	PB4	○	○	○
0%	U1_10	BS	○	○	○
0%	U1_25	PB12	○	○	○
0%	C20_2	SX_VR_PA	○	○	○
0%	C24_1	Net-(AE1-A)	○	○	○
0%	R1_2	Net-(U1-BOOT0)	○	○	○
0%	U6_1	SDA	○	○	○
0%	U6_2	SCK	○	○	○
0%	U1_5		○	○	○
0%	R15_2	LDR	○	○	○
0%	U2_13	SX_DIO1	○	○	○
0%	U2_21	SX_RFI_P	○	○	○
0%	U2_3	SX_XTA	○	○	○
0%	U2_19	SX_NSS	○	○	○
0%	U1_11	LDR	○	○	○
0%	U2_4	SX_XTB	○	○	○
0%	U2_7	Net-(U2-VREG)	○	○	○
0%	U2_6	SX_DIO3	○	○	○
0%	U2_9	Net-(U2-DCC_SW)	○	○	○
0%	U1_3		○	○	○
0%	R15_1	LDR Pwr	○	○	○
0%	U1_18	LDR Pwr	○	○	○
0%	U1_30	SX_DIO1	○	○	○
0%	R6_2	Net-(D2-A)	○	○	○
0%	U2_12	SX_DIO2	○	○	○
0%	U2_17	SX_MOSI	○	○	○
0%	U2_14	SX_BUSY	○	○	○
0%	U2_16	SX_MISO	○	○	○
0%	U2_18	CLK	○	○	○
0%	U2_15	SX_NRST	○	○	○
0%	U1_14	SCS	○	○	○
0%	R11_2	SCK	○	○	○
0%	U2_23	SX_RFO	○	○	○
0%	U1_13	PA3	○	○	○
0%	U2_24	SX_VR_PA	○	○	○
0%	J1_B8		○	○	○
0%	J1_A8		○	○	○
0%	J1_B5	Net-(J1-CC2)	○	○	○
0%	FL1_8	Net-(FL1-SW_RFO)	○	○	○
0%	FL1_1	SX_RFO	○	○	○
0%	FL1_3	SX_RFI_N	○	○	○
0%	FL1_4	SX_RFI_P	○	○	○
0%	FL1_6	Net-(FL1-SW_RFI)	○	○	○
0%	J1_B7	DI-	○	○	○
0%	J1_SH	Net-(J1-SHIELD)	○	○	○
0%	U9_5	Net-(U9-RFIN)	○	○	○
0%	U1_9	Net-(U1-VDDA)	○	○	○
0%	U9_3	Net-(FL1-SW_RFI)	○	○	○
0%	U9_4	Net-(U9-CTRL)	○	○	○
0%	U9_1	Net-(FL1-SW_RFO)	○	○	○
0%	U7_7		○	○	○
0%	U1_26	PB13	○	○	○
0%	U1_21	PB10	○	○	○
0%	U1_27	PB14	○	○	○
0%	J1_A6	DI+	○	○	○
0%	FB1_1	Net-(J1-SHIELD)	○	○	○
0%	U1_28	PB15	○	○	○
0%	U1_32	D-	○	○	○
0%	U5_2	Net-(U5-ISET)	○	○	○
0%	U1_12	PA2	○	○	○
0%	U5_5	Net-(D2-K)	○	○	○
0%	U1_6		○	○	○
0%	U5_7	Net-(U5-VSET)	○	○	○
0%	U5_6	Net-(D1-K)	○	○	○
0%	C21_2	SX_VR_PA	○	○	○
0%	U5_3	TS	○	○	○
0%	U1_19		○	○	○
0%	U2_22	SX_RFI_N	○	○	○

14.11.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Model Quality

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Model Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U3	F	6	0	0	0	0	0	0	0	6	USBLC6-2P6
U2	C	25	7	6	2	5	0	0	1	4	SX1262IMLTRT
U5	C	9	3	3	0	0	2	0	0	1	BQ25176J
U7	C	10	3	3	1	1	0	0	0	2	LPS25HB
U9	C	6	2	1	0	0	0	0	0	3	PE4259
U1	B	48	7	2	0	37	0	0	0	2	STM32L052C8Tx
U4	B	5	3	2	0	0	0	0	0	0	AP2112K-3.3
U6	B	4	2	1	0	1	0	0	0	0	SHT4x
U8	B	8	2	2	0	4	0	0	0	0	W25Q32JVSS

15.1.1 Library Quality Summary

Total ICs evaluated	9
Grade A (excellent)	0 (0.0%)
Grade B (good)	4 (44.4%)
Grade C (fair)	4 (44.4%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	1 (11.1%)
OVERALL LIBRARY QUALITY	B (3.02/4.00)

15.2 Component Library Validation

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (9 models)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
AP2112K-3.3	AP2112K-3.3	-	U4	5	Pwr:3 I:1 ?:1	No Industry Name property - BOM and procurement tools require this field
BQ25176J	BQ25176J	-	U5	9	P:1 Pwr:3 I:3 OC:2	Pin 4 (GND) at same location as pin 9 (GND); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Passive]
LPS25HB	LPS25HB	-	U7	10	P:2 Pwr:3 Bi:1 I:3 O:1	Pin 9 (GND) at same location as pin 3 (GND); Pin 9 (GND) at same location as pin 8 (GND); Pin 3 (GND) at same location as pin 8 (GND); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Passive, GND=Passive]
PE4259	PE4259	-	U9	6	P:3 Pwr:2 I:1	No Industry Name property - BOM and procurement tools require this field
SHT4x	SHT4x	-	U6	4	Pwr:2 Bi:1 I:1	No Industry Name property - BOM and procurement tools require this field
STM32L052C8Tx	STM32L052C8Tx	-	U1	48	P:2 Pwr:7 Bi:37 I:2	Pin 23 (VSS) at same location as pin 35 (VSS); Pin 23 (VSS) at same location as pin 47 (VSS); Pin 35 (VSS) at same location as pin 47 (VSS); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [VSS=Passive, VSS=Passive]
SX1262IMLTRT	SX1262IMLTRT	-	U2	25	P:4 Pwr:7 Bi:5 I:6 O:2 HiZ:1	Pin 2 (GND) at same location as pin 5 (GND); Pin 2 (GND) at same location as pin 8 (GND); Pin 2 (GND) at same location as pin 20 (GND); Pin 2 (GND) at same location as pin 25 (GND); Pin 5 (GND) at same location as pin 8 (GND); Pin 5 (GND) at same location as pin 20 (GND); Pin 5 (GND) at same location as pin 25 (GND); Pin 8 (GND) at same location as pin 20 (GND); Pin 8 (GND) at same location as pin 25 (GND); Pin 20 (GND) at same location as pin 25 (GND); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Passive, GND=Passive, GND=Passive, GND=Passive]
USBLC6-2P6	USBLC6-2P6	-	U3	6	P:6	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [VBUS=Passive, GND=Passive]
W25Q32JVSS	W25Q32JVSS	-	U8	8	Pwr:2 Bi:4 I:2	No Industry Name property - BOM and procurement tools require this field

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Shielded Connector Model Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.4 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
AE1	Antenna	1	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical
FL1	SX1261	10	Footprint	RF_Converter:Balun_Johanson_0900FM15K0039
J1	USB_C_Receptacle_USB2.0_16P	17	Footprint	Connector_USB:USB_C_Receptacle_GCT_USB4105-xx-A_16P_TopMnt_Horizontal
J2	Conn_01x04_Pin	4	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x04_P2.54mm_Vertical
J3	Conn_01x12_Pin	12	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Vertical
J4	Conn_01x12_Pin	12	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Vertical
J5	Power select	3	Footprint	Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical
U1	STM32L052C8Tx	48	Footprint	Package_QFP:LQFP-48_7x7mm_P0.5mm
U2	SX1262IMLTRT	25	Footprint	Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
U3	USBLC6-2P6	6	Footprint	Package_TO_SOT_SMD:SOT-666
U4	AP2112K-3.3	5	Footprint	Package_TO_SOT_SMD:SOT-23-5
U5	BQ25176J	9	Footprint	Package_SON:WSON-8-1EP_2x2mm_P0.5mm_EP0.9x1.6mm
U6	SHT4x	4	Footprint	Sensor_Humidity:Sensirion_DFN-4_1.5x1.5mm_P0.8mm_SHT4x_NoCentralPad
U7	LPS25HB	10	Footprint	Package_LGA:ST_HLGA-10_2.5x2.5mm_P0.6mm_LayoutBorder3x2y
U8	W25Q32JVSS	8	Footprint	Package_SO:SOIC-8_5.3x5.3mm_P1.27mm
U9	PE4259	6	Footprint	Package_TO_SOT_SMD:SOT-363_SC-70-6
Y1	Crystal_GND24	4	Footprint	Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm

15.5 IC Pin Electrical Properties

Unique IC models	9
Total IC instances	9

IC Library Models
Industry Name	Library Name	RefDes	Notes
AP2112K-3.3	AP2112K-3.3	U4
BQ25176J	BQ25176J	U5
LPS25HB	LPS25HB	U7
PE4259	PE4259	U9
SHT4x	SHT4x	U6
STM32L052C8Tx	STM32L052C8Tx	U1
SX1262IMLTRT	SX1262IMLTRT	U2
USBLC6-2P6	USBLC6-2P6	U3
W25Q32JVSS	W25Q32JVSS	U8

15.5.1 AP2112K-3.3 (AP2112K-3.3)

Pin	Pin Name	Electrical
1	VIN	Power In
2	GND	Power In
3	EN	Input
4	NC	Unknown
5	VOUT	Power Out

15.5.2 BQ25176J (BQ25176J)

Pin	Pin Name	Electrical
1	IN	Power In
2	ISET	Input
3	TS	Input
4	GND	Power In
5	STAT	Open Collector
6	PG	Open Collector
7	VSET	Input
8	OUT	Power Out
9	GND	Passive

15.5.3 LPS25HB (LPS25HB)

Pin	Pin Name	Electrical
1	Vdd_IO	Power In
2	SCL	Input
3	GND	Passive
4	SDA	Bidirectional
5	SA0	Input
6	CS	Input
7	INT_DRDY	Output
8	GND	Power In
9	GND	Passive
10	VDD	Power In

15.5.4 PE4259 (PE4259)

Pin	Pin Name	Electrical
1	RF1	Passive
2	GND	Power In
3	RF2	Passive
4	CTRL	Input
5	RFIN	Passive
6	VDD	Power In

15.5.5 SHT4x (SHT4x)

Pin	Pin Name	Electrical
1	SDA	Bidirectional
2	SCL	Input
3	VDD	Power In
4	VSS	Power In

15.5.6 STM32L052C8Tx (STM32L052C8Tx)

Pin	Pin Name	Electrical
1	VDD	Power In
2	PC13	Bidirectional
3	PC14	Bidirectional
4	PC15	Bidirectional
5	PH0	Bidirectional
6	PH1	Bidirectional
7	NRST	Input
8	VSSA	Power In
9	VDDA	Power In
10	PA0	Bidirectional
11	PA1	Bidirectional
12	PA2	Bidirectional
13	PA3	Bidirectional
14	PA4	Bidirectional
15	PA5	Bidirectional
16	PA6	Bidirectional
17	PA7	Bidirectional
18	PB0	Bidirectional
19	PB1	Bidirectional
20	PB2	Bidirectional
21	PB10	Bidirectional
22	PB11	Bidirectional
23	VSS	Power In
24	VDD	Power In
25	PB12	Bidirectional
26	PB13	Bidirectional
27	PB14	Bidirectional
28	PB15	Bidirectional
29	PA8	Bidirectional
30	PA9	Bidirectional
31	PA10	Bidirectional
32	PA11	Bidirectional
33	PA12	Bidirectional
34	PA13	Bidirectional
35	VSS	Passive
36	VDD_USB	Power In
37	PA14	Bidirectional
38	PA15	Bidirectional
39	PB3	Bidirectional
40	PB4	Bidirectional
41	PB5	Bidirectional
42	PB6	Bidirectional
43	PB7	Bidirectional
44	BOOT0	Input
45	PB8	Bidirectional
46	PB9	Bidirectional
47	VSS	Passive
48	VDD	Power In

15.5.7 SX1262IMLTRT (SX1262IMLTRT)

Pin	Pin Name	Electrical
1	VDD_IN	Power In
2	GND	Power In
3	XTA	Bidirectional
4	XTB	Bidirectional
5	GND	Passive
6	DIO3	Bidirectional
7	VREG	Power Out
8	GND	Passive
9	DCC_SW	Power Out
10	VBAT	Power In
11	VBAT_IO	Power In
12	DIO2	Bidirectional
13	DIO1	Bidirectional
14	BUSY	Output
15	RESET	Input
16	MISO	High Impedance
17	MOSI	Input
18	SCK	Input
19	NSS	Input
20	GND	Passive
21	RFI_P	Input
22	RFI_N	Input
23	RFO	Output
24	VR_PA	Power Out
25	GND	Passive

15.5.8 USBLC6-2P6 (USBLC6-2P6)

Pin	Pin Name	Electrical
1	I/O1	Passive
2	GND	Passive
3	I/O2	Passive
4	I/O2	Passive
5	VBUS	Passive
6	I/O1	Passive

15.5.9 W25Q32JVSS (W25Q32JVSS)

Pin	Pin Name	Electrical
1	CS	Input
2	DO/IO_{1}	Bidirectional
3	WP/IO_{2}	Bidirectional
4	GND	Power In
5	DI/IO_{0}	Bidirectional
6	CLK	Input
7	HOLD/RESET/IO_{3}	Bidirectional
8	VCC	Power In