Generated by Tomachie v4.48 2026-08-04 19:49:20
Copyright © 2026 Tomachie LLC. All rights reserved.
Copyright © 2026 Tomachie LLC. All rights reserved.
Icey Design Analysis
1 Design Summary
77
out of 100
Depth of review, as a baseline: 28 verified datasheet parameters applied and 216 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.
| Design Type | Flat (1 sheets) |
| Total Components | 113 |
| Total Pins | 513 |
| Total Nets | 88 |
| Total Test Points | 0 |
Improve your score:
Points deducted for open High/Medium AI findings:
- 1 High, 12 Medium -8
AI findings to review:
AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.
1.1 Design Overview
AI-Assisted —
Icey is a single-sheet, 113-component board built around a Lattice ICE40UP5K-SG48I FPGA (U2) in a 48-pin QFN with exposed pad. The FPGA is the system controller: it owns the QSPI configuration/storage path and the general-purpose I/O fabric that reaches the board's connectors. Configuration and non-volatile storage are provided by a Winbond W25Q128JVSIQ 128 Mbit serial NOR flash (U4) in 8-pin SOIC, operated as a 4-bit QSPI target of U2. Per the Winbond datasheet, the IQ ordering suffix fixes QE=1 and 25 % default output drive strength, so quad mode is available without status-register programming; the part supports up to 133 MHz at 3.0–3.6 V (page 64) and is the industrial −40 °C to +85 °C grade (page 60). The 8-pin SOIC package has no dedicated hardware /RESET pin (Winbond datasheet, pages 9–10).
USB and Host Functions
Two USB interfaces are implemented. An FTDI FT2232HL (U6) in LQFP-64 provides dual high-speed USB-to-UART/FIFO channels with JTAG-capable MPSSE operation, clocked by a 12 MHz crystal (YSX321SL-class X322512MSB4SI, 20 pF, 10 ppm, −40 °C to +85 °C). A Maxim MAX3421EETJ+T (U3) in VQFN-32 adds a SPI-attached USB host/peripheral controller, addressed by U2 as a SPI target, with its own 12 MHz crystal. Four USB differential pairs are present in total, brought out on two 16-pin USB Type-C receptacles (USB1, USB2). VBUS from the Type-C side feeds the board input, protected by a Bourns MF-NSMF020 resettable PTC (0,20 A hold, 0,46 A trip at 23 °C, 24 V max per the Bourns datasheet) and filtered with a Sunlord GZ2012D601TF ferrite bead (600 Ω ±25 % at 100 MHz, 500 mA, 0,30 Ω max DCR).
Storage, Display and User I/O
A SOFNG TF-008 push-type microSD socket (Card1) provides removable storage with a mechanical card-detect switch; the connector is rated 24 V DC, 25 mA per the SOFNG datasheet. Analog video is carried on a 15-position D-Sub VGA connector (DSub1) with RGB, HSYNC/VSYNC and DDC lines driven from FPGA I/O. User interface consists of two TS-1088-AR02016 tactile switches (50 mA at 12 V DC, 0,2 mm travel), three KT-0603R red indicator LEDs and one S4-3528RGBTA-A common-anode RGB LED; per the TZLED datasheet each RGB channel requires its own series current-limiting resistor (page 8), with 30 mA maximum forward current per die. Expansion I/O is presented on a 12-way and an 8-way 2,54 mm pin header (J1, J2); J2 also carries the SPI path shared with the configuration flash. Eight bridged solder jumpers (JP1–JP8) provide strap/option selection, and four plated M3 mounting holes are connected to GND.
Power Tree
The board is bus-powered from VBUS (11 pins). Two fixed LDOs in SOT-223 derive the logic rails: an AMS1117-3.3 (U5) produces the +3V3 rail (51 pins), the dominant rail feeding the FPGA I/O banks, flash, FT2232HL, MAX3421E, SD socket and indicators; an AMS1117-1.2 (U1) produces the +1V2 rail (9 pins) for the iCE40 core supply. Per the Advanced Monolithic Systems AMS1117 datasheet the 3.3 V device holds 3,251–3,349 V at VIN = 4,8 V with typical 1,1 V dropout at 0,8 A and 0,9–1,5 A current limit (pages 2–3); the UMW AMS1117-1.2 datasheet gives 1,176–1,224 V output and 2,1–2,5 A current limit (pages 4–5). Both devices' current capability comfortably exceeds what a 5 V, sub-0,5 A USB-powered logic board of this scale draws, which is benign margin. GND is the common return with 91 pins.
Temperature Rating
The narrowest operating window among the fitted parts is the KT-0603R indicator LED at −30 °C to +85 °C (Kento datasheet, page 3); the FPGA is the industrial "I" grade and the flash, RGB LED and crystals are all specified −40 °C to +85 °C. The board is therefore rated −30 °C to +85 °C ambient.
USB and Host Functions
Two USB interfaces are implemented. An FTDI FT2232HL (U6) in LQFP-64 provides dual high-speed USB-to-UART/
Storage, Display and User I/
A SOFNG TF-008 push-type microSD socket (Card1) provides removable storage with a mechanical card-detect switch; the connector is rated 24 V DC, 25 mA per the SOFNG datasheet. Analog video is carried on a 15-position D-Sub VGA connector (DSub1) with RGB, HSYNC/
Power Tree
The board is bus-powered from VBUS (11 pins). Two fixed LDOs in SOT-223 derive the logic rails: an AMS1117-3.3 (U5) produces the +3V3 rail (51 pins), the dominant rail feeding the FPGA I/
Temperature Rating
The narrowest operating window among the fitted parts is the KT-0603R indicator LED at −30 °C to +85 °C (Kento datasheet, page 3); the FPGA is the industrial "I" grade and the flash, RGB LED and crystals are all specified −40 °C to +85 °C. The board is therefore rated −30 °C to +85 °C ambient.
1.2 Processed Sheets
| # | Sheet Name |
|---|---|
| 1 | Icey.kicad_sch |
1.3 Footprint Compliance
Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.
| Footprint Naming | Status |
|---|---|
| 13 SMT footprints do not follow IPC-7351B naming | |
| 3 footprints (connectors, specialty) — compliance unknown | |
| 3 footprints could not be classified for inspection |
1.4 Incorrect BOM Settings
The following components have part types associated with non-BOM items (fiducials, mounting holes, test pads) but are not marked as excluded from the BOM in the schematic library. The default is parts with reference designators are BOM parts to populate on the PCB, so the "Include in BOM" setting needs to be false either in the component library or overriding within the schematic instance. This affects downstream processes that rely on the BOM or check for populated parts.
| RefDes | Part Type | Issue |
|---|---|---|
| TP3 | TestPoint | Missing BOM exclusion flag |
| TP4 | TestPoint | Missing BOM exclusion flag |
| TP5 | TestPoint | Missing BOM exclusion flag |
| TP6 | TestPoint | Missing BOM exclusion flag |
| TP7 | TestPoint | Missing BOM exclusion flag |
2 Component Value Properties
Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.
| Value Property Check | ||||
|---|---|---|---|---|
| Type | Check | Count | Components | Status |
| Capacitors | Values in VALUE or Capacitance | 37 | C38, C18, C26, C33, C3, C40, C20, C30 (+29 more) | ✓ |
| Resistors | Values in VALUE or Resistance | 36 | R29, R38, R6, R33, R36, R9, R40, R15 (+28 more) | ✓ |
| Inductors | Values in VALUE or Inductance | 2 | L1, L2 | ✓ |
| Fuses | Values in VALUE or Rated Current | 1 | F1 | ✓ |
| Oscillators | Values in VALUE or Frequency | 2 | X1, X2 | ✓ |
3 Pin Connectivity Report
All pins properly connected or marked.
3.1 Implied/Hidden Net Connections
No components with implied/hidden net connections found.
3.2 Open-Collector Pull-up Audit
Examined 0 candidate pin(s) on 0 net(s).
3.3 Summary
| Total NO_ERC markers in design | 53 |
| Pins needing attention (warnings) | 0 |
| Pins for information only | 0 |
4 Power Overview
| Power rails | 4 |
| Power management sources identified | 2 |
Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.
Power architecture overview. For test point coverage, see Design-for-Test section.
4.1 Power Rail Analysis
VBUS: 5 V assumed by USB convention, because a USB connector power pin is on this net. A design that negotiates a higher USB Power Delivery voltage must state the rail's actual nominal, minimum and maximum voltage — preferably recorded in the design itself, otherwise entered when prompted before the AI review starts. Until it is stated, the assumed 5 V is taken as the intended level.
| Power Rails | |||
|---|---|---|---|
| Rail | Voltage | Source | Consumers |
| VBUS | 5.00V | J1 External | U1 (AMS1117-1.2), U5 (AMS1117-3.3) |
| +3V3 | 3.30V | U5 AMS1117-3.3 | U2 (ICE40UP5K-SG48I), U3 (MAX3421EETJ+T), U4 (W25Q128JVSIQ), U6 (FT2232HL-REEL) |
| +1V2 | 1.20V | U1 AMS1117-1.2 | U2 (ICE40UP5K-SG48I) |
| GND | - | J1 External | - |
4.2 AI-Assisted Analysis
This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.
4.2.1 Power Tree Overview
AI-Assisted —
Power enters on VBUS (5.00 V), fed externally through J1 pin 12 and the USB2 receptacle VBUS pins (A4B9, B4A9). F1 (MF-NSMF020-2 resettable PTC) sits between the USB1 receptacle VBUS pins and the VBUS rail, so USB1 is fused while J1 and USB2 connect to VBUS directly and are unfused. VBUS feeds two parallel linear regulators: U1 (AMS1117-1.2) producing +1V2 and U5 (AMS1117-3.3) producing +3V3. There is no sequencing control on either device — both AMS1117 parts are fixed-output three-terminal LDOs with no enable pin, so +1V2 and +3V3 rise together with VBUS, each after its own dropout. With VIN = 5 V, U5 has 1.7 V headroom against a 1.3 V max dropout at 0.8 A (Advanced Monolithic Systems datasheet), and U1 has 3.8 V headroom. Total dissipation is the concern rather than regulation: U5 drops 1.7 V and U1 drops 3.8 V in SOT-223.
Downstream, +3V3 supplies U2 (ICE40UP5K), U3 (MAX3421E), U4 (W25Q128JV), U6 (FT2232HL VCCIO/VREGIN), the microSD socket Card1, and headers J1/J2. +1V2 supplies only the ICE40UP5K VCC core pins (5, 30), with VCCPLL fed from +1V2 through R33 (100 Ω) as an RC filter. U6 generates its own VCORE internally at VREGOUT (pin 49), tied to the VCORE pins 12/37/64. Two ferrite beads L1 and L2 (GZ2012D601TF, 600 Ω @ 100 MHz, 500 mA rated, 0.30 Ω max DCR) filter +3V3 into VPHY and VPLL respectively.
Downstream, +3V3 supplies U2 (ICE40UP5K), U3 (MAX3421E), U4 (W25Q128JV), U6 (FT2232HL VCCIO/
4.2.2 AMS1117-1.2 Core Regulator (U1)
AI-Assisted —
U1 VI (pin 3) is on VBUS, VO (pin 2) drives +1V2, and pin 1 (GND) is on GND — all three terminals have a proper DC path. Being the fixed 1.2 V variant, the ground pin is the reference and no external divider is used, per the UMW datasheet fixed-output configuration.
Output capacitance on +1V2 totals 5.9 µF (4.7 µF + 1 µF + 2×100 nF), plus 4.8 µF on the post-R33 VCCPLL node. The UMW datasheet states a 22 µF tantalum output capacitor is required for device stability; the fitted ceramic total is below that figure, though ceramics of far lower ESR are commonly substituted. The ADJ/GND pin is not bypassed here, which is the condition under which the datasheet allows smaller values. Input side: only C1 (4.7 µF) sits on VBUS against the datasheet's 10 µF input recommendation, and that single capacitor is shared with U5.
Dissipation: at 5 V in and 1.2 V out, each 100 mA of ICE40UP5K core current costs 0.38 W in U1. The core current is not stated in the schematic and cannot be computed from the data.
Capacitor voltage ratings are not stated in the schematic for any part on +1V2 or VBUS; the ratings need to be added as named Voltage properties and weighed against the 5.00 V and 1.20 V rail levels.
Output capacitance on +1V2 totals 5.9 µF (4.7 µF + 1 µF + 2×100 nF), plus 4.8 µF on the post-R33 VCCPLL node. The UMW datasheet states a 22 µF tantalum output capacitor is required for device stability; the fitted ceramic total is below that figure, though ceramics of far lower ESR are commonly substituted. The ADJ/
Dissipation: at 5 V in and 1.2 V out, each 100 mA of ICE40UP5K core current costs 0.38 W in U1. The core current is not stated in the schematic and cannot be computed from the data.
Capacitor voltage ratings are not stated in the schematic for any part on +1V2 or VBUS; the ratings need to be added as named Voltage properties and weighed against the 5.00 V and 1.20 V rail levels.
4.2.3 AMS1117-3.3 System Regulator (U5)
AI-Assisted —
U5 VI (pin 3) is on VBUS, VO (pin 2) drives +3V3, GND (pin 1) is on GND. Fixed 3.3 V trimmed output, 3.251–3.349 V at VIN = 4.8 V and 3.201–3.399 V over the full temperature range (Advanced Monolithic Systems datasheet).
+3V3 carries 21.9 µF of ceramic decoupling (4×4.7 µF + 2×1 µF + 11×100 nF), comfortably distributed across five ICs, the SD socket, and the two headers. The datasheet asks for a 22 µF solid tantalum output capacitor for loop stability under all operating conditions; the fitted ceramic bank reaches essentially that capacitance but with far lower ESR than a tantalum, so the ESR-based stability assumption in the datasheet is not reproduced. Adding one bulk tantalum or polymer capacitor at U5's output pin would restore the documented condition.
Current limit is 900 mA minimum / 1100 mA typical. Loads are the ICE40UP5K I/O banks, MAX3421E, W25Q128JV, FT2232HL (its internal 1.8 V core regulator included), the SD card, and 14 pull-ups of 10 kΩ plus four 510 Ω LED-class resistors — total pull-up draw under 2 mA. The aggregate is well inside the limit, but at 1.7 V drop the SOT-223 package dissipates 0.17 W per 100 mA of load.
The ferrite-filtered branches are correct: VPHY has 1.1 µF and VPLL 100 nF local capacitance, each returned to GND, with L1/L2 well below their 500 mA rating on these sub-50 mA analog supplies.
+3V3 carries 21.9 µF of ceramic decoupling (4×4.7 µF + 2×1 µF + 11×100 nF), comfortably distributed across five ICs, the SD socket, and the two headers. The datasheet asks for a 22 µF solid tantalum output capacitor for loop stability under all operating conditions; the fitted ceramic bank reaches essentially that capacitance but with far lower ESR than a tantalum, so the ESR-based stability assumption in the datasheet is not reproduced. Adding one bulk tantalum or polymer capacitor at U5's output pin would restore the documented condition.
Current limit is 900 mA minimum /
The ferrite-filtered branches are correct: VPHY has 1.1 µF and VPLL 100 nF local capacitance, each returned to GND, with L1/
4.3 Observations
AI-Assisted —
The fuse coordination is the main protection concern. F1 protects the USB1 receptacle path only. The VBUS rail is also driven by J1 pin 12 and by the USB2 receptacle VBUS pins, both on the unfused side, so a fault on the VBUS rail is not cleared by F1 when power arrives from either of those two sources, and the CC pull-ups R40/R44 sit on the unfused USB1 side upstream of nothing protective.
No capacitor, resistor, or ferrite on VBUS, +3V3, or +1V2 carries a stated voltage rating in the schematic. Each rating should be entered in a named Voltage property so BOM and test tools read it; the rail voltages themselves (5.00 V, 3.30 V, 1.20 V) are defined.
Thermally, both LDOs share one input capacitor and one 5 V source. Combined worst-case dissipation from the two SOT-223 packages should be planned into copper area at layout. No ESD/TVS protection is fitted on either USB-C receptacle's VBUS, CC, or data lines, nor on the DSub1 VGA analog outputs; the FPGA I/O and MAX3421E transceiver pins are directly exposed at the connectors.
No capacitor, resistor, or ferrite on VBUS, +3V3, or +1V2 carries a stated voltage rating in the schematic. Each rating should be entered in a named Voltage property so BOM and test tools read it; the rail voltages themselves (5.00 V, 3.30 V, 1.20 V) are defined.
Thermally, both LDOs share one input capacitor and one 5 V source. Combined worst-case dissipation from the two SOT-223 packages should be planned into copper area at layout. No ESD/
4.4 Findings
AI-Assisted —
| # | Device | Rail | Observation | Severity |
|---|---|---|---|---|
| 4.4.1 | F1 (MF-NSMF020-2) | VBUS | F1 is in series with USB1 VBUS only; J1 pin 12 and USB2 VBUS connect to the VBUS rail unfused, so those sources bypass the protection | Medium |
| 4.4.2 | USB1/ | VBUS, data | No ESD/ | Medium |
| 4.4.3 | R40/ | Net-(USB1-CC1/ | CC pull-ups on the USB1 side sit upstream of F1 and are unprotected | Low |
| 4.4.4 | All rails | VBUS/ | No capacitor, resistor, or ferrite on any rail states a voltage rating; add named Voltage properties for BOM/ | Low |
| 4.4.5 | U1 (AMS1117-1.2) | +1V2 | Output capacitance 5.9 µF ceramic vs 22 µF tantalum stated as required for stability (UMW datasheet, p.5/ | Review |
| 4.4.6 | U5 (AMS1117-3.3) | +3V3 | 21.9 µF ceramic output bank meets the capacitance but not the ESR of the 22 µF solid tantalum required for loop stability (Advanced Monolithic Systems datasheet, p.4); recommend one bulk tantalum/ | Review |
| 4.4.7 | U1/ | VBUS | Only C1 (4.7 µF) on the shared input node vs 10 µF ceramic/ | Review |
| 4.4.8 | U5 (AMS1117-3.3) | +3V3 | Load set (U2 banks, U3, U4, U6, Card1, pull-ups) is within the 900 mA minimum current limit; SOT-223 dissipates 0.17 W per 100 mA at 1.7 V drop — plan copper area | Review |
| 4.4.9 | U1 (AMS1117-1.2) | +1V2 | VI on VBUS, VO on +1V2, GND on GND — all terminals have a valid DC path; fixed-output configuration per UMW datasheet, no divider needed | ✓ |
| 4.4.10 | U5 (AMS1117-3.3) | +3V3 | VI on VBUS, VO on +3V3, GND on GND — all terminals correctly connected; fixed 3.3 V trim per Advanced Monolithic Systems datasheet | ✓ |
| 4.4.11 | U1/ | VBUS → +1V2/ | 5 V input gives 3.8 V and 1.7 V dropout headroom, both above the 1.30 V / | ✓ |
| 4.4.12 | L1/ | +3V3 → VPHY/ | 600 Ω @ 100 MHz beads, 500 mA rated, 0.30 Ω max DCR (Sunlord datasheet) — correct pi-filter for FT2232HL analog supplies, current well inside rating | ✓ |
| 4.4.13 | R33 (100 Ω) | +1V2 → Net-(U2-VCCPLL) | RC filter to ICE40UP5K VCCPLL with 4.8 µF local capacitance returned to GND — appropriate PLL supply isolation | ✓ |
| 4.4.14 | U6 (FT2232HL) | VCORE | VREGOUT (pin 49) ties to VCORE pins 12/ | ✓ |
| 4.4.15 | Card1 (TF-008) | +3V3 | Socket rated 24 V DC / | ✓ |
| 4.4.16 | U1/ | VBUS | No enable pins on either LDO; +1V2 and +3V3 rise together with VBUS with no sequencing control — acceptable for this load set | ✓ |
| 4.4.17 | Electrolytic/ | All | No polarized electrolytic or tantalum capacitors fitted; all decoupling is ceramic, so no orientation risk | ✓ |
4.5 Citations
AI-Assisted —
| References |
|---|
| AMS1117-1.2 (UMW) — datasheet datasheet.lcsc.com/datasheet/pdf/33adf36a71e298ca40968a58... |
| AMS1117-3.3 (Advanced Monolithic Systems) — datasheet, cited pages 1 micmodshop.ir/wp-content/uploads/2021/11/AMS1117-DataShee... |
| GZ2012D601TF (Sunlord) — datasheet, cited pages 1,4 GZ2012D601TF.pdf |
| TF-008 (SOFNG ELECTRONIC TECHNOLOGY Co., LTD) — datasheet, cited pages 1,2 datasheet.lcsc.com/datasheet/pdf/995e92cc2257e502563199b3... |
| CBL-VGA-002-12 (WinSystems Inc.) — datasheet resources.winsystems.com/datasheets/cbl-vga-002-12-ds.pdf |
5 Connector Pinouts
| Total connectors | 4 |
5.1 J1 Conn_01x12
| J1 - Conn_01x12 | |||
|---|---|---|---|
| Pin | Pin Name | Net | Notes |
| 1 | Pin_1 | IOT_42b | |
| 2 | Pin_2 | IOT_43a | |
| 3 | Pin_3 | IOT_44b | |
| 4 | Pin_4 | IOT_46b_G0 | |
| 5 | Pin_5 | IOT_48b | |
| 6 | Pin_6 | IOT_45a_G1 | |
| 7 | Pin_7 | IOT_50b | |
| 8 | Pin_8 | IOT_51a | |
| 9 | Pin_9 | IOT_49a | |
| 10 | Pin_10 | GND | |
| 11 | Pin_11 | +3V3 | |
| 12 | Pin_12 | VBUS | |
5.2 J2 Conn_01x08 (SPI)
| J2 - Conn_01x08 (SPI) | |||
|---|---|---|---|
| Pin | Pin Name | Net | Notes |
| 1 | Pin_1 | CS | |
| 2 | Pin_2 | SCK | |
| 3 | Pin_3 | MOSI | |
| 4 | Pin_4 | MISO | |
| 5 | Pin_5 | FLASH_WP | |
| 6 | Pin_6 | FLASH_HOLD | |
| 7 | Pin_7 | +3V3 | |
| 8 | Pin_8 | GND | |
5.3 USB1 TYPE-C 16PIN 2MD(073)
| USB1 - TYPE-C 16PIN 2MD(073) (TYPE-C 16PIN 2MD(073)) | |||
|---|---|---|---|
| Pin | Pin Name | Net | Notes |
| 13 | EH | GND | |
| 14 | EH | GND | |
| A1B12 | GND | GND | |
| A4B9 | VBUS | Net-(USB1-VBUS) | |
| A5 | CC1 | Net-(USB1-CC1) | |
| A6 | Dp1 | PER_D+ | |
| A7 | Dn1 | PER_D- | |
| A8 | SBU1 | NC | |
| B1A12 | GND | GND | |
| B4A9 | VBUS | Net-(USB1-VBUS) | |
| B5 | CC2 | Net-(USB1-CC2) | |
| B6 | Dp2 | PER_D+ | |
| B7 | Dn2 | PER_D- | |
| B8 | SBU2 | NC | |
5.4 USB2 TYPE-C 16PIN 2MD(073)
| USB2 - TYPE-C 16PIN 2MD(073) (TYPE-C 16PIN 2MD(073)) | |||
|---|---|---|---|
| Pin | Pin Name | Net | Notes |
| 13 | EH | GND | |
| 14 | EH | GND | |
| A1B12 | GND | GND | |
| A4B9 | VBUS | VBUS | |
| A5 | CC1 | Net-(USB2-CC1) | |
| A6 | Dp1 | PROG_D+ | |
| A7 | Dn1 | PROG_D- | |
| A8 | SBU1 | NC | |
| B1A12 | GND | GND | |
| B4A9 | VBUS | VBUS | |
| B5 | CC2 | Net-(USB2-CC2) | |
| B6 | Dp2 | PROG_D+ | |
| B7 | Dn2 | PROG_D- | |
| B8 | SBU2 | NC | |
6 Indicator Documentation
4 indicator device(s) found.
6.1 Indicator Assignments
| Indicators | |||||
|---|---|---|---|---|---|
| RefDes | Type | Color | Signal | Sheet | Notes |
| LED1 | KT-0603R | - | Net-(LED1-A) | Icey.kicad_sch | HIGH = On; R32 (510); A:Net-(LED1-A) K:GND |
| LED2 | KT-0603R | - | CDONE | Icey.kicad_sch | LOW = On; R21 (10K); A:Net-(LED2-A) K:CDONE |
| LED3 | KT-0603R | - | Net-(LED3-K) | Icey.kicad_sch | LOW = On; R18 (270); A:+3V3 K:Net-(LED3-K) |
| LED4 | S4-3528RGBTA-A | RGB | RGB1 | Icey.kicad_sch | No current-limiting resistor |
6.2 Indicator Testability
0 of 4 indicators have test coverage.
| Indicator Testability | ||||
|---|---|---|---|---|
| RefDes | Driver | Control Signal | DFT Status | Testable |
| LED1 | Direct | Net-(LED1-A) | Design Warning: Test point needed on Net-(LED1-A). Drive HIGH to turn on LED LED1. | |
| LED2 | Direct | CDONE | Design Warning: Test point needed on CDONE. Drive HIGH to turn on LED LED2. | |
| LED3 | Direct | Net-(LED3-K) | Design Warning: Test point needed on Net-(LED3-K). Drive HIGH to turn on LED LED3. | |
| LED4 | Direct | RGB1 | Design Warning: Test point needed on RGB1. Drive HIGH to turn on LED LED4. | |
7 Switch Documentation
2 switch(es) found in design.
7.1 Switch Configurations
| SW2 Contact Pairs (TS-1088-AR02016) | |||||||
|---|---|---|---|---|---|---|---|
| Contact | Pin A | Net A | Pin B | Net B | When Open | When Closed | Notes |
| 1 | 1 | BUTTON | 2 | GND | SIGNAL | LOW | |
| SW2 All Pins | ||||
|---|---|---|---|---|
| Pin # | Pin Name | Net | Paired With | Type |
| 1 | 1 | BUTTON | 2 | CONTACT |
| 2 | 2 | GND | 1 | CONTACT |
| SW3 Contact Pairs (TS-1088-AR02016) | |||||||
|---|---|---|---|---|---|---|---|
| Contact | Pin A | Net A | Pin B | Net B | When Open | When Closed | Notes |
| 1 | 1 | creset_b | 2 | GND | SIGNAL | LOW | |
| SW3 All Pins | ||||
|---|---|---|---|---|
| Pin # | Pin Name | Net | Paired With | Type |
| 1 | 1 | creset_b | 2 | CONTACT |
| 2 | 2 | GND | 1 | CONTACT |
7.2 Switch DFT Analysis
Switches for mode selection are useful for development and manual debug, but production test environments require electrical override capability. Latching switches (DIP) that hold a signal to GND need isolation resistors so ATE can override. Momentary switches (push buttons) don't hold the signal, but ATE still needs test point access to stimulate the signal.
Design Rationale: Switches for mode selection are valuable for engineering development and bench debug. However, production test and field returns require electrical override capability without manual intervention. Adding test points and isolation resistors creates a lifecycle-robust design that works across development, production test, and field returns without requiring procedure documentation or specialized knowledge of switch positions. The goal is a self-documenting, procedure-proof test interface. BOM impact: One 0201/0402 resistor per controlled signal.
| Switch | Signal | Function | Pullup | Rail | Issue | Test Point? |
|---|---|---|---|---|---|---|
| SW2 | BUTTON | Switch-controlled signal | R34 (10.00K) | +3V3 (3.3V) | No test point + Switch forces signal, ATE cannot override | |
| SW3 | creset_b | Reset/ | R20 (10.00K) | +3V3 (3.3V) | No test point + Switch forces signal, ATE cannot override |
7.2.1 Isolation Resistor Options: BUTTON
Circuit: +3V3 --- R34 (10.00K) --- [signal node/testpoint] --- R_series --- [switch to GND]. Adding R_series creates a voltage divider: when switch closes, IC sees V = Vcc × R_series / (R_pullup + R_series) instead of hard GND. ViL threshold (generic CMOS): 0.990000V max, target 0.841500V (15% margin for resistor tolerance). Verify against device datasheet.
Trade-offs: Lower R_series = more margin below ViL but higher ATE current draw. Higher R_series = lower current but reduced noise margin. Values near 1K-1.5K typically provide good balance for 1.8V signals.
| R_series | V at IC (switch closed) | Margin to ViL | ATE Current (override HIGH) | Status |
|---|---|---|---|---|
| 150 | 0.049V | 0.793V | 22.00 mA | HIGH |
| 220 | 0.071V | 0.770V | 15.00 mA | OK |
| 330 | 0.105V | 0.736V | 10.00 mA | OK |
| 470 | 0.148V | 0.693V | 7.02 mA | OK |
| 680 | 0.210V | 0.631V | 4.85 mA | OK |
| 1.0K | 0.300V | 0.541V | 3.30 mA | OK |
| 1.5K | 0.430V | 0.411V | 2.20 mA | BEST |
7.2.2 Isolation Resistor Options: creset_b
Circuit: +3V3 --- R20 (10.00K) --- [signal node/testpoint] --- R_series --- [switch to GND]. Adding R_series creates a voltage divider: when switch closes, IC sees V = Vcc × R_series / (R_pullup + R_series) instead of hard GND. ViL threshold (generic CMOS): 0.990000V max, target 0.841500V (15% margin for resistor tolerance). Verify against device datasheet.
Trade-offs: Lower R_series = more margin below ViL but higher ATE current draw. Higher R_series = lower current but reduced noise margin. Values near 1K-1.5K typically provide good balance for 1.8V signals.
| R_series | V at IC (switch closed) | Margin to ViL | ATE Current (override HIGH) | Status |
|---|---|---|---|---|
| 150 | 0.049V | 0.793V | 22.00 mA | HIGH |
| 220 | 0.071V | 0.770V | 15.00 mA | OK |
| 330 | 0.105V | 0.736V | 10.00 mA | OK |
| 470 | 0.148V | 0.693V | 7.02 mA | OK |
| 680 | 0.210V | 0.631V | 4.85 mA | OK |
| 1.0K | 0.300V | 0.541V | 3.30 mA | OK |
| 1.5K | 0.430V | 0.411V | 2.20 mA | BEST |
8 Low-Speed Serial Interfaces (LSSI)
Detected: 1 JTAG, 3 SPI
8.1 SPI
| SPI: U2 -> U4 | |||
|---|---|---|---|
| Topology: U2 » Targets (U4, J2) | |||
| Sig | Nets | Conn/TP | Target Pin |
| MOSI | MOSI | J2_3 | U4_5 (DI) |
| MISO | MISO | J2_4 | U4_2 (DO) |
| SCK | SCK | J2_2 | U4_6 (CLK) |
| CS | Net-(U4-CS) » R35 » CS | J2_1 | U4_1 (CS) |
| Target | CS Net | Industry Type | Description |
| U4 | Net-(U4-CS) (1 CS) | W25Q128JVSIQTR | |
| Controller | Industry Type | Description | |
| U2 | ICE40UP5K-SG48I | ||
| SPI: U2 -> U3 | ||||
|---|---|---|---|---|
| Topology: U2 » Targets (U3) | ||||
| Signal | Net Name | Connector | Test Point | Target Pin |
| MOSI | SD_MOSI / | (none) | (none) | U3_16 (MOSI) |
| MISO | SD_MISO / | (none) | (none) | U3_15 (MISO) |
| SCK | SD_SCK / | (none) | (none) | U3_13 (SCLK) |
| CS | SD_CS | (none) | (none) | U3_14 (SS) |
| Target | CS Net | Industry Type | Description | |
| U3 | USB_CS (14 SS) | MAX3421EETJ+T | ||
| Controller | Industry Type | Description | ||
| U2 | ICE40UP5K-SG48I | |||
| SPI [U2_SPI] -> U2 | ||||
|---|---|---|---|---|
| Topology: Access (J2) » Targets (U2) | ||||
| Signal | Net Name | Connector | Test Point | Target Pin |
| MOSI | MOSI | J2_3 | (none) | U2_17 (IOB_33b_SPI_SI) |
| MISO | MISO | J2_4 | (none) | U2_14 (IOB_32a_SPI_SO) |
| SCK | SCK | J2_2 | (none) | U2_15 (IOB_34a_SPI_SCK) |
| CS | CS | J2_1 | (none) | U2_16 (IOB_35b_SPI_SS) |
| Target | Industry Type | Description | ||
| U2 | ICE40UP5K-SG48I | |||
8.2 JTAG
| JTAG [JTAG]: U6 | |||
|---|---|---|---|
| Topology: U6 » Targets () | |||
| Signal | Net Name | Connector | Test Point |
| TCK | JTAG_TCK | (none) | (none) |
| TMS | JTAG_TMS | (none) | (none) |
| TDI | JTAG_TDI | (none) | (none) |
| TDO | JTAG_TDO | (none) | (none) |
| TRST | JTAG_TRST | (none) | (none) |
| Controller | Industry Type | Description | |
| U6 | FT2232HL | Dual High Speed USB To Multipurpose UARTFIFO IC, 64-pin LQFP, Tape and Reel | |
8.3 LSSI DFT Analysis
There is no access for boundary scan through JTAG via connector or full set of test points. At least one signal is missing access for boundary scan test.
17 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.
During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.
| Missing Test Points | |||
|---|---|---|---|
| Signal | Net Name | Connector | Interface |
| TCK | JTAG_TCK | (none) | JTAG |
| TDI | JTAG_TDI | (none) | JTAG |
| TDO | JTAG_TDO | (none) | JTAG |
| TMS | JTAG_TMS | (none) | JTAG |
| TRST | JTAG_TRST | (none) | JTAG |
| CS | CS | J2_1 | SPI -> U4 |
| MISO | MISO | J2_4 | SPI -> U4 |
| MOSI | MOSI | J2_3 | SPI -> U4 |
| SCK | SCK | J2_2 | SPI -> U4 |
| CS | SD_CS | (none) | SPI -> U3 |
| MISO | SD_MISO | (none) | SPI -> U3 |
| MOSI | SD_MOSI | (none) | SPI -> U3 |
| SCK | SD_SCK | (none) | SPI -> U3 |
| CS | CS | J2_1 | SPI -> U2 |
| MISO | MISO | J2_4 | SPI -> U2 |
| MOSI | MOSI | J2_3 | SPI -> U2 |
| SCK | SCK | J2_2 | SPI -> U2 |
9 High-Speed Serial Interfaces (HSSI)
4 differential pair(s)
Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.
2 USB differential pair(s) have no controlled-impedance net class assigned. Assign a 90 Ohm differential net class so the impedance intent carries into PCB layout and length tuning.
9.1 Differential Pairs
Differential pairs with designer-specified class annotations.
None of the 4 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.
| Differential Pairs | |||
|---|---|---|---|
| Net Name | Class | Impedance | Notes |
| PER_D+ | USB | ||
| PER_D- | USB | ||
| PROG_D+ | USB | ||
| PROG_D- | USB | ||
9.2 AI-Assisted Analysis
This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.
9.2.1 USB 2.0 device port on USB2 (FT2232HL programming/data channel)
AI-Assisted —
PROG_D+/PROG_D- run from the Type-C receptacle USB2 pins A6/B6 (Dp1/Dp2) and A7/B7 (Dn1/Dn2) through the 0 ohm series jumpers R15 and R14 to U6 pin 8 (DP) and pin 7 (DM). Tying Dp1 to Dp2 and Dn1 to Dn2 at the receptacle is the correct USB 2.0-only Type-C wiring and gives cable-flip independence. USB2 is configured as an upstream-facing device port: R3 and R4, both 5.1K, pull CC1 (USB2 pin A5) and CC2 (USB2 pin B5) to GND, which is the Rd advertisement required by USB Type-C R2.x for a sink/device, matching the FT2232HL's bus-powered device role. The FT2232HL is a Hi-Speed (480 Mbps) transceiver, so this pair requires a 90 ohm +/-15% differential channel per USB 2.0 Chapter 7; no impedance class is assigned to PROG_D+/PROG_D- in the schematic, so the pair carries no constraint into layout. USB 2.0 is DC-coupled by specification and no series AC coupling capacitor is required or fitted; termination is on-die in the FT2232HL and no external termination is present, which is correct. The 0 ohm jumpers R14/R15 are the only series discontinuity; in 0603 bodies each contributes a short uncontrolled stub at 480 Mbps, so they should be placed immediately adjacent to U6 with the pair length-matched across them, or removed and replaced by a direct route if no build option is needed.
9.2.2 USB 2.0 host port on USB1 (MAX3421E channel)
AI-Assisted —
PER_D+/PER_D- run from USB1 pins A6/B6 and A7/B7 through the 33 ohm series resistors R6 and R5 to U3 pin 21 (D+) and pin 20 (D-). R40 and R44, both 56K, pull USB1 CC1 (pin A5) and CC2 (pin B5) up to VBUS, which is the Rp source advertisement for a downstream-facing port at USB Type-C default current, consistent with the MAX3421E operating as a USB host. USB1 VBUS is sourced from the board VBUS rail through the polyfuse F1. The MAX3421E is a low-/full-speed (1.5/12 Mbps) USB host/peripheral controller, so the 33 ohm series elements represent roughly 66 ohm added into a nominally 90 ohm differential path; at 12 Mbps the resulting rise-time and amplitude effect is tolerable, but the resistors are not required by the device and are not a specified termination, so removing them or reducing them to 0 ohm removes an unnecessary impedance step and voltage drop at the D+/D- eye. As with the other pair, no differential impedance class is set on PER_D+/PER_D-, and no AC coupling is required. On-die termination and the 1.5 kohm/15 kohm bias behaviour are internal to the MAX3421E; nothing external is fitted, which is correct for this device.
9.3 Findings
AI-Assisted —
| # | Interface | Protocol | Finding | Severity |
|---|---|---|---|---|
| 9.3.1 | U3 pin 22 (VBCOMP) | MAX3421E VBUS sense | Net contains only U3 pin 22 and capacitor C4 (1 uF to GND) - no DC path; datasheet requires VBCOMP tied to VBUS (peripheral) or VCC (host-only) with C4 retained as bypass (Maxim MAX3421E datasheet, source: Tomachie) | High |
| 9.3.2 | PROG_D+/ | USB 2.0 Hi-Speed | No 90 ohm differential impedance class assigned to the pair; USB 2.0 requires 90 ohm +/ | Medium |
| 9.3.3 | USB1 VBUS / | USB Type-C power | Polyfuse MF-NSMF020-2 holds 200 mA and trips at 400 mA, below the default-current class advertised by the 56K Rp on USB1, so a compliant peripheral will trip it; also the only element separating USB2 host VBUS from the USB1 downstream port (source: Tomachie) | Medium |
| 9.3.4 | PROG_D+/ | USB 2.0 Hi-Speed | 0 ohm series jumpers R14, R15 in 0603 bodies add an uncontrolled discontinuity at 480 Mbps; place adjacent to U6 with the pair matched, or route directly | Low |
| 9.3.5 | PER_D+/ | USB 2.0 low/ | 33 ohm series resistors R5, R6 add approximately 66 ohm into a nominal 90 ohm differential path and are not a device-required termination; reduce to 0 ohm or remove (Maxim MAX3421E datasheet, source: Tomachie) | Low |
| 9.3.6 | DSub1 analog RGB | VGA (analog) | Output driven by a 510/ | Low |
| 9.3.7 | X1, X2 12 MHz references | U6 OSCI/ | Crystal specified for a 20 pF load is fitted with 22 pF load capacitors, giving an effective load near 16 pF and a positive frequency pull; motional and shunt capacitance are needed to compute the pull against the USB 2.0 +/ | Review |
| 9.3.8 | PROG_D+/ | USB 2.0 Hi-Speed, 480 Mbps | Type-C Dp1/ | ✓ |
| 9.3.9 | USB2 CC1/ | USB Type-C R2.x sink | R3, R4 (5.1K) to GND on USB2 pins A5/ | ✓ |
| 9.3.10 | PER_D+/ | USB 2.0 low/ | On-die termination and bias internal to U3; no external termination fitted, and no AC coupling required by the standard | ✓ |
| 9.3.11 | USB1 CC1/ | USB Type-C R2.x source | R40, R44 (56K) to VBUS on USB1 pins A5/ | ✓ |
| 9.3.12 | U6 PHY/ | FT2232HL analog rails | VPHY fed from +3V3 through ferrite L1 (600 ohm at 100 MHz) with 1 uF plus 100 nF; VPLL through L2 with 100 nF; core rail bypassed with 4.7 uF plus 3x100 nF (FTDI FT2232H datasheet, source: Tomachie) | ✓ |
| 9.3.13 | U2 PLL supply | ICE40UP5K VCCPLL | VCCPLL at U2 pin 29 isolated from +1V2 by R33 (100 ohm) with 4.7 uF plus 100 nF local, per Lattice iCE40 UltraPlus power guidance (source: Tomachie) | ✓ |
10 Memory Interface Analysis
Found 1 complete memory interface(s)
10.1 U4 QSPI
| U4 (W25Q128JVSIQTR) - QSPI [4-bit data] | |||||
|---|---|---|---|---|---|
| Signal | Pin Name | Pin # | Net Name | Test Point | Connector |
| CLOCK | CLK | 6 | SCK | - | J2_2 |
| DATA_2 | DO | 2 | MISO | - | J2_4 |
| DATA_3 | DI | 5 | MOSI | - | J2_3 |
| SELECT | CS | 1 | Net-(U4-CS) | - | J2_1 |
10.2 Programming Access Verification
Verifies that ICs sharing the QSPI bus can be disabled during non-volatile memory programming.
| U4 (W25Q128JVSIQTR) - Programming via J2 | |||
|---|---|---|---|
| Adjacent IC | Type | Can Disable | Control Path |
| U2 | ICE40UP5K-SG48I | [FAIL] | No disable pins (RESET, CE#, OE#) found on component |
| DESIGN_WARNING:U2 (ICE40UP5K-SG48I): No disable pins (RESET, CE#, OE#) found on component | |||
10.3 AI-Assisted Analysis
This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.
10.3.1 QSPI Configuration Flash (U4, W25Q128JVSIQ)
AI-Assisted —
U4 is the only memory device on the board: a Winbond W25Q128JV 128M-bit serial NOR flash in the 8-pin SOIC-208mil package, wired point-to-point to the ICE40UP5K-SG48I (U2) configuration/SPI port. SCK reaches U4 pin 6 from U2 IOB_34a_SPI_SCK, MISO from U4 DO to U2 IOB_32a_SPI_SO, MOSI from U2 IOB_33b_SPI_SI to U4 DI. The IQ suffix fixes QE=1 permanently (Winbond datasheet p.18), so quad mode is available without a status-register write; however only two data lines are wired as data. IO2 is on FLASH_WP and IO3 on FLASH_HOLD, each pulled to +3V3 through R41 and R42 (10K) respectively and also brought to U2 IOB_22a / IOB_20a and to J2 pins 5 and 6. With QE=1 these two pins are IO2/IO3, not /WP and /HOLD, so the pull-ups are the correct idle bias for x4 operation and the FPGA can drive them for true QSPI reads; the net names are misleading and should be renamed to FLASH_IO2/FLASH_IO3. There is no dedicated hardware /RESET on this package (Winbond datasheet p.9-10), so no reset pull-up is needed or possible. Chip select is not driven directly by the FPGA: U2 IOB_35b_SPI_SS drives net CS, which is pulled to +3V3 by R19 (10K) and passes through R35 (0Ω) to U4 /CS. That 0Ω link is a useful isolation option, and the pull-up on the FPGA side of it satisfies the datasheet's recommendation (p.9, p.12) that /CS track VCC during power sequencing — though U4 /CS itself sits behind the resistor with no local pull-up.
10.3.2 Flash Interface Signal Integrity and Timing
AI-Assisted —
No series damping resistors are fitted on SCK, DI, DO, IO2 or IO3. The W25Q128JV-IQ ships with 25% default output drive strength (Winbond datasheet p.19), which is the mildest of the family options and reduces edge-rate stress, so on a short point-to-point link this is defensible; the absence of series terminators is a signal-integrity item to close at layout with controlled trace length rather than a schematic defect. Clock capability is 133 MHz for all instructions except Read Data 03h at VCC 3.0-3.6 V; U4 is powered from the +3V3 rail, so the 133 MHz row applies, with tV (clock low to output valid) 6 ns max and tHO 1.5 ns min. iCE40 UP5K configuration reads run well below this, so no timing violation exists at the schematic level. Power-up ordering is also relevant: the datasheet requires tVSL 20 µs from VCC(min) to /CS low and tPUW 5 ms before a write instruction; with /CS pulled up through R19 and the FPGA holding its I/O tri-stated during power-up, this is satisfied by the FPGA's own configuration delay. Decoupling on U4 VCC is provided from the shared +3V3 rail; the rail carries 17 capacitors totalling 21.9 µF, including 100nF and 4.7µF parts, and the flash's peak demand is modest — 25 mA max during erase/program (iCC6/iCC7).
10.3.3 Flash Access, Bring-Up and Programming Path
AI-Assisted —
J2 is an 8-pin header that taps the full flash bus: CS on pin 1, SCK on pin 2, MOSI on pin 3, MISO on pin 4, plus FLASH_WP/FLASH_HOLD on pins 5 and 6, with +3V3 on pin 7 and GND on pin 8. This gives direct in-system programming of U4 from an external programmer. The material gap is contention: U2 shares every one of those lines and has no reset, chip-enable or output-enable pin that an external programmer can assert to force its I/Os off the bus. Driving the flash from J2 while U2 is configured and driving SPI_SO/SPI_SCK produces bus contention on MISO and SCK. The iCE40's own CRESET_B (net creset_b, pulled to +3V3 by R20, driven low by SW3 and available on JP5) does hold the FPGA in reset and releases its SPI pins — but the programmer must hold it low, and nothing on J2 exposes it. Bringing creset_b out to a spare pin of J2 (or a fly lead pad) removes the contention risk and makes the programming procedure self-contained rather than dependent on a manually held button. Separately, the CS net serves U2, J2, JP4 (JTAG_TMS on the other side) and R35 simultaneously; the solder-jumper option on JP4 must be open when programming through J2.
10.4 Observations
AI-Assisted —
No DDR, SDRAM, SRAM or NVRAM device is present in this design; the ICE40UP5K's memory is internal, so there is no external DDR topology, ODT, VTT or VREF network to review, and no ZQ calibration resistor applies. The only external memory bus is the single-slave QSPI link to U4, which is point-to-point — the JEDEC fly-by/T-branch and address-command termination considerations do not apply. Data-line direction is consistent: U4 DI is the only slave input on MOSI and U4 DO the only slave output on MISO, so there is no shared-wire direction conflict. Note that the SD card socket Card1 and the MAX3421E (U3) form a separate SPI segment (SD_SCK/SD_MOSI/SD_MISO with SD_CS from U2 IOB_18a), electrically independent of the flash bus — SD storage is a removable media interface, not part of the configuration memory path, and its lines carry 10K pull-ups to +3V3 on R45-R48 as required for SD bus idle states. No lifecycle restriction is stated for the W25Q128JV in Winbond's documentation.
10.5 Findings
AI-Assisted —
| # | Memory | Interface | Finding | Severity |
|---|---|---|---|---|
| 10.5.1 | U4 | In-system programming via J2 | J2 exposes CS/ | Medium |
| 10.5.2 | U4 | Bus sharing with jumpers | CS also reaches solder jumper JP4 (other side JTAG_TMS); JP4 must be open during flash access to avoid loading the chip-select line | Low |
| 10.5.3 | U4 | IO2 / | Nets named FLASH_WP and FLASH_HOLD; with the IQ option QE=1 is fixed so these pins are IO2/ | Review |
| 10.5.4 | U4 | Signal integrity | No series damping resistors on SCK/ | Review |
| 10.5.5 | U4 W25Q128JVSIQ | QSPI NOR flash | Point-to-point QSPI to U2; CLK/ | ✓ |
| 10.5.6 | U4 | QSPI / | CS pulled to +3V3 by R19 (10K) on the U2 side of the 0Ω link R35; satisfies / | ✓ |
| 10.5.7 | U4 | Reset | 8-pin SOIC-208mil has no dedicated hardware / | ✓ |
| 10.5.8 | U4 | Quad enable | QE=1 factory-fixed for the IQ suffix — no status-register write required for x4 reads (Winbond datasheet p.18) | ✓ |
| 10.5.9 | U4 | Clock rate | 133 MHz max at VCC 3.0-3.6 V (except 03h Read Data at 50 MHz); U4 on +3V3 so the 133 MHz row applies, tV 6 ns / | ✓ |
| 10.5.10 | U4 | Power-up sequencing | tVSL 20 µs (VCC to / | ✓ |
| 10.5.11 | U4 | Supply decoupling | VCC from +3V3, rail total 21.9 µF including 100nF and 4.7µF parts; adequate for 25 mA max erase/ | ✓ |
| 10.5.12 | DDR / | - | No DDR, SDRAM or SODIMM/ | ✓ |
| 10.5.13 | SRAM / | - | No external SRAM or NVRAM device present; no address/ | ✓ |
| 10.5.14 | Card1 SD socket | SPI (separate segment) | Removable media on its own SPI segment with SD_CS from U2; SD_SCK/ | ✓ |
| 10.5.15 | U4 | Lifecycle | No NRND or end-of-life status stated for the W25Q128JV family (Winbond W25Q128JV datasheet) | ✓ |
10.6 Citations
AI-Assisted —
| References |
|---|
| W25Q128JV-IQ (Winbond) — datasheet W25Q128JVSIQ.pdf |
11 Functional Analysis
15 device(s) to review across 2 category(ies)
| Device Inventory | |||||
|---|---|---|---|---|---|
| RefDes | Category | Part Number | Description | Interfaces | HSSI |
| Card1 | DEVICE | TF-008 | - | - | |
| DSub1 | DEVICE | VGA-002 | - | - | |
| JP1 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP2 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP3 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP4 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP5 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP6 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP7 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| JP8 | DEVICE | SolderJumper_2_Bridged | Solder Jumper, 2-pole, closed/ | - | - |
| U3 | DEVICE | MAX3421EETJ+T | SPI | - | |
| U6 | DEVICE | FT2232HL-REEL | Dual High Speed USB To Multipurpose UARTFIFO IC, 64-pin LQFP, Tape and Reel | JTAG [JTAG] | - |
| X1 | DEVICE | X322512MSB4SI | YSX321SL 12MHZ 20PF 10PPM -40~+85℃ | - | - |
| X2 | DEVICE | X322512MSB4SI | YSX321SL 12MHZ 20PF 10PPM -40~+85℃ | - | - |
| U2 | FPGA | ICE40UP5K-SG48I | SPI, SPI [U2_SPI] | - | |
11.1 Functional Analysis
This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.
11.1.1 Card1 — TF-008 microSD socket
AI-Assisted —
VDD is on +3V3 and both supply-return pins (VSS pin 6, GND pin 11) are on GND, so the socket has a valid DC path on both sides per the SOFNG datasheet pin assignment. The SPI-mode wiring is consistent: CMD is on SD_MOSI, CLK on SD_SCK, DAT0 on SD_MISO and CD/DAT3 on SD_CS, all three data/clock lines shared with U3 (MAX3421E) and U2. Each of the four bus lines carries a 10K pull-up to +3V3 (R45 CMD, R46 CLK, R47 DAT0, R39 CD/DAT3), and the two unused data lines are also biased high — DAT1 through R48 to +3V3 and DAT2 through R38 to +3V3 — which is the correct idle state for SPI-mode operation of an SD card. The mechanical card-detect switch is not usable as wired: both detect contacts (pins 9 and 10) are on GND, so the switch closure produces no signal for U2 to read; if card presence sensing is wanted, one contact must go to a pulled-up FPGA input instead. No series damping resistors are fitted on CLK/CMD/DAT0, which is acceptable for the low clock rates an SPI-mode card interface uses.
11.1.2 DSub1 — VGA-002 analog video output
AI-Assisted —
The three colour channels are driven from FPGA I/O through resistor ladders: RED from R24 (510), R25 (1K) and R26 (2K); GREEN from R27 (2K), R28 (510) and R29 (1K); BLUE from only R30 (820) and R31 (430). The green and red channels therefore give three weighted bits each while blue gives two, so the colour depth is asymmetric — intentional in many ice40 demo designs, but worth noting because the ladder Thevenin impedance differs per channel and the resulting full-scale amplitudes into the monitor's 75 ohm termination will not match between R, G and B. No 75 ohm shunt or series build-out resistor is fitted on any colour pin; the amplitude therefore depends entirely on the ladder values against the display's internal termination. HSYNC and VSYNC are driven directly from U2 at 3.3 V CMOS levels, which is compatible with the sync inputs on a VGA display. All shield/return pins (5, 6, 7, 8, 10, 16, 17) are on GND. The DDC clock and data pins (12 and 15) and pin 9 are unconnected in the schematic, so no EDID readback from the monitor is possible per the WinSystems datasheet pin function list — acceptable for a fixed-timing generator.
11.1.3 JP1-JP8 — bridged solder jumpers on the FT2232H to FPGA links
AI-Assisted —
All eight jumpers are the closed/bridged variety, so every link is connected as built and requires cutting the bridge to open it. JP1-JP4 place the FT2232H channel-A MPSSE pins on the FPGA configuration SPI bus: ADBUS0 to SCK, ADBUS1 to MOSI, ADBUS2 to MISO and ADBUS3 to CS, each of which also lands on the U4 flash and on header J2 pins 1-4. JP5 links ADBUS4 to creset_b, which also carries pushbutton SW3 and pull-up R20 to +3V3; JP6 links ADBUS5 to CDONE, pulled up by R21 to +3V3 and shared with the LED2 status indicator. JP7 and JP8 bring channel-B BDBUS1 and BDBUS0 to PROG_RX and PROG_TX for a UART to the FPGA fabric. Because the bridges are closed by default, the FT2232H remains attached to SCK, MOSI, CS and creset_b whenever an external programmer is plugged into J2, so the two SPI masters share the same wires; the jumpers are the intended isolation mechanism and should be opened when J2 is used. The net labels on the U6 side (JTAG_TCK/TDI/TDO/TMS/TRST) do not describe the function at the FPGA side, where the same wires are SPI clock, data and reset — renaming them to their SPI roles would remove a real source of confusion during bring-up and test.
11.1.4 U3 — MAX3421E USB host controller
AI-Assisted —
VL (pin 2) and VCC (pin 23) are on +3V3; GND pins 3, 19 and the exposed pad 33 are on GND, so all supply and return pins have valid DC paths. Local bypass on +3V3 is drawn from the shared bank; VBCOMP (pin 22) has C4 1uF to GND. The SPI slave port is correct: SCLK on SD_SCK, MOSI on SD_MOSI, MISO on SD_MISO, ~SS on USB_CS from U2, with INT to U2 IOB_8a and ~RES to U2 IOB_9b, so interrupt and reset are both under FPGA control. D+ and D- reach USB1 through 33 ohm series resistors R6 and R5 — series damping on a USB host port; no on-board VBUS switch or ESD device is fitted on this port. The 12 MHz crystal X1 is on XI/X0 as required. All GPIN/GPOUT pins and GPX are unconnected in the schematic, which the general-purpose I/O function permits.
11.1.5 U6 — FT2232HL dual USB bridge
AI-Assisted —
VREGIN (pin 50) is on +3V3 and VREGOUT (pin 49) ties to the VCORE pins 12/37/64, the correct internal-regulator strap; the four VCCIO pins are on +3V3 and all GND pins including AGND are on GND. VPHY and VPLL are fed through ferrites L1 and L2 from +3V3. REF (pin 6) is set by R16 12K to GND — the FTDI datasheet reference resistor. ~RESET is pulled up by R17 10K to +3V3 with no external reset driver, so the part self-releases. BDBUS3 is tied low through R9 1K to GND. TEST (pin 13) is on GND, the required state for normal operation. Channel A MPSSE and channel B UART pins reach U2 through the solder jumpers; the remaining bus pins and the EEPROM interface pins (EECS, ECLK, EEDATA) are unconnected, so the part runs from its internal default descriptors with no configuration EEPROM.
11.1.6 X1, X2 — 12 MHz crystals
AI-Assisted —
Both are the same YXC part specified as 12 MHz, 20 pF load, 10 ppm. X1 serves U3 (XI/X0) and X2 serves U6 (OSCI/OSCO), each with 22pF shunt capacitors (C6/C7 and C16/C15) and both frame pins grounded. With 22pF per leg plus stray, the presented load is close to but slightly above the 20 pF specified load, giving a small negative frequency pull; 18pF would centre it. 12 MHz matches the FT2232H requirement and the MAX3421E oscillator input.
11.1.7 U2 — ICE40UP5K FPGA
AI-Assisted —
VCC pins 5 and 30 are on +1V2 with 5.9 µF local capacitance; VCCIO_0, VCCIO_2, SPI_Vccio1 and VPP_2V5 are on +3V3; VCCPLL is filtered by R33 100 from +1V2 with 4.8 µF local. The exposed pad is on GND. Configuration is master-SPI from U4 (W25Q128JVSIQ, 128 Mbit — ample for a UP5K bitstream) on SCK/MOSI/MISO with CS via R35 0R, and flash WP and HOLD are held high by R41 and R42 10K to +3V3. creset_b and CDONE both carry 10K pull-ups and SW3 provides manual reconfiguration. No dedicated JTAG port is wired; programming is via the SPI path only.
11.1.8 Observations and Findings
AI-Assisted —
The most serious issue on the USB side is U3 pin 22 (VBCOMP). Its net contains only that pin and the 1 uF capacitor C4, whose other plate returns to GND; there is no DC path to any rail. A bypass capacitor does not supply this pin, so the MAX3421E VBUS comparator input is left floating and the part cannot resolve VBUS state. Per the Analog Devices/Maxim MAX3421E datasheet (source: Tomachie), VBCOMP must be connected to VBUS for peripheral operation, or to VCC when the device is used only as a host; C4 then remains as the local bypass. This must be wired before layout.
VBUS also merits attention as a system topology matter: the same VBUS net feeds the inputs of both regulators U1 and U5, is presented outward on USB1 through F1, and is fed inward from USB2. With cables in both receptacles the board ties an external host's VBUS to the downstream port, so the MF-NSMF020-2 polyfuse is the only element limiting that path. That part's 200 mA hold / 400 mA trip rating sits below the 500 mA the 56K Rp on USB1 advertises to an attached device, so a compliant peripheral drawing its advertised current will trip F1; a device-side ideal-diode or load switch, and a fuse matched to the advertised class, would close both issues.
Both 12 MHz crystals (X1, X2, specified for a 20 pF load) are fitted with 22 pF load capacitors, which with typical strays gives an effective load nearer 16 pF and a positive frequency pull. USB 2.0 allows +/-500 ppm, so this is very likely acceptable, but closing it requires the crystal's motional and shunt capacitance to compute the actual pull.
PHY supply filtering on U6 is sound in structure: VPHY is fed from +3V3 through the 600 ohm at 100 MHz ferrite L1 with 1 uF plus 100 nF local, and VPLL through L2 with 100 nF. The 1.2 V FPGA PLL supply is likewise isolated from +1V2 through the 100 ohm resistor R33 with 4.7 uF plus 100 nF at U2 pin 29.
The VGA output on DSub1 is driven by a resistor-ladder DAC from the FPGA (510/1K/2K network) rather than a video DAC; the ladder output impedance is not matched to the 75 ohm VGA load, which will reduce amplitude and limit usable pixel clock. This is a functional design choice, not a wiring error, but the ladder values should be sized against a 75 ohm termination if higher resolutions are intended.
VBUS also merits attention as a system topology matter: the same VBUS net feeds the inputs of both regulators U1 and U5, is presented outward on USB1 through F1, and is fed inward from USB2. With cables in both receptacles the board ties an external host's VBUS to the downstream port, so the MF-NSMF020-2 polyfuse is the only element limiting that path. That part's 200 mA hold /
Both 12 MHz crystals (X1, X2, specified for a 20 pF load) are fitted with 22 pF load capacitors, which with typical strays gives an effective load nearer 16 pF and a positive frequency pull. USB 2.0 allows +/
PHY supply filtering on U6 is sound in structure: VPHY is fed from +3V3 through the 600 ohm at 100 MHz ferrite L1 with 1 uF plus 100 nF local, and VPLL through L2 with 100 nF. The 1.2 V FPGA PLL supply is likewise isolated from +1V2 through the 100 ohm resistor R33 with 4.7 uF plus 100 nF at U2 pin 29.
The VGA output on DSub1 is driven by a resistor-ladder DAC from the FPGA (510/
11.2 Findings
AI-Assisted —
| # | Device | Finding | Severity |
|---|---|---|---|
| 11.2.1 | Card1 (TF-008) | Card-detect switch contacts (pins 9 and 10) are both tied to GND, so card presence cannot be sensed by U2; route one contact to a pulled-up FPGA input if detection is required | Low |
| 11.2.2 | DSub1 (VGA-002) | RED and GREEN driven by three-resistor ladders (510/ | Review |
| 11.2.3 | DSub1 (VGA-002) | No 75 ohm series or shunt build-out resistor on R, G or B; output amplitude relies wholly on the monitor's internal termination | Review |
| 11.2.4 | JP1-JP4 (SolderJumper_2_Bridged) | Bridges are closed by default, so U6 stays on SCK/ | Review |
| 11.2.5 | JP1-JP5 net naming | Nets named JTAG_TCK/ | Review |
| 11.2.6 | X1/ | 22pF load capacitors against the 20 pF specified load — slight over-load, 18pF would centre the frequency | Review |
| 11.2.7 | Card1 (TF-008) | VDD on +3V3 and both returns (pin 6 VSS, pin 11 GND) on GND — supply and ground pins have valid DC paths per SOFNG datasheet | ✓ |
| 11.2.8 | Card1 (TF-008) | SPI-mode bus wiring correct: CMD/ | ✓ |
| 11.2.9 | Card1 (TF-008) | Unused DAT1 and DAT2 held high through R48 and R38 (10K) to +3V3 — correct idle bias for SPI mode | ✓ |
| 11.2.10 | DSub1 (VGA-002) | HSYNC and VSYNC driven directly from U2 3.3 V I/ | ✓ |
| 11.2.11 | DSub1 (VGA-002) | All shield/ | ✓ |
| 11.2.12 | DSub1 (VGA-002) | DDC clock/ | ✓ |
| 11.2.13 | JP1-JP4 (SolderJumper_2_Bridged) | Closed jumpers connect FT2232H ADBUS0-ADBUS3 to SCK, MOSI, MISO and CS — configuration SPI path to U2 and U4 complete as built | ✓ |
| 11.2.14 | JP5 (SolderJumper_2_Bridged) | ADBUS4 to creset_b, net also carrying SW3 and pull-up R20 (10K) to +3V3 — defined reset level maintained | ✓ |
| 11.2.15 | JP6 (SolderJumper_2_Bridged) | ADBUS5 to CDONE, pulled up by R21 (10K) to +3V3 and shared with LED2 — status readback path valid | ✓ |
| 11.2.16 | JP7/ | BDBUS1 and BDBUS0 to PROG_RX and PROG_TX — UART link to FPGA fabric complete | ✓ |
| 11.2.17 | U3 (MAX3421E) | VL, VCC on +3V3; GND pins 3/ | ✓ |
| 11.2.18 | U3 (MAX3421E) | SPI slave, INT and ~RES all wired to U2; VBCOMP bypassed with C4 1uF | ✓ |
| 11.2.19 | U3 (MAX3421E) | D+/ | ✓ |
| 11.2.20 | U6 (FT2232HL) | VREGOUT strapped to VCORE, VREGIN and VCCIO on +3V3, all grounds on GND | ✓ |
| 11.2.21 | U6 (FT2232HL) | REF set by R16 12K to GND; TEST tied to GND for normal operation | ✓ |
| 11.2.22 | U6 (FT2232HL) | ~RESET pulled up by R17 10K to +3V3; no EEPROM fitted, internal defaults used | ✓ |
| 11.2.23 | U2 (ICE40UP5K) | VCC on +1V2, VCCIO/ | ✓ |
| 11.2.24 | U2 (ICE40UP5K) | Master-SPI boot from U4 128 Mbit flash; WP/ | ✓ |
11.3 Citations
AI-Assisted —
| References |
|---|
| AMS1117-1.2 (UMW) — datasheet datasheet.lcsc.com/datasheet/pdf/33adf36a71e298ca40968a58... |
| AMS1117-3.3 (Advanced Monolithic Systems) — datasheet, cited pages 1 micmodshop.ir/wp-content/uploads/2021/11/AMS1117-DataShee... |
| GZ2012D601TF (Sunlord) — datasheet, cited pages 1,4 GZ2012D601TF.pdf |
| TF-008 (SOFNG ELECTRONIC TECHNOLOGY Co., LTD) — datasheet, cited pages 1,2 datasheet.lcsc.com/datasheet/pdf/995e92cc2257e502563199b3... |
| CBL-VGA-002-12 (WinSystems Inc.) — datasheet resources.winsystems.com/datasheets/cbl-vga-002-12-ds.pdf |
12 Designer Annotated Nets
No designer-annotated nets found.
13 EMC & ESD Protection Checks
| Checks run | 1 |
| Passed | 1 |
| Issues found | 0 |
| EMC Check Summary | ||
|---|---|---|
| Check | Issues | Status |
| Connector Shell Grounding | 0 | ✓ |
13.1 ESD/TVS Protection Audit
No high-value interface connectors found for ESD audit.
13.2 EMC & ESD Analysis
This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.
13.2.1 EMC Architecture — grounding, filtering, shielding
AI-Assisted —
The board is a single-ground design: one GND net serves the FPGA U2, the USB host controller U3, the flash U4, the dual-channel bridge U6, both regulators, and all connector returns. There is no separated chassis/shield domain — the shell/mounting tabs of USB1 and USB2 (pins 13, 14 and both A1B12/B1A12 contacts) are on the same logic GND net, so the shield bond strategy is not captured as design intent on the schematic. Per IEC 61000-4-2 the shell is the primary ESD injection point on a Type-C receptacle; without a dedicated per-connector shield net (e.g. SHIELD_GND_USB1, SHIELD_GND_USB2) the layout tool receives no net-level guidance to keep each connector's pour separate or to place bond components. Scenario A, plastic enclosure: bond each shield pour directly to the logic ground plane with dense via stitching, no isolation network, so the plane and shell rise together during a strike and differential stress across the contacts stays near zero. Scenario B, metal chassis with earth: evaluate a 1 Mohm || 4.7 nF (2 kV or higher) bridge from each shield pour to logic GND with mechanical bonding of the pour to chassis at the panel opening; if the pour can bond to both earth and logic GND without a loop, the RC may be unnecessary. Line filtering is limited to 33 ohm series resistors on the USB1 data pair; no common-mode chokes or ferrites appear on VBUS or the header signals, leaving radiated emissions margin to CISPR 32/EN 55032 Class B dependent entirely on layout.
13.2.2 USB1 (Type-C, peripheral-side host port)
AI-Assisted —
USB1 is an external, user-accessible consumer port. It operates as a source: R40 and R44 (56K each) pull CC1 and CC2 to VBUS, which per USB Type-C R2.5 advertises Default USB Power to the attached sink. Its VBUS contacts are fed from the board VBUS rail through F1 (MF-NSMF020-2), a resettable PTC. PER_D+/PER_D- reach U3 (MAX3421EETJ+T) D+/D- through R6 and R5 (33 each), which is the correct USB 2.0 full-speed series termination and adds useful high-frequency damping, but provides no transient clamping. The data pair, CC1 and CC2 therefore present a direct low-impedance path from an exposed contact to the transceiver pins; there is no isolating magnetics as with Ethernet, so IEC 61000-4-2 contact discharge at the receptacle couples straight into U3. A low-capacitance (about 0.5 pF per line) bidirectional array on PER_D+/PER_D- and on the CC lines, sited at the receptacle, is the conventional answer for hot-plug interfaces; the CC pins are exposed on every insertion and are commonly the first to fail. SBU1/SBU2 are unused, so no protection is needed there. F1's 0.2 A hold current sits below the 500 mA the 56K Rp advertises, so a compliant sink drawing its advertised allocation will trip the port protector.
13.2.3 USB2 (Type-C, programming/power-input port)
AI-Assisted —
USB2 is the external power and programming port and the board's only supply entry. R3 and R4 (5.1K to GND) on CC1/CC2 are the correct sink Rd terminations per USB Type-C R2.5, so the port takes 5 V from an external source; VBUS from USB2 feeds U1 (AMS1117-1.2) and U5 (AMS1117-3.3) and is also exported on J1 pin 12. PROG_D+/PROG_D- reach U6 (FT2232HL) DP/DM through R15 and R14, both 0 ohm, i.e. placeholders with no series damping and no clamp element. The VBUS contact pair itself has no transient clamp: a cable-borne surge or an IEC 61000-4-2 discharge onto the VBUS contact propagates unattenuated to both regulator inputs and, through J1 pin 12, off-board. A 5 V-standoff unidirectional TVS at the USB2 VBUS contacts (clamping below the AMS1117 absolute-maximum input rating) plus a low-capacitance bidirectional array on PROG_D+/PROG_D- and on the CC lines is the standard treatment for this topology; any such part must be sited at the receptacle, not at the IC. Because USB2 is the supply inlet, conducted-emission behaviour on the cable (EN 55032 Class B, mains-port-equivalent limits for the DC inlet in ITE assessments) rests on C1 alone; a common-mode choke or ferrite in the VBUS/GND path is worth evaluating.
13.2.4 J1 and J2 (2.54 mm pin headers)
AI-Assisted —
J1 (1x12, vertical, 2.54 mm) and J2 (1x08, vertical, 2.54 mm) are unshielded, unlatched vertical headers — the classic board-to-board or ribbon-cable interconnect signature rather than a panel-mount external port. J1 carries nine FPGA IOs (IOT_42b, IOT_43a, IOT_44b, IOT_45a_G1, IOT_46b_G0, IOT_48b, IOT_49a, IOT_50b, IOT_51a) directly from U2 pins with no series resistors, no filtering and no clamps, plus +3V3 on pin 11 and VBUS on pin 12, both unfused and unprotected at the header. Two of these nets are global clock inputs (G0, G1), so any cable attached here becomes both a radiator and a receptor on a clock-capable input — a plausible source of radiated emissions above 30 MHz under CISPR 32 and of functional upset under IEC 61000-4-4 burst injection. If J1 is intended for anything longer than a short intra-enclosure jumper, small series resistors (22–33 ohm) at U2 and RC or ferrite filtering, together with a rail clamp on the exported +3V3 and VBUS pins, should be considered. J2 exposes the SPI flash bus (CS, SCK, MOSI, MISO) plus FLASH_WP and FLASH_HOLD, with JP1–JP4 in the FPGA path and R41/R42 (10K each) pulling FLASH_WP and FLASH_HOLD to +3V3 and R19 (10K) pulling CS to +3V3; these pull-ups are on-board and correct. The external side may supply its own termination.
13.3 Observations
AI-Assisted —
No TVS, ESD array, zener or clamp diode of any kind appears anywhere on the board, so there is no clamp orientation or polarity question to resolve — the orientation check is vacuous by construction, and nothing is mis-polarised. The board's ESD survival therefore rests entirely on the on-chip structures of U2, U3 and U6, which are specified to component-level HBM (JEDEC JS-001) conditions, not to the system-level ±8 kV contact / ±15 kV air discharge of IEC 61000-4-2 that a user-facing Type-C port sees; those two figures are measured under different waveforms and cannot be equated, so the gap cannot be closed numerically from the fitted parts. Both regulators are AMS1117 linear devices fed from the USB inlet, giving no series impedance against fast transients other than their own bandwidth. Decoupling on U2 is extensive on both +1V2 and +3V3 and on U4's +3V3 pin, which supports the high-frequency return-current control needed for emissions compliance. The single-ground architecture is otherwise coherent: every supply and return pin of U2, U3, U4, U6, U1 and U5 sits on a real rail or on GND, with no supply or ground pin isolated behind capacitors only.
13.4 Findings
AI-Assisted —
| # | Connector | Finding | Severity |
|---|---|---|---|
| 13.4.1 | USB1 | Shell/ | Medium |
| 13.4.2 | USB1 | PER_D+/ | Medium |
| 13.4.3 | USB1 | CC1 (via R40, 56K) and CC2 (via R44, 56K) are exposed contacts with no clamp; CC pins are the most insertion-stressed lines on a Type-C receptacle (USB Type-C R2.5; IEC 61000-4-2) | Medium |
| 13.4.4 | USB1 | F1 (MF-NSMF020-2) holding current 0.2 A is below the 500 mA advertised by the 56K Rp, so a compliant sink drawing its allocation trips the port protector; the protective element does not match the advertised source budget (Bourns MF-NSMF series datasheet; USB Type-C R2.5) | Medium |
| 13.4.5 | USB2 | Shell/ | Medium |
| 13.4.6 | USB2 | VBUS contacts (A4B9, B4A9) are the board's only supply entry and carry no transient clamp; a surge reaches U1 and U5 inputs and is exported on J1 pin 12. Investigate a 5 V-standoff clamp at the receptacle, clamping below the AMS1117 input maximum (IEC 61000-4-2, IEC 61000-4-5) | Medium |
| 13.4.7 | USB2 | PROG_D+/ | Medium |
| 13.4.8 | USB2 | Type-C inlet has no common-mode choke or ferrite in the VBUS/ | Low |
| 13.4.9 | J1 | Vertical unshielded 2.54 mm header exports nine FPGA IOs directly from U2 with no series resistance, filtering or clamping; IOT_45a_G1 and IOT_46b_G0 are global clock inputs, giving a radiated-emissions and burst-susceptibility path if cabled (CISPR 32; IEC 61000-4-4) | Low |
| 13.4.10 | J1 | +3V3 (pin 11) and VBUS (pin 12) exported unfused and unclamped at the header (IEC 61000-4-2) | Low |
| 13.4.11 | J2 | Vertical unshielded 2.54 mm SPI header (CS, SCK, MOSI, MISO, FLASH_WP, FLASH_HOLD) with no filtering; internal board-to-board signature, external TVS not normally warranted — off-board cable length governs (IEC 61000-4-2) | Review |
| 13.4.12 | All | System-level ESD immunity cannot be closed from device HBM ratings: JEDEC JS-001 HBM and IEC 61000-4-2 contact/ | Review |
| 13.4.13 | USB1 | R40/ | ✓ |
| 13.4.14 | USB1 | R6/ | ✓ |
| 13.4.15 | USB1 | SBU1/ | ✓ |
| 13.4.16 | USB2 | R3/ | ✓ |
| 13.4.17 | J2 | FLASH_WP and FLASH_HOLD pulled to +3V3 by R41/ | ✓ |
| 13.4.18 | All | No TVS, zener or clamp diode fitted anywhere on the board; clamp orientation/ | ✓ |
| 13.4.19 | All | Single unified GND domain with no separate chassis/ | ✓ |
| 13.4.20 | U2/ | Decoupling present on both +1V2 and +3V3 domains of U2 and on U4's +3V3 pin, supporting high-frequency return-current control for emissions compliance (Lattice iCE40 UltraPlus datasheet) | ✓ |
14 Design-for-Test
Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.
14.1 DFx Options Selected
| Option | Setting | Description |
|---|---|---|
| Test Point Insertion | ||
| Insert on power rails | Yes | Place test points on power rail nets in schematic |
| Insert on all nets | No | Extend TP insertion to signal nets beyond power rails |
| Exclude HSSI nets | Yes | Exclude HSSI/ |
| Exclude DRAM nets | Yes | Exclude SDRAM/ |
| Exclude BSCAN opens (full) | Yes | Exclude nets with 100% boundary scan opens coverage |
| Exclude BSCAN opens (partial) | No | Exclude nets with partial boundary scan opens coverage |
| Exclude BSCAN shorts | No | Exclude nets with boundary scan shorts coverage |
| GND test points | 6 | Number of GND test points to insert for BON fixture ground connections |
| Target PCOLA-SOQ | 0% | Insert TPs in priority order until this PCOLA-SOQ % is reached |
| Target fault coverage | 0% | Insert TPs in priority order until this shorts/ |
| Kelvin min resistance | 0.000 ohm | Lower bound (ohms) for Kelvin 4-wire TP insertion range |
| Kelvin max resistance | 1.000 ohm | Upper bound (ohms) for Kelvin 4-wire TP insertion range |
| Tester Styles | ||
| Optical | AOI | Automated Optical Inspection of visible solder joints |
| AXI | Yes | Automated X-ray Inspection of hidden solder joints (BGA, QFN) |
| ATE | Flying_probe | Digital IO, DMM, shorts/ |
| Test Access | ||
| JTAG/ | Yes | Connector access to JTAG, SPI, I2C buses |
| IO Connectors | No | IO connectors available for external stimulus/ |
| TP Access | Flying_probe | Flying probe access without fixture |
| Test Point Identification | ||
| BON TP refdes | TP#,TP-*,TP_*,TP#* | Refdes patterns identifying BON test points |
| BON TP footprints | * | All footprints accepted |
| FP TP refdes | TP#,TP-*,TP_*,TP#*,MP# | Refdes patterns identifying flying probe test points |
| FP TP footprints | * | All footprints accepted |
| Loopback | None | No loopback cables |
| Test Types | ||
| Powered-Off Shorts/ | Yes | Unpowered shorts and opens detection via probe access |
| Passives | Yes | R, C, L value measurement via probe or fixture access |
| Active Analog | No | Voltage regulator, reference, and op-amp output verification |
| Non-BSCAN Digital | No | Digital ICs without boundary scan: pin observability analysis |
| Boundary Scan | 1149.1_1149.6 | IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan |
| LSSI | No | JTAG chain, SPI, I2C, UART bus test coverage analysis |
| JTAG Functional | No | Functional verification beyond structural scan |
| Require Rail TPs for Diode Test | No | Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only) |
| Capacitance Probe Plate Target Devices | — | Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors) |
| Use Boundary Scan for Capacitance Probe Plate Stimulus | No | Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / |
| NVM Programming | ||
| Default Method | Direct | Program via direct pin access; TPs on flash data/ |
| Environment | ||
| Test environment | lab | Prototype/ |
14.2 Power Rail Test Point Check
| Power rails found | 4 |
| Rails with TPs | 4 |
| Rails without TPs | 0 |
| Power Rail Coverage | |||
|---|---|---|---|
| Net Name | Annotation | Test Point | Status |
| +1V2 | TP6 | ✓ | |
| +3V3 | TP5 | ✓ | |
| GND | TP3 | ✓ | |
| VBUS | TP4 | ✓ | |
14.3 Kelvin Test Points Check
| Threshold | 0.000 < R ≤ 1.000 Ω |
| Current sense resistors found | 0 |
No current sense resistors found in range (0 < R < 1.000 ohm).
14.4 Current Test Points
| Total test points | 5 |
| Test Points by Footprint | ||
|---|---|---|
| Footprint | Description | Count |
| TestPoint_Pad_D2.0mm | TestPoint | 5 |
14.4.1 By Sheet
| Test Point | Net Name | Footprint |
|---|---|---|
| Icey (5 test points) | ||
| TP3 | GND | TestPoint_Pad_D2.0mm |
| TP4 | VBUS | TestPoint_Pad_D2.0mm |
| TP5 | +3V3 | TestPoint_Pad_D2.0mm |
| TP6 | +1V2 | TestPoint_Pad_D2.0mm |
| TP7 | VCORE | TestPoint_Pad_D2.0mm |
14.4.2 All Test Points
| Test Point | Net Name | Sheet | Footprint |
|---|---|---|---|
| TP3 | GND | Icey | TestPoint_Pad_D2.0mm |
| TP4 | VBUS | Icey | TestPoint_Pad_D2.0mm |
| TP5 | +3V3 | Icey | TestPoint_Pad_D2.0mm |
| TP6 | +1V2 | Icey | TestPoint_Pad_D2.0mm |
| TP7 | VCORE | Icey | TestPoint_Pad_D2.0mm |
14.5 Powered-off Testing
5 nets with test points: 4 pins with opens coverage, 4 pins with partial opens, 167 pins with shorts coverage.
Open pin faults may be masked when two or more IC pins share a net (current flow through one internal pin ESD diode may mask the open on another).
| Powered-off Test Coverage by Net | ||||
|---|---|---|---|---|
| Pin ⇅ | Net ⇅ | Type ⇅ | Opens ⇅ | Shorts ⇅ |
| C9_2 | +1V2 | Capacitor | - | ● |
| C29_1 | +1V2 | Capacitor | - | ● |
| C30_2 | +1V2 | Capacitor | - | ● |
| C39_2 | +1V2 | Capacitor | - | ● |
| R33_1 | +1V2 | Passive | - | ● |
| U1_2 | +1V2 | IC | - | ● |
| U2_5 | +1V2 | IC | - | ● |
| U2_30 | +1V2 | IC | - | ● |
| Card1_4 | +3V3 | Passive | - | ● |
| C2_1 | +3V3 | Capacitor | - | ● |
| C3_2 | +3V3 | Capacitor | - | ● |
| C12_1 | +3V3 | Capacitor | - | ● |
| C20_1 | +3V3 | Capacitor | - | ● |
| C21_2 | +3V3 | Capacitor | - | ● |
| C22_2 | +3V3 | Capacitor | - | ● |
| C23_2 | +3V3 | Capacitor | - | ● |
| C26_1 | +3V3 | Capacitor | - | ● |
| C27_1 | +3V3 | Capacitor | - | ● |
| C31_2 | +3V3 | Capacitor | - | ● |
| C32_2 | +3V3 | Capacitor | - | ● |
| C33_1 | +3V3 | Capacitor | - | ● |
| C34_1 | +3V3 | Capacitor | - | ● |
| C35_2 | +3V3 | Capacitor | - | ● |
| C36_2 | +3V3 | Capacitor | - | ● |
| C37_2 | +3V3 | Capacitor | - | ● |
| C38_2 | +3V3 | Capacitor | - | ● |
| J1_11 | +3V3 | Connector | - | ● |
| J2_7 | +3V3 | Connector | - | ● |
| LED3_1 | +3V3 | Passive | - | ● |
| L1_2 | +3V3 | Passive | - | ● |
| L2_2 | +3V3 | Passive | - | ● |
| R17_1 | +3V3 | Passive | - | ● |
| R19_1 | +3V3 | Passive | - | ● |
| R20_1 | +3V3 | Passive | - | ● |
| R21_1 | +3V3 | Passive | - | ● |
| R34_2 | +3V3 | Passive | - | ● |
| R36_1 | +3V3 | Passive | - | ● |
| R38_1 | +3V3 | Passive | - | ● |
| R39_1 | +3V3 | Passive | - | ● |
| R41_2 | +3V3 | Passive | - | ● |
| R42_2 | +3V3 | Passive | - | ● |
| R45_1 | +3V3 | Passive | - | ● |
| R46_1 | +3V3 | Passive | - | ● |
| R47_1 | +3V3 | Passive | - | ● |
| R48_1 | +3V3 | Passive | - | ● |
| U2_1 | +3V3 | IC | - | ● |
| U2_22 | +3V3 | IC | - | ● |
| U2_24 | +3V3 | IC | - | ● |
| U2_33 | +3V3 | IC | - | ● |
| U3_2 | +3V3 | IC | - | ● |
| U3_23 | +3V3 | IC | - | ● |
| U4_8 | +3V3 | IC | - | ● |
| U5_2 | +3V3 | IC | - | ● |
| U6_20 | +3V3 | IC | - | ● |
| U6_31 | +3V3 | IC | - | ● |
| U6_42 | +3V3 | IC | - | ● |
| U6_50 | +3V3 | IC | - | ● |
| U6_56 | +3V3 | IC | - | ● |
| Card1_6 | GND | Passive | - | ● |
| Card1_9 | GND | Passive | - | ● |
| Card1_10 | GND | Passive | - | ● |
| Card1_11 | GND | Passive | - | ● |
| C1_2 | GND | Capacitor | - | ● |
| C2_2 | GND | Capacitor | - | ● |
| C3_1 | GND | Capacitor | - | ● |
| C4_1 | GND | Capacitor | - | ● |
| C5_1 | GND | Capacitor | - | ● |
| C6_2 | GND | Capacitor | - | ● |
| C7_2 | GND | Capacitor | - | ● |
| C8_1 | GND | Capacitor | - | ● |
| C9_1 | GND | Capacitor | - | ● |
| C12_2 | GND | Capacitor | - | ● |
| C13_2 | GND | Capacitor | - | ● |
| C14_2 | GND | Capacitor | - | ● |
| C15_2 | GND | Capacitor | - | ● |
| C16_2 | GND | Capacitor | - | ● |
| C17_2 | GND | Capacitor | - | ● |
| C18_1 | GND | Capacitor | - | ● |
| C19_1 | GND | Capacitor | - | ● |
| C20_2 | GND | Capacitor | - | ● |
| C21_1 | GND | Capacitor | - | ● |
| C22_1 | GND | Capacitor | - | ● |
| C23_1 | GND | Capacitor | - | ● |
| C24_2 | GND | Capacitor | - | ● |
| C26_2 | GND | Capacitor | - | ● |
| C27_2 | GND | Capacitor | - | ● |
| C29_2 | GND | Capacitor | - | ● |
| C30_1 | GND | Capacitor | - | ● |
| C31_1 | GND | Capacitor | - | ● |
| C32_1 | GND | Capacitor | - | ● |
| C33_2 | GND | Capacitor | - | ● |
| C34_2 | GND | Capacitor | - | ● |
| C35_1 | GND | Capacitor | - | ● |
| C36_1 | GND | Capacitor | - | ● |
| C37_1 | GND | Capacitor | - | ● |
| C38_1 | GND | Capacitor | - | ● |
| C39_1 | GND | Capacitor | - | ● |
| C40_1 | GND | Capacitor | - | ● |
| C41_2 | GND | Capacitor | - | ● |
| DSub1_5 | GND | Passive | - | ● |
| DSub1_6 | GND | Passive | - | ● |
| DSub1_7 | GND | Passive | - | ● |
| DSub1_8 | GND | Passive | - | ● |
| DSub1_10 | GND | Passive | - | ● |
| DSub1_16 | GND | Passive | - | ● |
| DSub1_17 | GND | Passive | - | ● |
| H1_1 | GND | Passive | ● | ● |
| H2_1 | GND | Passive | ● | ● |
| H3_1 | GND | Passive | ● | ● |
| H4_1 | GND | Passive | ● | ● |
| J1_10 | GND | Connector | - | ● |
| J2_8 | GND | Connector | - | ● |
| LED1_2 | GND | Passive | - | ● |
| R3_2 | GND | Passive | - | ● |
| R4_2 | GND | Passive | - | ● |
| R9_2 | GND | Passive | - | ● |
| R16_2 | GND | Passive | - | ● |
| SW2_2 | GND | Passive | - | ● |
| SW3_2 | GND | Passive | - | ● |
| USB1_A1B12 | GND | Connector | - | ● |
| USB1_B1A12 | GND | Connector | - | ● |
| USB1_13 | GND | Connector | - | ● |
| USB1_14 | GND | Connector | - | ● |
| USB2_A1B12 | GND | Connector | - | ● |
| USB2_B1A12 | GND | Connector | - | ● |
| USB2_13 | GND | Connector | - | ● |
| USB2_14 | GND | Connector | - | ● |
| U1_1 | GND | IC | - | ● |
| U2_49 | GND | IC | - | ● |
| U3_3 | GND | IC | - | ● |
| U3_19 | GND | IC | - | ● |
| U3_33 | GND | IC | - | ● |
| U4_4 | GND | IC | - | ● |
| U5_1 | GND | IC | - | ● |
| U6_1 | GND | IC | - | ● |
| U6_5 | GND | IC | - | ● |
| U6_10 | GND | IC | - | ● |
| U6_11 | GND | IC | - | ● |
| U6_13 | GND | IC | - | ● |
| U6_15 | GND | IC | - | ● |
| U6_25 | GND | IC | - | ● |
| U6_35 | GND | IC | - | ● |
| U6_47 | GND | IC | - | ● |
| U6_51 | GND | IC | - | ● |
| X1_2 | GND | Passive | - | ● |
| X1_4 | GND | Passive | - | ● |
| X2_2 | GND | Passive | - | ● |
| X2_4 | GND | Passive | - | ● |
| C1_1 | VBUS | Capacitor | - | ● |
| F1_2 | VBUS | Passive | - | ● |
| J1_12 | VBUS | Connector | - | ● |
| LED4_2 | VBUS | Passive | - | ● |
| R40_2 | VBUS | Passive | - | ● |
| R44_1 | VBUS | Passive | - | ● |
| USB2_A4B9 | VBUS | Connector | - | ● |
| USB2_B4A9 | VBUS | Connector | - | ● |
| U1_3 | VBUS | IC | - | ● |
| U5_3 | VBUS | IC | - | ● |
| C13_1 | VCORE | Capacitor | - | ● |
| C14_1 | VCORE | Capacitor | - | ● |
| C17_1 | VCORE | Capacitor | - | ● |
| C18_2 | VCORE | Capacitor | - | ● |
| C19_2 | VCORE | Capacitor | - | ● |
| U6_12 | VCORE | IC | ◐ | ● |
| U6_37 | VCORE | IC | ◐ | ● |
| U6_49 | VCORE | IC | ◐ | ● |
| U6_64 | VCORE | IC | ◐ | ● |
14.6 Powered-on Testing
Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.
4 power rail nets with test points: 61 source-path pins (opens + shorts), 101 sink pins (shorts only).
| Powered-on Test Coverage by Power Rail | ||||
|---|---|---|---|---|
| Pin ⇅ | Net ⇅ | Role ⇅ | Opens ⇅ | Shorts ⇅ |
| C9_2 | +1V2 | Sink | - | ● |
| C29_1 | +1V2 | Sink | - | ● |
| C30_2 | +1V2 | Sink | - | ● |
| C39_2 | +1V2 | Sink | - | ● |
| R33_1 | +1V2 | Series (U2 → R33) | ● | ● |
| TP6_1 | +1V2 | Sink | - | ● |
| U1_2 | +1V2 | Source (VO) | ● | ● |
| U2_5 | +1V2 | Series path | ● | ● |
| U2_30 | +1V2 | Series path | ● | ● |
| Card1_4 | +3V3 | Sink | - | ● |
| C2_1 | +3V3 | Sink | - | ● |
| C3_2 | +3V3 | Sink | - | ● |
| C12_1 | +3V3 | Sink | - | ● |
| C20_1 | +3V3 | Sink | - | ● |
| C21_2 | +3V3 | Sink | - | ● |
| C22_2 | +3V3 | Sink | - | ● |
| C23_2 | +3V3 | Sink | - | ● |
| C26_1 | +3V3 | Sink | - | ● |
| C27_1 | +3V3 | Sink | - | ● |
| C31_2 | +3V3 | Sink | - | ● |
| C32_2 | +3V3 | Sink | - | ● |
| C33_1 | +3V3 | Sink | - | ● |
| C34_1 | +3V3 | Sink | - | ● |
| C35_2 | +3V3 | Sink | - | ● |
| C36_2 | +3V3 | Sink | - | ● |
| C37_2 | +3V3 | Sink | - | ● |
| C38_2 | +3V3 | Sink | - | ● |
| J1_11 | +3V3 | Sink | - | ● |
| J2_7 | +3V3 | Sink | - | ● |
| LED3_1 | +3V3 | Sink | - | ● |
| L1_2 | +3V3 | Series (U6 → L1) | ● | ● |
| L2_2 | +3V3 | Series (U6 → L2) | ● | ● |
| R17_1 | +3V3 | Series (U6 → R17) | ● | ● |
| R19_1 | +3V3 | Series (U2 → R19) | ● | ● |
| R20_1 | +3V3 | Series (U2 → R20) | ● | ● |
| R21_1 | +3V3 | Series (U2 → R21) | ● | ● |
| R34_2 | +3V3 | Series (U2 → R34) | ● | ● |
| R36_1 | +3V3 | Sink | - | ● |
| R38_1 | +3V3 | Sink | - | ● |
| R39_1 | +3V3 | Series (U2 → R39) | ● | ● |
| R41_2 | +3V3 | Series (U4 → R41) | ● | ● |
| R42_2 | +3V3 | Series (U4 → R42) | ● | ● |
| R45_1 | +3V3 | Series (U3 → R45) | ● | ● |
| R46_1 | +3V3 | Series (U3 → R46) | ● | ● |
| R47_1 | +3V3 | Series (U3 → R47) | ● | ● |
| R48_1 | +3V3 | Sink | - | ● |
| TP5_1 | +3V3 | Sink | - | ● |
| U2_1 | +3V3 | Series path | ● | ● |
| U2_22 | +3V3 | Series path | ● | ● |
| U2_24 | +3V3 | Series path | ● | ● |
| U2_33 | +3V3 | Series path | ● | ● |
| U3_2 | +3V3 | Series path | ● | ● |
| U3_23 | +3V3 | Series path | ● | ● |
| U4_8 | +3V3 | Series path | ● | ● |
| U5_2 | +3V3 | Source (VO) | ● | ● |
| U6_20 | +3V3 | Series path | ● | ● |
| U6_31 | +3V3 | Series path | ● | ● |
| U6_42 | +3V3 | Series path | ● | ● |
| U6_50 | +3V3 | Series path | ● | ● |
| U6_56 | +3V3 | Series path | ● | ● |
| Card1_6 | GND | Sink | - | ● |
| Card1_9 | GND | Sink | - | ● |
| Card1_10 | GND | Sink | - | ● |
| Card1_11 | GND | Sink | - | ● |
| C1_2 | GND | Sink | - | ● |
| C2_2 | GND | Sink | - | ● |
| C3_1 | GND | Sink | - | ● |
| C4_1 | GND | Series (U3 → C4) | ● | ● |
| C5_1 | GND | Series (U2 → C5) | ● | ● |
| C6_2 | GND | Series (U3 → C6) | ● | ● |
| C7_2 | GND | Series (U3 → C7) | ● | ● |
| C8_1 | GND | Series (U2 → C8) | ● | ● |
| C9_1 | GND | Sink | - | ● |
| C12_2 | GND | Sink | - | ● |
| C13_2 | GND | Series (U6 → C13) | ● | ● |
| C14_2 | GND | Series (U6 → C14) | ● | ● |
| C15_2 | GND | Series (U6 → C15) | ● | ● |
| C16_2 | GND | Series (U6 → C16) | ● | ● |
| C17_2 | GND | Series (U6 → C17) | ● | ● |
| C18_1 | GND | Series (U6 → C18) | ● | ● |
| C19_1 | GND | Series (U6 → C19) | ● | ● |
| C20_2 | GND | Sink | - | ● |
| C21_1 | GND | Sink | - | ● |
| C22_1 | GND | Sink | - | ● |
| C23_1 | GND | Sink | - | ● |
| C24_2 | GND | Series (U6 → C24) | ● | ● |
| C26_2 | GND | Sink | - | ● |
| C27_2 | GND | Sink | - | ● |
| C29_2 | GND | Sink | - | ● |
| C30_1 | GND | Sink | - | ● |
| C31_1 | GND | Sink | - | ● |
| C32_1 | GND | Sink | - | ● |
| C33_2 | GND | Sink | - | ● |
| C34_2 | GND | Sink | - | ● |
| C35_1 | GND | Sink | - | ● |
| C36_1 | GND | Sink | - | ● |
| C37_1 | GND | Sink | - | ● |
| C38_1 | GND | Sink | - | ● |
| C39_1 | GND | Sink | - | ● |
| C40_1 | GND | Series (U6 → C40) | ● | ● |
| C41_2 | GND | Series (U6 → C41) | ● | ● |
| DSub1_5 | GND | Sink | - | ● |
| DSub1_6 | GND | Sink | - | ● |
| DSub1_7 | GND | Sink | - | ● |
| DSub1_8 | GND | Sink | - | ● |
| DSub1_10 | GND | Sink | - | ● |
| DSub1_16 | GND | Sink | - | ● |
| DSub1_17 | GND | Sink | - | ● |
| H1_1 | GND | Sink | - | ● |
| H2_1 | GND | Sink | - | ● |
| H3_1 | GND | Sink | - | ● |
| H4_1 | GND | Sink | - | ● |
| J1_10 | GND | Sink | - | ● |
| J2_8 | GND | Sink | - | ● |
| LED1_2 | GND | Sink | - | ● |
| R3_2 | GND | Sink | - | ● |
| R4_2 | GND | Sink | - | ● |
| R9_2 | GND | Series (U6 → R9) | ● | ● |
| R16_2 | GND | Series (U6 → R16) | ● | ● |
| SW2_2 | GND | Sink | - | ● |
| SW3_2 | GND | Sink | - | ● |
| TP3_1 | GND | Sink | - | ● |
| USB1_A1B12 | GND | Sink | - | ● |
| USB1_B1A12 | GND | Sink | - | ● |
| USB1_13 | GND | Sink | - | ● |
| USB1_14 | GND | Sink | - | ● |
| USB2_A1B12 | GND | Sink | - | ● |
| USB2_B1A12 | GND | Sink | - | ● |
| USB2_13 | GND | Sink | - | ● |
| USB2_14 | GND | Sink | - | ● |
| U1_1 | GND | Sink | - | ● |
| U2_49 | GND | Series path | ● | ● |
| U3_3 | GND | Series path | ● | ● |
| U3_19 | GND | Series path | ● | ● |
| U3_33 | GND | Series path | ● | ● |
| U4_4 | GND | Sink | - | ● |
| U5_1 | GND | Sink | - | ● |
| U6_1 | GND | Series path | ● | ● |
| U6_5 | GND | Series path | ● | ● |
| U6_10 | GND | Series path | ● | ● |
| U6_11 | GND | Series path | ● | ● |
| U6_13 | GND | Series path | ● | ● |
| U6_15 | GND | Series path | ● | ● |
| U6_25 | GND | Series path | ● | ● |
| U6_35 | GND | Series path | ● | ● |
| U6_47 | GND | Series path | ● | ● |
| U6_51 | GND | Series path | ● | ● |
| X1_2 | GND | Sink | - | ● |
| X1_4 | GND | Sink | - | ● |
| X2_2 | GND | Sink | - | ● |
| X2_4 | GND | Sink | - | ● |
| C1_1 | VBUS | Sink | - | ● |
| F1_2 | VBUS | Sink | - | ● |
| J1_12 | VBUS | Sink | - | ● |
| LED4_2 | VBUS | Sink | - | ● |
| R40_2 | VBUS | Sink | - | ● |
| R44_1 | VBUS | Sink | - | ● |
| TP4_1 | VBUS | Sink | - | ● |
| USB2_A4B9 | VBUS | Sink | - | ● |
| USB2_B4A9 | VBUS | Sink | - | ● |
| U1_3 | VBUS | Sink | - | ● |
| U5_3 | VBUS | Sink | - | ● |
14.7 Boundary Scan Testability
No boundary scan capable devices were found in this design.
14.8 Inspection
Total: 96 components, 370 of 410 pins with inspection coverage.
14.8.1 AOI
| Assumed Classification (Non-IPC Footprints) | |||||||
|---|---|---|---|---|---|---|---|
| Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect. | |||||||
| Footprint | Size (mil) | Pkg Type | Classification | Method | Count | Pins | Refdes |
| Opens + Shorts (all joints visible) | |||||||
| easyeda2kicad | |||||||
| LQFP-64_L10.0-W10.0-P0.50-LS12.0-TL | QFP (Quad Flat Pack) | Footprint | 1 | 64 | U6 | ||
| Package_TO_SOT_SMD | |||||||
| SOT-223-3_TabPin2 | SOT (Small Outline Transistor) | Footprint | 2 | 6 | U1, U5 | ||
| Capacitor_SMD | |||||||
| C_0603_1608Metric | Chip Passive | Designator | 29 | 58 | C12, C13, C15, C16, C17, C18, C19, C2 ...+21 more | ||
| C_0805_2012Metric | Chip Passive | Designator | 8 | 16 | C1, C14, C31, C33, C35, C37, C5, C9 | ||
| Resistor_SMD | |||||||
| R_0603_1608Metric | Chip Passive | Designator | 36 | 72 | R14, R15, R16, R17, R18, R19, R20, R21 ...+28 more | ||
| easyeda2kicad | |||||||
| F1206 | Chip Passive | Designator | 1 | 2 | F1 | ||
| L0805 | Chip Passive | Designator | 2 | 4 | L1, L2 | ||
| LED-SMD_4P-L3.2-W2.8-LS3.5-TL-1 | Chip Passive | Designator | 1 | 4 | LED4 | ||
| LED-SMD_L1.6-W0.8-R-RD | Chip Passive | Designator | 3 | 6 | LED1, LED2, LED3 | ||
| Subtotal: 83 components, 232 pins | |||||||
| Opens only (leads visible, shorts unreliable) | |||||||
| easyeda2kicad | |||||||
| SOIC-8_L5.3-W5.3-P1.27-LS8.0-BL | SOIC/ | Footprint | 1 | 8 | U4 | ||
| Subtotal: 1 components, 8 pins | |||||||
| Presence check (manual verification) | |||||||
| Connector_PinHeader_2.54mm | |||||||
| PinHeader_1x08_P2.54mm_Vertical | Connector | Designator | 1 | 8 | J2 | ||
| PinHeader_1x12_P2.54mm_Vertical | Connector | Designator | 1 | 12 | J1 | ||
| easyeda2kicad | |||||||
| USB-C-SMD_TYPE-C-16PIN-2MD-073 | Connector | Designator | 2 | 28 | USB1, USB2 | ||
| Subtotal: 4 components, 48 pins | |||||||
14.8.2 AXI
| Assumed Classification (Non-IPC Footprints) | |||||||
|---|---|---|---|---|---|---|---|
| Hidden-joint classification inferred from Pkg Type property or designator prefix. Footprint names are not IPC-7351B or IPC-7251. | |||||||
| Footprint | Size (mil) | Pkg Type | Classification | Method | Count | Pins | Refdes |
| easyeda2kicad | |||||||
| QFN-48_L7.0-W7.0-P0.50-TL-EP5.4-1 | QFN/ | Footprint | 1 | 49 | U2 | ||
| VQFN-32_L5.0-W5.0-P0.50-BL-EP3.2 | QFN/ | Footprint | 1 | 33 | U3 | ||
| Subtotal: 2 components, 82 pins | |||||||
14.8.3 Unclassified Components
| These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251. | |||||||
| Footprint | Size (mil) | Pkg Type | Classification | Method | Count | Pins | Refdes |
|---|---|---|---|---|---|---|---|
| easyeda2kicad | |||||||
| CRYSTAL-SMD_4P-L3.2-W2.5-BL | Oscillator / | Designator | 2 | 8 | X1, X2 | ||
| D-SUB-TH_VGA-002 | Unclassified | Unknown | 1 | 17 | DSub1 | ||
| SW-SMD_L3.9-W3.0-P4.45 | Unclassified | Unknown | 2 | 4 | SW2, SW3 | ||
| TF-SMD_TF-008 | Unclassified | Unknown | 1 | 11 | Card1 | ||
| Subtotal: 6 components, 40 pins | |||||||
14.9 Pin Fault Coverage
Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.
14.9.1 Fault Coverage Summary
| Fault Coverage Summary (426 pins) | ||
|---|---|---|
| Test Method | Opens | Shorts |
| X-ray (AXI) | 0 (0.0%) | 0 (0.0%) |
| Optical (AOI) | 0 (0.0%) | 0 (0.0%) |
| Electrical | ||
| Powered-off Testing | 65 (15.3%) | 163 (38.3%) |
| Boundary Scan | 0 (0.0%) | 0 (0.0%) |
| LSSI | 17 (4.0%) | 17 (4.0%) |
| Total | 82 (19.2%) | 180 (42.3%) |
| Total Fault Coverage | 82 (19.2%) | 180 (42.3%) |
| No coverage | 344 (80.8%) | 246 (57.7%) |
14.9.2 Uncovered Pins (246)
| These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied. | |
| Pin ⇅ | Net ⇅ |
|---|---|
| R29_2 | GREEN |
| R29_1 | Net-(U2-IOB_31b) |
| JP2_1 | JTAG_TDI |
| R38_2 | Net-(Card1-DAT2) |
| R6_2 | Net-(U3-D+) |
| R6_1 | PER_D+ |
| R33_2 | Net-(U2-VCCPLL) |
| L1_1 | Net-(U6-VPHY) |
| J2_6 | FLASH_HOLD |
| J2_5 | FLASH_WP |
| R36_2 | Net-(LED2-A) |
| R9_1 | Net-(U6-BDBUS3) |
| JP5_2 | creset_b |
| JP5_1 | JTAG_TRST |
| JP4_1 | JTAG_TMS |
| JP7_2 | Net-(JP7-B) |
| JP7_1 | PROG_RX |
| JP3_1 | JTAG_TDO |
| LED1_1 | Net-(LED1-A) |
| C40_2 | Net-(U6-VPHY) |
| R40_1 | Net-(USB1-CC1) |
| JP6_2 | CDONE |
| JP6_1 | ADBUS5 |
| SW2_1 | BUTTON |
| R15_2 | Net-(U6-DP) |
| R15_1 | PROG_D+ |
| LED2_2 | CDONE |
| LED2_1 | Net-(LED2-A) |
| C4_2 | Net-(U3-VBCOMP) |
| R25_2 | RED |
| R25_1 | Net-(U2-IOB_24a) |
| R31_2 | BLUE |
| R31_1 | Net-(U2-IOT_37a) |
| R44_2 | Net-(USB1-CC2) |
| J1_9 | IOT_49a |
| J1_4 | IOT_46b_G0 |
| J1_6 | IOT_45a_G1 |
| J1_1 | IOT_42b |
| J1_3 | IOT_44b |
| J1_5 | IOT_48b |
| J1_7 | IOT_50b |
| J1_2 | IOT_43a |
| J1_8 | IOT_51a |
| C41_1 | Net-(U6-VPLL) |
| USB2_A5 | Net-(USB2-CC1) |
| USB2_B8 | |
| USB2_A6 | PROG_D+ |
| USB2_A7 | PROG_D- |
| USB2_B6 | PROG_D+ |
| USB2_A8 | |
| USB2_B7 | PROG_D- |
| USB2_B5 | Net-(USB2-CC2) |
| R46_2 | SD_SCK |
| DSub1_3 | BLUE |
| DSub1_1 | RED |
| DSub1_9 | |
| DSub1_11 | |
| DSub1_2 | GREEN |
| DSub1_4 | |
| DSub1_13 | HSYNC |
| DSub1_15 | |
| DSub1_14 | VSYNC |
| DSub1_12 | |
| R39_2 | SD_CS |
| SW3_1 | creset_b |
| LED3_2 | Net-(LED3-K) |
| R47_2 | SD_MISO |
| R16_1 | Net-(U6-REF) |
| USB1_A4B9 | Net-(USB1-VBUS) |
| USB1_A5 | Net-(USB1-CC1) |
| USB1_B8 | |
| USB1_A6 | PER_D+ |
| USB1_A7 | PER_D- |
| USB1_B6 | PER_D+ |
| USB1_A8 | |
| USB1_B7 | PER_D- |
| USB1_B5 | Net-(USB1-CC2) |
| USB1_B4A9 | Net-(USB1-VBUS) |
| R4_1 | Net-(USB2-CC2) |
| R28_2 | Net-(U2-IOB_29b) |
| R28_1 | GREEN |
| R20_2 | creset_b |
| F1_1 | Net-(USB1-VBUS) |
| X1_1 | Net-(U3-X0) |
| X1_3 | Net-(U3-XI) |
| R30_2 | BLUE |
| R30_1 | Net-(U2-IOT_38b) |
| R34_1 | BUTTON |
| C6_1 | Net-(U3-XI) |
| C7_1 | Net-(U3-X0) |
| C8_2 | Net-(U2-VCCPLL) |
| R41_1 | FLASH_WP |
| R14_2 | Net-(U6-DM) |
| R14_1 | PROG_D- |
| C24_1 | Net-(U6-VPHY) |
| R24_2 | RED |
| R24_1 | Net-(U2-IOB_23b) |
| R26_2 | Net-(U2-IOB_25b_G3) |
| R26_1 | RED |
| LED4_1 | RGB1 |
| LED4_3 | RGB2 |
| LED4_4 | RGB0 |
| JP8_2 | PROG_TX |
| JP8_1 | Net-(JP8-A) |
| U6_62 | |
| U6_6 | Net-(U6-REF) |
| U6_14 | Net-(U6-RESET) |
| U6_4 | Net-(U6-VPHY) |
| U6_7 | Net-(U6-DM) |
| U6_8 | Net-(U6-DP) |
| U6_63 | |
| U6_61 | |
| U6_2 | Net-(U6-OSCI) |
| U6_3 | Net-(U6-OSCO) |
| U6_9 | Net-(U6-VPLL) |
| U6_33 | |
| U6_22 | ADBUS5 |
| U6_16 | JTAG_TCK |
| U6_27 | |
| U6_30 | |
| U6_34 | |
| U6_54 | Net-(U6-BCBUS3) |
| U6_52 | |
| U6_23 | |
| U6_29 | |
| U6_43 | |
| U6_17 | JTAG_TDI |
| U6_32 | |
| U6_38 | Net-(JP8-A) |
| U6_39 | Net-(JP7-B) |
| U6_19 | JTAG_TMS |
| U6_40 | |
| U6_21 | JTAG_TRST |
| U6_45 | |
| U6_46 | |
| U6_28 | |
| U6_48 | |
| U6_26 | |
| U6_24 | |
| U6_18 | JTAG_TDO |
| U6_53 | |
| U6_44 | |
| U6_41 | Net-(U6-BDBUS3) |
| U6_36 | |
| U6_55 | |
| U6_59 | |
| U6_60 | |
| U6_57 | |
| U6_58 | |
| Card1_1 | Net-(Card1-DAT2) |
| Card1_8 | Net-(Card1-DAT1) |
| Card1_3 | SD_MOSI |
| Card1_5 | SD_SCK |
| Card1_2 | SD_CS |
| Card1_7 | SD_MISO |
| C5_2 | Net-(U2-VCCPLL) |
| U4_1 | Net-(U4-CS) |
| U4_7 | FLASH_HOLD |
| U4_3 | FLASH_WP |
| R45_2 | SD_MOSI |
| R35_2 | Net-(U4-CS) |
| C15_1 | Net-(U6-OSCO) |
| R32_2 | Net-(LED1-A) |
| R32_1 | LED |
| C16_1 | Net-(U6-OSCI) |
| R21_2 | CDONE |
| R3_1 | Net-(USB2-CC1) |
| JP1_1 | JTAG_TCK |
| R5_2 | Net-(U3-D-) |
| R5_1 | PER_D- |
| X2_1 | Net-(U6-OSCO) |
| X2_3 | Net-(U6-OSCI) |
| R27_2 | Net-(U2-IOT_36b) |
| R27_1 | GREEN |
| R17_2 | Net-(U6-RESET) |
| R18_2 | Net-(U6-BCBUS3) |
| R18_1 | Net-(LED3-K) |
| R48_2 | Net-(Card1-DAT1) |
| L2_1 | Net-(U6-VPLL) |
| U2_23 | Net-(U2-IOT_37a) |
| U2_4 | USB_INT |
| U2_11 | FLASH_HOLD |
| U2_19 | Net-(U2-IOB_29b) |
| U2_20 | Net-(U2-IOB_25b_G3) |
| U2_41 | RGB2 |
| U2_12 | FLASH_WP |
| U2_7 | CDONE |
| U2_9 | LED |
| U2_6 | BUTTON |
| U2_8 | creset_b |
| U2_13 | Net-(U2-IOB_24a) |
| U2_3 | USB_RST |
| U2_2 | USB_CS |
| U2_10 | SD_CS |
| U2_18 | Net-(U2-IOB_31b) |
| U2_21 | Net-(U2-IOB_23b) |
| U2_48 | SD_MOSI |
| U2_46 | PROG_TX |
| U2_45 | SD_MISO |
| U2_47 | PROG_RX |
| U2_43 | IOT_49a |
| U2_44 | SD_SCK |
| U2_42 | IOT_51a |
| U2_39 | RGB0 |
| U2_32 | IOT_43a |
| U2_29 | Net-(U2-VCCPLL) |
| U2_36 | IOT_48b |
| U2_26 | HSYNC |
| U2_34 | IOT_44b |
| U2_40 | RGB1 |
| U2_37 | IOT_45a_G1 |
| U2_28 | VSYNC |
| U2_35 | IOT_46b_G0 |
| U2_31 | IOT_42b |
| U2_38 | IOT_50b |
| U2_27 | Net-(U2-IOT_38b) |
| U2_25 | Net-(U2-IOT_36b) |
| R42_1 | FLASH_HOLD |
| U3_4 | |
| U3_14 | USB_CS |
| U3_15 | SD_MISO |
| U3_6 | |
| U3_29 | |
| U3_12 | USB_RST |
| U3_21 | Net-(U3-D+) |
| U3_7 | |
| U3_28 | |
| U3_27 | |
| U3_9 | |
| U3_32 | |
| U3_11 | |
| U3_30 | |
| U3_10 | |
| U3_1 | |
| U3_5 | |
| U3_13 | SD_SCK |
| U3_8 | |
| U3_31 | |
| U3_16 | SD_MOSI |
| U3_26 | |
| U3_25 | Net-(U3-X0) |
| U3_24 | Net-(U3-XI) |
| U3_22 | Net-(U3-VBCOMP) |
| U3_18 | USB_INT |
| U3_17 | |
| U3_20 | Net-(U3-D-) |
14.9.3 Per-Pin Coverage Matrix
● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)
| Pin ⇅ | Net ⇅ | E Opens ⇅ | E Shorts ⇅ | O Opens ⇅ | O Shorts ⇅ | X Opens ⇅ | X Shorts ⇅ |
|---|---|---|---|---|---|---|---|
| R29_2 | GREEN | - | - | - | - | - | - |
| R29_1 | Net-(U2-IOB_31b) | - | - | - | - | - | - |
| C38_1 | GND | - | ● | - | - | - | - |
| C38_2 | +3V3 | - | ● | - | - | - | - |
| C18_1 | GND | ● | ● | - | - | - | - |
| C18_2 | VCORE | - | ● | - | - | - | - |
| JP2_2 | MOSI | ● | ◐ | - | - | - | - |
| JP2_1 | JTAG_TDI | - | - | - | - | - | - |
| R38_2 | Net-(Card1-DAT2) | - | - | - | - | - | - |
| R38_1 | +3V3 | - | ● | - | - | - | - |
| C26_1 | +3V3 | - | ● | - | - | - | - |
| C26_2 | GND | - | ● | - | - | - | - |
| R6_2 | Net-(U3-D+) | - | - | - | - | - | - |
| R6_1 | PER_D+ | - | - | - | - | - | - |
| R33_2 | Net-(U2-VCCPLL) | - | - | - | - | - | - |
| R33_1 | +1V2 | ● | ● | - | - | - | - |
| L1_2 | +3V3 | ● | ● | - | - | - | - |
| L1_1 | Net-(U6-VPHY) | - | - | - | - | - | - |
| J2_3 | MOSI | ● | ◐ | - | - | - | - |
| J2_6 | FLASH_HOLD | - | - | - | - | - | - |
| J2_1 | CS | ● | ◐ | - | - | - | - |
| J2_7 | +3V3 | - | ● | - | - | - | - |
| J2_8 | GND | - | ● | - | - | - | - |
| J2_2 | SCK | ● | ◐ | - | - | - | - |
| J2_5 | FLASH_WP | - | - | - | - | - | - |
| J2_4 | MISO | ● | ◐ | - | - | - | - |
| C33_1 | +3V3 | - | ● | - | - | - | - |
| C33_2 | GND | - | ● | - | - | - | - |
| R36_2 | Net-(LED2-A) | - | - | - | - | - | - |
| R36_1 | +3V3 | - | ● | - | - | - | - |
| R9_2 | GND | ● | ● | - | - | - | - |
| R9_1 | Net-(U6-BDBUS3) | - | - | - | - | - | - |
| JP5_2 | creset_b | - | - | - | - | - | - |
| JP5_1 | JTAG_TRST | - | - | - | - | - | - |
| JP4_2 | CS | ● | ◐ | - | - | - | - |
| JP4_1 | JTAG_TMS | - | - | - | - | - | - |
| JP7_2 | Net-(JP7-B) | - | - | - | - | - | - |
| JP7_1 | PROG_RX | - | - | - | - | - | - |
| C3_1 | GND | - | ● | - | - | - | - |
| C3_2 | +3V3 | - | ● | - | - | - | - |
| JP3_2 | MISO | ● | ◐ | - | - | - | - |
| JP3_1 | JTAG_TDO | - | - | - | - | - | - |
| LED1_2 | GND | - | ● | - | - | - | - |
| LED1_1 | Net-(LED1-A) | - | - | - | - | - | - |
| C40_1 | GND | ● | ● | - | - | - | - |
| C40_2 | Net-(U6-VPHY) | - | - | - | - | - | - |
| C20_1 | +3V3 | - | ● | - | - | - | - |
| C20_2 | GND | - | ● | - | - | - | - |
| C30_1 | GND | - | ● | - | - | - | - |
| C30_2 | +1V2 | - | ● | - | - | - | - |
| R40_2 | VBUS | - | ● | - | - | - | - |
| R40_1 | Net-(USB1-CC1) | - | - | - | - | - | - |
| JP6_2 | CDONE | - | - | - | - | - | - |
| JP6_1 | ADBUS5 | - | - | - | - | - | - |
| SW2_1 | BUTTON | - | - | - | - | - | - |
| SW2_2 | GND | - | ● | - | - | - | - |
| R15_2 | Net-(U6-DP) | - | - | - | - | - | - |
| R15_1 | PROG_D+ | - | - | - | - | - | - |
| LED2_2 | CDONE | - | - | - | - | - | - |
| LED2_1 | Net-(LED2-A) | - | - | - | - | - | - |
| C27_1 | +3V3 | - | ● | - | - | - | - |
| C27_2 | GND | - | ● | - | - | - | - |
| C4_1 | GND | ● | ● | - | - | - | - |
| C4_2 | Net-(U3-VBCOMP) | - | - | - | - | - | - |
| C31_1 | GND | - | ● | - | - | - | - |
| C31_2 | +3V3 | - | ● | - | - | - | - |
| R25_2 | RED | - | - | - | - | - | - |
| R25_1 | Net-(U2-IOB_24a) | - | - | - | - | - | - |
| R31_2 | BLUE | - | - | - | - | - | - |
| R31_1 | Net-(U2-IOT_37a) | - | - | - | - | - | - |
| R44_2 | Net-(USB1-CC2) | - | - | - | - | - | - |
| R44_1 | VBUS | - | ● | - | - | - | - |
| J1_9 | IOT_49a | - | - | - | - | - | - |
| J1_4 | IOT_46b_G0 | - | - | - | - | - | - |
| J1_6 | IOT_45a_G1 | - | - | - | - | - | - |
| J1_1 | IOT_42b | - | - | - | - | - | - |
| J1_3 | IOT_44b | - | - | - | - | - | - |
| J1_5 | IOT_48b | - | - | - | - | - | - |
| J1_7 | IOT_50b | - | - | - | - | - | - |
| J1_2 | IOT_43a | - | - | - | - | - | - |
| J1_8 | IOT_51a | - | - | - | - | - | - |
| J1_10 | GND | - | ● | - | - | - | - |
| J1_11 | +3V3 | - | ● | - | - | - | - |
| J1_12 | VBUS | - | ● | - | - | - | - |
| C41_1 | Net-(U6-VPLL) | - | - | - | - | - | - |
| C41_2 | GND | ● | ● | - | - | - | - |
| USB2_A1B12 | GND | - | ● | - | - | - | - |
| USB2_A4B9 | VBUS | - | ● | - | - | - | - |
| USB2_13 | GND | - | ● | - | - | - | - |
| USB2_A5 | Net-(USB2-CC1) | - | - | - | - | - | - |
| USB2_B8 | - | - | - | - | - | - | |
| USB2_A6 | PROG_D+ | - | - | - | - | - | - |
| USB2_A7 | PROG_D- | - | - | - | - | - | - |
| USB2_B6 | PROG_D+ | - | - | - | - | - | - |
| USB2_A8 | - | - | - | - | - | - | |
| USB2_B7 | PROG_D- | - | - | - | - | - | - |
| USB2_B5 | Net-(USB2-CC2) | - | - | - | - | - | - |
| USB2_B4A9 | VBUS | - | ● | - | - | - | - |
| USB2_B1A12 | GND | - | ● | - | - | - | - |
| USB2_14 | GND | - | ● | - | - | - | - |
| R46_2 | SD_SCK | - | - | - | - | - | - |
| R46_1 | +3V3 | ● | ● | - | - | - | - |
| DSub1_3 | BLUE | - | - | - | - | - | - |
| DSub1_1 | RED | - | - | - | - | - | - |
| DSub1_5 | GND | - | ● | - | - | - | - |
| DSub1_9 | - | - | - | - | - | - | |
| DSub1_11 | - | - | - | - | - | - | |
| DSub1_2 | GREEN | - | - | - | - | - | - |
| DSub1_4 | - | - | - | - | - | - | |
| DSub1_6 | GND | - | ● | - | - | - | - |
| DSub1_7 | GND | - | ● | - | - | - | - |
| DSub1_8 | GND | - | ● | - | - | - | - |
| DSub1_10 | GND | - | ● | - | - | - | - |
| DSub1_13 | HSYNC | - | - | - | - | - | - |
| DSub1_15 | - | - | - | - | - | - | |
| DSub1_14 | VSYNC | - | - | - | - | - | - |
| DSub1_17 | GND | - | ● | - | - | - | - |
| DSub1_12 | - | - | - | - | - | - | |
| DSub1_16 | GND | - | ● | - | - | - | - |
| R39_2 | SD_CS | - | - | - | - | - | - |
| R39_1 | +3V3 | ● | ● | - | - | - | - |
| SW3_1 | creset_b | - | - | - | - | - | - |
| SW3_2 | GND | - | ● | - | - | - | - |
| C23_1 | GND | - | ● | - | - | - | - |
| C23_2 | +3V3 | - | ● | - | - | - | - |
| LED3_2 | Net-(LED3-K) | - | - | - | - | - | - |
| LED3_1 | +3V3 | - | ● | - | - | - | - |
| R47_2 | SD_MISO | - | - | - | - | - | - |
| R47_1 | +3V3 | ● | ● | - | - | - | - |
| R16_2 | GND | ● | ● | - | - | - | - |
| R16_1 | Net-(U6-REF) | - | - | - | - | - | - |
| USB1_A1B12 | GND | - | ● | - | - | - | - |
| USB1_A4B9 | Net-(USB1-VBUS) | - | - | - | - | - | - |
| USB1_13 | GND | - | ● | - | - | - | - |
| USB1_A5 | Net-(USB1-CC1) | - | - | - | - | - | - |
| USB1_B8 | - | - | - | - | - | - | |
| USB1_A6 | PER_D+ | - | - | - | - | - | - |
| USB1_A7 | PER_D- | - | - | - | - | - | - |
| USB1_B6 | PER_D+ | - | - | - | - | - | - |
| USB1_A8 | - | - | - | - | - | - | |
| USB1_B7 | PER_D- | - | - | - | - | - | - |
| USB1_B5 | Net-(USB1-CC2) | - | - | - | - | - | - |
| USB1_B4A9 | Net-(USB1-VBUS) | - | - | - | - | - | - |
| USB1_B1A12 | GND | - | ● | - | - | - | - |
| USB1_14 | GND | - | ● | - | - | - | - |
| R4_2 | GND | - | ● | - | - | - | - |
| R4_1 | Net-(USB2-CC2) | - | - | - | - | - | - |
| C12_1 | +3V3 | - | ● | - | - | - | - |
| C12_2 | GND | - | ● | - | - | - | - |
| R28_2 | Net-(U2-IOB_29b) | - | - | - | - | - | - |
| R28_1 | GREEN | - | - | - | - | - | - |
| C21_1 | GND | - | ● | - | - | - | - |
| C21_2 | +3V3 | - | ● | - | - | - | - |
| R20_2 | creset_b | - | - | - | - | - | - |
| R20_1 | +3V3 | ● | ● | - | - | - | - |
| F1_1 | Net-(USB1-VBUS) | - | - | - | - | - | - |
| F1_2 | VBUS | - | ● | - | - | - | - |
| X1_1 | Net-(U3-X0) | - | - | - | - | - | - |
| X1_3 | Net-(U3-XI) | - | - | - | - | - | - |
| X1_4 | GND | - | ● | - | - | - | - |
| X1_2 | GND | - | ● | - | - | - | - |
| R30_2 | BLUE | - | - | - | - | - | - |
| R30_1 | Net-(U2-IOT_38b) | - | - | - | - | - | - |
| R34_2 | +3V3 | ● | ● | - | - | - | - |
| R34_1 | BUTTON | - | - | - | - | - | - |
| C39_1 | GND | - | ● | - | - | - | - |
| C39_2 | +1V2 | - | ● | - | - | - | - |
| C6_1 | Net-(U3-XI) | - | - | - | - | - | - |
| C6_2 | GND | ● | ● | - | - | - | - |
| C2_1 | +3V3 | - | ● | - | - | - | - |
| C2_2 | GND | - | ● | - | - | - | - |
| U5_3 | VBUS | ● | ● | - | - | - | - |
| U5_1 | GND | ● | ● | - | - | - | - |
| U5_2 | +3V3 | ● | ● | - | - | - | - |
| C7_1 | Net-(U3-X0) | - | - | - | - | - | - |
| C7_2 | GND | ● | ● | - | - | - | - |
| C8_1 | GND | ● | ● | - | - | - | - |
| C8_2 | Net-(U2-VCCPLL) | - | - | - | - | - | - |
| R41_2 | +3V3 | ● | ● | - | - | - | - |
| R41_1 | FLASH_WP | - | - | - | - | - | - |
| R19_2 | CS | ● | ◐ | - | - | - | - |
| R19_1 | +3V3 | ● | ● | - | - | - | - |
| R14_2 | Net-(U6-DM) | - | - | - | - | - | - |
| R14_1 | PROG_D- | - | - | - | - | - | - |
| C24_1 | Net-(U6-VPHY) | - | - | - | - | - | - |
| C24_2 | GND | ● | ● | - | - | - | - |
| R24_2 | RED | - | - | - | - | - | - |
| R24_1 | Net-(U2-IOB_23b) | - | - | - | - | - | - |
| C34_1 | +3V3 | - | ● | - | - | - | - |
| C34_2 | GND | - | ● | - | - | - | - |
| R26_2 | Net-(U2-IOB_25b_G3) | - | - | - | - | - | - |
| R26_1 | RED | - | - | - | - | - | - |
| C14_1 | VCORE | - | ● | - | - | - | - |
| C14_2 | GND | ● | ● | - | - | - | - |
| LED4_1 | RGB1 | - | - | - | - | - | - |
| LED4_3 | RGB2 | - | - | - | - | - | - |
| LED4_2 | VBUS | - | ● | - | - | - | - |
| LED4_4 | RGB0 | - | - | - | - | - | - |
| JP8_2 | PROG_TX | - | - | - | - | - | - |
| JP8_1 | Net-(JP8-A) | - | - | - | - | - | - |
| C17_1 | VCORE | - | ● | - | - | - | - |
| C17_2 | GND | ● | ● | - | - | - | - |
| U6_50 | +3V3 | ● | ● | - | - | - | - |
| U6_1 | GND | ● | ● | - | - | - | - |
| U6_62 | - | - | - | - | - | - | |
| U6_13 | GND | ● | ● | - | - | - | - |
| U6_37 | VCORE | - | ● | - | - | - | - |
| U6_64 | VCORE | - | ● | - | - | - | - |
| U6_10 | GND | ● | ● | - | - | - | - |
| U6_6 | Net-(U6-REF) | - | - | - | - | - | - |
| U6_11 | GND | ● | ● | - | - | - | - |
| U6_14 | Net-(U6-RESET) | - | - | - | - | - | - |
| U6_4 | Net-(U6-VPHY) | - | - | - | - | - | - |
| U6_49 | VCORE | - | ● | - | - | - | - |
| U6_7 | Net-(U6-DM) | - | - | - | - | - | - |
| U6_8 | Net-(U6-DP) | - | - | - | - | - | - |
| U6_63 | - | - | - | - | - | - | |
| U6_61 | - | - | - | - | - | - | |
| U6_2 | Net-(U6-OSCI) | - | - | - | - | - | - |
| U6_3 | Net-(U6-OSCO) | - | - | - | - | - | - |
| U6_9 | Net-(U6-VPLL) | - | - | - | - | - | - |
| U6_5 | GND | ● | ● | - | - | - | - |
| U6_12 | VCORE | - | ● | - | - | - | - |
| U6_15 | GND | ● | ● | - | - | - | - |
| U6_35 | GND | ● | ● | - | - | - | - |
| U6_47 | GND | ● | ● | - | - | - | - |
| U6_25 | GND | ● | ● | - | - | - | - |
| U6_51 | GND | ● | ● | - | - | - | - |
| U6_56 | +3V3 | ● | ● | - | - | - | - |
| U6_20 | +3V3 | ● | ● | - | - | - | - |
| U6_31 | +3V3 | ● | ● | - | - | - | - |
| U6_42 | +3V3 | ● | ● | - | - | - | - |
| U6_33 | - | - | - | - | - | - | |
| U6_22 | ADBUS5 | - | - | - | - | - | - |
| U6_16 | JTAG_TCK | - | - | - | - | - | - |
| U6_27 | - | - | - | - | - | - | |
| U6_30 | - | - | - | - | - | - | |
| U6_34 | - | - | - | - | - | - | |
| U6_54 | Net-(U6-BCBUS3) | - | - | - | - | - | - |
| U6_52 | - | - | - | - | - | - | |
| U6_23 | - | - | - | - | - | - | |
| U6_29 | - | - | - | - | - | - | |
| U6_43 | - | - | - | - | - | - | |
| U6_17 | JTAG_TDI | - | - | - | - | - | - |
| U6_32 | - | - | - | - | - | - | |
| U6_38 | Net-(JP8-A) | - | - | - | - | - | - |
| U6_39 | Net-(JP7-B) | - | - | - | - | - | - |
| U6_19 | JTAG_TMS | - | - | - | - | - | - |
| U6_40 | - | - | - | - | - | - | |
| U6_21 | JTAG_TRST | - | - | - | - | - | - |
| U6_45 | - | - | - | - | - | - | |
| U6_46 | - | - | - | - | - | - | |
| U6_28 | - | - | - | - | - | - | |
| U6_48 | - | - | - | - | - | - | |
| U6_26 | - | - | - | - | - | - | |
| U6_24 | - | - | - | - | - | - | |
| U6_18 | JTAG_TDO | - | - | - | - | - | - |
| U6_53 | - | - | - | - | - | - | |
| U6_44 | - | - | - | - | - | - | |
| U6_41 | Net-(U6-BDBUS3) | - | - | - | - | - | - |
| U6_36 | - | - | - | - | - | - | |
| U6_55 | - | - | - | - | - | - | |
| U6_59 | - | - | - | - | - | - | |
| U6_60 | - | - | - | - | - | - | |
| U6_57 | - | - | - | - | - | - | |
| U6_58 | - | - | - | - | - | - | |
| Card1_1 | Net-(Card1-DAT2) | - | - | - | - | - | - |
| Card1_6 | GND | - | ● | - | - | - | - |
| Card1_8 | Net-(Card1-DAT1) | - | - | - | - | - | - |
| Card1_3 | SD_MOSI | - | - | - | - | - | - |
| Card1_5 | SD_SCK | - | - | - | - | - | - |
| Card1_2 | SD_CS | - | - | - | - | - | - |
| Card1_4 | +3V3 | - | ● | - | - | - | - |
| Card1_7 | SD_MISO | - | - | - | - | - | - |
| Card1_11 | GND | - | ● | - | - | - | - |
| Card1_9 | GND | - | ● | - | - | - | - |
| Card1_10 | GND | - | ● | - | - | - | - |
| C37_1 | GND | - | ● | - | - | - | - |
| C37_2 | +3V3 | - | ● | - | - | - | - |
| C5_1 | GND | ● | ● | - | - | - | - |
| C5_2 | Net-(U2-VCCPLL) | - | - | - | - | - | - |
| U4_1 | Net-(U4-CS) | - | - | - | - | - | - |
| U4_7 | FLASH_HOLD | - | - | - | - | - | - |
| U4_6 | SCK | ● | ◐ | - | - | - | - |
| U4_3 | FLASH_WP | - | - | - | - | - | - |
| U4_2 | MISO | ● | ◐ | - | - | - | - |
| U4_5 | MOSI | ● | ◐ | - | - | - | - |
| U4_4 | GND | - | ● | - | - | - | - |
| U4_8 | +3V3 | ● | ● | - | - | - | - |
| C36_1 | GND | - | ● | - | - | - | - |
| C36_2 | +3V3 | - | ● | - | - | - | - |
| R45_2 | SD_MOSI | - | - | - | - | - | - |
| R45_1 | +3V3 | ● | ● | - | - | - | - |
| C9_1 | GND | - | ● | - | - | - | - |
| C9_2 | +1V2 | - | ● | - | - | - | - |
| R35_2 | Net-(U4-CS) | - | - | - | - | - | - |
| R35_1 | CS | ● | ◐ | - | - | - | - |
| C15_1 | Net-(U6-OSCO) | - | - | - | - | - | - |
| C15_2 | GND | ● | ● | - | - | - | - |
| R32_2 | Net-(LED1-A) | - | - | - | - | - | - |
| R32_1 | LED | - | - | - | - | - | - |
| C1_1 | VBUS | - | ● | - | - | - | - |
| C1_2 | GND | - | ● | - | - | - | - |
| C16_1 | Net-(U6-OSCI) | - | - | - | - | - | - |
| C16_2 | GND | ● | ● | - | - | - | - |
| C29_1 | +1V2 | - | ● | - | - | - | - |
| C29_2 | GND | - | ● | - | - | - | - |
| R21_2 | CDONE | - | - | - | - | - | - |
| R21_1 | +3V3 | ● | ● | - | - | - | - |
| C13_1 | VCORE | - | ● | - | - | - | - |
| C13_2 | GND | ● | ● | - | - | - | - |
| R3_2 | GND | - | ● | - | - | - | - |
| R3_1 | Net-(USB2-CC1) | - | - | - | - | - | - |
| JP1_2 | SCK | ● | ◐ | - | - | - | - |
| JP1_1 | JTAG_TCK | - | - | - | - | - | - |
| R5_2 | Net-(U3-D-) | - | - | - | - | - | - |
| R5_1 | PER_D- | - | - | - | - | - | - |
| X2_1 | Net-(U6-OSCO) | - | - | - | - | - | - |
| X2_3 | Net-(U6-OSCI) | - | - | - | - | - | - |
| X2_4 | GND | - | ● | - | - | - | - |
| X2_2 | GND | - | ● | - | - | - | - |
| R27_2 | Net-(U2-IOT_36b) | - | - | - | - | - | - |
| R27_1 | GREEN | - | - | - | - | - | - |
| R17_2 | Net-(U6-RESET) | - | - | - | - | - | - |
| R17_1 | +3V3 | ● | ● | - | - | - | - |
| C35_1 | GND | - | ● | - | - | - | - |
| C35_2 | +3V3 | - | ● | - | - | - | - |
| U1_3 | VBUS | ● | ● | - | - | - | - |
| U1_2 | +1V2 | ● | ● | - | - | - | - |
| U1_1 | GND | ● | ● | - | - | - | - |
| C32_1 | GND | - | ● | - | - | - | - |
| C32_2 | +3V3 | - | ● | - | - | - | - |
| R18_2 | Net-(U6-BCBUS3) | - | - | - | - | - | - |
| R18_1 | Net-(LED3-K) | - | - | - | - | - | - |
| R48_2 | Net-(Card1-DAT1) | - | - | - | - | - | - |
| R48_1 | +3V3 | - | ● | - | - | - | - |
| L2_2 | +3V3 | ● | ● | - | - | - | - |
| L2_1 | Net-(U6-VPLL) | - | - | - | - | - | - |
| U2_23 | Net-(U2-IOT_37a) | - | - | - | - | - | - |
| U2_49 | GND | ● | ● | - | - | - | - |
| U2_4 | USB_INT | - | - | - | - | - | - |
| U2_11 | FLASH_HOLD | - | - | - | - | - | - |
| U2_15 | SCK | ● | ◐ | - | - | - | - |
| U2_16 | CS | ● | ◐ | - | - | - | - |
| U2_19 | Net-(U2-IOB_29b) | - | - | - | - | - | - |
| U2_20 | Net-(U2-IOB_25b_G3) | - | - | - | - | - | - |
| U2_41 | RGB2 | - | - | - | - | - | - |
| U2_12 | FLASH_WP | - | - | - | - | - | - |
| U2_1 | +3V3 | ● | ● | - | - | - | - |
| U2_7 | CDONE | - | - | - | - | - | - |
| U2_22 | +3V3 | ● | ● | - | - | - | - |
| U2_9 | LED | - | - | - | - | - | - |
| U2_5 | +1V2 | ● | ● | - | - | - | - |
| U2_6 | BUTTON | - | - | - | - | - | - |
| U2_8 | creset_b | - | - | - | - | - | - |
| U2_13 | Net-(U2-IOB_24a) | - | - | - | - | - | - |
| U2_3 | USB_RST | - | - | - | - | - | - |
| U2_2 | USB_CS | - | - | - | - | - | - |
| U2_10 | SD_CS | - | - | - | - | - | - |
| U2_14 | MISO | ● | ◐ | - | - | - | - |
| U2_17 | MOSI | ● | ◐ | - | - | - | - |
| U2_18 | Net-(U2-IOB_31b) | - | - | - | - | - | - |
| U2_21 | Net-(U2-IOB_23b) | - | - | - | - | - | - |
| U2_24 | +3V3 | ● | ● | - | - | - | - |
| U2_48 | SD_MOSI | - | - | - | - | - | - |
| U2_46 | PROG_TX | - | - | - | - | - | - |
| U2_45 | SD_MISO | - | - | - | - | - | - |
| U2_47 | PROG_RX | - | - | - | - | - | - |
| U2_43 | IOT_49a | - | - | - | - | - | - |
| U2_44 | SD_SCK | - | - | - | - | - | - |
| U2_42 | IOT_51a | - | - | - | - | - | - |
| U2_39 | RGB0 | - | - | - | - | - | - |
| U2_32 | IOT_43a | - | - | - | - | - | - |
| U2_33 | +3V3 | ● | ● | - | - | - | - |
| U2_29 | Net-(U2-VCCPLL) | - | - | - | - | - | - |
| U2_36 | IOT_48b | - | - | - | - | - | - |
| U2_26 | HSYNC | - | - | - | - | - | - |
| U2_34 | IOT_44b | - | - | - | - | - | - |
| U2_40 | RGB1 | - | - | - | - | - | - |
| U2_37 | IOT_45a_G1 | - | - | - | - | - | - |
| U2_28 | VSYNC | - | - | - | - | - | - |
| U2_35 | IOT_46b_G0 | - | - | - | - | - | - |
| U2_31 | IOT_42b | - | - | - | - | - | - |
| U2_30 | +1V2 | ● | ● | - | - | - | - |
| U2_38 | IOT_50b | - | - | - | - | - | - |
| U2_27 | Net-(U2-IOT_38b) | - | - | - | - | - | - |
| U2_25 | Net-(U2-IOT_36b) | - | - | - | - | - | - |
| C22_1 | GND | - | ● | - | - | - | - |
| C22_2 | +3V3 | - | ● | - | - | - | - |
| R42_2 | +3V3 | ● | ● | - | - | - | - |
| R42_1 | FLASH_HOLD | - | - | - | - | - | - |
| C19_1 | GND | ● | ● | - | - | - | - |
| C19_2 | VCORE | - | ● | - | - | - | - |
| U3_4 | - | - | - | - | - | - | |
| U3_14 | USB_CS | - | - | - | - | - | - |
| U3_15 | SD_MISO | - | - | - | - | - | - |
| U3_6 | - | - | - | - | - | - | |
| U3_29 | - | - | - | - | - | - | |
| U3_2 | +3V3 | ● | ● | - | - | - | - |
| U3_12 | USB_RST | - | - | - | - | - | - |
| U3_23 | +3V3 | ● | ● | - | - | - | - |
| U3_21 | Net-(U3-D+) | - | - | - | - | - | - |
| U3_7 | - | - | - | - | - | - | |
| U3_28 | - | - | - | - | - | - | |
| U3_27 | - | - | - | - | - | - | |
| U3_9 | - | - | - | - | - | - | |
| U3_19 | GND | ● | ● | - | - | - | - |
| U3_32 | - | - | - | - | - | - | |
| U3_11 | - | - | - | - | - | - | |
| U3_30 | - | - | - | - | - | - | |
| U3_10 | - | - | - | - | - | - | |
| U3_1 | - | - | - | - | - | - | |
| U3_3 | GND | ● | ● | - | - | - | - |
| U3_5 | - | - | - | - | - | - | |
| U3_13 | SD_SCK | - | - | - | - | - | - |
| U3_8 | - | - | - | - | - | - | |
| U3_31 | - | - | - | - | - | - | |
| U3_33 | GND | ● | ● | - | - | - | - |
| U3_16 | SD_MOSI | - | - | - | - | - | - |
| U3_26 | - | - | - | - | - | - | |
| U3_25 | Net-(U3-X0) | - | - | - | - | - | - |
| U3_24 | Net-(U3-XI) | - | - | - | - | - | - |
| U3_22 | Net-(U3-VBCOMP) | - | - | - | - | - | - |
| U3_18 | USB_INT | - | - | - | - | - | - |
| U3_17 | - | - | - | - | - | - | |
| U3_20 | Net-(U3-D-) | - | - | - | - | - | - |
14.10 PCOLA/SOQ Fault Coverage
PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.
14.10.1 Coverage by Test Method
P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality
| PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full). | ||||||||
| Test Method | P | C | O | L | A | S | Opens | Solder Quality |
|---|---|---|---|---|---|---|---|---|
| Electrical Test | 56.2% | 28.1% | 0.0% | 6.2% | 0.0% | 21.5% | 19.0% | 0.0% |
| Optical Inspection (AOI) | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% |
| X-Ray Inspection (AXI) | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% | 0.0% |
| Combined | 56.2% | 28.1% | 0.0% | 6.2% | 0.0% | 21.5% | 19.0% | 0.0% |
14.10.2 PCB Device/Pin Count
Devices (PCOLA): 96
Pins (SOQ): 410
14.10.3 Board-Level Scores
| Board-Level Coverage (0 – 100,000 scale) | ||
|---|---|---|
| Dimension | Score | Coverage |
| PCOLA | 18125 / | 18.1% |
| SOQ | 13496 / | 13.5% |
| Combined | 15810 / | 15.8% |
| Electrical vs Inspection | ||
|---|---|---|
| Source | PCOLA Score | SOQ Score |
| Electrical Test | 18125 / | 13496 / |
| Optical/ | 0 / | 0 / |
| Combined (max) | 18125 / | 13496 / |
14.10.4 PCOLA (96 devices)
● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored
| Score ⇅ | RefDes ⇅ | Type / Footprint ⇅ | Class ⇅ | P ⇅ | C ⇅ | O ⇅ | L ⇅ | A ⇅ | Method ⇅ |
|---|---|---|---|---|---|---|---|---|---|
| 40% | C3 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C38 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C18 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C37 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C26 | 1uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C36 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C27 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C34 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C31 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C33 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C17 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C14 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C21 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C2 | 1uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C23 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C20 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C30 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C12 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C39 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C9 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C1 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C29 | 1uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C13 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C35 | 4.7uF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C32 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C22 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 40% | C19 | 100nF / | Capacitor | ● | ● | ○ | — | ○ | Passive_Meas, Powered_Off |
| 20% | U4 | W25Q128JVSIQTR / | IC | ◐ | ○ | ○ | ◐ | ○ | LSSI, Powered_Off |
| 20% | U2 | ICE40UP5K-SG48I / | IC | ◐ | ○ | ○ | ◐ | ○ | LSSI, Powered_Off |
| 10% | R40 | 56K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | SW2 | TS-1088-AR02016 / | Switch | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | C4 | 1uF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R44 | 56K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | J1 | Conn_01x12 / | Connector | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | C41 | 100nF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | USB2 | TYPE-C 16PIN 2MD / | Connector | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R46 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | DSub1 | VGA-002 / | Other | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | R39 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | SW3 | TS-1088-AR02016 / | Switch | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | LED3 | KT-0603R / | LED | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | R16 | 12K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | USB1 | TYPE-C 16PIN 2MD / | Connector | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R4 | 5.1K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R20 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | F1 | MF-NSMF020-2 / | Fuse | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | X1 | X322512MSB4SI / | Oscillator | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | R34 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | U3 | MAX3421EETJ+T / | IC | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | C6 | 22pF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | U5 | AMS1117-3.3 / | IC | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | C7 | 22pF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | C8 | 100nF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R41 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R19 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | C24 | 100nF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | LED4 | S4-3528RGBTA-A / | LED | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | U6 | FT2232HL / | IC | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | Card1 | TF-008 / | Other | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | C5 | 4.7uF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R45 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R38 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R35 | 0 / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | C15 | 22pF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R33 | 100 / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | C16 | 22pF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | L1 | 600@100MHz / | Inductor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R21 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | J2 | Conn_01x08 / | Connector | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R3 | 5.1K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | X2 | X322512MSB4SI / | Oscillator | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | R17 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R36 | 510 / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | U1 | AMS1117-1.2 / | IC | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | R9 | 1K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R48 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | L2 | 600@100MHz / | Inductor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | R47 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | LED1 | KT-0603R / | LED | ◐ | ○ | ○ | ○ | ○ | Powered_Off |
| 10% | R42 | 10K / | Resistor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 10% | C40 | 1uF / | Capacitor | ◐ | ○ | ○ | — | ○ | Powered_Off |
| 0% | R5 | 33 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R26 | 2K / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R29 | 1K / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R31 | 430 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R14 | 0 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R25 | 1K / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R32 | 510 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R18 | 270 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R30 | 820 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R24 | 510 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | LED2 | KT-0603R / | LED | ○ | ○ | ○ | ○ | ○ | |
| 0% | R28 | 510 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R15 | 0 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R6 | 33 / | Resistor | ○ | ○ | ○ | — | ○ | |
| 0% | R27 | 2K / | Resistor | ○ | ○ | ○ | — | ○ |
14.10.5 SOQ (410 pins)
● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)
| Score ⇅ | Pin ⇅ | Net ⇅ | S ⇅ | O ⇅ | Q ⇅ |
|---|---|---|---|---|---|
| 50% | U5_2 | +3V3 | ◐ | ● | ○ |
| 50% | C17_2 | GND | ◐ | ● | ○ |
| 50% | C4_1 | GND | ◐ | ● | ○ |
| 50% | C7_2 | GND | ◐ | ● | ○ |
| 50% | C18_1 | GND | ◐ | ● | ○ |
| 50% | C40_1 | GND | ◐ | ● | ○ |
| 50% | C6_2 | GND | ◐ | ● | ○ |
| 50% | U5_1 | GND | ◐ | ● | ○ |
| 50% | U6_1 | GND | ◐ | ● | ○ |
| 50% | U6_11 | GND | ◐ | ● | ○ |
| 50% | C8_1 | GND | ◐ | ● | ○ |
| 50% | R20_1 | +3V3 | ◐ | ● | ○ |
| 50% | R39_1 | +3V3 | ◐ | ● | ○ |
| 50% | R33_1 | +1V2 | ◐ | ● | ○ |
| 50% | L1_2 | +3V3 | ◐ | ● | ○ |
| 50% | R41_2 | +3V3 | ◐ | ● | ○ |
| 50% | J2_3 | MOSI | ◐ | ● | ○ |
| 50% | R47_1 | +3V3 | ◐ | ● | ○ |
| 50% | J2_1 | CS | ◐ | ● | ○ |
| 50% | R16_2 | GND | ◐ | ● | ○ |
| 50% | U6_50 | +3V3 | ◐ | ● | ○ |
| 50% | J2_2 | SCK | ◐ | ● | ○ |
| 50% | U6_13 | GND | ◐ | ● | ○ |
| 50% | J2_4 | MISO | ◐ | ● | ○ |
| 50% | R19_2 | CS | ◐ | ● | ○ |
| 50% | C24_2 | GND | ◐ | ● | ○ |
| 50% | U6_10 | GND | ◐ | ● | ○ |
| 50% | R19_1 | +3V3 | ◐ | ● | ○ |
| 50% | R9_2 | GND | ◐ | ● | ○ |
| 50% | U5_3 | VBUS | ◐ | ● | ○ |
| 50% | C41_2 | GND | ◐ | ● | ○ |
| 50% | R46_1 | +3V3 | ◐ | ● | ○ |
| 50% | R34_2 | +3V3 | ◐ | ● | ○ |
| 50% | C14_2 | GND | ◐ | ● | ○ |
| 50% | U6_5 | GND | ◐ | ● | ○ |
| 50% | U6_15 | GND | ◐ | ● | ○ |
| 50% | U6_35 | GND | ◐ | ● | ○ |
| 50% | U6_47 | GND | ◐ | ● | ○ |
| 50% | U6_25 | GND | ◐ | ● | ○ |
| 50% | U6_51 | GND | ◐ | ● | ○ |
| 50% | U6_56 | +3V3 | ◐ | ● | ○ |
| 50% | U6_20 | +3V3 | ◐ | ● | ○ |
| 50% | U6_31 | +3V3 | ◐ | ● | ○ |
| 50% | U6_42 | +3V3 | ◐ | ● | ○ |
| 50% | C5_1 | GND | ◐ | ● | ○ |
| 50% | U4_6 | SCK | ◐ | ● | ○ |
| 50% | U4_2 | MISO | ◐ | ● | ○ |
| 50% | U4_5 | MOSI | ◐ | ● | ○ |
| 50% | U4_8 | +3V3 | ◐ | ● | ○ |
| 50% | R45_1 | +3V3 | ◐ | ● | ○ |
| 50% | U3_33 | GND | ◐ | ● | ○ |
| 50% | R35_1 | CS | ◐ | ● | ○ |
| 50% | C15_2 | GND | ◐ | ● | ○ |
| 50% | C16_2 | GND | ◐ | ● | ○ |
| 50% | R21_1 | +3V3 | ◐ | ● | ○ |
| 50% | C13_2 | GND | ◐ | ● | ○ |
| 50% | R17_1 | +3V3 | ◐ | ● | ○ |
| 50% | U1_3 | VBUS | ◐ | ● | ○ |
| 50% | U1_2 | +1V2 | ◐ | ● | ○ |
| 50% | U1_1 | GND | ◐ | ● | ○ |
| 50% | L2_2 | +3V3 | ◐ | ● | ○ |
| 50% | U2_49 | GND | ◐ | ● | ○ |
| 50% | U2_15 | SCK | ◐ | ● | ○ |
| 50% | U2_16 | CS | ◐ | ● | ○ |
| 50% | U2_1 | +3V3 | ◐ | ● | ○ |
| 50% | U2_22 | +3V3 | ◐ | ● | ○ |
| 50% | U2_5 | +1V2 | ◐ | ● | ○ |
| 50% | U2_14 | MISO | ◐ | ● | ○ |
| 50% | U2_17 | MOSI | ◐ | ● | ○ |
| 50% | U2_24 | +3V3 | ◐ | ● | ○ |
| 50% | U2_33 | +3V3 | ◐ | ● | ○ |
| 50% | U2_30 | +1V2 | ◐ | ● | ○ |
| 50% | R42_2 | +3V3 | ◐ | ● | ○ |
| 50% | C19_1 | GND | ◐ | ● | ○ |
| 50% | U3_2 | +3V3 | ◐ | ● | ○ |
| 50% | U3_23 | +3V3 | ◐ | ● | ○ |
| 50% | U3_19 | GND | ◐ | ● | ○ |
| 50% | U3_3 | GND | ◐ | ● | ○ |
| 17% | USB2_A4B9 | VBUS | ◐ | ○ | ○ |
| 17% | USB2_13 | GND | ◐ | ○ | ○ |
| 17% | C21_1 | GND | ◐ | ○ | ○ |
| 17% | C21_2 | +3V3 | ◐ | ○ | ○ |
| 17% | C34_1 | +3V3 | ◐ | ○ | ○ |
| 17% | F1_2 | VBUS | ◐ | ○ | ○ |
| 17% | C34_2 | GND | ◐ | ○ | ○ |
| 17% | USB2_B4A9 | VBUS | ◐ | ○ | ○ |
| 17% | USB2_B1A12 | GND | ◐ | ○ | ○ |
| 17% | USB2_14 | GND | ◐ | ○ | ○ |
| 17% | U6_64 | VCORE | ◐ | ○ | ○ |
| 17% | DSub1_17 | GND | ◐ | ○ | ○ |
| 17% | X1_4 | GND | ◐ | ○ | ○ |
| 17% | X1_2 | GND | ◐ | ○ | ○ |
| 17% | DSub1_5 | GND | ◐ | ○ | ○ |
| 17% | U6_37 | VCORE | ◐ | ○ | ○ |
| 17% | C14_1 | VCORE | ◐ | ○ | ○ |
| 17% | C38_1 | GND | ◐ | ○ | ○ |
| 17% | C38_2 | +3V3 | ◐ | ○ | ○ |
| 17% | DSub1_6 | GND | ◐ | ○ | ○ |
| 17% | DSub1_7 | GND | ◐ | ○ | ○ |
| 17% | DSub1_8 | GND | ◐ | ○ | ○ |
| 17% | DSub1_10 | GND | ◐ | ○ | ○ |
| 17% | C39_1 | GND | ◐ | ○ | ○ |
| 17% | C39_2 | +1V2 | ◐ | ○ | ○ |
| 17% | C18_2 | VCORE | ◐ | ○ | ○ |
| 17% | U6_12 | VCORE | ◐ | ○ | ○ |
| 17% | R38_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C26_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C26_2 | GND | ◐ | ○ | ○ |
| 17% | DSub1_16 | GND | ◐ | ○ | ○ |
| 17% | C2_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C2_2 | GND | ◐ | ○ | ○ |
| 17% | SW3_2 | GND | ◐ | ○ | ○ |
| 17% | J2_7 | +3V3 | ◐ | ○ | ○ |
| 17% | J2_8 | GND | ◐ | ○ | ○ |
| 17% | Card1_6 | GND | ◐ | ○ | ○ |
| 17% | Card1_4 | +3V3 | ◐ | ○ | ○ |
| 17% | Card1_11 | GND | ◐ | ○ | ○ |
| 17% | Card1_9 | GND | ◐ | ○ | ○ |
| 17% | Card1_10 | GND | ◐ | ○ | ○ |
| 17% | C37_1 | GND | ◐ | ○ | ○ |
| 17% | C37_2 | +3V3 | ◐ | ○ | ○ |
| 17% | C33_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C33_2 | GND | ◐ | ○ | ○ |
| 17% | C23_2 | +3V3 | ◐ | ○ | ○ |
| 17% | R36_1 | +3V3 | ◐ | ○ | ○ |
| 17% | U4_4 | GND | ◐ | ○ | ○ |
| 17% | C3_1 | GND | ◐ | ○ | ○ |
| 17% | C36_1 | GND | ◐ | ○ | ○ |
| 17% | C36_2 | +3V3 | ◐ | ○ | ○ |
| 17% | C3_2 | +3V3 | ◐ | ○ | ○ |
| 17% | C9_1 | GND | ◐ | ○ | ○ |
| 17% | LED1_2 | GND | ◐ | ○ | ○ |
| 17% | LED3_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C20_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C1_1 | VBUS | ◐ | ○ | ○ |
| 17% | C1_2 | GND | ◐ | ○ | ○ |
| 17% | C20_2 | GND | ◐ | ○ | ○ |
| 17% | C29_1 | +1V2 | ◐ | ○ | ○ |
| 17% | C29_2 | GND | ◐ | ○ | ○ |
| 17% | C30_1 | GND | ◐ | ○ | ○ |
| 17% | C13_1 | VCORE | ◐ | ○ | ○ |
| 17% | C30_2 | +1V2 | ◐ | ○ | ○ |
| 17% | R3_2 | GND | ◐ | ○ | ○ |
| 17% | X2_4 | GND | ◐ | ○ | ○ |
| 17% | X2_2 | GND | ◐ | ○ | ○ |
| 17% | R40_2 | VBUS | ◐ | ○ | ○ |
| 17% | C35_1 | GND | ◐ | ○ | ○ |
| 17% | C35_2 | +3V3 | ◐ | ○ | ○ |
| 17% | SW2_2 | GND | ◐ | ○ | ○ |
| 17% | C23_1 | GND | ◐ | ○ | ○ |
| 17% | USB1_A1B12 | GND | ◐ | ○ | ○ |
| 17% | C32_1 | GND | ◐ | ○ | ○ |
| 17% | C32_2 | +3V3 | ◐ | ○ | ○ |
| 17% | C9_2 | +1V2 | ◐ | ○ | ○ |
| 17% | USB1_13 | GND | ◐ | ○ | ○ |
| 17% | C27_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C27_2 | GND | ◐ | ○ | ○ |
| 17% | C31_1 | GND | ◐ | ○ | ○ |
| 17% | C31_2 | +3V3 | ◐ | ○ | ○ |
| 17% | LED4_2 | VBUS | ◐ | ○ | ○ |
| 17% | U6_49 | VCORE | ◐ | ○ | ○ |
| 17% | R44_1 | VBUS | ◐ | ○ | ○ |
| 17% | C17_1 | VCORE | ◐ | ○ | ○ |
| 17% | USB1_B1A12 | GND | ◐ | ○ | ○ |
| 17% | USB1_14 | GND | ◐ | ○ | ○ |
| 17% | R4_2 | GND | ◐ | ○ | ○ |
| 17% | C22_1 | GND | ◐ | ○ | ○ |
| 17% | C22_2 | +3V3 | ◐ | ○ | ○ |
| 17% | C12_1 | +3V3 | ◐ | ○ | ○ |
| 17% | C12_2 | GND | ◐ | ○ | ○ |
| 17% | C19_2 | VCORE | ◐ | ○ | ○ |
| 17% | J1_10 | GND | ◐ | ○ | ○ |
| 17% | J1_11 | +3V3 | ◐ | ○ | ○ |
| 17% | J1_12 | VBUS | ◐ | ○ | ○ |
| 17% | USB2_A1B12 | GND | ◐ | ○ | ○ |
| 17% | R48_1 | +3V3 | ◐ | ○ | ○ |
| 0% | F1_1 | Net-(USB1-VBUS) | ○ | ○ | ○ |
| 0% | X1_1 | Net-(U3-X0) | ○ | ○ | ○ |
| 0% | X1_3 | Net-(U3-XI) | ○ | ○ | ○ |
| 0% | R30_2 | BLUE | ○ | ○ | ○ |
| 0% | R30_1 | Net-(U2-IOT_38b) | ○ | ○ | ○ |
| 0% | R34_1 | BUTTON | ○ | ○ | ○ |
| 0% | C6_1 | Net-(U3-XI) | ○ | ○ | ○ |
| 0% | C7_1 | Net-(U3-X0) | ○ | ○ | ○ |
| 0% | C8_2 | Net-(U2-VCCPLL) | ○ | ○ | ○ |
| 0% | R41_1 | FLASH_WP | ○ | ○ | ○ |
| 0% | R14_2 | Net-(U6-DM) | ○ | ○ | ○ |
| 0% | R14_1 | PROG_D- | ○ | ○ | ○ |
| 0% | C24_1 | Net-(U6-VPHY) | ○ | ○ | ○ |
| 0% | R24_2 | RED | ○ | ○ | ○ |
| 0% | R24_1 | Net-(U2-IOB_23b) | ○ | ○ | ○ |
| 0% | R26_2 | Net-(U2-IOB_25b_G3) | ○ | ○ | ○ |
| 0% | R26_1 | RED | ○ | ○ | ○ |
| 0% | LED4_1 | RGB1 | ○ | ○ | ○ |
| 0% | LED4_3 | RGB2 | ○ | ○ | ○ |
| 0% | LED4_4 | RGB0 | ○ | ○ | ○ |
| 0% | U6_62 | ○ | ○ | ○ | |
| 0% | U6_6 | Net-(U6-REF) | ○ | ○ | ○ |
| 0% | U6_14 | Net-(U6-RESET) | ○ | ○ | ○ |
| 0% | U6_4 | Net-(U6-VPHY) | ○ | ○ | ○ |
| 0% | U6_7 | Net-(U6-DM) | ○ | ○ | ○ |
| 0% | U6_8 | Net-(U6-DP) | ○ | ○ | ○ |
| 0% | U6_63 | ○ | ○ | ○ | |
| 0% | U6_61 | ○ | ○ | ○ | |
| 0% | U6_2 | Net-(U6-OSCI) | ○ | ○ | ○ |
| 0% | U6_3 | Net-(U6-OSCO) | ○ | ○ | ○ |
| 0% | U6_9 | Net-(U6-VPLL) | ○ | ○ | ○ |
| 0% | R29_2 | GREEN | ○ | ○ | ○ |
| 0% | R29_1 | Net-(U2-IOB_31b) | ○ | ○ | ○ |
| 0% | R38_2 | Net-(Card1-DAT2) | ○ | ○ | ○ |
| 0% | R6_2 | Net-(U3-D+) | ○ | ○ | ○ |
| 0% | R6_1 | PER_D+ | ○ | ○ | ○ |
| 0% | R33_2 | Net-(U2-VCCPLL) | ○ | ○ | ○ |
| 0% | L1_1 | Net-(U6-VPHY) | ○ | ○ | ○ |
| 0% | J2_6 | FLASH_HOLD | ○ | ○ | ○ |
| 0% | J2_5 | FLASH_WP | ○ | ○ | ○ |
| 0% | R36_2 | Net-(LED2-A) | ○ | ○ | ○ |
| 0% | R9_1 | Net-(U6-BDBUS3) | ○ | ○ | ○ |
| 0% | U6_33 | ○ | ○ | ○ | |
| 0% | U6_22 | ADBUS5 | ○ | ○ | ○ |
| 0% | U6_16 | JTAG_TCK | ○ | ○ | ○ |
| 0% | U6_27 | ○ | ○ | ○ | |
| 0% | U6_30 | ○ | ○ | ○ | |
| 0% | U6_34 | ○ | ○ | ○ | |
| 0% | U6_54 | Net-(U6-BCBUS3) | ○ | ○ | ○ |
| 0% | U6_52 | ○ | ○ | ○ | |
| 0% | U6_23 | ○ | ○ | ○ | |
| 0% | U6_29 | ○ | ○ | ○ | |
| 0% | U6_43 | ○ | ○ | ○ | |
| 0% | U6_17 | JTAG_TDI | ○ | ○ | ○ |
| 0% | U6_32 | ○ | ○ | ○ | |
| 0% | U6_38 | Net-(JP8-A) | ○ | ○ | ○ |
| 0% | U6_39 | Net-(JP7-B) | ○ | ○ | ○ |
| 0% | U6_19 | JTAG_TMS | ○ | ○ | ○ |
| 0% | U6_40 | ○ | ○ | ○ | |
| 0% | U6_21 | JTAG_TRST | ○ | ○ | ○ |
| 0% | U6_45 | ○ | ○ | ○ | |
| 0% | U6_46 | ○ | ○ | ○ | |
| 0% | U6_28 | ○ | ○ | ○ | |
| 0% | U6_48 | ○ | ○ | ○ | |
| 0% | U6_26 | ○ | ○ | ○ | |
| 0% | U6_24 | ○ | ○ | ○ | |
| 0% | U6_18 | JTAG_TDO | ○ | ○ | ○ |
| 0% | U6_53 | ○ | ○ | ○ | |
| 0% | U6_44 | ○ | ○ | ○ | |
| 0% | U6_41 | Net-(U6-BDBUS3) | ○ | ○ | ○ |
| 0% | U6_36 | ○ | ○ | ○ | |
| 0% | U6_55 | ○ | ○ | ○ | |
| 0% | U6_59 | ○ | ○ | ○ | |
| 0% | U6_60 | ○ | ○ | ○ | |
| 0% | U6_57 | ○ | ○ | ○ | |
| 0% | U6_58 | ○ | ○ | ○ | |
| 0% | Card1_1 | Net-(Card1-DAT2) | ○ | ○ | ○ |
| 0% | LED1_1 | Net-(LED1-A) | ○ | ○ | ○ |
| 0% | Card1_8 | Net-(Card1-DAT1) | ○ | ○ | ○ |
| 0% | Card1_3 | SD_MOSI | ○ | ○ | ○ |
| 0% | Card1_5 | SD_SCK | ○ | ○ | ○ |
| 0% | Card1_2 | SD_CS | ○ | ○ | ○ |
| 0% | C40_2 | Net-(U6-VPHY) | ○ | ○ | ○ |
| 0% | Card1_7 | SD_MISO | ○ | ○ | ○ |
| 0% | R40_1 | Net-(USB1-CC1) | ○ | ○ | ○ |
| 0% | SW2_1 | BUTTON | ○ | ○ | ○ |
| 0% | R15_2 | Net-(U6-DP) | ○ | ○ | ○ |
| 0% | R15_1 | PROG_D+ | ○ | ○ | ○ |
| 0% | LED2_2 | CDONE | ○ | ○ | ○ |
| 0% | LED2_1 | Net-(LED2-A) | ○ | ○ | ○ |
| 0% | C5_2 | Net-(U2-VCCPLL) | ○ | ○ | ○ |
| 0% | U4_1 | Net-(U4-CS) | ○ | ○ | ○ |
| 0% | U4_7 | FLASH_HOLD | ○ | ○ | ○ |
| 0% | C4_2 | Net-(U3-VBCOMP) | ○ | ○ | ○ |
| 0% | U4_3 | FLASH_WP | ○ | ○ | ○ |
| 0% | R25_2 | RED | ○ | ○ | ○ |
| 0% | R25_1 | Net-(U2-IOB_24a) | ○ | ○ | ○ |
| 0% | R31_2 | BLUE | ○ | ○ | ○ |
| 0% | R31_1 | Net-(U2-IOT_37a) | ○ | ○ | ○ |
| 0% | R44_2 | Net-(USB1-CC2) | ○ | ○ | ○ |
| 0% | J1_9 | IOT_49a | ○ | ○ | ○ |
| 0% | R45_2 | SD_MOSI | ○ | ○ | ○ |
| 0% | J1_4 | IOT_46b_G0 | ○ | ○ | ○ |
| 0% | J1_6 | IOT_45a_G1 | ○ | ○ | ○ |
| 0% | J1_1 | IOT_42b | ○ | ○ | ○ |
| 0% | R35_2 | Net-(U4-CS) | ○ | ○ | ○ |
| 0% | J1_3 | IOT_44b | ○ | ○ | ○ |
| 0% | C15_1 | Net-(U6-OSCO) | ○ | ○ | ○ |
| 0% | J1_5 | IOT_48b | ○ | ○ | ○ |
| 0% | R32_2 | Net-(LED1-A) | ○ | ○ | ○ |
| 0% | R32_1 | LED | ○ | ○ | ○ |
| 0% | J1_7 | IOT_50b | ○ | ○ | ○ |
| 0% | J1_2 | IOT_43a | ○ | ○ | ○ |
| 0% | C16_1 | Net-(U6-OSCI) | ○ | ○ | ○ |
| 0% | J1_8 | IOT_51a | ○ | ○ | ○ |
| 0% | C41_1 | Net-(U6-VPLL) | ○ | ○ | ○ |
| 0% | USB2_A5 | Net-(USB2-CC1) | ○ | ○ | ○ |
| 0% | R21_2 | CDONE | ○ | ○ | ○ |
| 0% | USB2_B8 | ○ | ○ | ○ | |
| 0% | USB2_A6 | PROG_D+ | ○ | ○ | ○ |
| 0% | USB2_A7 | PROG_D- | ○ | ○ | ○ |
| 0% | USB2_B6 | PROG_D+ | ○ | ○ | ○ |
| 0% | R3_1 | Net-(USB2-CC1) | ○ | ○ | ○ |
| 0% | R5_2 | Net-(U3-D-) | ○ | ○ | ○ |
| 0% | R5_1 | PER_D- | ○ | ○ | ○ |
| 0% | X2_1 | Net-(U6-OSCO) | ○ | ○ | ○ |
| 0% | X2_3 | Net-(U6-OSCI) | ○ | ○ | ○ |
| 0% | USB2_A8 | ○ | ○ | ○ | |
| 0% | USB2_B7 | PROG_D- | ○ | ○ | ○ |
| 0% | R27_2 | Net-(U2-IOT_36b) | ○ | ○ | ○ |
| 0% | R27_1 | GREEN | ○ | ○ | ○ |
| 0% | R17_2 | Net-(U6-RESET) | ○ | ○ | ○ |
| 0% | USB2_B5 | Net-(USB2-CC2) | ○ | ○ | ○ |
| 0% | R46_2 | SD_SCK | ○ | ○ | ○ |
| 0% | DSub1_3 | BLUE | ○ | ○ | ○ |
| 0% | DSub1_1 | RED | ○ | ○ | ○ |
| 0% | DSub1_9 | ○ | ○ | ○ | |
| 0% | DSub1_11 | ○ | ○ | ○ | |
| 0% | DSub1_2 | GREEN | ○ | ○ | ○ |
| 0% | DSub1_4 | ○ | ○ | ○ | |
| 0% | R18_2 | Net-(U6-BCBUS3) | ○ | ○ | ○ |
| 0% | R18_1 | Net-(LED3-K) | ○ | ○ | ○ |
| 0% | R48_2 | Net-(Card1-DAT1) | ○ | ○ | ○ |
| 0% | DSub1_13 | HSYNC | ○ | ○ | ○ |
| 0% | DSub1_15 | ○ | ○ | ○ | |
| 0% | L2_1 | Net-(U6-VPLL) | ○ | ○ | ○ |
| 0% | U2_23 | Net-(U2-IOT_37a) | ○ | ○ | ○ |
| 0% | DSub1_14 | VSYNC | ○ | ○ | ○ |
| 0% | U2_4 | USB_INT | ○ | ○ | ○ |
| 0% | U2_11 | FLASH_HOLD | ○ | ○ | ○ |
| 0% | DSub1_12 | ○ | ○ | ○ | |
| 0% | R39_2 | SD_CS | ○ | ○ | ○ |
| 0% | U2_19 | Net-(U2-IOB_29b) | ○ | ○ | ○ |
| 0% | U2_20 | Net-(U2-IOB_25b_G3) | ○ | ○ | ○ |
| 0% | U2_41 | RGB2 | ○ | ○ | ○ |
| 0% | U2_12 | FLASH_WP | ○ | ○ | ○ |
| 0% | SW3_1 | creset_b | ○ | ○ | ○ |
| 0% | U2_7 | CDONE | ○ | ○ | ○ |
| 0% | LED3_2 | Net-(LED3-K) | ○ | ○ | ○ |
| 0% | U2_9 | LED | ○ | ○ | ○ |
| 0% | R47_2 | SD_MISO | ○ | ○ | ○ |
| 0% | U2_6 | BUTTON | ○ | ○ | ○ |
| 0% | U2_8 | creset_b | ○ | ○ | ○ |
| 0% | U2_13 | Net-(U2-IOB_24a) | ○ | ○ | ○ |
| 0% | U2_3 | USB_RST | ○ | ○ | ○ |
| 0% | U2_2 | USB_CS | ○ | ○ | ○ |
| 0% | U2_10 | SD_CS | ○ | ○ | ○ |
| 0% | R16_1 | Net-(U6-REF) | ○ | ○ | ○ |
| 0% | USB1_A4B9 | Net-(USB1-VBUS) | ○ | ○ | ○ |
| 0% | U2_18 | Net-(U2-IOB_31b) | ○ | ○ | ○ |
| 0% | U2_21 | Net-(U2-IOB_23b) | ○ | ○ | ○ |
| 0% | USB1_A5 | Net-(USB1-CC1) | ○ | ○ | ○ |
| 0% | U2_48 | SD_MOSI | ○ | ○ | ○ |
| 0% | U2_46 | PROG_TX | ○ | ○ | ○ |
| 0% | U2_45 | SD_MISO | ○ | ○ | ○ |
| 0% | U2_47 | PROG_RX | ○ | ○ | ○ |
| 0% | U2_43 | IOT_49a | ○ | ○ | ○ |
| 0% | U2_44 | SD_SCK | ○ | ○ | ○ |
| 0% | U2_42 | IOT_51a | ○ | ○ | ○ |
| 0% | U2_39 | RGB0 | ○ | ○ | ○ |
| 0% | U2_32 | IOT_43a | ○ | ○ | ○ |
| 0% | USB1_B8 | ○ | ○ | ○ | |
| 0% | U2_29 | Net-(U2-VCCPLL) | ○ | ○ | ○ |
| 0% | U2_36 | IOT_48b | ○ | ○ | ○ |
| 0% | U2_26 | HSYNC | ○ | ○ | ○ |
| 0% | U2_34 | IOT_44b | ○ | ○ | ○ |
| 0% | U2_40 | RGB1 | ○ | ○ | ○ |
| 0% | U2_37 | IOT_45a_G1 | ○ | ○ | ○ |
| 0% | U2_28 | VSYNC | ○ | ○ | ○ |
| 0% | U2_35 | IOT_46b_G0 | ○ | ○ | ○ |
| 0% | U2_31 | IOT_42b | ○ | ○ | ○ |
| 0% | USB1_A6 | PER_D+ | ○ | ○ | ○ |
| 0% | U2_38 | IOT_50b | ○ | ○ | ○ |
| 0% | U2_27 | Net-(U2-IOT_38b) | ○ | ○ | ○ |
| 0% | U2_25 | Net-(U2-IOT_36b) | ○ | ○ | ○ |
| 0% | USB1_A7 | PER_D- | ○ | ○ | ○ |
| 0% | USB1_B6 | PER_D+ | ○ | ○ | ○ |
| 0% | USB1_A8 | ○ | ○ | ○ | |
| 0% | R42_1 | FLASH_HOLD | ○ | ○ | ○ |
| 0% | USB1_B7 | PER_D- | ○ | ○ | ○ |
| 0% | USB1_B5 | Net-(USB1-CC2) | ○ | ○ | ○ |
| 0% | U3_4 | ○ | ○ | ○ | |
| 0% | U3_14 | USB_CS | ○ | ○ | ○ |
| 0% | U3_15 | SD_MISO | ○ | ○ | ○ |
| 0% | U3_6 | ○ | ○ | ○ | |
| 0% | U3_29 | ○ | ○ | ○ | |
| 0% | USB1_B4A9 | Net-(USB1-VBUS) | ○ | ○ | ○ |
| 0% | U3_12 | USB_RST | ○ | ○ | ○ |
| 0% | R4_1 | Net-(USB2-CC2) | ○ | ○ | ○ |
| 0% | U3_21 | Net-(U3-D+) | ○ | ○ | ○ |
| 0% | U3_7 | ○ | ○ | ○ | |
| 0% | U3_28 | ○ | ○ | ○ | |
| 0% | U3_27 | ○ | ○ | ○ | |
| 0% | U3_9 | ○ | ○ | ○ | |
| 0% | R28_2 | Net-(U2-IOB_29b) | ○ | ○ | ○ |
| 0% | U3_32 | ○ | ○ | ○ | |
| 0% | U3_11 | ○ | ○ | ○ | |
| 0% | U3_30 | ○ | ○ | ○ | |
| 0% | U3_10 | ○ | ○ | ○ | |
| 0% | U3_1 | ○ | ○ | ○ | |
| 0% | R28_1 | GREEN | ○ | ○ | ○ |
| 0% | U3_5 | ○ | ○ | ○ | |
| 0% | U3_13 | SD_SCK | ○ | ○ | ○ |
| 0% | U3_8 | ○ | ○ | ○ | |
| 0% | U3_31 | ○ | ○ | ○ | |
| 0% | R20_2 | creset_b | ○ | ○ | ○ |
| 0% | U3_16 | SD_MOSI | ○ | ○ | ○ |
| 0% | U3_26 | ○ | ○ | ○ | |
| 0% | U3_25 | Net-(U3-X0) | ○ | ○ | ○ |
| 0% | U3_24 | Net-(U3-XI) | ○ | ○ | ○ |
| 0% | U3_22 | Net-(U3-VBCOMP) | ○ | ○ | ○ |
| 0% | U3_18 | USB_INT | ○ | ○ | ○ |
| 0% | U3_17 | ○ | ○ | ○ | |
| 0% | U3_20 | Net-(U3-D-) | ○ | ○ | ○ |
14.10.6 Scoring Matrix
PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.
| Method | P | C | O | L | A | S | Opens | Q |
|---|---|---|---|---|---|---|---|---|
| AOI | Full | Full | Full | — | Partial | Partial | Partial | Partial |
| AXI | — | — | — | — | Partial | Partial | Partial | Partial |
| JTAG/ | Full | Full | Full | Partial | — | Full | Full | — |
| BSCAN_Passives | Full | Full | Full | Full | — | Full | Full | — |
| I2C | Partial | Partial | — | Partial | — | Partial | Partial | — |
| SPI | Partial | Partial | — | Partial | — | Partial | Partial | — |
| UART | — | — | — | Partial | — | — | — | — |
| Passive_Meas | Full | Full | Full | Full | — | Full | Full | — |
| Powered_Off | Partial | — | — | — | — | Partial | Full | — |
15 Component Properties
Schematic symbol and library model quality analysis.
15.1 Library Model Grades
Grading schematic library model quality based on pin electrical type definitions:
| Grade Definitions | ||
|---|---|---|
| Grade | Rating | Description |
| A | Excellent | Has Power pins AND properly typed I/ |
| B | Good | >=70% typed OR (>=50% typed AND has Power) |
| C | Fair | Mix of typed and Passive pins (>=40% typed) |
| D | Poor | Mostly Passive with few typed pins (>=10% typed) |
| F | Fail | All pins Passive/ |
| IC Library Model Grades (sorted worst to best) | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| RefDes | Grd | Pins | Pwr | In | Out | IO | OC | OE | HiZ | Pas | Part Number | Creator |
| U2 | C | 49 | 0 | 49 | 0 | 0 | 0 | 0 | 0 | 0 | ICE40UP5K-SG48I | |
| U3 | C | 33 | 0 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | MAX3421EETJ+T | |
| U4 | C | 8 | 0 | 8 | 0 | 0 | 0 | 0 | 0 | 0 | W25Q128JVSIQTR | |
| U5 | B | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | AMS1117-3.3 | |
| U1 | A | 3 | 3 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | AMS1117-1.2 | |
| U6 | A | 64 | 20 | 6 | 4 | 34 | 0 | 0 | 0 | 0 | FT2232HL | |
15.1.1 Library Quality Summary
| Total ICs evaluated | 6 |
| Grade A (excellent) | 2 (33.3%) |
| Grade B (good) | 1 (16.7%) |
| Grade C (fair) | 3 (50.0%) |
| Grade D (poor) | 0 (0.0%) |
| Grade F (fail) | 0 (0.0%) |
| OVERALL LIBRARY QUALITY | B (3.43/4.00) |
15.2 Component Library Validation
The shared part-number check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.
Checking for generic/incomplete library models using statistical patterns.
| Library Model Issues (4 models) | ||||||
|---|---|---|---|---|---|---|
| Library Name | Industry Name | Part Number | RefDes | Pins | Distribution | Issues |
| AMS1117-3.3 | AMS1117-3.3 | - | U5 | 3 | Pwr:3 | No Industry Name property - BOM and procurement tools require this field |
| ICE40UP5K-SG48I | ICE40UP5K-SG48I | - | U2 | 49 | ?:49 | No Power pins - may use separate power symbol; Only 0 pin type used - no electrical differentiation; 100% of pins are Unknown type; Power-named pins not typed as Power - library pin types incomplete [VCCIO_2=Unknown, VCC=Unknown, VCCIO_0=Unknown, VCCPLL=Unknown, VCC=Unknown] |
| MAX3421EETJ+T | MAX3421EETJ+T | - | U3 | 33 | ?:33 | No Power pins - may use separate power symbol; Only 0 pin type used - no electrical differentiation; 100% of pins are Unknown type; Power-named pins not typed as Power - library pin types incomplete [VCC=Unknown, GND=Unknown, GND=Unknown] |
| W25Q128JVSIQTR | W25Q128JVSIQ | - | U4 | 8 | ?:8 | No Power pins - may use separate power symbol; Only 0 pin type used - no electrical differentiation; 100% of pins are Unknown type; Power-named pins not typed as Power - library pin types incomplete [GND=Unknown, VCC=Unknown] |
15.2.1 Validation Heuristics
All pins same type: Generic library with no electrical rules
High % passive pins on IC: Incomplete type information
No power pins: May indicate separate power symbol
Low type diversity: Very underspecified library model
Power-named pins not typed as Power: Library pin types incomplete
15.3 Shielded Connector Model Quality
| Shielded connectors with missing pin names | 0 |
All shielded connectors have proper pin names for EMC analysis.
15.4 Footprints and Other Models
| Components with model data | 15 |
| Component Model Assignments | ||||
|---|---|---|---|---|
| RefDes | Industry Name | Pins | Model Type | Model |
| Card1 | TF-008 | 11 | Footprint | easyeda2kicad:TF-SMD_TF-008 |
| DSub1 | VGA-002 | 17 | Footprint | easyeda2kicad:D-SUB-TH_VGA-002 |
| J1 | Conn_01x12 | 12 | Footprint | Connector_PinHeader_2.54mm:PinHeader_1x12_P2.54mm_Vertical |
| J2 | Conn_01x08 | 8 | Footprint | Connector_PinHeader_2.54mm:PinHeader_1x08_P2.54mm_Vertical |
| LED4 | S4-3528RGBTA-A | 4 | Footprint | easyeda2kicad:LED-SMD_4P-L3.2-W2.8-LS3.5-TL-1 |
| U1 | AMS1117-1.2 | 3 | Footprint | Package_TO_SOT_SMD:SOT-223-3_TabPin2 |
| U2 | ICE40UP5K-SG48I | 49 | Footprint | easyeda2kicad:QFN-48_L7.0-W7.0-P0.50-TL-EP5.4-1 |
| U3 | MAX3421EETJ+T | 33 | Footprint | easyeda2kicad:VQFN-32_L5.0-W5.0-P0.50-BL-EP3.2 |
| U4 | W25Q128JVSIQ | 8 | Footprint | easyeda2kicad:SOIC-8_L5.3-W5.3-P1.27-LS8.0-BL |
| U5 | AMS1117-3.3 | 3 | Footprint | Package_TO_SOT_SMD:SOT-223-3_TabPin2 |
| U6 | FT2232HL-REEL | 64 | Footprint | easyeda2kicad:LQFP-64_L10.0-W10.0-P0.50-LS12.0-TL |
| USB1 | TYPE-C 16PIN 2MD(073) | 14 | Footprint | easyeda2kicad:USB-C-SMD_TYPE-C-16PIN-2MD-073 |
| USB2 | TYPE-C 16PIN 2MD(073) | 14 | Footprint | easyeda2kicad:USB-C-SMD_TYPE-C-16PIN-2MD-073 |
| X1 | X322512MSB4SI | 4 | Footprint | easyeda2kicad:CRYSTAL-SMD_4P-L3.2-W2.5-BL |
| X2 | X322512MSB4SI | 4 | Footprint | easyeda2kicad:CRYSTAL-SMD_4P-L3.2-W2.5-BL |
15.5 IC Pin Electrical Properties
| Unique IC models | 6 |
| Total IC instances | 6 |
| IC Library Models | |||
|---|---|---|---|
| Industry Name | Library Name | RefDes | Notes |
| AMS1117-1.2 | AMS1117-1.2 | U1 | |
| AMS1117-3.3 | AMS1117-3.3 | U5 | |
| FT2232HL-REEL | FT2232HL | U6 | |
| ICE40UP5K-SG48I | ICE40UP5K-SG48I | U2 | |
| MAX3421EETJ+T | MAX3421EETJ+T | U3 | |
| W25Q128JVSIQ | W25Q128JVSIQTR | U4 | |
15.5.1 AMS1117-1.2 (AMS1117-1.2)
| Pin | Pin Name | Electrical | Notes |
|---|---|---|---|
| 1 | GND | Power Out | |
| 2 | VO | Power Out | |
| 3 | VI | Power In |
15.5.2 AMS1117-3.3 (AMS1117-3.3)
| Pin | Pin Name | Electrical | Notes |
|---|---|---|---|
| 1 | GND | Power In | |
| 2 | VO | Power Out | |
| 3 | VI | Power In |
15.5.3 FT2232HL (FT2232HL-REEL)
| Pin | Pin Name | Electrical | Notes |
|---|---|---|---|
| 1 | GND | Power In | |
| 2 | OSCI | Unknown | |
| 3 | OSCO | Output | |
| 4 | VPHY | Power In | |
| 5 | GND | Power In | |
| 6 | REF | Unknown | |
| 7 | DM | Unknown | |
| 8 | DP | Unknown | |
| 9 | VPLL | Power In | |
| 10 | AGND | Power In | |
| 11 | GND | Power In | |
| 12 | VCORE | Power In | |
| 13 | TEST | Unknown | |
| 14 | RESET | Unknown | |
| 15 | GND | Power In | |
| 16 | ADBUS0 | Bidirectional | |
| 17 | ADBUS1 | Bidirectional | |
| 18 | ADBUS2 | Bidirectional | |
| 19 | ADBUS3 | Bidirectional | |
| 20 | VCCIO | Power In | |
| 21 | ADBUS4 | Bidirectional | |
| 22 | ADBUS5 | Bidirectional | |
| 23 | ADBUS6 | Bidirectional | |
| 24 | ADBUS7 | Bidirectional | |
| 25 | GND | Power In | |
| 26 | ACBUS0 | Bidirectional | |
| 27 | ACBUS1 | Bidirectional | |
| 28 | ACBUS2 | Bidirectional | |
| 29 | ACBUS3 | Bidirectional | |
| 30 | ACBUS4 | Bidirectional | |
| 31 | VCCIO | Power In | |
| 32 | ACBUS5 | Bidirectional | |
| 33 | ACBUS6 | Bidirectional | |
| 34 | ACBUS7 | Bidirectional | |
| 35 | GND | Power In | |
| 36 | SUSPEND | Output | |
| 37 | VCORE | Power In | |
| 38 | BDBUS0 | Bidirectional | |
| 39 | BDBUS1 | Bidirectional | |
| 40 | BDBUS2 | Bidirectional | |
| 41 | BDBUS3 | Bidirectional | |
| 42 | VCCIO | Power In | |
| 43 | BDBUS4 | Bidirectional | |
| 44 | BDBUS5 | Bidirectional | |
| 45 | BDBUS6 | Bidirectional | |
| 46 | BDBUS7 | Bidirectional | |
| 47 | GND | Power In | |
| 48 | BCBUS0 | Bidirectional | |
| 49 | VREGOUT | Power In | |
| 50 | VREGIN | Power In | |
| 51 | GND | Power In | |
| 52 | BCBUS1 | Bidirectional | |
| 53 | BCBUS2 | Bidirectional | |
| 54 | BCBUS3 | Bidirectional | |
| 55 | BCBUS4 | Bidirectional | |
| 56 | VCCIO | Power In | |
| 57 | BCBUS5 | Bidirectional | |
| 58 | BCBUS6 | Bidirectional | |
| 59 | BCBUS7 | Bidirectional | |
| 60 | PWREN | Output | |
| 61 | EEDATA | Bidirectional | |
| 62 | EECLK | Output | |
| 63 | EECS | Bidirectional | |
| 64 | VCORE | Power In |
15.5.4 ICE40UP5K-SG48I (ICE40UP5K-SG48I)
| Pin | Pin Name | Electrical | Notes |
|---|---|---|---|
| 1 | VCCIO_2 | Unknown | |
| 2 | IOB_6a | Unknown | |
| 3 | IOB_9b | Unknown | |
| 4 | IOB_8a | Unknown | |
| 5 | VCC | Unknown | |
| 6 | IOB_13b | Unknown | |
| 7 | CDONE | Unknown | |
| 8 | creset_b | Unknown | |
| 9 | IOB_16a | Unknown | |
| 10 | IOB_18a | Unknown | |
| 11 | IOB_20a | Unknown | |
| 12 | IOB_22a | Unknown | |
| 13 | IOB_24a | Unknown | |
| 14 | IOB_32a_SPI_SO | Unknown | |
| 15 | IOB_34a_SPI_SCK | Unknown | |
| 16 | IOB_35b_SPI_SS | Unknown | |
| 17 | IOB_33b_SPI_SI | Unknown | |
| 18 | IOB_31b | Unknown | |
| 19 | IOB_29b | Unknown | |
| 20 | IOB_25b_G3 | Unknown | |
| 21 | IOB_23b | Unknown | |
| 22 | SPI_Vccio1 | Unknown | |
| 23 | IOT_37a | Unknown | |
| 24 | VPP_2V5 | Unknown | |
| 25 | IOT_36b | Unknown | |
| 26 | IOT_39a | Unknown | |
| 27 | IOT_38b | Unknown | |
| 28 | IOT_41a | Unknown | |
| 29 | VCCPLL | Unknown | |
| 30 | VCC | Unknown | |
| 31 | IOT_42b | Unknown | |
| 32 | IOT_43a | Unknown | |
| 33 | VCCIO_0 | Unknown | |
| 34 | IOT_44b | Unknown | |
| 35 | IOT_46b_G0 | Unknown | |
| 36 | IOT_48b | Unknown | |
| 37 | IOT_45a_G1 | Unknown | |
| 38 | IOT_50b | Unknown | |
| 39 | RGB0 | Unknown | |
| 40 | RGB1 | Unknown | |
| 41 | RGB2 | Unknown | |
| 42 | IOT_51a | Unknown | |
| 43 | IOT_49a | Unknown | |
| 44 | IOB_3b_G6 | Unknown | |
| 45 | IOB_5b | Unknown | |
| 46 | IOB_0a | Unknown | |
| 47 | IOB_2a | Unknown | |
| 48 | IOB_4a | Unknown | |
| 49 | EP | Unknown |
15.5.5 MAX3421EETJ+T (MAX3421EETJ+T)
| Pin | Pin Name | Electrical | Notes |
|---|---|---|---|
| 1 | GPIN7 | Unknown | |
| 2 | VL | Unknown | |
| 3 | GND | Unknown | |
| 4 | GPOUT0 | Unknown | |
| 5 | GPOUT1 | Unknown | |
| 6 | GPOUT2 | Unknown | |
| 7 | GPOUT3 | Unknown | |
| 8 | GPOUT4 | Unknown | |
| 9 | GPOUT5 | Unknown | |
| 10 | GPOUT6 | Unknown | |
| 11 | GPOUT7 | Unknown | |
| 12 | RES | Unknown | |
| 13 | SCLK | Unknown | |
| 14 | SS | Unknown | |
| 15 | MISO | Unknown | |
| 16 | MOSI | Unknown | |
| 17 | GPX | Unknown | |
| 18 | INT | Unknown | |
| 19 | GND | Unknown | |
| 20 | D- | Unknown | |
| 21 | D+ | Unknown | |
| 22 | VBCOMP | Unknown | |
| 23 | VCC | Unknown | |
| 24 | XI | Unknown | |
| 25 | X0 | Unknown | |
| 26 | GPIN0 | Unknown | |
| 27 | GPIN1 | Unknown | |
| 28 | GPIN2 | Unknown | |
| 29 | GPIN3 | Unknown | |
| 30 | GPIN4 | Unknown | |
| 31 | GPIN5 | Unknown | |
| 32 | GPIN6 | Unknown | |
| 33 | EP | Unknown |
15.5.6 W25Q128JVSIQTR (W25Q128JVSIQ)
| Pin | Pin Name | Electrical | Notes |
|---|---|---|---|
| 1 | CS | Unknown | |
| 2 | DO | Unknown | |
| 3 | IO2 | Unknown | |
| 4 | GND | Unknown | |
| 5 | DI | Unknown | |
| 6 | CLK | Unknown | |
| 7 | IO3 | Unknown | |
| 8 | VCC | Unknown |