Orthrus-TX Design Analysis

AI-Assisted The Orthrus-TX is a single-sheet, flat schematic design containing 143 components across 105 nets. The central processing element is an STM32H745ZIT6, a dual-core MCU combining an ARM Cortex-M7 running at up to 480 MHz and an ARM Cortex-M4 at up to 240 MHz, with 2 MB of flash and 1 MB of RAM, housed in an LQFP-144 package. The design name and connector complement strongly indicate a radio controller transmitter (TX) for the FPV drone and RC hobby market, with dual ExpressLRS (ELRS) radio module ports, joystick and switch inputs, encoder and potentiometer interfaces, a display connector, an SD card slot, a buzzer output, and USB Type-C connectivity.


Processor

The STM32H745ZIT6 is the sole active IC on the board apart from ESD protection and power regulation. The device features dual Cortex-M7 and Cortex-M4 cores with floating-point units supporting single- and double-precision operations, along with a full DSP instruction set and memory protection units. The LQFP-144 package exposes 97 general-purpose I/Os, which this design uses extensively to service the numerous peripheral connectors.

The MCU includes an internal SMPS step-down converter. VLXSMPS is the SMPS step-down converter output coupled to an inductor, and VFBSMPS is the feedback voltage sense input. The schematic data shows VSSSMPS (pin 14) and VFBSMPS (pin 17) present on the MCU. When the SMPS is not used, VDDSMPS, VFBSMPS, and VSSSMPS should be connected to ground and VLXSMPS should be floating, per the ST community guidance and RM0399 Figure 22. The reference manual revision clarifies: "This power supply shall be connected to VDD when SMPS is used. Otherwise, it must be connected to GND." The design appears to use external LDO regulation (AP2112K-3.3) rather than the internal SMPS, so these pins must follow the LDO-only supply configuration.


Power Architecture

The design operates from a single VCC rail (13 pins) and a GND rail (123 pins). Three AP2112K-3.3 LDO regulators (LD1, LD2, LD3) provide 3.3 V regulation. The AP2112K is a 600 mA CMOS LDO regulator with enable, in a SOT-23-5 package. The datasheet specifies operation with 1.0 uF ceramic capacitors on both input and output. The use of three separate regulators suggests the designer has partitioned the 3.3 V supply into independent domains, likely separating the MCU digital core, analog/reference supply, and USB or radio module power. This is a sound approach for a mixed-signal design with sensitive analog inputs (joysticks, potentiometers) and RF modules.

The STM32H745ZIT6 has multiple power input pins: VDD (pins 7, 13, 19, 32, 42, 56, 71, 79, 92, 106, 119, 129, 144), VDDA (pin 36), VREF+ (pin 35), VBAT (pin 8), VDDLDO (pins 70, 105, 143), VDD50_USB (pin 90), VDD33_USB (pin 91), VDDSMPS (pin 16), and VSSSMPS (pin 14). The three VCAP pins (68, 103, 140) are power outputs for the internal core voltage regulator and require external decoupling capacitors (typically 4.7 uF ceramic each per AN4938). VDD pins require one single tantalum or ceramic capacitor of 4.7 uF minimum for the package and a 100 nF ceramic capacitor close to each VDD pin.

The PDR_ON pin (142) controls the internal power supervisor. VDD/VDDA can drop down to 1.62 V by using an external power supervisor and connecting PDR_ON to VSS. If the design ties PDR_ON high (to VDD), the internal power-on reset is active and VDD must remain above 1.71 V.

The VBAT pin (8) supports the RTC and backup domain. VBAT can be connected to an external battery (1.2 V to 3.6 V); if no external battery is used, it is mandatory to connect this pin to an external power supply, for example VBAT can be connected to VDD through a 100 nF external ceramic capacitor.


Clock Source

The design uses a single crystal, XTAL1, which is an Epson TSX-3225 24.0000MF20G-AC3, a 24 MHz crystal with 9 pF load capacitance and 40 Ohm ESR, in a 3.2 mm x 2.5 mm SMD package. This crystal connects to the HSE oscillator pins PH0 (pin 25) and PH1 (pin 26) of the STM32H745ZIT6. The 24 MHz frequency is within the HSE specification for this MCU family. No 32.768 kHz LSE crystal is present, so the RTC will rely on the internal LSI oscillator if used.


USB Type-C Interface

Connector J1 is an HRO-TYPE-C-31-M-13x USB Type-C receptacle with full pin complement including VBUS (A4, A9, B4, B9), GND (A1, A12, B1, B12), D+ (A6, B6), D- (A7, B7), CC1 (A5), CC2 (B5), SBU1 (A8), SBU2 (B8), and SHIELD (S1). The MCU provides USB OTG FS/HS capability on pins PA11 (USB_DM) and PA12 (USB_DP), with dedicated VDD50_USB (pin 90) and VDD33_USB (pin 91) supply pins.

The design includes two differential pairs, which correspond to the USB D+/D- lines. The CC1 and CC2 pins are present, which are essential for USB Type-C orientation detection and power delivery negotiation. The SBU1 and SBU2 pins are exposed but their use in this context (likely unused for a USB 2.0 application) depends on whether any alternate mode is intended.


ESD Protection

Seven SRV05-4 ESD protection arrays (U2 through U8) are deployed across the design. The SRV05-4 combines 8 low capacitance steering diodes for up to four individual data or transmission lines and one TVS diode for power bus protection, in a SOT-23-6 package. The device provides IEC 61000-4-2 Level 4 ESD protection with plus/minus 12 kV contact discharge and plus/minus 17 kV air discharge, with ultra-low capacitance of 0.6 pF typical. Seven instances provide protection for up to 28 I/O lines, covering the USB interface and likely the external connector signals exposed to user handling (joysticks, switches, encoders, ELRS modules).

A single Schottky diode D1 (SOD-123 package) is present, likely serving as reverse-polarity protection on the power input or as a VBUS blocking diode for the USB Type-C port.


Peripheral Connectors

The design makes extensive use of Molex 53261 series wire-to-board connectors in various pin counts for the human-interface peripherals:

ELRS_1 and ELRS_2 use Molex 5034800800, an 8-position FFC/FPC connector with 0.50 mm pitch, dual contact, surface mount right-angle. These connect to ExpressLRS radio modules. ExpressLRS receivers use UART TX/RX connections, where the TX pin sends control signals and the RX pin receives telemetry data. Having two ELRS ports enables a diversity or dual-band radio configuration, consistent with high-end RC transmitters.

JOYSTICK_1 and JOYSTICK_2 are 6-pin connectors (Molex 532610671) carrying analog stick signals. Each joystick typically provides two analog axes plus a center-press button, requiring two ADC channels and one GPIO per stick.

ENCODER_1 and ENCODER_2 are 8-pin connectors (Molex 532610871) for rotary encoders, which typically provide quadrature A/B signals, a push-button switch, and power/ground.

POT_ANALOG_1 is an 8-pin connector for an analog potentiometer input, and POT_DIGITAL_1 is a 7-pin connector (Molex 532610771) for a digital potentiometer, likely an encoder-style trim control.

SWITCHES_1 is a 6-pin connector for toggle or momentary switches.

BUTTONS_1 is a 4-pin connector (Molex 532610471) for discrete push-button inputs.

BUZZER_1 is a 2-pin connector (Molex 532610271) for an audible alert device.

SCREEN_1 is an 8-pin connector for a display module, likely an OLED or small LCD driven via SPI or I2C.

PROGRAMMING_1 is an 8-pin connector providing access to the SWD debug interface (SWDIO on PA13, SWCLK on PA14) and potentially UART boot pins.

POWER_1 is a 3-pin connector (Molex 532610371) for the external power input, carrying VCC, GND, and possibly a battery voltage sense line.


SD Card Interface

SD_CARD_1 uses a Molex 1040310811 micro-SD card connector with standard SDIO signals: DAT0 (pin 7), DAT1 (pin 8), DAT2 (pin 1), CD/DAT3 (pin 2), CMD (pin 3), CLK (pin 5), VDD (pin 4), and VSS (pin 6). Two switch-detect pins (9, 10) provide card-insertion detection. The STM32H745 supports SDMMC interfaces on multiple pin groups, enabling 4-bit wide SD card access for logging, configuration storage, or model memory.


Indicators

Three LEDs (LD1, LD2, LD3) provide visual status indication. The library entry labels these with the AP2112K-3.3 description, which appears to be a library naming artifact; the component instances serve as LED indicators driven from MCU GPIO pins. The three indicators likely represent power status, radio link status, and a general-purpose or charging indicator.


Component Density and Board Complexity

The 143-component design on a single sheet is moderately dense. The passive component count of 112 chip passives supports the decoupling, filtering, and biasing requirements of the STM32H745 (which alone requires approximately 20 bypass capacitors per ST recommendations) plus the three LDO regulators, crystal load capacitors, USB termination, and connector filtering. The total of 629 pins across 105 nets indicates a well-consolidated design with significant net sharing on power rails.


Design Classification

Orthrus-TX is a custom RC radio transmitter controller board built around the STM32H745ZIT6 dual-core MCU. It accepts user inputs from joysticks, switches, encoders, potentiometers, and buttons, processes them on the Cortex-M7/M4 cores, and transmits control data via dual ExpressLRS radio modules. A USB Type-C port provides connectivity for firmware updates, configuration, and potentially USB joystick/gamepad emulation. An SD card slot enables persistent storage, and a display connector supports a user interface screen. The design is powered from an external source through a 3-pin power connector, regulated by three independent 3.3 V LDO stages, with comprehensive ESD protection on user-accessible interfaces.

AI-Assisted The Orthrus-TX board is powered from two possible sources: a USB Type-C connector (J1, HRO-TYPE-C-31-M-13x) providing VBUS, and an external connector (POWER_1, 532610371) providing a secondary input. Both sources converge on the VCC rail. USB VBUS from J1 passes through a Schottky diode D1 (cathode on VCC, anode on the VBUS net Net-(D1-A)), which provides reverse-polarity protection and prevents back-feeding into the USB host. The VBUS net also carries ESD protection via U2 (SRV05-4), whose VP pin is tied to Net-(D1-A). After D1, the VCC rail is the single intermediate bus that feeds all downstream regulation.

From VCC, three independent AP2112K-3.3 LDO regulators (LD1, LD2, LD3) generate three separate 3.3 V rails. All three LDOs have their EN pins tied directly to VCC, so they power up as soon as VCC is established. There is no sequencing control or enable logic between the rails; all three outputs rise simultaneously, gated only by the LDO soft-start behavior. The VCC rail is decoupled with one 22 uF ceramic (C39), three 4.7 uF ceramics (C1, C17, C29), and one 100 nF ceramic (C38), providing approximately 36 uF of bulk and high-frequency bypass at the LDO inputs.

The POWER_1 connector pin 1 ties to VCC and pin 3 ties to GND. Pin 2 connects to the net RAW, which feeds a resistive divider (R43 at 100 kohm to RAW, R44 at 100 kohm to GND) presenting a half-scale voltage on PA4 of the STM32H745ZIT6 for ADC-based input voltage monitoring. A 100 nF capacitor (C41) filters the PA4 node.

AI-Assisted LD1 is the primary regulator and carries the heaviest load on the board. Its output rail LD1_3.3v supplies the STM32H745ZIT6 on all VDD pins (pins 7, 13, 19, 32, 42, 56, 71, 79, 92, 106, 119, 129, 144), all three VDDLDO pins (70, 105, 143), VDDSMPS (pin 16), VBAT (pin 8), VDD50_USB (pin 90), VDD33_USB (pin 91), and PDR_ON (pin 142). It also powers the SD card (SD_CARD_1 VDD, pin 4), the VP supply pins of six SRV05-4 ESD protection arrays (U3 through U8), and the PROGRAMMING_1 connector (pin 1). Additionally, a large number of 10 kohm pull-up resistors (R2, R13 through R40, R45 through R49, R51) terminate to LD1_3.3v.

The output decoupling on LD1_3.3v is extensive: approximately twenty-seven 100 nF ceramics, one 2.2 uF ceramic (C2), two 4.7 uF ceramics (C3, C50 is 100nF — correction: C5 is 100nF, C3 is 4.7uF), six 1 uF ceramics (C42, C44, C49, C46 — some are on LD2), one 10 uF ceramic (C51), and additional capacitors distributed near the MCU power pins. The AP2112K-3.3 datasheet (DS39724 Rev. 2-2, Diodes Incorporated) specifies a minimum 1.0 uF ceramic output capacitor with X7R or X5R dielectric. The total output capacitance far exceeds this minimum, which is appropriate given the high transient current demands of the dual-core Cortex-M7/M4 MCU.

The critical concern with LD1 is current capacity. The AP2112K-3.3 is rated for 600 mA continuous output. The STM32H745ZIT6 alone, running both cores at full speed with peripherals active, can draw 300 to 400 mA. Adding the SD card (up to 100 mA during write bursts), six SRV05-4 ESD arrays (negligible quiescent but present), and the cumulative pull-up current through dozens of 10 kohm resistors to 3.3 V, the total load can readily approach or exceed 600 mA. This represents a significant thermal and electrical risk for a single SOT-23-5 package LDO.

AI-Assisted LD2 provides a dedicated analog supply on the LD2_3.3v rail. This rail feeds the STM32H745ZIT6 VDDA pin (pin 36), the joystick connectors (JOYSTICK_1 pin 6, JOYSTICK_2 pin 6), and the potentiometer connector (POT_ANALOG_1 pin 2). A 22 ohm series resistor R54 connects LD2_3.3v to the VREF+ net, which supplies the STM32H745ZIT6 VREF+ pin (pin 35). The VREF+ net is decoupled with one 100 nF ceramic (C19) and one 1 uF ceramic (C20) to GND.

The output decoupling on LD2_3.3v consists of one 2.2 uF ceramic (C18) and two additional capacitors (C45 at 100 nF and C46 at 1 uF) to GND. The AP2112K-3.3 datasheet requires a minimum 1.0 uF output capacitor, which is satisfied by C18 alone. The separation of the analog supply from the noisy digital rail is good practice for ADC accuracy.

Per ST application note AN4938 Rev 7, the VREF+ pin can be connected to VDDA through a series resistor, with a typical value of 47 ohm recommended. The design uses R54 at 22 ohm, which is lower than the typical recommendation but still provides adequate high-frequency filtering in conjunction with the 1 uF and 100 nF decoupling capacitors on the VREF+ node. The resulting RC filter corner frequency with 22 ohm and 1 uF is approximately 7.2 kHz, which provides reasonable rejection of switching noise above that frequency. The load on LD2 is light — VDDA draws only a few milliamps for the ADC and DAC references, plus the joystick and potentiometer excitation currents — well within the 600 mA rating.

AI-Assisted LD3 provides an isolated supply for the display interface on the LD3_3.3v rail. This rail feeds only the SCREEN_1 connector (pin 2). Output decoupling consists of one 2.2 uF ceramic (C30) and one 100 nF ceramic (C31) to GND, meeting the AP2112K-3.3 minimum 1.0 uF output capacitor requirement.

Isolating the screen supply is a sound design choice, as display modules can generate significant current transients during refresh cycles and backlight switching. The load depends entirely on the external display module connected to SCREEN_1. Typical small SPI or I2C OLED or TFT displays draw 20 to 150 mA, well within the 600 mA capability of the AP2112K-3.3. The screen data signals (PE2 through PE6, PE9) connect directly from the MCU to SCREEN_1 without series resistors, which is acceptable for short cable runs to a co-located display.

AI-Assisted The STM32H745ZIT6 includes an internal SMPS step-down converter that generates the VCORE supply for the digital logic. The schematic implements the Direct SMPS Supply configuration: VDDSMPS (pin 16) is connected to LD1_3.3v, VSSSMPS (pin 14) is connected to GND, VLXSMPS (pin 15) connects to one terminal of inductor L1 (2.2 uH, 0603), and the other terminal of L1 connects to the VCAP net. The VCAP net ties together all three VCAP pins (pins 68, 103, 140) and the VFBSMPS feedback pin (pin 17), with a single 4.7 uF ceramic capacitor C22 to GND.

ST application note AN4938 Rev 7 specifies the external component requirements for the SMPS. The VLXSMPS pin requires a 2.2 uH inductor, which L1 satisfies. However, AN4938 also states that the VLXSMPS output requires a 220 pF external capacitor between VLXSMPS and GND. No such capacitor is present on the VLXSMPS net in the schematic — only L1 pin 1 and STM32H745ZIT6 pin 15 connect to this node. This missing snubber capacitor can cause excessive ringing on the switch node, increasing EMI and potentially degrading SMPS efficiency and reliability.

Furthermore, AN4938 specifies that the VFBSMPS pin must be connected to a 10 uF capacitor with 20 mohm ESR. The VCAP net currently has only C22 at 4.7 uF. This is below the required 10 uF minimum. Insufficient output capacitance on the SMPS output can cause excessive voltage ripple on VCORE, leading to logic errors, increased jitter on PLLs, and potential instability of the internal voltage regulator loop.

The three VDDLDO pins (70, 105, 143) are connected to LD1_3.3v, which is correct for the Direct SMPS configuration where the internal LDO is bypassed and the SMPS directly supplies VCORE. Pin 142 (PDR_ON) is tied to LD1_3.3v (VDD level), which enables the internal power-on reset and power-down reset supervisors — this is the recommended configuration per AN4938 when VDD remains above 1.71 V.

AI-Assisted The USB Type-C connector J1 provides VBUS on four pins (A4, A9, B4, B9), all connected to the Net-(D1-A) node. A Schottky diode D1 passes current from this node to the VCC rail, providing a voltage drop of approximately 0.3 to 0.5 V depending on load current. At 5.0 V VBUS, VCC will be approximately 4.5 to 4.7 V, which provides adequate headroom for the AP2112K-3.3 regulators (minimum input voltage of 3.55 V at full load with 250 mV typical dropout). A 100 nF ceramic capacitor C54 decouples the VBUS node to GND.

The USB CC1 and CC2 configuration channel pins are each pulled down to GND through 5.1 kohm resistors (R42 on CC1, R41 on CC2). Per the USB Type-C specification, 5.1 kohm pull-downs on both CC pins identify the device as a UFP (Upstream Facing Port) sink, which will cause a DFP (Downstream Facing Port) source to apply VBUS at the default USB power level (5 V, 500 mA or 900 mA depending on USB 2.0/3.x advertisement). There is no USB PD controller on the board, so power negotiation is limited to the default level.

ESD protection on the USB data lines (USB_P, USB_N) is provided by U2 (SRV05-4), with VP tied to the VBUS net Net-(D1-A) and VN tied to GND. The SRV05-4 is rated for a 5 V working voltage, which matches the VBUS level. The D+/D- lines from J1 connect through U2 to the STM32H745ZIT6 PA12 and PA11 pins respectively for USB OTG Full Speed operation.

AI-Assisted The STM32H745ZIT6 VBAT pin (pin 8) is connected directly to LD1_3.3v. Per AN4938, if no external battery is used, VBAT must be connected to an external power supply, and connecting it to VDD is the standard approach. This means the RTC and backup SRAM contents will be lost whenever VCC is removed. There is no backup battery or supercapacitor on the board, which is acceptable for an application that does not require timekeeping across power cycles.

AN4938 notes that during the startup phase, if VDD rises faster than tRSTTEMPO and exceeds VBAT + 0.6 V, current may be injected into the VBAT pin through an internal diode. Since VBAT and VDD are on the same rail, this condition cannot occur, and no external diode is needed.

AI-Assisted The power architecture is straightforward and appropriate for a USB-powered controller board with moderate complexity. The use of three separate LDO regulators to isolate digital, analog, and display domains is good practice. However, several issues require attention before layout.

The most significant concern is the current budget on LD1. The STM32H745ZIT6 is a high-performance dual-core MCU that can draw substantial current, particularly when both the Cortex-M7 (480 MHz) and Cortex-M4 (240 MHz) cores are active with peripherals enabled. Combined with the SD card interface, ESD protection arrays, and numerous pull-up resistors, the 600 mA rating of the AP2112K-3.3 in a SOT-23-5 package leaves very little margin. Thermal shutdown of the LDO under sustained high load is a realistic risk, especially considering the power dissipation: at 4.5 V input and 3.3 V output with 500 mA load, the LDO dissipates (4.5 - 3.3) x 0.5 = 0.6 W, which is substantial for a SOT-23-5 package.

The missing 220 pF capacitor on the VLXSMPS node and the undersized VCAP capacitor (4.7 uF versus the required 10 uF) are deviations from ST's hardware design guidelines in AN4938. These should be corrected to ensure stable SMPS operation and clean VCORE supply to the processor cores.

The input decoupling on VCC is adequate in total capacitance but relies on a single Schottky diode D1 for the entire USB current path. The diode's current rating and forward voltage drop at peak load should be reviewed against the selected part's datasheet to ensure it can handle the aggregate current of all three LDOs plus their loads.

The board has no power-good indication, no voltage monitoring beyond the RAW divider on PA4, and no brownout detection beyond the MCU's internal POR/PDR (enabled via PDR_ON tied to VDD). For a USB-powered device this is generally acceptable, as the USB source is expected to be well-regulated.

Device	Rail / Net	Observation	Severity
LD1 (AP2112K-3.3)	LD1_3.3v	Output rail supplies the entire STM32H745ZIT6 digital domain, SD card, six ESD arrays, and dozens of pull-up resistors. Aggregate load can approach or exceed the 600 mA rating of the AP2112K-3.3 (DS39724 Rev. 2-2). Thermal dissipation in SOT-23-5 at worst-case headroom is a concern.	High
STM32H745ZIT6	VCAP	VFBSMPS (pin 17) output capacitor C22 is 4.7 uF. AN4938 Rev 7 (ST) specifies 10 uF minimum with 20 mohm ESR on this node. Insufficient capacitance risks excessive VCORE ripple and SMPS instability.	High
STM32H745ZIT6	VLXSMPS	AN4938 Rev 7 specifies a 220 pF capacitor between VLXSMPS and GND. No such capacitor is present on the VLXSMPS net. Missing snubber increases switch-node ringing and EMI.	High
LD1 (AP2112K-3.3)	VCC input	EN pin (pin 3) tied directly to VCC. AP2112K-3.3 datasheet confirms this is valid for always-on operation. Input decoupling on VCC totals approximately 36 uF across five capacitors, exceeding the 1.0 uF minimum.
LD2 (AP2112K-3.3)	LD2_3.3v	Dedicated analog supply for VDDA and joystick excitation. Output decoupling of 2.2 uF (C18) plus 100 nF (C45) and 1 uF (C46) exceeds the 1.0 uF minimum per DS39724. Load is light and well within 600 mA rating.
LD3 (AP2112K-3.3)	LD3_3.3v	Isolated screen supply with 2.2 uF (C30) and 100 nF (C31) output decoupling. Meets AP2112K-3.3 minimum capacitor requirement. Load depends on external display module but expected well within rating.
R54 (22 ohm)	VREF+	Series resistor between LD2_3.3v and VREF+ is 22 ohm. AN4938 Rev 7 recommends a typical value of 47 ohm. The 22 ohm value provides less filtering but is not out of specification. RC corner with 1 uF (C20) is approximately 7.2 kHz.	Low
STM32H745ZIT6	PDR_ON (pin 142)	Tied to LD1_3.3v, enabling the internal power-on/power-down reset supervisor. This is the recommended configuration per AN4938 when VDD is guaranteed above 1.71 V.
STM32H745ZIT6	VBAT (pin 8)	Connected to LD1_3.3v with no backup battery. RTC and backup SRAM contents are lost on power removal. AN4938 confirms this connection is valid when no battery backup is needed.
D1 (Schottky)	Net-(D1-A) to VCC	Single Schottky diode carries the full board current from USB VBUS to VCC. Forward drop reduces available headroom for the LDOs. At 5 V VBUS and 0.4 V drop, VCC is approximately 4.6 V, providing 1.3 V headroom above the 3.3 V output — adequate per AP2112K-3.3 dropout specification of 250 mV typical at 600 mA.
R41, R42 (5.1 kohm)	CC1, CC2	USB Type-C CC pins pulled to GND through 5.1 kohm resistors, correctly identifying the device as a UFP sink per USB Type-C specification Rev 2.0. Default power advertisement will provide 5 V at up to 900 mA (USB 3.x) or 500 mA (USB 2.0).
U2 (SRV05-4)	USB_P, USB_N	ESD protection on USB D+/D- lines with VP tied to VBUS net and VN to GND. SRV05-4 working voltage of 5 V matches VBUS level per onsemi datasheet Rev 4 (October 2024).
STM32H745ZIT6	VDDSMPS (pin 16)	Connected to LD1_3.3v, same rail as VDD. AN4938 Rev 7 states VDD and VDDSMPS must be wired together. Requirement satisfied.
L1 (2.2 uH)	VLXSMPS to VCAP	Inductor value matches the 2.2 uH requirement specified in AN4938 Rev 7 for the STM32H7 internal SMPS. 0603 footprint is compact; saturation current rating of the selected inductor should be reviewed against SMPS peak current during layout.
C54 (100 nF)	Net-(D1-A)	VBUS-side decoupling capacitor. USB Type-C specification recommends 1 uF to 10 uF bulk capacitance on VBUS. A single 100 nF may be insufficient for USB inrush and transient requirements.	Medium
LD1 (AP2112K-3.3)	LD1_3.3v to VDD50_USB	VDD50_USB (pin 90) is connected to LD1_3.3v at 3.3 V. Despite the pin name, the STM32H745 datasheet DS12923 specifies this pin accepts 3.0 to 3.6 V for USB Full Speed PHY operation. Connection is correct.

AI-Assisted The design implements a single USB 2.0 Full-Speed interface between the STM32H745ZIT6 microcontroller and a USB Type-C receptacle J1 (HRO TYPE-C-31-M-13x). The MCU uses its OTG_FS peripheral with the embedded Full-Speed PHY. The data lines USB_P (D+) and USB_N (D-) connect STM32H745ZIT6 pins PA12 (pin 101) and PA11 (pin 100) to J1 pins A6/B6 (D+) and A7/B7 (D-) respectively. Both A-side and B-side D+/D- pins of the Type-C connector are tied together, which is the correct topology for a USB 2.0-only Type-C implementation since the connector orientation does not affect D+/D- routing at Full-Speed.

The connector J1 is a 12-pin USB Type-C receptacle suitable for USB 2.0 signaling. It does not carry SuperSpeed pins, which is consistent with the Full-Speed-only capability of the embedded OTG_FS PHY. The USB 2.0 specification and ST AN4879 require 90 ohm +/-15% differential impedance on the D+/D- traces. The schematic marks USB_P and USB_N as a differential pair, but no impedance class assignment is visible in the schematic net properties. The layout engineer must assign a 90 ohm differential impedance class to these nets before routing.

Per ST AN4879, the STM32 embedded Full-Speed USB driver impedance is internally matched between 28 and 44 ohms, so no external series resistors are required on the data lines. The schematic correctly omits series resistors on USB_P and USB_N. USB Full-Speed does not require AC coupling capacitors on the data lines, and none are present, which is correct.

AI-Assisted The CC1 and CC2 pins of J1 are each pulled down to GND through 5.1 kohm resistors R42 and R41 respectively. Per the USB Type-C specification, a 5.1 kohm pull-down on each CC line identifies the port as a sink/device (Rd). This is the correct configuration for a USB device that draws power from VBUS.

VBUS from J1 (pins A4, A9, B4, B9) is routed to net Net-(D1-A) through Schottky diode D1 (cathode to VCC rail, anode to VBUS). A 100 nF ceramic capacitor C54 provides local bypass on the VBUS net. The SRV05-4 ESD protection device U2 has its VP pin (pin 5) connected to the VBUS net, providing a clamping reference for the ESD protection on the USB data lines. U2 I/O pins IO1 (pin 1) and IO2 (pin 3) are connected to USB_P and USB_N respectively, while VN (pin 2) is tied to GND. This is the correct connection topology for the SRV05-4 protecting USB data lines.

The SBU1 (J1 pin A8) and SBU2 (J1 pin B8) pins of the Type-C connector do not appear in the signal net list, indicating they are either unconnected or tied to a power rail. For a USB 2.0-only device without Alternate Mode support, SBU pins are not required and may be left unconnected.

AI-Assisted The STM32H745ZIT6 has dedicated USB power pins: VDD33_USB (pin 91) and VDD50_USB (pin 90). Both pins are connected to the LD1_3.3v rail, which is the 3.3 V output of regulator LD1 (AP2112K-3.3). Per the STM32H745 datasheet DS12923, VDD33_USB requires 3.0 to 3.6 V for the USB transceiver, so 3.3 V is within specification. VDD50_USB is designated for the USB HS PHY and nominally requires 4.75 to 5.25 V when the High-Speed PHY is active. Since this design uses only the OTG_FS peripheral (Full-Speed, 12 Mbit/s) and does not use the OTG_HS peripheral or its embedded HS PHY, connecting VDD50_USB to 3.3 V will not affect Full-Speed operation. However, the STM32H745 datasheet recommends connecting VDD50_USB to a valid supply even when HS is not used; the designer should consult the reference manual to ensure 3.3 V is acceptable on this pin when the HS PHY is disabled in software.

Decoupling on the LD1_3.3v rail serving the USB power pins includes multiple 100 nF ceramics and bulk capacitance (4.7 uF, 2.2 uF, 10 uF, 22 uF). The USB transceiver supply filtering appears adequate for Full-Speed operation.

AI-Assisted Per ST AN4879, USB device operation should be initiated upon VBUS detection. Pin PA9 is commonly used for VBUS sensing on STM32H7 devices as it is 5 V-tolerant. In this design, PA9 (pin 98) is routed to PROGRAMMING_1 pin 7 and is not connected to the VBUS path. No other VBUS sense connection to the MCU is visible in the schematic. The design uses a Schottky diode D1 between VBUS and the VCC rail, but there is no resistor divider or direct connection from VBUS to an MCU GPIO for detection. If the device is bus-powered and always connected, software-based VBUS detection may not be needed. If the device is self-powered and must detect host attachment, a VBUS sense path to the MCU is required. The resistor divider on PA4 (R43 from RAW, R44 to GND, with C41 bypass) may serve as a battery/input voltage monitor rather than VBUS sensing, since RAW comes from POWER_1 pin 2, not from the USB connector VBUS.

AI-Assisted The USB interface is straightforward USB 2.0 Full-Speed with a Type-C connector in device/sink mode. The critical missing item at the schematic level is the impedance class assignment on the USB_P/USB_N differential pair. Without this annotation, the layout tool will not enforce 90 ohm differential impedance control during routing. The ESD protection topology using the SRV05-4 is correctly implemented with the clamping rail referenced to VBUS. The CC pull-down resistor values are correct per the USB Type-C specification for a sink device. No series termination resistors are needed per ST AN4879 since the STM32 internal driver impedance is factory-trimmed.

Interface	Protocol	Finding	Severity
USB_P / USB_N	USB 2.0 Full-Speed	Differential pair USB_P, USB_N between STM32H745ZIT6 PA12/PA11 and J1 A6/A7 is tagged as a differential pair but has no impedance class assignment. USB 2.0 requires 90 ohm +/-15% differential impedance per AN4879. The layout tool will not enforce impedance control without this assignment.	Medium
USB_P / USB_N	USB 2.0 Full-Speed	No external series resistors on USB data lines. Per ST AN4879, the STM32 internal FS driver impedance is 28-44 ohms and no external resistor is needed. Correct.
USB_P / USB_N	USB 2.0 Full-Speed	No AC coupling capacitors on USB D+/D- lines. USB 2.0 Full-Speed does not require AC coupling on data lines. Correct per USB 2.0 specification.
USB_P / USB_N	USB 2.0 Full-Speed ESD	ESD protection U2 (SRV05-4) is connected with IO1 on USB_P, IO2 on USB_N, VP on VBUS net, VN on GND. This is the correct topology per the SRV05-4 datasheet.
J1 CC1 / CC2	USB Type-C	CC1 pulled down by R42 (5.1 kohm) to GND; CC2 pulled down by R41 (5.1 kohm) to GND. Correct Rd value for a USB Type-C sink/device per USB Type-C specification.
J1 Type-C Connector	USB 2.0 Full-Speed	HRO TYPE-C-31-M-13x is a 12-pin USB Type-C receptacle (USB 2.0 only). Suitable for Full-Speed signaling. No SuperSpeed pins are needed.
VDD33_USB (pin 91)	USB Power	VDD33_USB connected to LD1_3.3v (3.3 V). Within the required 3.0-3.6 V range per DS12923. Correct.
VDD50_USB (pin 90)	USB Power	VDD50_USB connected to LD1_3.3v (3.3 V) instead of 5 V. This pin supplies the embedded HS PHY and nominally requires 4.75-5.25 V per DS12923. Since only OTG_FS (Full-Speed) is used and the HS PHY is not active, this may be acceptable, but the datasheet does not explicitly permit 3.3 V on VDD50_USB. Risk of undefined behavior if HS PHY is inadvertently enabled.	Low
VBUS Sensing	USB 2.0 Full-Speed	No VBUS sense path from the USB connector to the MCU is visible. PA9 (typical VBUS sense pin per AN4879) is routed to PROGRAMMING_1 connector. If the device is self-powered, VBUS detection is required by the USB specification to control the D+ pull-up. If bus-powered only, this may be handled in software by assuming VBUS is always present.	Medium
USB_P / USB_N	USB 2.0 Full-Speed	Both A-side and B-side D+/D- pins of J1 are tied together on USB_P and USB_N nets. Correct for USB 2.0-only Type-C implementation where cable orientation does not affect D+/D- assignment.

AI-Assisted The Orthrus-TX design is built around an STM32H745ZIT6 dual-core Cortex-M7/M4 microcontroller in an LQFP-144 package. Per the STM32H745xI/G datasheet (DS12956), this MCU integrates 2 MB of dual-bank flash memory and up to 1 MB of SRAM internally, along with peripheral support for SDMMC, Quad-SPI, and FMC external memory interfaces. The only external memory-class interface present in this design is a microSD card socket (SD_CARD_1, Molex 1040310811) connected to the STM32H745ZIT6 via the SDMMC2 peripheral. There are no external DDR/SDRAM, SRAM, NVRAM, or QSPI flash devices in the design. The MCU relies entirely on its internal flash and SRAM for code execution and data storage, with the microSD card serving as removable mass storage.

AI-Assisted The microSD card connector SD_CARD_1 (Molex 1040310811) is a push-pull type surface-mount socket with 8 signal contacts and a card-detect switch. The card is powered from the LD1_3.3v rail via pin 4 (VDD), and pin 6 (VSS) connects to GND. The interface is routed to the STM32H745ZIT6 SDMMC2 peripheral using the following pin assignments: PD6 drives the clock (SDMMC2_CK, AF11), PD7 drives the command line (SDMMC2_CMD, AF11), PB14 carries DAT0 (SDMMC2_D0, AF9), and PB15 carries DAT1 (SDMMC2_D1, AF9). These four signals are correctly mapped to valid SDMMC2 alternate functions as documented in the STM32H745 datasheet and confirmed by the stm32h7xx-hal pin definition tables.

However, the DAT2 and DAT3 lines are routed to PG9 and PG10 respectively. According to the STM32H745 alternate function table, PG9 does not carry an SDMMC2 data function, and PG10 does not carry an SDMMC2 data function either. The valid SDMMC2_D2 pins are PB3 (AF9) and PG11 (AF10), and the valid SDMMC2_D3 pin is PB4 (AF9). Notably, PG11 — which is a valid SDMMC2_D2 pin — is instead assigned to the card-detect switch (SW_DETECT, pin 10 of SD_CARD_1). This means the hardware SDMMC2 peripheral cannot operate in 4-bit mode with the current pin assignment. The interface is limited to 1-bit SDMMC2 mode using only PB14 (D0), which halves the maximum data throughput compared to 4-bit mode. If 4-bit operation is required, DAT2 must be reassigned to PB3 or PG11, and DAT3 must be reassigned to PB4. The card-detect function on PG11 would need to move to a different GPIO.

AI-Assisted The clock line SD_CLK is routed from PD6 through a 33 ohm series resistor (R50) to the SD card CLK pin and the ESD protection device U3 (SRV05-4). This series resistance provides edge-rate control and impedance matching for the clock signal, which is appropriate for SD card interfaces operating at default and high-speed modes. No pull-up is present on the clock line, which is correct per the SD Physical Layer Specification.

The command line (PD7) and all four data lines (PB14, PB15, PG9, PG10) each have a 10 kohm pull-up resistor to LD1_3.3v (R47, R49, R48, R45, R46 respectively). The SD specification requires pull-ups on CMD and DAT0-DAT3 to ensure proper bus idle states and card detection. The 10 kohm value is within the acceptable range specified by the SD Physical Layer Specification (10 kohm to 100 kohm). The card-detect switch line (PG11) also has a 10 kohm pull-up to LD1_3.3v via R51, allowing the MCU to detect card insertion by reading the GPIO state.

ESD protection is provided by two SRV05-4 devices: U3 covers the CLK, CMD, DAT0, and DAT1 signals, while U4 covers DAT2, DAT3/CS, and the card-detect switch. The SRV05-4 VP pins on U3 and U4 are connected to LD1_3.3v, providing the correct clamping reference for a 3.3V interface. The VN pins connect to GND. This is a well-structured ESD protection arrangement for the SD card interface.

AI-Assisted The SD card VDD pin is powered from the LD1_3.3v rail, which is generated by LD1 (AP2112K-3.3, a 600 mA LDO regulator). The LD1_3.3v rail carries extensive decoupling: the output of LD1 is bypassed with a 2.2 uF capacitor (C2) and a 4.7 uF capacitor (C3), plus numerous 100 nF capacitors distributed across the MCU VDD pins and other loads on this rail. The AP2112K-3.3 datasheet specifies a minimum output capacitance of 1 uF for stability, which is satisfied. The SD card itself does not have a dedicated local bypass capacitor at its VDD pin visible in the schematic; during layout, a 100 nF capacitor placed close to SD_CARD_1 pin 4 is recommended for clean power delivery during high-current card write bursts.

AI-Assisted The primary concern in this design is the SDMMC2 DAT2/DAT3 pin assignment error that prevents hardware 4-bit SD card operation. If the application only requires 1-bit SDMMC mode or SPI mode for the SD card, the current routing to PG9 and PG10 can function as GPIO-managed lines (with DAT2 and DAT3 held high via their pull-ups during 1-bit operation). However, if 4-bit throughput is needed — which is typical for applications involving audio streaming, data logging, or firmware updates from SD — the pin assignment must be corrected before layout.

The absence of external DDR, SRAM, NVRAM, or QSPI flash means the system is constrained to the STM32H745's internal 2 MB flash and 1 MB SRAM. For a dual-core application where both the Cortex-M7 and Cortex-M4 are active, the available internal memory may become a limiting factor depending on application complexity. The STM32H745 supports external memory via its FMC and Quad-SPI interfaces, but neither is utilized in this design. This is an architectural observation, not necessarily a defect, as the Orthrus-TX appears to be a compact radio controller transmitter where internal memory may be sufficient.

Memory	Interface	Finding	Severity
microSD (SD_CARD_1)	SDMMC2	Clock (PD6), CMD (PD7), DAT0 (PB14), and DAT1 (PB15) are correctly mapped to SDMMC2 alternate functions AF11/AF9 per the STM32H745xI/G datasheet (DS12956).
microSD (SD_CARD_1)	SDMMC2	DAT2 is routed to PG9 and DAT3 to PG10, neither of which has an SDMMC2 alternate function. Valid SDMMC2_D2 pins are PB3 (AF9) or PG11 (AF10); valid SDMMC2_D3 is PB4 (AF9). PG11, a valid D2 pin, is used for card-detect instead. Hardware 4-bit SDMMC2 mode is not possible with this pinout. Per STM32H745 datasheet and stm32h7xx-hal pin definitions.	High
microSD (SD_CARD_1)	SDMMC2	33 ohm series resistor R50 on SD_CLK provides appropriate edge-rate control for SD card clock signal integrity, per SD Physical Layer Specification.
microSD (SD_CARD_1)	SDMMC2	10 kohm pull-up resistors to LD1_3.3v on CMD (R47), DAT0 (R49), DAT1 (R48), DAT2 (R45), and DAT3 (R46) are within the 10-100 kohm range required by the SD Physical Layer Specification.
microSD (SD_CARD_1)	SDMMC2	ESD protection via SRV05-4 devices U3 (CLK, CMD, DAT0, DAT1) and U4 (DAT2, DAT3, card-detect) with VP tied to LD1_3.3v and VN to GND provides correct clamping for a 3.3V interface.
microSD (SD_CARD_1)	SDMMC2	Card-detect switch (pin 10) routed to PG11 with 10 kohm pull-up (R51) to LD1_3.3v allows software card-insertion detection.
microSD (SD_CARD_1)	SDMMC2	SD card VDD powered from LD1_3.3v (AP2112K-3.3 LDO). No dedicated local bypass capacitor is visible at the SD card VDD pin; a 100 nF capacitor close to SD_CARD_1 pin 4 is recommended during layout.	Low
microSD (SD_CARD_1)	SDMMC2	No series resistors on CMD or DAT lines. For default-speed and high-speed SD modes this is acceptable; series resistors are not required by the SD specification for these lines.
External DDR/SDRAM	FMC	No external DDR or SDRAM devices present in the design. The STM32H745 FMC interface is unused. Internal 1 MB SRAM is the only available RAM.
External QSPI Flash	QUADSPI	No external QSPI flash devices present. The STM32H745 Quad-SPI interface (capable of up to 133 MHz per DS12956) is unused. Internal 2 MB flash is the only program storage.
External SRAM/NVRAM	FMC/SPI	No external SRAM or NVRAM devices present in the design.

AI-Assisted The Orthrus-TX design contains a single external connector, J1, a USB Type-C receptacle (HRO-TYPE-C-31-M-13x). No EMC barrier or doghouse annotations are present on the schematic, indicating the design does not employ a formal shielded/unshielded zone architecture. All ground connections share a single GND net: the connector ground pins (J1 A1, A12, B1, B12), the connector shield pin (J1 S1), and all STM32H745ZIT6 VSS, VSSA, and VSSSMPS pins are on the same net. There is no separate chassis ground domain and no single-point connection between chassis and signal ground.

The direct tie of J1 shield pin S1 to signal GND means that any ESD current injected into the connector shell will flow directly into the signal ground plane. Per IEC 61000-4-2 and general EMC design practice, this creates a path for ESD-induced ground bounce to couple into sensitive analog and digital circuits. The STM32H745ZIT6 VSSA pin (pin 34) and VREF+ filtering (C19, C20) share this same GND net, so ESD energy on the connector shell can directly disturb the analog reference. A preferred approach for consumer-facing USB Type-C connectors is to connect the shell to a chassis ground plane through a low-impedance path (e.g., a ferrite bead or 1 MOhm resistor in parallel with a 4.7nF capacitor to signal GND), providing a controlled impedance between the two ground domains. This limits high-frequency ESD coupling into the signal ground while maintaining DC bonding for safety.

No common-mode choke is present on the USB_P / USB_N differential pair between J1 and the STM32H745ZIT6. For USB 2.0 Full Speed (12 Mbps) operation, a common-mode choke is not strictly required but is recommended for radiated emissions compliance per CISPR 32 / EN 55032 Class B. The absence of filtering on the USB data lines increases the risk of conducted and radiated emissions from the USB cable acting as an antenna, particularly in the 30 to 300 MHz range where USB harmonics are strongest.

AI-Assisted J1 is a USB Type-C receptacle, a consumer-facing, hot-plug interface that is directly exposed to user contact and cable insertion events. Per IEC 61000-4-2, consumer electronics are typically tested to Level 4 (plus 8 kV contact discharge, plus 15 kV air discharge). All signal pins on J1 that connect to active silicon require ESD protection adequate for this exposure level.

USB D+ and D- lines (USB_P, USB_N): These signals connect from J1 directly to STM32H745ZIT6 pins PA12 (pin 101) and PA11 (pin 100), with ESD protection provided by U2, an SRV05-4 TVS diode array in SOT-23-6. U2 pin 1 (IO1) is on USB_P, pin 3 (IO2) is on USB_N, pin 2 (VN) is tied to GND, and pin 5 (VP) is tied to the VBUS net via Net-(D1-A). The SRV05-4 is rated for IEC 61000-4-2 ESD at plus/minus 15 kV air discharge and plus/minus 8 kV contact discharge per the Semtech SRV05-4 datasheet, which meets Level 4 requirements. The device has low capacitance suitable for USB 2.0 data rates. U2 IO3 (pin 4) and IO4 (pin 6) are unused, which is acceptable as only two data lines require protection in a USB 2.0 implementation. The SRV05-4 VP pin is connected to the VBUS net (Net-(D1-A)), which serves as the positive rail reference for the internal TVS clamp. This is the correct topology per the SRV05-4 datasheet application circuit for USB port protection.

VBUS pins (A4, A9, B4, B9): The VBUS net (Net-(D1-A)) connects through D1, a Schottky diode in SOD-123, to the VCC rail. C54, a 100nF capacitor, is placed between VBUS and GND. There is no dedicated TVS diode on the VBUS line itself. The Schottky diode D1 provides reverse-polarity protection but does not clamp positive ESD transients. For a USB Type-C port exposed to user handling, a TVS diode on VBUS with a working voltage of at least 5 V (or 20 V if USB PD is supported) is a standard industry practice. The absence of a VBUS TVS means that positive ESD transients on VBUS will propagate through D1 into the VCC rail, which powers the three LDO regulators (LD1, LD2, LD3) and their downstream loads. This is a potential vulnerability for ESD coupling into the entire power tree.

CC1 and CC2 pins (A5, B5): CC1 connects through R42 (5.1 kOhm) to GND, and CC2 connects through R41 (5.1 kOhm) to GND. The 5.1 kOhm resistors identify the port as a UFP (Upstream Facing Port / sink) per the USB Type-C specification. There is no TVS or ESD protection on either CC line. The CC pins are directly adjacent to VBUS pins in the USB Type-C connector, and short-to-VBUS events due to debris, moisture, or connector wear are a well-documented failure mode. Per the TI TPD2S300 datasheet and Semtech application note SI21-03, CC pins require both ESD protection and overvoltage protection against VBUS shorts. The 5.1 kOhm resistors alone provide no transient voltage clamping. An ESD strike on CC1 or CC2 will see only the 5.1 kOhm resistor to ground, which limits current but does not clamp voltage. If the CC pins are not routed to any active IC (they terminate at the pull-down resistors only), the risk is limited to resistor damage and potential arcing to adjacent VBUS traces. However, a VBUS-to-CC short would apply up to 5 V (or higher if a non-compliant charger is connected) across the 5.1 kOhm resistor, dissipating up to 5 mW under normal conditions, but potentially much more during a transient.

SBU1 and SBU2 pins (A8, B8): These pins are marked as NC (no connect). For a USB 2.0-only implementation without alternate mode support, leaving SBU pins unconnected is acceptable. No ESD protection is needed on unconnected pins provided they are truly floating and not routed to any trace that could couple to adjacent signals.

Shield pin (S1): As noted in the EMC architecture section, S1 is tied directly to signal GND. This provides a low-impedance ESD return path but at the cost of injecting ESD current directly into the signal ground plane.

AI-Assisted The VBUS net from J1 passes through D1 (Schottky diode, SOD-123) to the VCC rail. The VCC rail feeds LD1, LD2, and LD3 (three LDO regulators) through their VIN pins, and also connects to C1, C17, C29, C38, C39 as bulk and decoupling capacitors. The Schottky diode D1 provides reverse-polarity protection, preventing current from flowing back from VCC to the USB connector if the board is powered from another source.

C54 (100nF) is placed on the VBUS side of D1, between Net-(D1-A) and GND. This capacitor provides local high-frequency decoupling on the VBUS net and also serves as the bypass capacitor for U2 VP pin. Per the SRV05-4 datasheet, the VP pin should have a low-impedance connection to the power rail being protected. The 100nF capacitor on this net is adequate for this purpose.

The D1 Schottky diode is specified as a generic D_Schottky in SOD-123 package. The forward voltage drop of a typical SOD-123 Schottky is 0.3 to 0.5 V, which reduces the available voltage at VCC. For USB 2.0 at 5 V VBUS, this leaves approximately 4.5 to 4.7 V at VCC, which is within the input range of typical 3.3 V LDO regulators. The SOD-123 package typically supports 1 A continuous current, which is adequate for the 3 A maximum current rating of the HRO TYPE-C-31-M-13 connector only if the total board current draw remains below 1 A. If higher current is expected, the SOD-123 package may be undersized.

AI-Assisted The design has a single external connector (J1, USB Type-C) with partial ESD protection. The USB D+/D- data lines are properly protected by U2 (SRV05-4), which meets IEC 61000-4-2 Level 4 requirements. However, several gaps exist in the overall protection strategy.

The CC1 and CC2 lines lack any TVS or ESD clamping. While these lines terminate in 5.1 kOhm pull-down resistors and do not connect to active silicon, they are exposed to user contact and VBUS-to-CC short events. Industry best practice for USB Type-C ports, as documented in TI application notes for the TPD2S300 and TPD4S311, and Semtech application note SI21-03, recommends ESD and overvoltage protection on CC pins.

The VBUS line lacks a dedicated TVS diode. ESD energy on VBUS passes through D1 into the VCC power rail, potentially disturbing all downstream regulators and their loads. A TVS diode with a working voltage of 5 V (or higher for USB PD) placed between VBUS and GND, on the connector side of D1, would clamp transients before they reach the power distribution network.

The connector shell ground (S1) is tied directly to signal GND without any filtering or impedance control. This creates a direct path for ESD currents from the connector shell into the signal ground plane, which can cause ground bounce affecting the STM32H745ZIT6 analog subsystem (VSSA, VREF+). A controlled connection (e.g., RC filter or ferrite bead between shell and signal ground) would reduce this coupling.

No common-mode filtering is present on the USB data lines. While not strictly required for USB 2.0 Full Speed, a common-mode choke would improve radiated emissions performance and is recommended for CISPR 32 / EN 55032 Class B compliance.

The design uses a single ground domain for all functions. There is no separation between analog ground, digital ground, and chassis ground. For a design with ADC inputs (the STM32H745ZIT6 has VDDA and VREF+ powered from a separate LDO, LD2), mixing ESD return currents with the analog ground reference can degrade ADC performance during and after ESD events.

Connector	Finding	Risk
J1 (USB Type-C)	USB D+/D- lines (USB_P, USB_N) are protected by U2 (SRV05-4), rated plus/minus 15 kV air and plus/minus 8 kV contact per IEC 61000-4-2 (Semtech SRV05-4 datasheet). Meets Level 4 requirements. U2 VN (pin 2) tied to GND and VP (pin 5) tied to VBUS — correct topology per datasheet application circuit.
J1 (USB Type-C)	CC1 (R42, 5.1 kOhm to GND) and CC2 (R41, 5.1 kOhm to GND) have no TVS or ESD clamping. CC pins are adjacent to VBUS in the Type-C connector and are vulnerable to short-to-VBUS events and direct ESD strikes. Per TI TPD2S300 datasheet and Semtech application note SI21-03, ESD and overvoltage protection on CC pins is recommended for consumer-facing USB Type-C ports.	Medium
J1 (USB Type-C)	VBUS line (Net-(D1-A)) has no dedicated TVS diode. D1 (Schottky, SOD-123) provides reverse-polarity protection only. Positive ESD transients on VBUS propagate through D1 into the VCC power rail feeding all three LDO regulators (LD1, LD2, LD3). Per Semtech application note SI21-03, a TVS diode on VBUS with appropriate working voltage is standard practice for USB Type-C ports.	Medium
J1 (USB Type-C)	Connector shell pin S1 is tied directly to signal GND with no filtering or impedance control. ESD current on the shell flows directly into the signal ground plane shared with STM32H745ZIT6 VSSA (pin 34) and VREF+ decoupling. This can cause ground bounce affecting ADC accuracy during ESD events. Per IEC 61000-4-2 design guidance, a controlled shell-to-signal-ground connection (RC network or ferrite bead) reduces ESD coupling.	Medium
J1 (USB Type-C)	No common-mode choke on USB_P / USB_N between J1 and STM32H745ZIT6. For USB 2.0 Full Speed, a common-mode choke is not mandatory but improves radiated emissions margin for CISPR 32 / EN 55032 Class B compliance.	Low
J1 (USB Type-C)	SBU1 (A8) and SBU2 (B8) are NC. Acceptable for USB 2.0-only implementation without alternate mode support. No ESD protection required on unconnected pins.
J1 (USB Type-C)	C54 (100nF) on VBUS net provides local decoupling and serves as U2 VP bypass. Adequate per SRV05-4 datasheet layout guidance.
J1 (USB Type-C)	Single GND domain used for connector ground, connector shell, digital VSS, analog VSSA, and SMPS VSSSMPS. No ground domain separation exists. ESD return currents from J1 share the same ground plane as the STM32H745ZIT6 analog reference (VDDA supplied by LD2, VREF+ filtered by C19/C20). Risk of ESD-induced noise coupling into ADC measurements.	Low