ESP32-game-console Design Analysis

1 Design Summary

out of 100

Depth of review, as a baseline: 36 verified datasheet parameters applied and 107 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

Design Type	Flat (1 sheets)
Total Components	57
Total Pins	235
Total Nets	46
Total Test Points	0

Improve your score:

Improve fault coverage (opens/shorts) +9
Add I2C pull-up resistors +2
Use IPC-compliant footprint names +2
Add test points on power rails +1
Add test points on indicator signals +1
Add test points on switch signals +1
Improve schematic library models +1
Move component values to VALUE property +1
Fix connector shell grounding +1
Add test points on OE/enable pins +1

Points deducted for open High/Medium AI findings:

3 High, 5 Medium -8.5

AI findings to review:

Power findings — 1 High, 2 Medium, 1 Low
HSSI findings — 1 Medium, 3 Review
Memory findings — 1 Medium, 2 Low, 4 Review
Functional findings — 2 High, 5 Review
EMC/ESD findings — 1 Medium, 4 Low, 6 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 20 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

The inserted test point count is unusually high because Optical (AOI) and X-ray (AXI) inspection contributes no coverage — none of the footprint names are recognized as IPC-7351B or IPC-7251 compliant. Repair the library footprint names to follow IPC naming and resubmit; the inserted test point count will drop to typical levels.

1.1 Design Overview

AI-Assisted — The board is a single-sheet, battery-powered handheld game console built around an ESP32-S3-WROOM-1U module (U1), which provides the Xtensa LX7 dual-core application processor, integrated flash, Wi-Fi 802.11b/g/n and Bluetooth LE radio with a u.FL/external antenna variant of the module. All user interface, storage, display and audio functions hang directly off the module's GPIO; there is no secondary MCU, FPGA or external memory controller on the board.

Processing and Storage

Removable mass storage is provided by a Hirose DM3AT microSD socket (J2) wired as a 4-bit SD/SDIO-capable interface to the module. A ST7789V-based SPI graphics panel (U5) provides the display, driven with the usual CS/DC/RST plus clock and data lines from the module. The panel and card socket share module bus pins J2_3 and J2_5, so display and card traffic are multiplexed by firmware.

Connectivity and Human Interface

External connectivity is a 16-position USB 2.0-only Type-C receptacle (J1, HRO TYPE-C-31-M-12), carrying VBUS, GND, CC1/CC2 and the flippable D+/D− pair; the D+/D− pair is routed through a USBLC6-2SC6 (U2) two-line ESD array before reaching the module's native USB peripheral. Per the STMicroelectronics datasheet, that device offers 15 kV IEC 61000-4-2 contact and air discharge protection with 2.5 pF typical I/O-to-GND capacitance, which keeps the pair inside USB 2.0 balance limits. User input is eleven momentary tactile switches (D-pad, A/B, L/R shoulder, SELECT, START, plus BOOT and RESET) and a slide switch (SW3) for power; a red indicator LED (D3) is fitted.

Audio

Audio output uses a PAM8403D filterless Class-D stereo amplifier (U6) driving a speaker terminal (LS1). Per the Diodes Incorporated datasheet (https://www.diodes.com/assets/Datasheets/products_inactive_data/PAM8403.pdf), the part operates from 2.5 V to 5.5 V, delivers typically 3.2 W per channel into 4 Ω at 5.0 V and 10 % THD+N, switches at 260 kHz typical, and has integrated over-temperature and output short-circuit protection. This device is marked "NOT RECOMMENDED FOR NEW DESIGN — USE PAM8406" on its datasheet cover page.

Power Tree

Input power is USB Type-C VBUS (+5 V) from J1. The +5 V rail feeds a TP4056 single-cell Li-ion/LiPo linear charger (U4) in the thermally-enhanced ESOP-8 package. Per the NanJing Top Power datasheet (REV 2.4, source: Tomachie), the charger provides a 4.2 V float voltage, up to 1000 mA programmable charge current with RPROG = 1.1 kΩ, 4.0 V minimum input and 8.0 V absolute maximum input, C/10 charge termination, and open-drain CHRG/STDBY status outputs. Its BAT output sources the battery node Net-(J3-Pin_1), which reaches the cell through the J3/J4 solder-wire terminals. A DO-41 40 V 1 A Schottky rectifier (D1) is fitted in the input/battery path.

The system 3.3 V rail is generated by an LF33 low-dropout regulator (U3) in TO-252-2, rated 500 mA output at fixed 3.3 V. The +3.3 V rail is the largest signal-side rail on the board, serving the ESP32-S3 module, the display and the microSD socket. The +5 V rail additionally supplies the Class-D amplifier and the ESD array's VBUS clamp reference. Ground is a single common return.

Thermal and Environmental Ratings

The narrowest operating window among the active devices sets the board's rating: the TP4056 charger is specified for −40 °C to +85 °C ambient with a 145 °C maximum junction temperature, and the PAM8403 for −40 °C to +85 °C ambient with a 125 °C maximum operating junction temperature and a +140 °C over-temperature trip. The USBLC6-2SC6 is rated −40 °C to +125 °C junction. The board is therefore a commercial/consumer-grade assembly with a −40 °C to +85 °C ambient envelope, subject to the charger's exposed-pad thermal path being soldered to board copper as the datasheet requires (page 13).

1.2 Processed Sheets

#	Sheet Name
1	ESP32-game-console.kicad_sch

1.3 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
13 SMT footprints do not follow IPC-7351B naming
3 footprints (connectors, specialty) — compliance unknown
5 footprints could not be classified for inspection

1.4 Invalid Placements

Sheet	Components	Observation
ESP32-game-console.kicad_sch	R11 / R16	Overlapping symbols

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

The part-number cross-check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	14	C1, C5, C14, C3, C12, C11, C6, C13 (+6 more)	✓
Resistors	Values in VALUE or Resistance	16	R17, R9, R10, R3, R14, R8, R18, R11 (+8 more)	✓
Fuses	VALUE has no usable electrical value — it is blank or a placeholder symbol letter ("C", "R"). Set VALUE to just the magnitude and units (e.g. 10k, 100nF, 10uH) or a =Property formula pointing at the typed value (e.g. =Resistance). Keep wattage, current, tolerance and voltage ratings out of VALUE, each in its own named property (Power, Current, Tolerance, Voltage) — not the Description, which is another free-form field. Without a magnitude, BOM queries, value parsing, and AI analysis cannot use it. (F1 currently has VALUE="Polyfuse_Small")	1	F1

2.1 Derating Check

Derating profile	commercial_default
Maximum ambient	40 °C
Checks performed	0

A part is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Capacitors qualify most often; a resistor or inductor appears under the same conditions. All other derating checks - current, power dissipation, temperature margins, and any check needing an operating point - are provided by the AI analysis within its report sections.

9 part(s) sit across a resolved power rail with no stated voltage rating and could not be checked: C1, C10, C11, C2, C5, C6, C7, C8, C9. Record each rating in a Voltage property.

Derating Settings Used in This Analysis
Parameter	Value	Applied
capacitor_voltage_pct	15% (85)	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_mno2_voltage_pct	50% (50)	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
capacitor_ripple_current_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
capacitor_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence
capacitor_aluminum_temperature_margin_c	20 °C	Applied by the AI analysis where the rating is in evidence
resistor_power_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
resistor_temperature_margin_c	20 °C	Applied by the AI analysis where the rating is in evidence
diode_reverse_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
diode_average_forward_current_pct	25% (75)	Applied by the AI analysis where the rating is in evidence
diode_power_dissipation_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_margin_c	25 °C	Applied by the AI analysis where the rating is in evidence
regulator_input_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
regulator_output_current_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
regulator_power_dissipation_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_margin_c	25 °C	Applied by the AI analysis where the rating is in evidence
ic_supply_voltage_absolute_max_pct	15% (85)	Applied by the AI analysis where the rating is in evidence
ic_input_voltage_absolute_max_pct	15% (85)	Applied by the AI analysis where the rating is in evidence
ic_output_current_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
ic_power_dissipation_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_margin_c	25 °C	Applied by the AI analysis where the rating is in evidence
connector_current_per_contact_pct	30% (70)	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
connector_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence
switch_current_pct	30% (70)	Applied by the AI analysis where the rating is in evidence
switch_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
switch_switching_power_pct	50% (50)	Applied by the AI analysis where the rating is in evidence
switch_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence
fuse_continuous_current_pct	25% (75)	Applied by the AI analysis where the rating is in evidence
fuse_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
fuse_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence
pptc_hold_current_pct	40% (60)	Applied by the AI analysis where the rating is in evidence
pptc_voltage_pct	20% (80)	Applied by the AI analysis where the rating is in evidence
pptc_temperature_margin_c	15 °C	Applied by the AI analysis where the rating is in evidence

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

1 unconnected pin(s) found:

1 unconnected pin(s) — all are electrical types that are safe to leave open (Bidirectional, Output, Passive, High-Impedance, or Unspecified). Common on partially-populated bus connectors (VME, backplanes, expansion headers) and on outputs whose consumer was omitted. Review to confirm intent, but no action is required by default.

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name	Notes
U6_9	NC	Unknown	PAM8403D	-	No net

3.2 Implied/Hidden Net Connections

No components with implied/hidden net connections found.

3.3 Open-Collector Pull-up Audit

Examined 1 candidate pin(s) on 1 net(s). 1 to verify with destination IC.

Finding	Recommended Action	Severity
Open-collector / open-drain outputs need an external pull-up resistor to a power rail to function. This audit lists pins where a pull-up appears to be missing or where the pin type may not match the schematic library.
U4_7 (CHRG) on Net-(U4-CHRG) U4 (TP4056-42-ESOP8) 1A Standalone Linear Li-ion/LiPo single-cell battery charger, 4.2V ±1% charge voltage, VCC = 4.0..8.0V, SOIC-8 (SOP-8) on-board only · library: Open Collector	Information: this net may be missing a pull-up. The destination IC (MCU/FPGA/other) may enable a configurable internal pull-up — verify its datasheet/BSDL. If none, add an external pull-up to a power rail.	Review

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation	Severity
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires that pin 1, the cathode, is on the left with the footprint at zero rotation. Tomachie will call out schematic-symbol problems that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, or a novice may wrongly indict a correct part — keeping consistent is the least-expensive path for everyone who handles the PCB.
D1 DO-41 unidirectional · pin_names · Schottky Rectifier	Pin 1 (K): +5V Pin 2 (A): Net-(D1-A)	Consistent

3.5 Summary

Total NO_ERC markers in design	23
Pins needing attention (warnings)	1
Pins for information only	0

4 Power Overview

Power rails	4
Power management sources identified	2

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Power Rail Analysis

Power Rails
Rail	Voltage	Source	Consumers
+5V	5.00V	-	U2 (USBLC6-2SC6), U3 (LF33_TO252), U4 (TP4056-42-ESOP8)
+3.3V	3.30V	U3 LF33_TO252	U1 (ESP32-S3-WROOM-1), U5 (SPIScreen), U6 (PAM8403D)
GND	-	J1 External	-
Net-(J3-Pin_1)	-	U4 TP4056-42-ESOP8	-

4.2 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.2.1 Power Tree Overview

AI-Assisted — USB-C J1 supplies VBUS to F1 (polyfuse) and D1 (40V/1A Schottky, cathode on +5V) forming reverse/blocking protection into +5V. +5V feeds U2 (USBLC6-2SC6 VBUS clamp), U3 (LF33, 3.3V/500mA LDO) and U4 (TP4056 charger). U3 sources +3.3V for U1, U5, U6 and J2. U4 BAT drives Net-(J3-Pin_1), joined to +5V through SW3.

4.2.2 U3 LF33 3.3V LDO

AI-Assisted — +3.3V carries 2x22µF + 3x0.1µF = 44.3µF, ample for LF33 stability; ceramic dielectric on all. VI/GND/VO DC paths are correct. Load estimate (ESP32-S3 peaks, ST7789V, PAM8403 quiescent 16mA) approaches the 500mA rating; U6 audio current is on +3.3V, giving reduced output power per PAM8403 tables.

4.2.3 U4 TP4056 Charger

AI-Assisted — VCC, GND and EPAD wiring are sound; BAT has 10µF as required. TEMP is tied to GND, disabling thermistor sensing. PROG returns through R11/R16 rather than a single resistor to GND, which perturbs the 1V programming node. STDBY is unconnected. CHRG drives D3 through R7 to +5V, a valid open-drain indicator.

4.3 Observations

AI-Assisted — PAM8403 is marked Not Recommended for New Design (use PAM8406). No capacitor voltage ratings are stated anywhere in the schematic, so derating cannot be closed. SW3 ties the battery node to +5V without isolation from the charger output.

4.4 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.4.1	U6	+3.3V	PAM8403 is NRND, use PAM8406 (Diodes datasheet)	High
4.4.2	U4	PROG	Programming resistor path returns via R11/R16, not directly to GND	Medium
4.4.3	All caps	all	Voltage ratings not stated in the schematic data	Medium
4.4.4	U4	TEMP	Tied to GND: battery temperature protection disabled	Low
4.4.5	U3	+3.3V	44.3µF ceramic output capacitance, VI/GND/VO correctly connected (ST datasheet)	✓
4.4.6	U4	BAT	10µF present per TP4056 datasheet page 3	✓
4.4.7	D1	+5V	40V/1A Schottky, orientation consistent	✓
4.4.8	U2	+5V	0.1µF on VBUS per ST datasheet	✓

4.5 Citations

AI-Assisted —

References
PAM8403 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/products_inactive_data/P...
TP4056 (NanJing Top Power ASIC Corp.) — datasheet TP4056.pdf
USBLC6-2SC6 (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7c...

5 Connector Pinouts

Total connectors

5.1 J1 USB_C_Receptacle_USB2.0_16P

J1 - USB_C_Receptacle_USB2.0_16P
Pin	Pin Name	Net	Notes
A1	GND	GND
A4	VBUS	Net-(J1-VBUS)
A5	CC1	Net-(J1-CC1)
A6	D+	USBC_D+
A7	D-	USBC_D-
A8	SBU1	NC
A9	VBUS	Net-(J1-VBUS)
A12	GND	GND
B1	GND	GND
B4	VBUS	Net-(J1-VBUS)
B5	CC2	Net-(J1-CC2)
B6	D+	USBC_D+
B7	D-	USBC_D-
B8	SBU2	NC
B9	VBUS	Net-(J1-VBUS)
B12	GND	GND
SH	SHIELD	GND

5.2 J2 Micro_SD_Card (I2C)

J2 - Micro_SD_Card (I2C)
Pin	Pin Name	Net	Notes
1	DAT2	NC
2	DAT3/CD	SDCard_CS
3	CMD	SDA
4	VDD	+3.3V
5	CLK	SCL
6	VSS	GND
7	DAT0	SDCard_MISO
8	DAT1	NC
SH	SHIELD	GND

5.3 J3 BAT+

J3 - BAT+
Pin	Pin Name	Net	Notes
1	Pin_1	Net-(J3-Pin_1)

5.4 J4 BAT-

J4 - BAT-
Pin	Pin Name	Net	Notes
1	Pin_1	GND

6 Indicator Documentation

1 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D3	RED	Red	Net-(D3-K)	ESP32-game-console.kicad_sch	LOW = On; R7 (1K); A:+5V K:Net-(D3-K)

6.2 Indicator Testability

0 of 1 indicators have test coverage.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D3	Direct	Net-(D3-K)	Design Warning: Test point needed on Net-(D3-K). Drive HIGH to turn on LED D3.

7 Switch Documentation

11 switch(es) found in design.

7.1 Switch Configurations

SW1 Contact Pairs (LEFT)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_LEFT	1	GND	SIGNAL	LOW

SW1 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_LEFT	1	CONTACT
1	1	GND	2	CONTACT

SW2 Contact Pairs (RIGHT)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_RIGHT	1	GND	SIGNAL	LOW

SW2 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_RIGHT	1	CONTACT
1	1	GND	2	CONTACT

SW3 Contact Pairs (SW_DPST_x2)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	Net-(J3-Pin_1)	2	+5V	SIGNAL	HIGH

SW3 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	B	+5V	-	-
1	A	Net-(J3-Pin_1)	2	CONTACT

SW7 Contact Pairs (UP)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_UP	1	GND	SIGNAL	LOW

SW7 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_UP	1	CONTACT
1	1	GND	2	CONTACT

SW8 Contact Pairs (DOWN)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_DOWN	1	GND	SIGNAL	LOW

SW8 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_DOWN	1	CONTACT
1	1	GND	2	CONTACT

SW9 Contact Pairs (A)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_A	1	GND	SIGNAL	LOW

SW9 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_A	1	CONTACT
1	1	GND	2	CONTACT

SW10 Contact Pairs (B)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_B	1	GND	SIGNAL	LOW

SW10 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_B	1	CONTACT
1	1	GND	2	CONTACT

SW11 Contact Pairs (L)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_L	1	GND	SIGNAL	LOW

SW11 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_L	1	CONTACT
1	1	GND	2	CONTACT

SW12 Contact Pairs (R)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Btn_R	1	GND	SIGNAL	LOW

SW12 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Btn_R	1	CONTACT
1	1	GND	2	CONTACT

SW18 Contact Pairs (SELECT)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Net-(R5-Pad1)	1	+3.3V	SIGNAL	HIGH

SW18 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Net-(R5-Pad1)	1	CONTACT
1	1	+3.3V	2	CONTACT

SW19 Contact Pairs (START)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	2	Net-(R13-Pad1)	1	+3.3V	SIGNAL	HIGH

SW19 All Pins
Pin #	Pin Name	Net	Paired With	Type
2	2	Net-(R13-Pad1)	1	CONTACT
1	1	+3.3V	2	CONTACT

7.2 Switch DFT Analysis

Switches for mode selection are useful for development and manual debug, but production test environments require electrical override capability. Latching switches (DIP) that hold a signal to GND need isolation resistors so ATE can override. Momentary switches (push buttons) don't hold the signal, but ATE still needs test point access to stimulate the signal.

Testpoint and Rs isolation resistor placement

Design Rationale: Switches for mode selection are valuable for engineering development and bench debug. However, production test and field returns require electrical override capability without manual intervention. Adding test points and isolation resistors creates a lifecycle-robust design that works across development, production test, and field returns without requiring procedure documentation or specialized knowledge of switch positions. The goal is a self-documenting, procedure-proof test interface. BOM impact: One 0201/0402 resistor per controlled signal.

Switch	Signal	Function	Pullup	Rail	Issue
SW11	Btn_L	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW3	Net-(J3-Pin_1)	Switch-controlled signal	(not found)	+5V (5.0V)	No test point + Switch forces signal, ATE cannot override
SW9	Btn_A	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW8	Btn_DOWN	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW10	Btn_B	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW18	Net-(R5-Pad1)	Momentary control	(not found)	+3.3V (3.3V)	No test point — Momentary — ATE needs probe access
SW2	Btn_RIGHT	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW7	Btn_UP	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW1	Btn_LEFT	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW12	Btn_R	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access
SW19	Net-(R13-Pad1)	Momentary control	(not found)	+3.3V (3.3V)	No test point — Momentary — ATE needs probe access

8 Low-Speed Serial Interfaces (LSSI)

Detected: 1 I2C

8.1 I2C

I2C: U1 -> U5
Topology: U1 » Targets (U5, J2)
Signal	Net Name	Connector	Test Point	Target Pin
SCL (needs pull-up)	SCL	J2_5	(none)	U1_18 (IO10), U5_5 (SCL)
SDA	SDA	J2_3	(none)	U1_19 (IO11), U5_4 (SDA)
Address	Target	Industry Type	Description
	U5	SPIScreen
Controller	Industry Type	Description
U1	ESP32-S3-WROOM-1	RF Module, ESP32-S3 SoC, Wi-Fi 802.11b/g/n, Bluetooth, BLE, 32-bit, 3.3V, onboard antenna, SMD

I2C Pull-up Check
Net	Component	Status
SDA	R8	Pull-up resistor 100K (R8) found on SDA	✓
SCL		Pull-up on SCL was not detected. A pull-up for basic I2C operation would be about 4.7K ohms. Even if an IC has internal pull-ups on its inputs, they are likely just for biasing the input high (47-100K ohms) and are not sufficient for I2C. We did not consult the datasheet for U5 but low-value resistors cost silicon area, so it is unlikely the IC has them.

8.2 LSSI DFT Analysis

2 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
SCL	SCL	J2_5	I2C -> U5
SDA	SDA	J2_3	I2C -> U5

9 High-Speed Serial Interfaces (HSSI)

4 differential pair(s)

Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.

1 USB differential pair(s) have no controlled-impedance net class assigned. Assign a 90 Ohm differential net class so the impedance intent carries into PCB layout and length tuning.

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

None of the 4 differential pairs specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM, 90_OHM, 50_OHM. The pairs are already identified by their nets, so the ohm value is the useful part to capture for layout.

Differential Pairs
Net Name	Class	Impedance	Notes
D+	DIFF_PAIR
D-	DIFF_PAIR
USBC_D+	USB
USBC_D-	USB

9.2 AI-Assisted Analysis

9.2.1 USB 2.0 Interface at the Type-C Receptacle J1

AI-Assisted — The only high-speed serial link in this design is a single USB 2.0 channel. It runs from the 16-pin USB Type-C receptacle J1 (D+ on A6/B6, D- on A7/B7, both positions strapped together as required for a USB 2.0-only Type-C receptacle) on nets USBC_D+ and USBC_D- into the ESD array U2, and continues on nets D+ and D- to U1 pins 14 (USB_D+) and 13 (USB_D-) of the ESP32-S3-WROOM-1 module. U2 is wired in-line as intended: USBC_D- to pin 1 and D- to pin 6 (the I/O1 pair), USBC_D+ to pin 3 and D+ to pin 4 (the I/O2 pair), so each channel passes through one protection cell without cross-pairing. The link carries at most USB 2.0 High Speed, 480 Mbit/s; the USBLC6-2SC6 is specified for data transmission to 480 Mbit/s (STMicroelectronics datasheet, Rev 5, https://datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7ccf534db0.pdf), so the protection device is not the bandwidth limit. USB 2.0 requires 90 ohm differential characteristic impedance; no impedance net class is assigned to USBC_D+/USBC_D- or D+/D- in the schematic. Because impedance control is a net-class property that the layout tool consumes, it must be set in the schematic before layout rather than carried as a text note. The two segments should also be length-matched intra-pair and kept as a single continuous 90 ohm path through the U2 pads.

9.2.2 AC Coupling, Termination and ESD Clamping on the USB Channel

AI-Assisted — USB 2.0 High Speed is a DC-coupled, current-driven signalling scheme; the standard requires no series AC coupling capacitors on D+/D-, and none are fitted here. That is correct, and no series damping resistors are present either — correct, since High Speed termination is the transceiver's on-die 45 ohm single-ended impedance and the full-speed/low-speed 1.5 kohm pull-up is internal to the ESP32-S3 USB Serial/JTAG PHY. No external bias network is required or fitted. The only series elements between the connector and the module are the U2 protection cells, whose I/O-to-GND capacitance is 2.5 pF typical (3.5 pF max) with I/O-to-GND matching of 0.015 pF typical, explicitly stated as compliant with the USB 2.0 D+/D- balance requirement. Clamping is 12 V maximum at 1 A and 17 V maximum at 5 A (8/20 us). Those clamp figures sit well above the 3.6 V absolute maximum of the ESP32-S3 USB pads, but the two numbers are taken under different conditions — an 8/20 us surge clamp against a DC absolute-maximum rating — so a protection margin cannot be closed from the available data; this is the industry-standard device for this exact position and is noted rather than scored as a gap. Layout must keep the U2 GND path and the connector-to-I/O tracks short, since the datasheet shows track inductance dominating the effective clamp voltage.

9.2.3 Connector Suitability, CC Configuration and Supply Filtering

AI-Assisted — J1 is a moulded USB Type-C receptacle with a defined mating impedance, appropriate for 480 Mbit/s; no unshielded pin header carries the differential pair, so there is no non-impedance-controlled discontinuity in the link. The shield pin SH of J1 is tied directly to GND, giving a single common reference — acceptable on a battery-powered handheld with no separate chassis ground, and the correct return for the ESD current U2 diverts. As an upstream-facing port, both CC lines are pulled to GND by 5.1K resistors: R4 from J1 pin A5 (CC1) to GND and R3 from J1 pin B5 (CC2) to GND, which is the Rd advertisement required for default 5 V sourcing. SBU1 and SBU2 are left unused, correct for a USB 2.0-only port. VBUS from the receptacle is fused by F1 before reaching the +5V rail. The VBUS clamp pin of U2 (pin 5) sits on +5V, which carries 32.1 uF total including C5, 0.1uF — this satisfies the 100 nF VBUS decoupling the STMicroelectronics datasheet shows in its layout guidance, and C5 must be placed at the U2 VBUS pin rather than shared with the bulk capacitors. The ESP32-S3-WROOM-1 module contains its own 40 MHz reference; no external oscillator is required for the USB PHY, and its 3V3 pin is fed from a rail carrying 44.3 uF total.

9.3 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.3.1	USBC_D+/USBC_D-, D+/D-	USB 2.0 High Speed	No 90 ohm differential impedance net class assigned to either segment of the pair; impedance control must be set as a net class in the schematic so the layout tool enforces it (USB 2.0 specification, 90 ohm differential)	Medium
9.3.2	U2 clamping	ESD protection	Clamp voltage 12 V max at 1 A and 17 V max at 5 A (8/20 us) sits above the ESP32-S3 USB pad DC absolute maximum; the two figures use different test conditions (surge pulse versus DC rating) so the margin cannot be closed from available data (STMicroelectronics datasheet)	Review
9.3.3	SCL/SDA shared bus	SPI (display and SD card)	U5 and J2 share clock net SCL and data net SDA with separate chip selects Screen_CS and SDCard_CS; route as a short star from U1 rather than a daisy chain, and bound the clock rate by the slower device	Review
9.3.4	SDA, SDCard_MISO, SDCard_CS	SPI (SD card)	R8, R9, R10 each 100k with pin 2 on +3.3V provide idle-state bias only; adequate because all three nets are actively driven during transfers, but high for edge-rate support if the lines are ever released mid-transfer	Review
9.3.5	J1 to U2 to U1 (D+/D-)	USB 2.0 High Speed	Channel wired end to end: J1 A6/B6 and A7/B7 to U2 I/O2 and I/O1 cells, continuing to U1 pins 14 and 13; no cross-pairing between the two protection cells (STMicroelectronics USBLC6-2SC6 datasheet, Rev 5)	✓
9.3.6	D+/D-	USB 2.0 High Speed	No series AC coupling capacitors fitted, correct: USB 2.0 High Speed is DC-coupled and the standard requires no series capacitors	✓
9.3.7	D+/D-	USB 2.0 High Speed	No external series or parallel termination fitted, correct: High Speed termination and the speed-identification pull-up are on-die in the ESP32-S3 USB PHY	✓
9.3.8	U2 protection cells	USB 2.0 High Speed	I/O capacitance 2.5 pF typical, 3.5 pF max, with 0.015 pF typical I/O-to-GND matching, stated as compliant with USB 2.0 D+/D- balance; rated to 480 Mbit/s (STMicroelectronics datasheet)	✓
9.3.9	U2 VBUS pin 5	Supply filtering	Pin sits on the +5V rail carrying 32.1 uF total including C5, 0.1uF, meeting the 100 nF VBUS decoupling shown in the manufacturer layout guidance; C5 must be placed at the pin (STMicroelectronics datasheet, page 9)	✓
9.3.10	J1 CC1/CC2	USB Type-C sink	R4 from J1 pin A5 to GND and R3 from J1 pin B5 to GND, both 5.1K, correctly advertise Rd for a default 5 V upstream-facing port (USB Type-C specification)	✓
9.3.11	J1 connector	USB 2.0 High Speed	Moulded Type-C receptacle with defined mating impedance is suitable for 480 Mbit/s; no pin header or unshielded connector in the differential path	✓
9.3.12	J1 shield	Grounding	Shield pin SH tied directly to GND, providing the ESD return path for U2 on a single-reference battery-powered board	✓
9.3.13	U1 USB PHY clock	USB 2.0 High Speed	ESP32-S3-WROOM-1 module integrates its own 40 MHz reference; no external oscillator required for the USB PHY, and the module 3V3 pin is fed from a rail carrying 44.3 uF total	✓

9.4 Citations

AI-Assisted —

References
USBLC6-2SC6 (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7c...

10 Memory Interface Analysis

Found 2 complete memory interface(s)

10.1 U5 I2C

U5 (SPIScreen) - I2C
Signal	Pin Name	Pin #	Net Name	Test Point	Connector
CLOCK	SCL	5	SCL	-	J2_5
DATA_0	SDA	4	SDA	-	J2_3
Direct 1-bit programming access via connector

10.2 J2 EMMC Connector

J2 (Micro_SD_Card) - EMMC Connector Interface [4-bit]
Signal	Pin Name	Pin #	Net Name	Test Point	Source IC
CLOCK	CLK	5	SCL	-	U1_18
CTRL_SDA	CMD	3	SDA	-	U1_19
DATA_0	DAT1	8		-	-
DATA_1	DAT2	1		-	-
DATA_2	DAT3/CD	2	SDCard_CS	-	U1_21
DATA_3	DAT0	7	SDCard_MISO	-	U1_17
DESIGN_WARNING: Test points needed on for direct on-board programming

10.3 AI-Assisted Analysis

10.3.1 microSD Card Socket (J2) — SPI-Mode SD Interface

AI-Assisted — J2 is a Hirose DM3AT-SF-PEJM5 push-push socket wired for 1-bit SPI mode: CLK on the SCL net driven by U1 IO10, CMD on the SDA net driven by U1 IO11 (data into the card), DAT0 returning on SDCard_MISO to U1 IO9, and DAT3/CD used as chip select on SDCard_CS from U1 IO13. This is the standard SPI-mode mapping of the SD Physical Layer Simplified Specification, and the pin directions on the shared write line are consistent — CMD is a card input and DAT0 is the only card output, so no two devices contend on one wire.

Power and return are properly established: VDD (pin 4) sits on the +3.3V rail from U3, VSS (pin 6) is on GND, and the shell is bonded to GND. No dedicated local ceramic is placed at the socket; all +3.3V bulk and bypass capacitance (44.3 µF total, 2x22 µF plus 3x0.1 µF) is distributed at the regulator and the module, so the card's write-burst current step is served from a distance.

DAT1 (pin 8) and DAT2 (pin 1) are left open. The SD Simplified Specification requires all card data lines to be held at a defined level; floating CMOS inputs on the card raise standby current and can allow spurious mode changes. Pull-ups of 100k are fitted on CMD (R8), DAT0 (R9) and DAT3/CD (R10), each returning to +3.3V, which biases the bus during power-up before firmware drives it. No series damping is present on CLK, CMD or the data lines.

10.3.2 Shared SPI Bus — SD Card and ST7789V Display

AI-Assisted — The SD socket shares its clock (SCL) and write data line (SDA) with the ST7789V panel U5, which takes SCL, SDA, DC (IO7), RST (IO8) and CS (IO12). The display is write-only and does not drive the bus, so bus arbitration reduces to chip-select discipline: SDCard_CS on IO13 and Screen_CS on IO12 are separate GPIOs, which is correct multi-slave decoding.

The asymmetry is at reset. SDCard_CS is held high by R10 to +3.3V, so the card ignores traffic until firmware asserts it. Screen_CS has no pull-up and no other net member besides U1 IO12 and U5 pin 1; between power-on and firmware GPIO configuration it floats, and any SD initialization traffic issued on the shared clock and data lines during that window can be latched by the ST7789V as command/parameter bytes, corrupting the panel state. A pull-up on Screen_CS to +3.3V of the same class as R10 closes this deterministically.

The 100k pull-up value is at the top of the range the SD Simplified Specification permits for the SPI-mode chip select; it defines the idle level but contributes essentially no drive against line capacitance. Since all three lines are actively driven push-pull by the ESP32-S3 during transfers, this is a bias function only and does not limit clock rate. Using DAT3/CD as chip select means the socket's card-detect function is consumed; no separate insertion-detect signal reaches U1.

10.4 Observations

AI-Assisted — No DDR, SDRAM, SRAM, NVRAM or external QSPI Flash device is present. Program and data storage is the SPI flash integrated inside the ESP32-S3-WROOM-1U module on the module's dedicated internal flash pins, which are not brought out to the module edge and therefore need no board-level series termination, pull-ups or decoupling beyond the module's own 3V3 bypassing. The GPIOs used for buttons and peripherals avoid the module's strapping pins other than IO0, which carries the Boot1 button with R2 as a pull-down to GND — the boot-mode function is intended there.

Signal integrity risk on the shared bus is low for a THT/hand-assembled console at typical SD SPI clocks of 20–40 MHz, but with three loads on SCL (U1, U5, J2) and no source series resistor at the driver, overshoot at the socket depends entirely on layout. Placing a footprint for a small series resistor (22–33 Ω) at the U1 clock output costs nothing at schematic stage and gives a tuning option after the first board.

The +3.3V rail feeding the card, the module, the panel and the PAM8403 amplifier is a single LF33 (ST datasheet, 500 mA maximum output current). SD write bursts, Wi-Fi transmit bursts from the module and class-D audio draw all land on that one linear regulator; a summed worst-case current budget from each device's datasheet maximum has not been computed here and is the analysis needed to close the question.

10.5 Findings

AI-Assisted —

#	Memory	Interface	Finding	Severity
10.5.1	ST7789V panel U5	SPI select	Screen_CS has no pull-up and floats until firmware configures IO12; SD initialization traffic on the shared clock and data lines can be latched as display commands. Add a pull-up to +3.3V (Sitronix ST7789V datasheet, source: Tomachie)	Medium
10.5.2	microSD socket J2	Decoupling	No local bypass capacitor at the socket VDD; all +3.3V capacitance (44.3 µF) is remote at the regulator and module. Add a 0.1 µF ceramic at J2 pin 4 per SD Physical Layer Simplified Specification host recommendations	Low
10.5.3	microSD socket J2	Unused data lines	DAT1 (pin 8) and DAT2 (pin 1) are left open; the SD specification requires defined levels on all card data lines. Fit 10k–100k pull-ups to +3.3V	Low
10.5.4	microSD socket J2	Bias resistors	R8 (CMD), R9 (DAT0), R10 (DAT3/CD) are 100k to +3.3V — valid but at the weak end of the SPI-mode range; lines are actively driven, so this is a bias-only function	Review
10.5.5	microSD socket J2	Card detect	DAT3/CD is consumed as chip select, so no insertion-detect signal reaches U1; firmware must poll for card presence (SD Physical Layer Simplified Specification)	Review
10.5.6	Shared SPI bus (J2, U5)	Signal integrity	No series damping on SCL/SDA with three loads; provide a 22–33 Ω series footprint at the U1 clock output as a layout-stage tuning option	Review
10.5.7	+3.3V rail (U3)	Supply headroom	Card write bursts, Wi-Fi transmit bursts and the audio amplifier share one 500 mA LDO; a summed worst-case current budget from each device's datasheet maximum was not computed here (ST LF33 datasheet)	Review
10.5.8	microSD socket J2	SD, SPI mode	Pin mapping CLK/CMD/DAT0/DAT3-as-CS matches SPI-mode wiring of the SD Physical Layer Simplified Specification; card input (CMD) and card output (DAT0) are on separate wires, no direction conflict	✓
10.5.9	microSD socket J2	Power	VDD (pin 4) on +3.3V from U3, VSS (pin 6) on GND, shell bonded to GND — DC paths for supply and return are established (ST LF33 datasheet)	✓
10.5.10	Shared SPI bus (J2, U5)	Chip-select decoding	SDCard_CS (IO13) and Screen_CS (IO12) are independent GPIOs — correct multi-slave select scheme	✓
10.5.11	ESP32-S3-WROOM-1U (U1)	Internal SPI flash	Module flash is internal on dedicated pins not exposed at the module edge; no board-level termination or pull-ups required (Espressif ESP32-S3-WROOM-1/1U datasheet)	✓
10.5.12	ESP32-S3-WROOM-1U (U1)	Boot strapping	IO0 pulled down by R2 to GND with Boot1 to GND — download-boot strapping intended and consistent (Espressif ESP32-S3-WROOM-1/1U datasheet)	✓

11 Functional Analysis

6 device(s) to review across 2 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
Boot1	DEVICE	SW_Push	Push button switch, generic, two pins	-	-
LS1	DEVICE	Speaker	Speaker	-	-
Reset1	DEVICE	SW_Push	Push button switch, generic, two pins	-	-
U2	DEVICE	USBLC6-2SC6	Very low capacitance ESD protection diode, 2 data-line, SOT-23-6	-	-
U6	DEVICE	PAM8403D	3W Filterless Class-D Stereo Audio Amplifier, SOIC-16	-	-
U1	WIRELESS	ESP32-S3-WROOM-1	RF Module, ESP32-S3 SoC, Wi-Fi 802.11b/g/n, Bluetooth, BLE, 32-bit, 3.3V, onboard antenna, SMD	I2C	-

11.1 Functional Analysis

11.1.1 ESP32-S3-WROOM-1 (U1) — supply, boot straps, interfaces

AI-Assisted — U1 is powered from the +3.3V rail sourced by U3, and that rail carries 44.3 uF total (2x22uF + 3x0.1uF). EN is held by R1 (pin 2 on Net-(U1-EN), pin 1 on +3.3V) with C3 (0.1uF) and C4 (0.1uF) to GND and Reset1 shorting the node to GND — a correct power-on reset and manual reset network, although 0.2 uF total on EN gives a long release delay in parallel with the 100k pull-up. IO0 is pulled to GND by R2 (pin 2 on Net-(U1-IO0), pin 1 on GND) with Boot1 also to GND: this holds the strap LOW at reset, forcing download boot on every power-up. IO0 must be pulled UP to +3.3V for normal SPI-flash boot, with the button pulling it low — as drawn the console will not run application code. Screen U5 uses SPI with CS on IO12, DC on IO7, RST on IO8, SCL on IO10, SDA on IO11; SDA/SCL are shared with the microSD socket J2 (CMD, CLK) and SDCard_MISO is on IO9 with R9 to +3.3V, SDCard_CS on IO13 with R10 to +3.3V. The screen's CS (Screen_CS) has no pull-up and no stated internal pull on the module pin, so its reset-state level is the one unknown holding the display deselected before firmware runs. The module's antenna is integral (WROOM-1U variant footprint is fitted with an external-antenna module part number); no matching network is required for the on-module antenna. All button inputs (Btn_UP/DOWN/LEFT/RIGHT/A/B/L/R, and START/SELECT via R13/R5 into Btn_HELPERS with R14 to GND) switch to GND with no external pull-ups, relying on the ESP32-S3 internal pull-ups, which is acceptable.

11.1.2 USBLC6-2SC6 (U2) — USB ESD protection

AI-Assisted — U2 sits between connector J1 and the module: I/O2 pins on USBC_D+ and D+, I/O1 pins on USBC_D- and D-, GND on GND, VBUS on the +5V rail. This is the correct rail-to-rail placement with the protected data lines passing through the device. Clamping is 12 V max at 1 A (8/20 us) and 17 V max at 5 A per the STMicroelectronics datasheet, below the ESP32-S3 USB pin ratings, so the parts behind the connector are covered. The datasheet asks for a 100 nF decoupling capacitor on the VBUS pin; C5 (0.1uF) is on +5V and serves this role. The device is bidirectional on the I/O lines, so no orientation concern applies.

11.1.3 PAM8403D (U6) — Class-D audio amplifier

AI-Assisted — U6 is supplied from +3.3V on VDD and both PVDD pins, inside the 2.5–5.5 V recommended range (Diodes datasheet); at 3.6 V it delivers 0.9 W into 8 ohm at 10% THD, so output power is roughly a quarter of the 3 W headline figure at this rail. VREF is bypassed by C12 (0.1uF) to GND, matching the 0.1uF shown in the typical application circuit. The right channel is driven through R15 and the C13/C14 (1uF each) network into INR; the left input INL and both left outputs are unconnected in the schematic, so only the right channel is used and LS1 is wired across ROUT+/ROUT-. ~SHDN is driven from IO14 via R17 and ~MUTE from IO15 via R18, both correct active-low control inputs with internal pull-ups. Pin 9 (NC) is unconnected, which the datasheet permits. No ferrite bead plus 220 pF is fitted on the speaker lines; the datasheet recommends this for EMI suppression in filterless operation.

11.1.4 Push buttons, speaker and charge-status LED

AI-Assisted — Boot1 and Reset1 are simple two-pin switches to GND on the IO0 and EN nets respectively, each with its capacitor/resistor network described above. LS1 is a two-terminal speaker directly across the bridge-tied outputs of U6, which is the correct filterless connection. D3 is the charge-status LED: its anode is on +5V and its cathode goes through R7 (1K) to the open-drain ~CHRG output of U4, so the LED sinks into the charger when charging is active — correct polarity and the 1k series resistor the TP4056 datasheet specifies. No separate pull-up on ~CHRG is needed because the LED and R7 provide the pull to +5V.

11.1.5 Observations and Findings

AI-Assisted — Beyond the USB channel there are no multi-gigabit or SerDes interfaces on this board. The remaining serial buses are low-speed synchronous links: the ST7789V display U5 and the microSD socket J2 share a clock net (SCL, driven from U1 pin 18) and a host-to-device data net (SDA, U1 pin 19), with separate chip selects Screen_CS and SDCard_CS and a dedicated return path SDCard_MISO. This is a shared SPI bus operated in SD SPI mode; J2 DAT1 and DAT2 are unused, which is normal for SPI-mode operation, and the card's DAT3/CD line serves as its chip select. Pull-ups R8, R9 and R10 (each 100k, pin 2 on +3.3V, pin 1 on SDA, SDCard_MISO and SDCard_CS respectively) keep the card lines defined while the bus is idle; 100k is high for an SPI bus at speed but adequate as idle-state biasing since all three nets are actively driven during transfers. Because the display and the card share SCL and SDA, the schematic-level bus topology should be laid out as a short star from U1 rather than a daisy chain, and the SPI clock rate is bounded by the slower of the two devices. Nothing in the data indicates any part in this design is end-of-life or not recommended for new designs.

11.2 Findings

AI-Assisted —

#	Device	Finding	Severity
11.2.1	U1 (ESP32-S3-WROOM-1)	IO0 strap held low by R2 to GND and Boot1: forces download boot at every reset; a pull-up to +3.3V is required for normal flash boot	High
11.2.2	U6	Part is marked Not Recommended for New Design on the Diodes datasheet cover (PAM8406 successor)	High
11.2.3	U1	EN network R1 to +3.3V with C3+C4 (0.1uF each) and Reset1 to GND — valid reset topology; 0.2 uF gives an extended release delay	Review
11.2.4	U1	Screen_CS has no external pull-up; deselect level before firmware init depends on the module pin reset state, which is not established here	Review
11.2.5	U6 (PAM8403D)	Supplied at 3.3 V, within the 2.5–5.5 V recommended range; output power ~0.9 W into 8 ohm rather than 3 W (Diodes datasheet)	Review
11.2.6	U6	Left channel INL and left outputs unconnected; only the right channel drives LS1	Review
11.2.7	U6	No ferrite bead plus 220 pF on the speaker lines, recommended for filterless EMI suppression (Diodes datasheet)	Review
11.2.8	U1	SD card lines: R9/R10 to +3.3V on MISO and CS; CMD/CLK shared with display SPI — wiring consistent	✓
11.2.9	U2 (USBLC6-2SC6)	Data lines routed through I/O pairs, GND to ground, VBUS to +5V; clamping 12 V at 1 A per ST datasheet protects downstream USB pins	✓
11.2.10	U2	VBUS decoupling of 100 nF provided by C5 (0.1uF) as required by the ST datasheet	✓
11.2.11	U6	VREF bypassed by C12 (0.1uF), matching the typical application circuit	✓
11.2.12	U6	~SHDN and ~MUTE driven from U1 GPIOs via R17/R18; active-low polarity correct with internal pull-ups	✓
11.2.13	LS1 (speaker)	Connected across the bridge-tied ROUT+/ROUT- outputs — correct filterless connection	✓
11.2.14	D3 / ~CHRG	LED anode on +5V, cathode through R7 (1K) to the open-drain ~CHRG output of U4 — correct polarity and the 1k series resistor per the TP4056 datasheet; no separate pull-up needed	✓
11.2.15	Boot1 / Reset1	Two-pin switches to GND on the IO0 and EN nets; wiring correct	✓

11.3 Citations

AI-Assisted —

References
PAM8403 (Diodes Incorporated) — datasheet www.diodes.com/assets/Datasheets/products_inactive_data/P...
TP4056 (NanJing Top Power ASIC Corp.) — datasheet TP4056.pdf
USBLC6-2SC6 (STMicroelectronics) — datasheet datasheet.lcsc.com/datasheet/pdf/0d3a2ab954b34651a0695e7c...

12 Designer Annotated Nets

No designer-annotated nets found.

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	2

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	2

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J1	USB_C_Receptacle_USB2.0_16P	J1 (USB_C_Receptacle_USB2.0_16P): Shell pins connected directly to logic GND which masks design intent for layout.	Per USB Type-C Specification R2.5, Section 3.2.1: the receptacle shell shall be connected to the PCB ground plane — this is a directive to prevent a floating shell, not a directive to ignore IEC 61000-4-2 ESD requirements and mandate a direct short. Place shell/shield tabs on a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD). This net represents the copper pour under the shielded connector. For plastic enclosed products with no earth ground, add a schematic note for dense via stitching of the shield copper pours to the ground plane with no isolation network. For earth ground connected products, review if the product requires R\|\|C isolation of shields from logic GND to meet ESD compliance (IEC 61000-4-2).
J2	Micro_SD_Card	J2 (Micro_SD_Card): Shield pins SHIELD connected directly to logic GND which masks design intent for layout.	Place shell/shield tabs on a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD). This net represents the copper pour under the shielded connector. For plastic enclosed products with no earth ground, add a schematic note for dense via stitching of the shield copper pours to the ground plane with no isolation network. For earth ground connected products, review if the product requires R\|\|C isolation of shields from logic GND to meet ESD compliance (IEC 61000-4-2).

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed:9 connector-facing signal(s). 0 protected, 9 unprotected, 0 orientation issue(s).

13.2.1 Unprotected Signal Nets

Signal Net	Connector	Status
USBC_D+	J1	No ESD Protection
Net-(J1-CC2)	J1	No ESD Protection
SDA	J2	No ESD Protection
SDCard_CS	J2	No ESD Protection
Net-(J1-VBUS)	J1	No ESD Protection
SCL	J2	No ESD Protection
SDCard_MISO	J2	No ESD Protection
Net-(J1-CC1)	J1	No ESD Protection
USBC_D-	J1	No ESD Protection

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture — Grounding, Filtering and Shielding

AI-Assisted — The board uses a single logic ground domain. All returns — the USB-C receptacle ground contacts A1, A12, B1, B12 and its shell SH, the microSD socket VSS and shell SH, the ESP32-S3 module grounds, the LDO, the charger, the audio amplifier and every decoupling capacitor — share one GND net. For a plastic-enclosed, battery-capable consumer device this single-domain approach is correct: there is no earth reference, so the logic plane is the only ESD sink and a uniform common-mode rise during a strike keeps differential voltage across connector pins near zero.

The shell contacts of both shielded connectors (J1 SH, J2 SH) carry the logic GND net name. The schematic therefore does not capture the shield-bonding strategy as design intent: a layout tool sees no distinct pour for each connector opening and no place to fit bond components. Recommended practice is a dedicated net per shielded connector (SHIELD_GND_TYPE_C, SHIELD_GND_SD), each representing the outer-layer copper pour beneath its connector, stitched densely to the ground plane for the lowest-inductance ESD return path per IEC 61000-4-2. In a metal-chassis, earth-referenced product a 1 Mohm || 4.7 nF (2 kV rated) bridge from each shield pour to logic GND with a mechanical bond to chassis at the connector opening is the alternative arrangement; enclosure type is not shown, so both are valid targets.

No filtering elements (common-mode chokes, ferrite beads, series resistors) appear on any signal entering or leaving the enclosure.

13.3.2 J1 — USB Type-C Receptacle (external, consumer-facing)

AI-Assisted — J1 is a 16-pin USB 2.0-only Type-C receptacle and is unambiguously an external hot-plug port subject to IEC 61000-4-2 (±8 kV contact / ±15 kV air, consumer level 4) and to EN 55032 Class B for conducted and radiated emissions.

The data pair is properly protected: USBC_D+ and USBC_D- run from the receptacle contacts A6/B6 and A7/B7 directly to U2, a USBLC6-2SC6, whose I/O1 and I/O2 pins terminate both lines and whose GND pin is on the logic GND net. The ST datasheet rates this device at 15 kV contact / 17 kV air per IEC 61000-4-2 with typically 1.5 pF line capacitance, which is compatible with USB 2.0 high-speed eye requirements. The device is symmetric on the data lines, so no orientation check applies.

CC1 and CC2 are pulled to GND through R4 and R3 respectively, both 5.1K — the correct Rd sink termination for a UFP under USB Type-C R2.5, sized for the default/1.5 A/3.0 A advertisement detection. These two contacts are exposed pins in the receptacle mouth and carry no transient clamp of their own; a low-capacitance clamp on CC1/CC2 is common practice on consumer ports.

VBUS enters at A4/A9/B4/B9 into F1 and then D1, and has no transient clamp at the entry point. SBU1/SBU2 (A8/B8) are unused, consistent with a USB 2.0-only build.

13.3.3 J1 VBUS Path — Fuse and Blocking Diode

AI-Assisted — VBUS passes through F1, a resettable PPTC, into the anode of D1, whose cathode feeds the +5V rail supplying U2, the LF33 LDO U3 and the TP4056 charger U4. D1 is specified as a 1N5819, a 40 V / 1 A Schottky rectifier in DO-41; its reverse standoff is far above the 5.25 V maximum VBUS and its orientation is consistent with a series blocking/steering role, cathode to +5V.

Two points are open. First, F1 carries no hold/trip current value on the schematic. As a protective element its rating must be matched to what it protects — the 1 A rectifier D1 and the Type-C contact current class implied by the 5.1K Rd advertisement. Without a stated hold current there is nothing to compare against, so protection adequacy for the VBUS branch cannot be closed. Second, F1 is assigned a 7.0 mm disc capacitor through-hole footprint; a radial PPTC of matching lead pitch and body diameter would normally be selected, and the footprint choice constrains the trip rating that can actually be fitted.

A PPTC responds in milliseconds and a series Schottky does not clamp, so neither element addresses an IEC 61000-4-2 or IEC 61000-4-5 transient arriving on the VBUS contact. Any clamp sitting on the +5V rail is downstream of both and does not cover the connector contact itself.

13.3.4 J2 — microSD Card Socket (user-accessible media slot)

AI-Assisted — J2 is a push-push microSD socket. Although mounted on the board, a card slot is a user-accessible port: the card and the operator's fingers reach the contacts, so IEC 61000-4-2 air-discharge levels apply at the slot opening even inside a closed enclosure. No ESD array is fitted on CLK, CMD, DAT0 or DAT3/CD, and each of those lines runs directly to an ESP32-S3 GPIO (IO10, IO11, IO9, IO13). The SD contacts are recessed and the card body provides some standoff, so many consumer designs accept this; a 4-channel low-capacitance array would close the exposure if the slot is on an outer wall.

The card is operated in 1-bit SPI mode. R8, R9 and R10 (all 100k) pull SDA, SDCard_MISO and SDCard_CS to +3.3V, matching the SD Physical Layer Specification recommendation for pull-ups on CMD, DAT0 and DAT3. Socket pins 1 (DAT2) and 8 (DAT1) are left open; the SD specification recommends these be pulled high rather than floating to avoid the card entering an unintended state and to prevent floating inputs radiating at the clock rate.

J2 shares SCL with the display U5 and SDA with U5's data input, so the SD bus is a multi-drop stub.

13.4 Observations

AI-Assisted — The SPI clock net SCL is a single driver (U1 IO10) feeding two loads on separate stubs — the microSD socket J2 and the display module U5. A fast-edge clock on a branched net is the dominant radiated-emissions source on a board of this scale, with harmonics falling squarely in the 30 MHz–1 GHz measurement band of EN 55032 / CISPR 32 Class B. No series source-termination resistor is present at the driver. A 22–33 ohm series element placed at U1 on SCL, and matching elements on SDA and SDCard_MISO, slows the edge and damps the stub reflection without affecting functional timing at SD/display SPI rates. The same net topology also feeds display module U5 through a flying lead, which acts as a radiating stub.

The USB data pair reaches U1's native USB peripheral with no common-mode choke fitted between the receptacle and the transceiver. For a 12 Mbit/s or 480 Mbit/s port on a device with an on-board 2.4 GHz radio, a common-mode choke is the standard remedy for common-mode noise coupled onto the cable, which behaves as the dominant radiator during Class B radiated scans; the ESD array U2 does not perform this function.

Decoupling on the connector-facing devices is present: the ESP32-S3 module and the display rail carry bulk plus high-frequency capacitors, and the +5V rail feeding U2 is bulk- and HF-decoupled.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J1	F1 resettable fuse carries no hold/trip current value, so its rating cannot be matched to the 1 A rectifier D1 or to the port current class implied by the 5.1K Rd advertisement; the hold current and the actual +5V branch load must be computed to close this	Medium
13.5.2	J1	F1 is assigned a 7.0 mm disc capacitor through-hole footprint rather than a radial PPTC land pattern, constraining which trip rating can be fitted	Low
13.5.3	J1	Shell contact SH shares the logic GND net, so the shield bonding strategy is not captured as design intent; a dedicated SHIELD_GND_TYPE_C net with dense via stitching to the plane (plastic enclosure) or a 1 Mohm \|\| 4.7 nF 2 kV bridge plus chassis bond (earthed metal chassis) should carry the bond per IEC 61000-4-2	Low
13.5.4	J2	Shell contact SH shares the logic GND net; a dedicated SHIELD_GND_SD net would capture the pour and bond intent for the layout engineer per IEC 61000-4-2 return-path practice	Low
13.5.5	J2, U5	SCL clock driven from U1 IO10 into two stubs (J2 and display U5) with no series source termination; branched fast-edge clock is the leading radiated-emissions risk against EN 55032 / CISPR 32 Class B	Low
13.5.6	J1	VBUS contact (A4/A9/B4/B9) has no transient clamp at the entry point; F1 is a thermal element and D1 is a series blocking device, neither clamps an IEC 61000-4-2 or IEC 61000-4-5 transient	Review
13.5.7	J1	CC1 and CC2 are exposed receptacle contacts with no low-capacitance clamp; USB Type-C R2.5 treats CC as an exposed pin subject to IEC 61000-4-2 discharge	Review
13.5.8	J1	D1 forward-current headroom against the combined +5V load of U2, U3 and U4 not computed; the LDO and charger input currents must be summed against the 1 A rating and the Schottky forward drop budgeted against LF33 dropout	Review
13.5.9	J1	No common-mode choke between the receptacle and the ESP32-S3 native USB pins; common-mode cable current is the dominant radiator in EN 55032 / CISPR 32 Class B radiated scans	Review
13.5.10	J2	User-accessible card slot with CLK, CMD, DAT0 and DAT3/CD running directly to ESP32-S3 GPIO with no ESD array; IEC 61000-4-2 air discharge applies at the slot opening	Review
13.5.11	J2	Socket pins 1 (DAT2) and 8 (DAT1) left floating; the SD Physical Layer Specification recommends these be pulled high to prevent undefined card state and floating-input radiation	Review
13.5.12	J1	D+/D- protected by U2 (USBLC6-2SC6) on the connector side, GND pin on logic ground; 15 kV contact / 17 kV air per ST datasheet, meets IEC 61000-4-2 level 4 for a consumer port	✓
13.5.13	J1	CC1/CC2 terminated to GND by R4 and R3, both 5.1K — correct Rd sink advertisement per USB Type-C Specification R2.5	✓
13.5.14	J1	D1 (1N5819, 40 V / 1 A, DO-41) orientation consistent — anode on the fused VBUS node, cathode on +5V; reverse standoff far exceeds the 5.25 V maximum VBUS of USB 2.0/Type-C	✓
13.5.15	J2	R8, R9, R10 (100k) pull SDA, SDCard_MISO and SDCard_CS to +3.3V, matching the SD Physical Layer Specification pull-up recommendation for CMD, DAT0 and DAT3	✓
13.5.16	J1, J2	Single logic ground domain shared by all connector returns, module grounds and decoupling — appropriate for a plastic-enclosed consumer device where the ground plane is the sole ESD sink	✓
13.5.17	J1, J2	Connector-facing devices decoupled: ESP32-S3 and display on +3.3V with bulk 22uF plus 0.1uF, U2 on +5V with 22uF, 10uF and 0.1uF	✓

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
GND test points	6	Number of GND test points to insert for BON fixture ground connections
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target fault coverage	0%	Insert TPs in priority order until this shorts/opens fault coverage % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable

14.2 Power Rail Test Point Check

Power rails found	4
Rails with TPs	0
Rails without TPs	4

4 power rail(s) need test points in the submitted design.

20 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+3.3V		-	NEEDS TP
+5V		-	NEEDS TP
GND		-	NEEDS TP
Net-(J3-Pin_1)		-	NEEDS TP

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP1	+3.3V	ESP32-game-console.kicad_sch
TP2	+5V	ESP32-game-console.kicad_sch
TP3	GND	ESP32-game-console.kicad_sch
TP4	Net-(J3-Pin_1)	ESP32-game-console.kicad_sch
TP16	GND	ESP32-game-console.kicad_sch
TP17	GND	ESP32-game-console.kicad_sch
TP18	GND	ESP32-game-console.kicad_sch
TP19	GND	ESP32-game-console.kicad_sch
TP20	GND	ESP32-game-console.kicad_sch

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP5	Btn_A	ESP32-game-console.kicad_sch
TP6	Btn_B	ESP32-game-console.kicad_sch
TP7	Btn_DOWN	ESP32-game-console.kicad_sch
TP8	Btn_L	ESP32-game-console.kicad_sch
TP9	Btn_LEFT	ESP32-game-console.kicad_sch
TP10	Btn_R	ESP32-game-console.kicad_sch
TP11	Btn_RIGHT	ESP32-game-console.kicad_sch
TP12	Btn_UP	ESP32-game-console.kicad_sch
TP13	Net-(R13-Pad1)	ESP32-game-console.kicad_sch
TP14	Net-(R5-Pad1)	ESP32-game-console.kicad_sch
TP15	Net-(D3-K)	ESP32-game-console.kicad_sch

14.3 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U1	ESP32-S3-WROOM-1	EN	3	EN has pull-up resistor but no test point at C3_2, C4_2, R1_2, Reset1_2, U1_3
U4	TP4056-42-ESOP8	CE	8	tied to VCC - recommend pull-up resistor and test point

14.4 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.5 Current Test Points

Total test points

No test points found in design.

14.6 Powered-off Testing

No nets with BON test points detected.

14.7 Powered-on Testing

No power rail nets have BON test points.

14.8 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.9 Inspection

Total: 57 components, 176 of 204 pins with inspection coverage.

14.9.1 AOI

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Package_TO_SOT_SMD
SOT-23-6			SOT (Small Outline Transistor)	Footprint	1	6	U2
Capacitor_SMD
C_0805_2012Metric			Chip Passive	Designator	1	2	C5
C_0805_2012Metric_Pad1.18x1.45mm_HandSolder			Chip Passive	Designator	13	26	C1, C10, C11, C12, C13, C14, C2, C3 ...+5 more
Capacitor_THT
C_Disc_D7.0mm_W2.5mm_P5.00mm			Chip Passive	Designator	1	2	F1
Resistor_SMD
R_0805_2012Metric_Pad1.20x1.40mm_HandSolder			Chip Passive	Designator	14	28	R1, R10, R11, R13, R14, R15, R16, R2 ...+6 more
Resistor_THT
R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal			Chip Passive	Designator	2	4	R17, R18
Diode_THT
D_DO-41_SOD81_P10.16mm_Horizontal			SOD (Diode Package)	Footprint	1	2	D1
LED_THT
LED_D3.0mm			SOD (Diode Package)	Designator	1	2	D3
Subtotal: 34 components, 72 pins
Opens only (leads visible, shorts unreliable)
Package_SO
SOIC-16_3.9x9.9mm_P1.27mm			SOIC/SOP	Footprint	1	16	U6
SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias			SOIC/SOP	Footprint	1	9	U4
Package_TO_SOT_SMD
TO-252-2			SOIC/SOP	Designator	1	3	U3
RF_Module
ESP32-S3-WROOM-1U			SOIC/SOP	Designator	1	41	U1
enes
ST7789V			SOIC/SOP	Designator	1	7	U5
Subtotal: 5 components, 76 pins
Presence check (manual verification)
Connector_Card
microSD_HC_Hirose_DM3AT-SF-PEJM5			Connector	Designator	1	9	J2
Connector_Wire
SolderWire-0.75sqmm_1x01_D1.25mm_OD3.5mm			Connector	Designator	2	2	J3, J4
enes
USB_C_Receptacle_HRO_TYPE-C-31-M-12			Connector	Designator	1	17	J1
Subtotal: 4 components, 28 pins

14.9.2 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library model lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
Button_Switch_THT
SW_TH_Tactile_Omron_B3F-100x	Unclassified	Unknown	6	12	SW1, SW10, SW2, SW7, SW8, SW9
TestPoint
TestPoint_2Pads_Pitch5.08mm_Drill1.3mm	Unclassified	Unknown	1	2	LS1
enes
DS1042-07-1-1KRR16008	Unclassified	Unknown	2	4	Boot1, Reset1
L-KLS7-MSK-12C03	Unclassified	Unknown	1	2	SW3
L-KLS7-TS3609-1.8-160-T	Unclassified	Unknown	4	8	SW11, SW12, SW18, SW19
Subtotal: 14 components, 28 pins

14.10 Pin Fault Coverage

Predicted status of each pin for shorts and opens based on DFx options selected in section 13.1.

14.10.1 Fault Coverage Summary

Fault Coverage Summary (204 pins)
Test Method	Opens	Shorts
X-ray (AXI)	0 (0.0%)	0 (0.0%)
Optical (AOI)	0 (0.0%)	0 (0.0%)
Electrical
Powered-off Testing	0 (0.0%)	0 (0.0%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	7 (3.4%)	7 (3.4%)
Total	30 (14.7%)	82 (40.2%)
Total Fault Coverage	30 (14.7%)	82 (40.2%)
No coverage	174 (85.3%)	122 (59.8%)

14.10.2 Uncovered Pins (122)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
R17_2	Net-(U6-SHDN)
R17_1	Sound_SHDN
D1_2	Net-(D1-A)
C14_1	Net-(C13-Pad1)
R9_1	SDCard_MISO
Reset1_2	Net-(U1-EN)
R10_1	SDCard_CS
C3_2	Net-(U1-EN)
U1_3	Net-(U1-EN)
U1_22	Sound_SHDN
U1_8	Sound_MUTE
U1_15
U1_30
U1_20	Screen_CS
U1_38	Btn_RIGHT
U1_39	Btn_LEFT
U1_5	Btn_UP
U1_37
U1_35
U1_7	Screen_DC
U1_10
U1_9	Sound_INR
U1_6	Btn_A
U1_4	Btn_HELPERS
U1_34	Btn_L
U1_14	D+
U1_13	D-
U1_33	Btn_DOWN
U1_21	SDCard_CS
U1_31
U1_27	Net-(U1-IO0)
U1_16
U1_17	SDCard_MISO
U1_24	Btn_R
U1_26
U1_29
U1_23
U1_32	Btn_B
U1_28
U1_25
U1_36
U1_11
U1_12	Screen_RST
R3_1	Net-(J1-CC2)
SW11_2	Btn_L
C12_2	Net-(U6-VREF)
SW3_1	Net-(J3-Pin_1)
SW9_2	Btn_A
R14_1	Btn_HELPERS
SW8_2	Btn_DOWN
U6_3
U6_8	Net-(U6-VREF)
U6_1
U6_16	Net-(U6-ROUT+)
U6_9
U6_10	Net-(U6-INR)
U6_14	Net-(U6-ROUT-)
U6_12	Net-(U6-SHDN)
U6_5	Net-(U6-MUTE)
U6_7
R18_2	Net-(U6-MUTE)
R18_1	Sound_MUTE
U4_9
U4_7	Net-(U4-CHRG)
U4_5	Net-(J3-Pin_1)
U4_6
U4_2	Net-(U4-PROG)
R11_2	Net-(U4-PROG)
R11_1	Net-(R11-Pad1)
C13_2	Net-(U6-INR)
C13_1	Net-(C13-Pad1)
R4_1	Net-(J1-CC1)
J3_1	Net-(J3-Pin_1)
LS1_2	Net-(U6-ROUT+)
LS1_1	Net-(U6-ROUT-)
SW10_2	Btn_B
R15_2	Net-(C13-Pad1)
R15_1	Sound_INR
R7_2	Net-(U4-CHRG)
R7_1	Net-(D3-K)
D3_1	Net-(D3-K)
SW18_2	Net-(R5-Pad1)
F1_2	Net-(D1-A)
F1_1	Net-(J1-VBUS)
U2_1	USBC_D-
U2_6	D-
U2_3	USBC_D+
U2_4	D+
R16_2	Net-(R11-Pad1)
J2_8
J2_1
J2_2	SDCard_CS
J2_7	SDCard_MISO
SW2_2	Btn_RIGHT
R2_2	Net-(U1-IO0)
C9_1	Net-(J3-Pin_1)
Boot1_2	Net-(U1-IO0)
SW7_2	Btn_UP
R5_1	Net-(R5-Pad1)
R5_2	Btn_HELPERS
U5_3	Screen_RST
U5_2	Screen_DC
U5_1	Screen_CS
SW1_2	Btn_LEFT
R1_2	Net-(U1-EN)
R13_2	Btn_HELPERS
R13_1	Net-(R13-Pad1)
SW12_2	Btn_R
J1_B6	USBC_D+
J1_A5	Net-(J1-CC1)
J1_A4	Net-(J1-VBUS)
J1_A6	USBC_D+
J1_B9	Net-(J1-VBUS)
J1_A7	USBC_D-
J1_B4	Net-(J1-VBUS)
J1_B7	USBC_D-
J1_B5	Net-(J1-CC2)
J1_B8
J1_A8
J1_A9	Net-(J1-VBUS)
C4_2	Net-(U1-EN)
SW19_2	Net-(R13-Pad1)

14.10.3 Per-Pin Coverage Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
C1_2	GND	-	●	-	-	-	-
C1_1	+3.3V	-	●	-	-	-	-
R17_2	Net-(U6-SHDN)	-	-	-	-	-	-
R17_1	Sound_SHDN	-	-	-	-	-	-
D1_1	+5V	-	●	-	-	-	-
D1_2	Net-(D1-A)	-	-	-	-	-	-
C5_2	GND	-	●	-	-	-	-
C5_1	+5V	-	●	-	-	-	-
C14_2	GND	●	●	-	-	-	-
C14_1	Net-(C13-Pad1)	-	-	-	-	-	-
R9_2	+3.3V	●	●	-	-	-	-
R9_1	SDCard_MISO	-	-	-	-	-	-
Reset1_1	GND	-	●	-	-	-	-
Reset1_2	Net-(U1-EN)	-	-	-	-	-	-
R10_2	+3.3V	●	●	-	-	-	-
R10_1	SDCard_CS	-	-	-	-	-	-
C3_1	GND	●	●	-	-	-	-
C3_2	Net-(U1-EN)	-	-	-	-	-	-
U1_1	GND	●	●	-	-	-	-
U1_3	Net-(U1-EN)	-	-	-	-	-	-
U1_40	GND	●	●	-	-	-	-
U1_22	Sound_SHDN	-	-	-	-	-	-
U1_8	Sound_MUTE	-	-	-	-	-	-
U1_18	SCL	●	◐	-	-	-	-
U1_15		-	-	-	-	-	-
U1_30		-	-	-	-	-	-
U1_20	Screen_CS	-	-	-	-	-	-
U1_38	Btn_RIGHT	-	-	-	-	-	-
U1_39	Btn_LEFT	-	-	-	-	-	-
U1_5	Btn_UP	-	-	-	-	-	-
U1_37		-	-	-	-	-	-
U1_35		-	-	-	-	-	-
U1_7	Screen_DC	-	-	-	-	-	-
U1_10		-	-	-	-	-	-
U1_9	Sound_INR	-	-	-	-	-	-
U1_6	Btn_A	-	-	-	-	-	-
U1_4	Btn_HELPERS	-	-	-	-	-	-
U1_34	Btn_L	-	-	-	-	-	-
U1_2	+3.3V	●	●	-	-	-	-
U1_14	D+	-	-	-	-	-	-
U1_13	D-	-	-	-	-	-	-
U1_33	Btn_DOWN	-	-	-	-	-	-
U1_21	SDCard_CS	-	-	-	-	-	-
U1_31		-	-	-	-	-	-
U1_19	SDA	●	◐	-	-	-	-
U1_27	Net-(U1-IO0)	-	-	-	-	-	-
U1_16		-	-	-	-	-	-
U1_17	SDCard_MISO	-	-	-	-	-	-
U1_24	Btn_R	-	-	-	-	-	-
U1_26		-	-	-	-	-	-
U1_29		-	-	-	-	-	-
U1_23		-	-	-	-	-	-
U1_32	Btn_B	-	-	-	-	-	-
U1_28		-	-	-	-	-	-
U1_41	GND	●	●	-	-	-	-
U1_25		-	-	-	-	-	-
U1_36		-	-	-	-	-	-
U1_11		-	-	-	-	-	-
U1_12	Screen_RST	-	-	-	-	-	-
R3_1	Net-(J1-CC2)	-	-	-	-	-	-
R3_2	GND	-	●	-	-	-	-
SW11_2	Btn_L	-	-	-	-	-	-
SW11_1	GND	-	●	-	-	-	-
C12_2	Net-(U6-VREF)	-	-	-	-	-	-
C12_1	GND	●	●	-	-	-	-
C11_2	GND	-	●	-	-	-	-
C11_1	+3.3V	-	●	-	-	-	-
SW3_2	+5V	-	●	-	-	-	-
SW3_1	Net-(J3-Pin_1)	-	-	-	-	-	-
SW9_2	Btn_A	-	-	-	-	-	-
SW9_1	GND	-	●	-	-	-	-
R14_2	GND	●	●	-	-	-	-
R14_1	Btn_HELPERS	-	-	-	-	-	-
R8_2	+3.3V	●	●	-	-	-	-
R8_1	SDA	●	◐	-	-	-	-
SW8_2	Btn_DOWN	-	-	-	-	-	-
SW8_1	GND	-	●	-	-	-	-
U6_2	GND	●	●	-	-	-	-
U6_3		-	-	-	-	-	-
U6_4	+3.3V	-	●	-	-	-	-
U6_15	GND	●	●	-	-	-	-
U6_8	Net-(U6-VREF)	-	-	-	-	-	-
U6_1		-	-	-	-	-	-
U6_13	+3.3V	-	●	-	-	-	-
U6_16	Net-(U6-ROUT+)	-	-	-	-	-	-
U6_9		-	-	-	-	-	-
U6_10	Net-(U6-INR)	-	-	-	-	-	-
U6_11	GND	●	●	-	-	-	-
U6_14	Net-(U6-ROUT-)	-	-	-	-	-	-
U6_12	Net-(U6-SHDN)	-	-	-	-	-	-
U6_5	Net-(U6-MUTE)	-	-	-	-	-	-
U6_6	+3.3V	-	●	-	-	-	-
U6_7		-	-	-	-	-	-
C6_2	GND	-	●	-	-	-	-
C6_1	+5V	-	●	-	-	-	-
R18_2	Net-(U6-MUTE)	-	-	-	-	-	-
R18_1	Sound_MUTE	-	-	-	-	-	-
U4_1	GND	●	●	-	-	-	-
U4_9		-	-	-	-	-	-
U4_8	+5V	-	●	-	-	-	-
U4_4	+5V	-	●	-	-	-	-
U4_7	Net-(U4-CHRG)	-	-	-	-	-	-
U4_3	GND	●	●	-	-	-	-
U4_5	Net-(J3-Pin_1)	-	-	-	-	-	-
U4_6		-	-	-	-	-	-
U4_2	Net-(U4-PROG)	-	-	-	-	-	-
R11_2	Net-(U4-PROG)	-	-	-	-	-	-
R11_1	Net-(R11-Pad1)	-	-	-	-	-	-
C13_2	Net-(U6-INR)	-	-	-	-	-	-
C13_1	Net-(C13-Pad1)	-	-	-	-	-	-
R4_1	Net-(J1-CC1)	-	-	-	-	-	-
R4_2	GND	-	●	-	-	-	-
J3_1	Net-(J3-Pin_1)	-	-	-	-	-	-
LS1_2	Net-(U6-ROUT+)	-	-	-	-	-	-
LS1_1	Net-(U6-ROUT-)	-	-	-	-	-	-
SW10_2	Btn_B	-	-	-	-	-	-
SW10_1	GND	-	●	-	-	-	-
R15_2	Net-(C13-Pad1)	-	-	-	-	-	-
R15_1	Sound_INR	-	-	-	-	-	-
R7_2	Net-(U4-CHRG)	-	-	-	-	-	-
R7_1	Net-(D3-K)	-	-	-	-	-	-
U3_2	GND	-	●	-	-	-	-
U3_1	+5V	-	●	-	-	-	-
U3_3	+3.3V	●	●	-	-	-	-
D3_1	Net-(D3-K)	-	-	-	-	-	-
D3_2	+5V	-	●	-	-	-	-
SW18_2	Net-(R5-Pad1)	-	-	-	-	-	-
SW18_1	+3.3V	-	●	-	-	-	-
J4_1	GND	-	●	-	-	-	-
F1_2	Net-(D1-A)	-	-	-	-	-	-
F1_1	Net-(J1-VBUS)	-	-	-	-	-	-
C7_2	GND	-	●	-	-	-	-
C7_1	+3.3V	-	●	-	-	-	-
U2_2	GND	-	●	-	-	-	-
U2_1	USBC_D-	-	-	-	-	-	-
U2_5	+5V	-	●	-	-	-	-
U2_6	D-	-	-	-	-	-	-
U2_3	USBC_D+	-	-	-	-	-	-
U2_4	D+	-	-	-	-	-	-
R16_2	Net-(R11-Pad1)	-	-	-	-	-	-
R16_1	GND	●	●	-	-	-	-
C2_2	+3.3V	-	●	-	-	-	-
C2_1	GND	-	●	-	-	-	-
J2_5	SCL	●	◐	-	-	-	-
J2_8		-	-	-	-	-	-
J2_1		-	-	-	-	-	-
J2_2	SDCard_CS	-	-	-	-	-	-
J2_3	SDA	●	◐	-	-	-	-
J2_6	GND	-	●	-	-	-	-
J2_SH	GND	-	●	-	-	-	-
J2_7	SDCard_MISO	-	-	-	-	-	-
J2_4	+3.3V	-	●	-	-	-	-
SW2_2	Btn_RIGHT	-	-	-	-	-	-
SW2_1	GND	-	●	-	-	-	-
R2_2	Net-(U1-IO0)	-	-	-	-	-	-
R2_1	GND	●	●	-	-	-	-
C9_2	GND	●	●	-	-	-	-
C9_1	Net-(J3-Pin_1)	-	-	-	-	-	-
Boot1_1	GND	-	●	-	-	-	-
Boot1_2	Net-(U1-IO0)	-	-	-	-	-	-
SW7_2	Btn_UP	-	-	-	-	-	-
SW7_1	GND	-	●	-	-	-	-
C10_2	GND	-	●	-	-	-	-
C10_1	+3.3V	-	●	-	-	-	-
R5_1	Net-(R5-Pad1)	-	-	-	-	-	-
R5_2	Btn_HELPERS	-	-	-	-	-	-
U5_7	GND	-	●	-	-	-	-
U5_5	SCL	●	◐	-	-	-	-
U5_4	SDA	●	◐	-	-	-	-
U5_3	Screen_RST	-	-	-	-	-	-
U5_2	Screen_DC	-	-	-	-	-	-
U5_1	Screen_CS	-	-	-	-	-	-
U5_6	+3.3V	●	●	-	-	-	-
SW1_2	Btn_LEFT	-	-	-	-	-	-
SW1_1	GND	-	●	-	-	-	-
R1_2	Net-(U1-EN)	-	-	-	-	-	-
R1_1	+3.3V	●	●	-	-	-	-
R13_2	Btn_HELPERS	-	-	-	-	-	-
R13_1	Net-(R13-Pad1)	-	-	-	-	-	-
C8_2	GND	-	●	-	-	-	-
C8_1	+5V	-	●	-	-	-	-
SW12_2	Btn_R	-	-	-	-	-	-
SW12_1	GND	-	●	-	-	-	-
J1_B6	USBC_D+	-	-	-	-	-	-
J1_SH	GND	-	●	-	-	-	-
J1_A5	Net-(J1-CC1)	-	-	-	-	-	-
J1_A4	Net-(J1-VBUS)	-	-	-	-	-	-
J1_A12	GND	-	●	-	-	-	-
J1_B1	GND	-	●	-	-	-	-
J1_A6	USBC_D+	-	-	-	-	-	-
J1_A1	GND	-	●	-	-	-	-
J1_B9	Net-(J1-VBUS)	-	-	-	-	-	-
J1_A7	USBC_D-	-	-	-	-	-	-
J1_B4	Net-(J1-VBUS)	-	-	-	-	-	-
J1_B7	USBC_D-	-	-	-	-	-	-
J1_B12	GND	-	●	-	-	-	-
J1_B5	Net-(J1-CC2)	-	-	-	-	-	-
J1_B8		-	-	-	-	-	-
J1_A8		-	-	-	-	-	-
J1_A9	Net-(J1-VBUS)	-	-	-	-	-	-
C4_2	Net-(U1-EN)	-	-	-	-	-	-
C4_1	GND	●	●	-	-	-	-
SW19_2	Net-(R13-Pad1)	-	-	-	-	-	-
SW19_1	+3.3V	-	●	-	-	-	-

14.11 PCOLA/SOQ Fault Coverage

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The Combined score is the average of PCOLA and SOQ.

14.11.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	40.4%	0.0%	0.0%	4.5%	0.0%	20.1%	14.7%	0.0%
Optical Inspection (AOI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%	0.0%
Combined	40.4%	0.0%	0.0%	4.5%	0.0%	20.1%	14.7%	0.0%

14.11.2 PCB Device/Pin Count

Devices (PCOLA): 57
Pins (SOQ): 204

14.11.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	8979 / 100,000	9.0%
SOQ	11601 / 100,000	11.6%
Combined	10290 / 100,000	10.3%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	8979 / 100,000	11601 / 100,000
Optical/X-ray Inspection	0 / 100,000	0 / 100,000
Combined (max)	8979 / 100,000	11601 / 100,000

14.11.4 PCOLA (57 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
20%	U5	SPIScreen / ST7789V *	IC	◐	○	○	◐	○	LSSI, Powered_Off
20%	U1	ESP32-S3-WROOM-1 / ESP32-S3-WROOM-1U *	IC	◐	○	○	◐	○	LSSI, Powered_Off
10%	C1	22uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	SW12	R / L-KLS7-TS3609-1.8-160-T *	Switch	◐	○	○	○	○	Powered_Off
10%	D1	1N5819 / D_DO-41_SOD81_P10.16mm_Horizontal *	Diode	◐	○	○	○	○	Powered_Off
10%	C5	0.1uF / C_0805_2012Metric *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C14	1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R9	100k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	Reset1	SW_Push / DS1042-07-1-1KRR16008 *	Other	◐	○	○	○	○	Powered_Off
10%	R10	100k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	C3	0.1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R3	5.1K / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	SW11	L / L-KLS7-TS3609-1.8-160-T *	Switch	◐	○	○	○	○	Powered_Off
10%	C12	0.1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	C11	0.1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	SW3	SW_DPST_x2 / L-KLS7-MSK-12C03 *	Switch	◐	○	○	○	○	Powered_Off
10%	SW9	A / SW_TH_Tactile_Omron_B3F-100x *	Switch	◐	○	○	○	○	Powered_Off
10%	R14	100k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	R8	100k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	SW8	DOWN / SW_TH_Tactile_Omron_B3F-100x *	Switch	◐	○	○	○	○	Powered_Off
10%	U6	PAM8403D / SOIC-16_3.9x9.9mm_P1.27mm *	IC	◐	○	○	○	○	Powered_Off
10%	C6	22uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	SW10	B / SW_TH_Tactile_Omron_B3F-100x *	Switch	◐	○	○	○	○	Powered_Off
10%	U4	TP4056-42-ESOP8 / SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias *	IC	◐	○	○	○	○	Powered_Off
10%	J1	USB_C_Receptacle_USB2.0_16P / USB_C_Receptacle_HRO_TYPE-C-31-M-12 *	Connector	◐	○	○	—	○	Powered_Off
10%	C4	0.1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R4	5.1K / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	SW19	START / L-KLS7-TS3609-1.8-160-T *	Switch	◐	○	○	○	○	Powered_Off
10%	SW1	LEFT / SW_TH_Tactile_Omron_B3F-100x *	Switch	◐	○	○	○	○	Powered_Off
10%	U3	LF33_TO252 / TO-252-2 *	IC	◐	○	○	○	○	Powered_Off
10%	D3	RED / LED_D3.0mm *	Diode	◐	○	○	○	○	Powered_Off
10%	SW18	SELECT / L-KLS7-TS3609-1.8-160-T *	Switch	◐	○	○	○	○	Powered_Off
10%	J4	BAT- / SolderWire-0.75sqmm_1x01_D1.25mm_OD3.5mm *	Connector	◐	○	○	—	○	Powered_Off
10%	C7	22uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	U2	USBLC6-2SC6 / SOT-23-6 *	IC	◐	○	○	○	○	Powered_Off
10%	R16	1K / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	C2	0.1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	J2	Micro_SD_Card / microSD_HC_Hirose_DM3AT-SF-PEJM5 *	Connector	◐	○	○	—	○	Powered_Off
10%	SW2	RIGHT / SW_TH_Tactile_Omron_B3F-100x *	Switch	◐	○	○	○	○	Powered_Off
10%	R2	100k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	C9	10uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	Boot1	SW_Push / DS1042-07-1-1KRR16008 *	Other	◐	○	○	○	○	Powered_Off
10%	SW7	UP / SW_TH_Tactile_Omron_B3F-100x *	Switch	◐	○	○	○	○	Powered_Off
10%	C10	0.1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
10%	R1	100k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	◐	○	○	—	○	Powered_Off
10%	C8	10uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	◐	○	○	—	○	Powered_Off
0%	R17	10k / R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal *	Resistor	○	○	○	—	○
0%	R11	1K / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	○	○	○	—	○
0%	C13	1uF / C_0805_2012Metric_Pad1.18x1.45mm_HandSolder *	Capacitor	○	○	○	—	○
0%	J3	BAT+ / SolderWire-0.75sqmm_1x01_D1.25mm_OD3.5mm *	Connector	○	○	○	—	○
0%	F1	Polyfuse_Small / C_Disc_D7.0mm_W2.5mm_P5.00mm *	Fuse	○	○	○	—	○
0%	R13	1k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	○	○	○	—	○
0%	R15	1k / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	○	○	○	—	○
0%	R7	1K / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	○	○	○	—	○
0%	R5	5.1K / R_0805_2012Metric_Pad1.20x1.40mm_HandSolder *	Resistor	○	○	○	—	○
0%	LS1	Speaker / TestPoint_2Pads_Pitch5.08mm_Drill1.3mm *	Other	○	○	○	○	○
0%	R18	10k / R_Axial_DIN0207_L6.3mm_D2.5mm_P10.16mm_Horizontal *	Resistor	○	○	○	—	○

14.11.5 SOQ (204 pins)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
50%	U5_5	SCL	◐	●	○
50%	R8_2	+3.3V	◐	●	○
50%	U1_41	GND	◐	●	○
50%	R8_1	SDA	◐	●	○
50%	C9_2	GND	◐	●	○
50%	U4_1	GND	◐	●	○
50%	U6_2	GND	◐	●	○
50%	R2_1	GND	◐	●	○
50%	C14_2	GND	◐	●	○
50%	U1_2	+3.3V	◐	●	○
50%	R9_2	+3.3V	◐	●	○
50%	R16_1	GND	◐	●	○
50%	U6_15	GND	◐	●	○
50%	U3_3	+3.3V	◐	●	○
50%	R10_2	+3.3V	◐	●	○
50%	J2_3	SDA	◐	●	○
50%	C3_1	GND	◐	●	○
50%	C12_1	GND	◐	●	○
50%	U1_1	GND	◐	●	○
50%	U1_19	SDA	◐	●	○
50%	U1_40	GND	◐	●	○
50%	J2_5	SCL	◐	●	○
50%	C4_1	GND	◐	●	○
50%	U1_18	SCL	◐	●	○
50%	R1_1	+3.3V	◐	●	○
50%	U4_3	GND	◐	●	○
50%	U5_6	+3.3V	◐	●	○
50%	U6_11	GND	◐	●	○
50%	U5_4	SDA	◐	●	○
50%	R14_2	GND	◐	●	○
17%	C1_2	GND	◐	○	○
17%	C1_1	+3.3V	◐	○	○
17%	C8_2	GND	◐	○	○
17%	C11_2	GND	◐	○	○
17%	D1_1	+5V	◐	○	○
17%	C11_1	+3.3V	◐	○	○
17%	C5_2	GND	◐	○	○
17%	C5_1	+5V	◐	○	○
17%	SW3_2	+5V	◐	○	○
17%	C8_1	+5V	◐	○	○
17%	Reset1_1	GND	◐	○	○
17%	SW12_1	GND	◐	○	○
17%	SW9_1	GND	◐	○	○
17%	J1_SH	GND	◐	○	○
17%	J1_A12	GND	◐	○	○
17%	SW8_1	GND	◐	○	○
17%	J1_B1	GND	◐	○	○
17%	U6_4	+3.3V	◐	○	○
17%	J1_A1	GND	◐	○	○
17%	J1_B12	GND	◐	○	○
17%	U6_13	+3.3V	◐	○	○
17%	U6_6	+3.3V	◐	○	○
17%	C6_2	GND	◐	○	○
17%	C6_1	+5V	◐	○	○
17%	U4_8	+5V	◐	○	○
17%	U4_4	+5V	◐	○	○
17%	SW19_1	+3.3V	◐	○	○
17%	R4_2	GND	◐	○	○
17%	SW10_1	GND	◐	○	○
17%	U3_2	GND	◐	○	○
17%	U3_1	+5V	◐	○	○
17%	D3_2	+5V	◐	○	○
17%	SW18_1	+3.3V	◐	○	○
17%	J4_1	GND	◐	○	○
17%	C7_2	GND	◐	○	○
17%	C7_1	+3.3V	◐	○	○
17%	U2_2	GND	◐	○	○
17%	U2_5	+5V	◐	○	○
17%	C2_2	+3.3V	◐	○	○
17%	C2_1	GND	◐	○	○
17%	J2_6	GND	◐	○	○
17%	J2_SH	GND	◐	○	○
17%	J2_4	+3.3V	◐	○	○
17%	SW2_1	GND	◐	○	○
17%	Boot1_1	GND	◐	○	○
17%	SW7_1	GND	◐	○	○
17%	C10_2	GND	◐	○	○
17%	C10_1	+3.3V	◐	○	○
17%	U5_7	GND	◐	○	○
17%	R3_2	GND	◐	○	○
17%	SW1_1	GND	◐	○	○
17%	SW11_1	GND	◐	○	○
0%	R17_2	Net-(U6-SHDN)	○	○	○
0%	R17_1	Sound_SHDN	○	○	○
0%	D1_2	Net-(D1-A)	○	○	○
0%	C14_1	Net-(C13-Pad1)	○	○	○
0%	R9_1	SDCard_MISO	○	○	○
0%	Reset1_2	Net-(U1-EN)	○	○	○
0%	R10_1	SDCard_CS	○	○	○
0%	C3_2	Net-(U1-EN)	○	○	○
0%	U1_3	Net-(U1-EN)	○	○	○
0%	U1_22	Sound_SHDN	○	○	○
0%	U1_8	Sound_MUTE	○	○	○
0%	U1_15		○	○	○
0%	U1_20	Screen_CS	○	○	○
0%	U1_38	Btn_RIGHT	○	○	○
0%	U1_39	Btn_LEFT	○	○	○
0%	U1_5	Btn_UP	○	○	○
0%	U1_37		○	○	○
0%	U1_35		○	○	○
0%	U1_7	Screen_DC	○	○	○
0%	U1_10		○	○	○
0%	U1_9	Sound_INR	○	○	○
0%	U1_6	Btn_A	○	○	○
0%	U1_4	Btn_HELPERS	○	○	○
0%	U1_34	Btn_L	○	○	○
0%	U1_14	D+	○	○	○
0%	U1_13	D-	○	○	○
0%	U1_33	Btn_DOWN	○	○	○
0%	U1_21	SDCard_CS	○	○	○
0%	U1_31		○	○	○
0%	U1_27	Net-(U1-IO0)	○	○	○
0%	U1_16		○	○	○
0%	U1_17	SDCard_MISO	○	○	○
0%	U1_24	Btn_R	○	○	○
0%	U1_26		○	○	○
0%	U1_29		○	○	○
0%	U1_23		○	○	○
0%	U1_32	Btn_B	○	○	○
0%	U1_28		○	○	○
0%	U1_25		○	○	○
0%	U1_36		○	○	○
0%	U1_11		○	○	○
0%	U1_12	Screen_RST	○	○	○
0%	R3_1	Net-(J1-CC2)	○	○	○
0%	SW11_2	Btn_L	○	○	○
0%	C12_2	Net-(U6-VREF)	○	○	○
0%	SW3_1	Net-(J3-Pin_1)	○	○	○
0%	SW9_2	Btn_A	○	○	○
0%	R14_1	Btn_HELPERS	○	○	○
0%	SW8_2	Btn_DOWN	○	○	○
0%	U6_3		○	○	○
0%	U6_8	Net-(U6-VREF)	○	○	○
0%	U6_1		○	○	○
0%	U2_1	USBC_D-	○	○	○
0%	LS1_2	Net-(U6-ROUT+)	○	○	○
0%	U2_6	D-	○	○	○
0%	U2_3	USBC_D+	○	○	○
0%	U2_4	D+	○	○	○
0%	R16_2	Net-(R11-Pad1)	○	○	○
0%	U4_9		○	○	○
0%	LS1_1	Net-(U6-ROUT-)	○	○	○
0%	SW10_2	Btn_B	○	○	○
0%	R18_1	Sound_MUTE	○	○	○
0%	J2_8		○	○	○
0%	J2_1		○	○	○
0%	J2_2	SDCard_CS	○	○	○
0%	R18_2	Net-(U6-MUTE)	○	○	○
0%	U4_6		○	○	○
0%	R15_2	Net-(C13-Pad1)	○	○	○
0%	J2_7	SDCard_MISO	○	○	○
0%	R15_1	Sound_INR	○	○	○
0%	SW2_2	Btn_RIGHT	○	○	○
0%	R7_2	Net-(U4-CHRG)	○	○	○
0%	R2_2	Net-(U1-IO0)	○	○	○
0%	U6_7		○	○	○
0%	U6_5	Net-(U6-MUTE)	○	○	○
0%	C9_1	Net-(J3-Pin_1)	○	○	○
0%	R7_1	Net-(D3-K)	○	○	○
0%	Boot1_2	Net-(U1-IO0)	○	○	○
0%	SW7_2	Btn_UP	○	○	○
0%	U4_2	Net-(U4-PROG)	○	○	○
0%	R11_2	Net-(U4-PROG)	○	○	○
0%	U4_7	Net-(U4-CHRG)	○	○	○
0%	R5_1	Net-(R5-Pad1)	○	○	○
0%	R5_2	Btn_HELPERS	○	○	○
0%	D3_1	Net-(D3-K)	○	○	○
0%	U6_12	Net-(U6-SHDN)	○	○	○
0%	U6_14	Net-(U6-ROUT-)	○	○	○
0%	U5_3	Screen_RST	○	○	○
0%	U5_2	Screen_DC	○	○	○
0%	U5_1	Screen_CS	○	○	○
0%	U6_10	Net-(U6-INR)	○	○	○
0%	SW1_2	Btn_LEFT	○	○	○
0%	R11_1	Net-(R11-Pad1)	○	○	○
0%	R1_2	Net-(U1-EN)	○	○	○
0%	U6_9		○	○	○
0%	R13_2	Btn_HELPERS	○	○	○
0%	U1_30		○	○	○
0%	SW18_2	Net-(R5-Pad1)	○	○	○
0%	C13_2	Net-(U6-INR)	○	○	○
0%	SW12_2	Btn_R	○	○	○
0%	C13_1	Net-(C13-Pad1)	○	○	○
0%	J1_B6	USBC_D+	○	○	○
0%	F1_2	Net-(D1-A)	○	○	○
0%	J1_A5	Net-(J1-CC1)	○	○	○
0%	J1_A4	Net-(J1-VBUS)	○	○	○
0%	F1_1	Net-(J1-VBUS)	○	○	○
0%	R4_1	Net-(J1-CC1)	○	○	○
0%	J1_A6	USBC_D+	○	○	○
0%	U4_5	Net-(J3-Pin_1)	○	○	○
0%	J1_B9	Net-(J1-VBUS)	○	○	○
0%	J1_A7	USBC_D-	○	○	○
0%	J1_B4	Net-(J1-VBUS)	○	○	○
0%	J1_B7	USBC_D-	○	○	○
0%	J3_1	Net-(J3-Pin_1)	○	○	○
0%	J1_B5	Net-(J1-CC2)	○	○	○
0%	J1_B8		○	○	○
0%	J1_A8		○	○	○
0%	J1_A9	Net-(J1-VBUS)	○	○	○
0%	C4_2	Net-(U1-EN)	○	○	○
0%	U6_16	Net-(U6-ROUT+)	○	○	○
0%	SW19_2	Net-(R13-Pad1)	○	○	○
0%	R13_1	Net-(R13-Pad1)	○	○	○

14.11.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Partial	Partial	Partial	Partial
AXI	—	—	—	—	Partial	Partial	Partial	Partial
JTAG/BSCAN	Full	Full	Full	Partial	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Full	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Partial	Full	—

15 Component Properties

Schematic symbol and library model quality analysis.

15.1 Library Model Grades

Grading schematic library model quality based on pin electrical type definitions:

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Model Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	Part Number	Creator
U2	F	6	0	0	0	0	0	0	0	6	USBLC6-2SC6
U4	C	9	3	2	0	0	2	0	0	2	TP4056-42-ESOP8
U5	C	7	0	7	0	0	0	0	0	0	SPIScreen
U6	C	16	4	6	4	0	0	0	0	2	PAM8403D
U1	B	41	2	1	0	36	0	0	0	2	ESP32-S3-WROOM-1
U3	B	3	3	0	0	0	0	0	0	0	LF33_TO252

15.1.1 Library Quality Summary

Total ICs evaluated	6
Grade A (excellent)	0 (0.0%)
Grade B (good)	2 (33.3%)
Grade C (fair)	3 (50.0%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	1 (16.7%)
OVERALL LIBRARY QUALITY	B (2.75/4.00)

15.2 Component Library Validation

The shared part-number check could not be performed: no part-number property is populated on the passive components. The AI-enriched run resolves part identities and enables this check.

Checking for generic/incomplete library models using statistical patterns.

Library Model Issues (6 models)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
ESP32-S3-WROOM-1	ESP32-S3-WROOM-1	-	U1	41	P:2 Pwr:2 Bi:36 I:1	Pin 1 (GND) at same location as pin 40 (GND); Pin 1 (GND) at same location as pin 41 (GND); Pin 40 (GND) at same location as pin 41 (GND); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Passive, GND=Passive]
LF33_TO252	LF33_TO252	-	U3	3	Pwr:3	No Industry Name property - BOM and procurement tools require this field
PAM8403D	PAM8403D	-	U6	16	P:2 Pwr:4 I:5 O:4 ?:1	Pin 2 (PGND) at same location as pin 15 (PGND); Pin 4 (PVDD) at same location as pin 13 (PVDD); Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [PGND=Passive, VREF=Input]
SPIScreen	SPIScreen	-	U5	7	I:7	No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Input, VCC=Input]
TP4056-42-ESOP8	TP4056-42-ESOP8	-	U4	9	P:2 Pwr:3 I:2 OC:2	No Industry Name property - BOM and procurement tools require this field
USBLC6-2SC6	USBLC6-2SC6	-	U2	6	P:6	All pins marked as Passive - likely generic library model; No Power pins - may use separate power symbol; Only 1 pin type used - no electrical differentiation; Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [GND=Passive, VBUS=Passive]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library model

Power-named pins not typed as Power: Library pin types incomplete

15.3 Shielded Connector Model Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.4 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
J1	USB_C_Receptacle_USB2.0_16P	17	Footprint	enes:USB_C_Receptacle_HRO_TYPE-C-31-M-12
J2	Micro_SD_Card	9	Footprint	Connector_Card:microSD_HC_Hirose_DM3AT-SF-PEJM5
J3	BAT+	1	Footprint	Connector_Wire:SolderWire-0.75sqmm_1x01_D1.25mm_OD3.5mm
J4	BAT-	1	Footprint	Connector_Wire:SolderWire-0.75sqmm_1x01_D1.25mm_OD3.5mm
U1	ESP32-S3-WROOM-1	41	Footprint	RF_Module:ESP32-S3-WROOM-1U
U2	USBLC6-2SC6	6	Footprint	Package_TO_SOT_SMD:SOT-23-6
U3	LF33_TO252	3	Footprint	Package_TO_SOT_SMD:TO-252-2
U4	TP4056-42-ESOP8	9	Footprint	Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm_ThermalVias
U5	SPIScreen	7	Footprint	enes:ST7789V
U6	PAM8403D	16	Footprint	Package_SO:SOIC-16_3.9x9.9mm_P1.27mm

15.5 IC Pin Electrical Properties

Unique IC models	6
Total IC instances	6

IC Library Models
Industry Name	Library Name	RefDes	Notes
ESP32-S3-WROOM-1	ESP32-S3-WROOM-1	U1
LF33_TO252	LF33_TO252	U3
PAM8403D	PAM8403D	U6
SPIScreen	SPIScreen	U5
TP4056-42-ESOP8	TP4056-42-ESOP8	U4
USBLC6-2SC6	USBLC6-2SC6	U2

15.5.1 ESP32-S3-WROOM-1 (ESP32-S3-WROOM-1)

Pin	Pin Name	Electrical
1	GND	Power In
2	3V3	Power In
3	EN	Input
4	IO4	Bidirectional
5	IO5	Bidirectional
6	IO6	Bidirectional
7	IO7	Bidirectional
8	IO15	Bidirectional
9	IO16	Bidirectional
10	IO17	Bidirectional
11	IO18	Bidirectional
12	IO8	Bidirectional
13	USB_D-	Bidirectional
14	USB_D+	Bidirectional
15	IO3	Bidirectional
16	IO46	Bidirectional
17	IO9	Bidirectional
18	IO10	Bidirectional
19	IO11	Bidirectional
20	IO12	Bidirectional
21	IO13	Bidirectional
22	IO14	Bidirectional
23	IO21	Bidirectional
24	IO47	Bidirectional
25	IO48	Bidirectional
26	IO45	Bidirectional
27	IO0	Bidirectional
28	IO35	Bidirectional
29	IO36	Bidirectional
30	IO37	Bidirectional
31	IO38	Bidirectional
32	IO39	Bidirectional
33	IO40	Bidirectional
34	IO41	Bidirectional
35	IO42	Bidirectional
36	RXD0	Bidirectional
37	TXD0	Bidirectional
38	IO2	Bidirectional
39	IO1	Bidirectional
40	GND	Passive
41	GND	Passive

15.5.2 LF33_TO252 (LF33_TO252)

Pin	Pin Name	Electrical
1	VI	Power In
2	GND	Power In
3	VO	Power Out

15.5.3 PAM8403D (PAM8403D)

Pin	Pin Name	Electrical
1	LOUT+	Output
2	PGND	Power In
3	LOUT-	Output
4	PVDD	Power In
5	MUTE	Input
6	VDD	Power In
7	INL	Input
8	VREF	Input
9	NC	Unknown
10	INR	Input
11	GND	Power In
12	SHDN	Input
13	PVDD	Passive
14	ROUT-	Output
15	PGND	Passive
16	ROUT+	Output

15.5.4 SPIScreen (SPIScreen)

Pin	Pin Name	Electrical
1	CS	Input
2	DC	Input
3	RST	Input
4	SDA	Input
5	SCL	Input
6	VCC	Input
7	GND	Input

15.5.5 TP4056-42-ESOP8 (TP4056-42-ESOP8)

Pin	Pin Name	Electrical
1	TEMP	Input
2	PROG	Passive
3	GND	Power In
4	V_CC	Power In
5	BAT	Power Out
6	STDBY	Open Collector
7	CHRG	Open Collector
8	CE	Input
9	EPAD	Passive

15.5.6 USBLC6-2SC6 (USBLC6-2SC6)

Pin	Pin Name	Electrical
1	I/O1	Passive
2	GND	Passive
3	I/O2	Passive
4	I/O2	Passive
5	VBUS	Passive
6	I/O1	Passive