Schematic Lint Engine
Performs advisory checks for localized rule violations and best-practice issues beyond native ERC.
What it checks
- Unconnected pins without NOERC directive
- Unconnected pins with NOERC (audit trail)
- Nets without ERC checks applied
- NC (No Connect) pins that are connected to nets
- Pin connectivity anomalies
Output
Pin Connectivity Report with categorized findings and summary counts.
Library Model Evaluation
Letter-grades the quality of schematic library models to document areas needing improvement, enforce uniformity, and establish a baseline of library quality.
What it evaluates
- IC pin electrical properties (input/output/bidirectional/power)
- Shielded connector model completeness
- Component validation against heuristics
- Footprint assignments
- 3D model availability
- Simulation model availability
Output
Library Quality Summary with letter grades, validation heuristics legend, component-by-component audit, and footprints/models inventory.
Schematic Review Engine
Evaluates cross-sheet and cross-interface consistency, including checks that span multiple sheets and functional boundaries.
What it checks
- ERC exclusions audit
- Unconnected and unmarked pins
- EMC design checks (connector shell grounding)
- LSSI (Low-Speed Serial Interface) usage: I2C, SPI, JTAG, Microwire
- HSSI (High-Speed Serial Interface) usage
- Non-volatile memory interfaces and constraints
- Partial interface detection (nets not fully detected)
Output
Low-Speed Serial Interfaces report, Memory Interface Analysis (with complete and incomplete interface flags), EMC Design Checks report.
Documentation Engine
Generates schematic-derived documentation artifacts suitable for direct inclusion in formal documentation packages.
What it generates
- Connector pinouts with signal names and descriptions
- Mating connector cross-reference with manufacturer and part number
- Signal tables
- Test point tables with physical size
- Component descriptions with PCB footprint assignments
- 3D and simulation model inventory
- Switch documentation and configuration tables
- JTAG connector assignments by target device
Output
Connector Pinouts section, Switch Documentation, component inventory tables—all formatted for inclusion in design documentation or manufacturing packages.
DFT Engine
Reviews schematic-level test intent to support design-for-test planning and boundary scan development.
What it checks
- Test-point coverage across the design
- Power rail testpoints
- Programming interface testpoints (JTAG, SWD)
- Oscillator output-enable testpoints
- Probe access considerations
- Resistors requiring Kelvin test
- Tied-off enables and outputs
- Switch DFT analysis
Output
Physical Testpoint DFT report organized by category: power rails, programming interfaces, oscillator OE, Kelvin resistors. Testpoints indexed by sheet and in aggregate.
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