blackwing-cm5-payload-v1 Design Analysis

Job 9d794808

1 Design Summary

out of 100

Depth of review, as a baseline: 245 verified datasheet parameters applied and 386 automated circuit checks performed. Additional checks that are not as easily quantifiable are also made.

Design Type	Hierarchical (9 sheets)
Total Components	171
Total Pins	775
Total Nets	193
Total Test Points	22
Not Fitted (DNP)	41

Improve your score:

Fix impedance continuity across controlled impedance paths +3
Add the datasheet pins missing from the symbols listed in the Symbol vs Datasheet Pin Table +2
Add test points on power rails +1
Add test points on switch signals +1
Add ordering part numbers to resistors, inductors and capacitors +1
Fix connector shell grounding +1
Use IPC-compliant footprint names +1

Points deducted for open High/Medium AI findings:

2 High, 6 Medium -7

AI findings to review:

pin_connectivity — 5 Review
Power findings — 1 Medium
Power findings — 2 Medium
Power findings — 2 High, 3 Medium, 2 Low, 22 Review
HSSI findings — 3 Low, 11 Review
Functional findings — 2 Medium, 1 Low, 19 Review
EMC/ESD findings — 1 Medium, 8 Review

AI assistance is enabled for this report. Each section marked "AI-Assisted" contains AI-generated engineering observations produced during schematic-phase design review. Findings are based solely on connectivity, component values, and net annotations present in the schematic data at the time of analysis. The AI has no access to PCB layout, routing, thermal data, BOM pricing or availability, assembly constraints, or any information outside the schematic. Findings are observations to investigate, not pass/fail judgments. The absence of a finding for a given device or net does not constitute a clearance. STANDARD MODE — this analysis was produced by the standard model tier.

Based on user-selected TP insertion settings, 15 test point(s) were added and a modified design is available for download. Review the modified schematic and resubmit to update this report.

1.1 Design Overview

AI-Assisted — The Blackwing CM5 payload board is a nine-sheet hierarchical carrier for a Raspberry Pi Compute Module 5. It is organised into USB, power, CM5, M.2, Ethernet, CSI, peripherals and Blackwing-connector sheets.

The module mates through two Amphenol 10164227-1001A1RLF 100-pin board-to-board connectors:

- Module401 carries the low-speed side: GPIO, SD/eMMC, Ethernet MDI, the fan, power inputs and control.
- Module402 carries the high-speed side: PCIe, USB 3, HDMI and the MIPI camera and display lanes.

The design routes 92 differential pairs, split between 90 Ω and 100 Ω classes, plus 22 single-ended 50 Ω signals.

Processing Subsystem

The CM5 is the board's only processor. Three of its boot-time settings are left unstrapped:

- nRPIBOOT is open, so the module boots from its eMMC. Solder jumper J102 can assert the USB boot mode when required.
- EEPROM_nWP is open, so the module's boot EEPROM is not write-protected. Solder jumper J106 is provided to change this.
- SD_VDD_OVERRIDE is left unconnected, which selects 3.3 V SD/eMMC signalling.

Solder jumpers J102 to J106 (normally open) and JP101 to JP105 (normally bridged) give build-time options on signal paths. Two side-actuated tactile switches, SW101 and SW102, provide user input. Status indication comes from three violet LEDs (D101 to D103), a white LED (D104) and a green LED (D105). An SN74AHCT1G04 single inverter (U401) provides logic-level buffering.

The module's real-time clock is backed from the VBAT_RTC rail through a Keystone 2998 coin-cell retainer (BT401) for a 6.8 mm cell. A BAS116 low-leakage diode (D401) is also fitted.

Peripherals and Non-Volatile Storage

A TDK InvenSense IAM-20380 three-axis gyroscope (U801) shares an I2C bus with the U302 regulator. The gyroscope offers ±250 to ±2000 dps full scale and up to 8 kHz output data rate, and runs from a 1.71 V to 3.6 V supply. The bus carries targets at 0x08 and 0x68; 0x68 is the IAM-20380 address with SA0 low (TDK InvenSense datasheet, page 24, Datasheet).

A 2 Mbit Infineon CY15B102Q-SXET F-RAM (U802) sits on a single-chip-select SPI bus from the module. It supports SPI clocks up to 25 MHz, 10^13 read/write cycles and an Automotive-E grade of −40 °C to +125 °C (Infineon datasheet, pages 13 to 15, Datasheet).

External Interfaces

USB enters through a JAE DX07S016JA1R1500 USB Type-C receptacle (J201). VBUS on J201 carries an ESD751 TVS diode (D201).

Data interfaces leave the board through the following connectors:

- J101, a Samtec SFM-120 40-position 1.27 mm receptacle, is the Blackwing system connector. It carries the shared I2C bus, the SPI bus, a UART and six high-speed paths to the module.
- J701 and J702 are Hirose FH12A 22-position 0.5 mm FPC connectors serving the MIPI camera and display lanes. Each has its own dedicated I2C bus from the module.
- J202 and J601 are Molex PicoBlade 4-position headers.

The M.2 sheet carries the module's PCIe link with its own +3V3_M.2 supply. The Ethernet sheet carries the module's four-pair MDI.

Six TI TPD4E1B06 quad low-capacitance protection arrays (U101 to U103, U201, U202, U601) sit on the external signal interfaces. Four M3 plated mounting holes (H101 to H104) complete the mechanical interface.

Power Architecture

Power is managed by two devices.

U301 is a TI TPS2121 2:1 power multiplexer that sources the main +5V rail, which feeds the module's 5 V inputs. Per the Texas Instruments datasheet (source: Tomachie), the TPS2121:

- accepts 2.8 V to 22 V inputs;
- delivers up to 4.5 A;
- has a 56 mΩ typical on-resistance at 5 V and 25 °C;
- switches over in 5 µs typical;
- provides a programmable current limit.

U302 is a TDK FS1603A-5000-AL µPOL module that generates the 5V_POL rail. Per the TDK datasheet (Datasheet, pages 6, 18 and 22), the FS1603A:

- has a factory-preset 5.0 V output;
- delivers 3 A continuous from a 6.75 V to 16 V PVIN range;
- switches at 1.4 MHz;
- holds ±1% accuracy from 25 °C to 125 °C;
- reports input voltage, output voltage, output current and temperature telemetry over I2C.

The remaining rails are:

- +3V3, a 25-pin logic rail;
- +3V3_M.2;
- VCC1;
- VBAT_RTC;
- the input-side rails +5V_USB, +5V_BUS and +VBAT_BUS.

The sources of these rails are not shown in the rail data.

Temperature Ratings

The characterised silicon spans the following ranges:

- CY15B102Q: −40 °C to +125 °C.
- FS1603A: −40 °C to +125 °C operating junction.
- TPS2121: specified to 125 °C.
- IAM-20380: −40 °C to +85 °C. This is the narrowest range among the devices with datasheet data, so it sets the board's verified ambient ceiling.

1.2 Processed Sheets

#	Sheet Name
1	blackwing-cm5-payload-v1.kicad_sch
2	usb.kicad_sch
3	power.kicad_sch
4	cm5.kicad_sch
5	m2.kicad_sch
6	ethernet.kicad_sch
7	csi.kicad_sch
8	peripherals.kicad_sch
9	connectors-blackwing.kicad_sch

1.3 Structured DNP (Not Fitted)

Parts marked do-not-populate at the part level, outside of assembly variants. They remain present in the netlist but are not assembled.

Status	RefDes	Part Type	Value	Footprint
DNP	C103	47u	47u	Blackwing CM5 v1:C-2917
DNP	C104	47u	47u	Blackwing CM5 v1:C-2917
DNP	C106	10u	10u	Blackwing CM5 v1:C-0805-10u
DNP	C107	10u	10u	Blackwing CM5 v1:C-0805-10u
DNP	C109	0.1u	0.1u	Blackwing CM5 v1:C-0603-0.1u
DNP	C110	0.1u	0.1u	Blackwing CM5 v1:C-0603-0.1u
DNP	C302	22u	22u	Capacitor_SMD:C_1210_3225Metric
DNP	C307	1u	1u	Blackwing CM5 v1:C-0603-1u
DNP	C308	22u	22u	Capacitor_SMD:C_1210_3225Metric
DNP	C309	1u	1u	Blackwing CM5 v1:C-0603-1u
DNP	C310	2u2	2u2	Blackwing CM5 v1:C-0603
DNP	C311	22u	22u	Capacitor_SMD:C_1210_3225Metric
DNP	C312	22u	22u	Capacitor_SMD:C_1210_3225Metric
DNP	C501	0.1u	0.1u	Blackwing CM5 v1:C-0603-0.1u
DNP	D106	WE 150060VS55040 LED G	WE 150060VS55040 LED G	Blackwing CM5 v1:WE-150060VS55040-LED-G
DNP	J107	Conn_01x02_Socket	Conn_01x02_Socket	Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical
DNP	J108	Conn_01x02_Socket	Conn_01x02_Socket	Connector_PinHeader_1.27mm:PinHeader_1x02_P1.27mm_Vertical
DNP	J501	Amphenol MDT420M01002 M.2 Key-M	Amphenol MDT420M01002 M.2 Key-M	Blackwing CM5 v1:Amphenol-MDT420M01002-M.2-Key-M-2230-2242
DNP	JP106	SolderJumper_2_Bridged	SolderJumper_2_Bridged	Jumper:SolderJumper-2_P1.3mm_Bridged_RoundedPad1.0x1.5mm
DNP	M501	M2.5 Solder Nut 2230	M2.5 Solder Nut 2230	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
DNP	M502	M2.5 Solder Nut 2242	M2.5 Solder Nut 2242	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
DNP	M503	M2.5 Solder Nut 2260	M2.5 Solder Nut 2260	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
DNP	M504	M2.5 Solder Nut 2260	M2.5 Solder Nut 2260	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
DNP	R106	1k	1k	Blackwing CM5 v1:R-0603-1k
DNP	R313	1k13	1k13	Blackwing CM5 v1:R-0603
DNP	R314	47k	47k	Blackwing CM5 v1:R-0603
DNP	R315	22k	22k	Blackwing CM5 v1:R-0603
DNP	R316	10k	10k	Blackwing CM5 v1:R-0603-10k
DNP	R317	33k	33k	Blackwing CM5 v1:R-0603
DNP	R318	10k	10k	Blackwing CM5 v1:R-0603-10k
DNP	R319	47k	47k	Blackwing CM5 v1:R-0603
DNP	R320	10k	10k	Blackwing CM5 v1:R-0603-10k
DNP	R321	47k	47k	Blackwing CM5 v1:R-0603
DNP	R322	10k	10k	Blackwing CM5 v1:R-0603-10k
DNP	R323	2R7	2R7	Blackwing CM5 v1:R-0603
DNP	R324	100k	100k	Blackwing CM5 v1:R-0603-100k
DNP	R326	47k	47k	Blackwing CM5 v1:R-0603
DNP	R406	10k	10k	Blackwing CM5 v1:R-0603-10k
DNP	U303	TI TPS2121RUX	TI TPS2121RUX	Blackwing CM5 v1:TI-TPS2121
DNP	U304	TDK FS1603A-3300-AL	TDK FS1603A-3300-AL	Blackwing CM5 v1:TDK-FS1606
DNP	U501	Abracon ASEK-32.768KHZ-L-R-T	Abracon ASEK-32.768KHZ-L-R-T	Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm

1.4 Footprint Compliance

Production pick-n-place, AOI, AXI, ATE and Design Quality tools rely on proper descriptions of component footprints.

Footprint Naming	Status
21 SMT footprints do not follow IPC-7351B naming
6 footprints (connectors, specialty) — compliance unknown
1 footprints could not be classified for inspection

2 Component Value Properties

Component values should be in the VALUE property, either as a direct value (e.g. 100nF) or as a formula reference (e.g. =Capacitance). The typed property (Resistance, Capacitance, Inductance, Impedance, etc.) holds the actual electrical value; VALUE should point to it or contain the same data.

Value Property Check
Type	Check	Count	Components	Status
Capacitors	Values in VALUE or Capacitance	22	C101, C113, C102, C114, C115, C303, C306, C304 (+14 more)	✓
Resistors	Values in VALUE or Resistance	37	R102, R105, R101, R103, R104, R402, R404, R403 (+29 more)	✓

2.1 Not a Part Number

RefDes	Status	Issue
C101, C102, C111-C115, C301, C303, C304, C701, C702, C801-C806, R101-R105, R107-R118, R301-R312, R325, R401-R404, R801-R803		We looked across all the properties provided in the design for a Manufacturer's Part Number and could not find one which would lead to a datasheet. We did deterministic checks and AI checks, and nothing was identified. You can proceed with an AI review but this part will not be analyzed.

2.2 Part Number vs Stated Values

Each passive states its electrical facts twice: in the properties the designer set, and encoded inside the MANUFACTURER part number. This check decodes the manufacturer part number and compares the two. A distributor catalogue number is a different thing and cannot be used here - an LCSC C-number or a Digi-Key -ND number identifies a stock item, it encodes no capacitance, voltage or tolerance, so there is nothing in it to check against. Where the two readings disagree both are shown and neither is assumed correct: if VALUE is wrong the analysis used the wrong number, and if the part number is wrong the BOM orders the wrong part. Only the designer knows which field is authoritative. Parts whose numbering scheme is not recognized are reported as not checked rather than passed.

55 of 59 fitted resistor/inductor/capacitor part(s) carry no ordering part number: C101, C102, C111, C112, C113, C114, C115, C301, C303, C304, C701, C702, C801, C802, C803, C804, C805, C806, R101, R102 (+35 more). Without a part number the BOM cannot state what to buy, and none of the part-number cross-checks in this section can run for these parts. Add a manufacturer part number to each part in the library. AC parameters are not available for AI analysis or PDN Analysis as the part numbers and datasheets are unknown.

Part Number	Decoded from Part Number	Stated on Schematic	What Differs	Count	Components	Status
GCJ32EC71E226KE02L Manufacturer PN / Murata	22uF 25V +/-10% 1210	22u 25V 10%: C305, C306	Nothing - all stated values agree	2	C305, C306	✓ Match
T591D476M025ATE060 Manufacturer PN / KEMET (tantalum)	47uF 25V +/-20%	47u 25V 20%: C105, C108	Nothing - all stated values agree	2	C105, C108	✓ Match

2.3 Capacitor Derating Check

Derating profile	ECSS-Q-ST-30-11C
Maximum ambient	85 °C
Checks performed	19
Over-specified	14

A capacitor is checked here when the comparison can be made without an operating-point calculation: it has two terminals, sits between a power rail and ground so the rail's resolved voltage is the voltage across it, and states a voltage rating - a Voltage property, or a rating decoded from the part number. Every other derating check - for capacitors and for every other part class - is applied by the AI analysis within its report sections.

Derating applied: 40% (capacitor_voltage_pct = 60)

Status key: ↓ = Over-specified ✓ = Adequately rated

Derating is how much is taken off a part's catalogue rating. What remains is the most of that rating the part may be worked at - a 16 V capacitor derated 15% has a maximum permitted value of 13.6 V - and the part is correctly sized when the voltage its position applies stays within it, taken at the worst case of the rail's stated range. This judges DC working voltage only; ripple and switching transients are not included in the compared value.

Review: 14 part(s) carry a voltage rating far higher than needed. A lower-cost part can be used, down to the voltage indicated.

Part Voltage Rating vs Design Voltage
RefDes	Net Name	Rated Voltage	Max Permitted	Design Voltage	% of Rating	Sufficient Rating	Status
C101	+5V	25.00 V	15.00 V	5.00 V	20.0%	16.00 V	↓
C102	+5V	25.00 V	15.00 V	5.00 V	20.0%	16.00 V	↓
C306	5V_POL	25.00 V	15.00 V	5.00 V	20.0%	16.00 V	↓
C305	5V_POL	25.00 V	15.00 V	5.00 V	20.0%	16.00 V	↓
C113	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C114	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C115	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C701	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C702	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C801	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C806	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C805	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C804	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C802	+3V3	25.00 V	15.00 V	3.30 V	13.2%	16.00 V	↓
C304	+VBAT_BUS	25.00 V	15.00 V	8.40 V	33.6%		✓
C112	+VBAT_BUS	25.00 V	15.00 V	8.40 V	33.6%		✓
C108	+VBAT_BUS	25.00 V	15.00 V	8.40 V	33.6%		✓
C105	+VBAT_BUS	25.00 V	15.00 V	8.40 V	33.6%		✓
C111	+VBAT_BUS	25.00 V	15.00 V	8.40 V	33.6%		✓

Derating Settings Used in This Analysis
Parameter	Value	Source	Applied
capacitor_voltage_pct	40% (60)	ECSS-Q-ST-30-11C Rev.2 Table 6-1 (to 85 C)	Checked in the table above (19 part(s))
capacitor_aluminum_voltage_pct	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - no aluminium family	Not applied - the AI is not given this parameter
capacitor_tantalum_mno2_voltage_pct	40% (60)	ECSS-Q-ST-30-11C Rev.2 Table 6-2	Applied by the AI analysis where the rating is in evidence
capacitor_tantalum_polymer_voltage_pct	40% (60)	ECSS-Q-ST-30-11C Rev.2 Table 6-2 with 6.3.3c	Applied by the AI analysis where the rating is in evidence
capacitor_ripple_current_pct	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - no numeric factor (6.2.1d)	Not applied - the AI is not given this parameter
capacitor_temperature_margin_c	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - handled inside the voltage curve	Not applied - the AI is not given this parameter
capacitor_aluminum_temperature_margin_c	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - no aluminium family	Not applied - the AI is not given this parameter
resistor_power_pct	50% (50)	ECSS-Q-ST-30-11C Rev.2 Tables 6-25..6-33 most styles	Applied by the AI analysis where the rating is in evidence
resistor_working_voltage_pct	20% (80)	ECSS-Q-ST-30-11C Rev.2 all types	Applied by the AI analysis where the rating is in evidence
resistor_temperature_margin_c	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - power-to-zero curve	Not applied - the AI is not given this parameter
diode_reverse_voltage_pct	25% (75)	ECSS-Q-ST-30-11C Rev.2 Table 6-13	Applied by the AI analysis where the rating is in evidence
diode_average_forward_current_pct	25% (75)	ECSS-Q-ST-30-11C Rev.2 Table 6-13	Applied by the AI analysis where the rating is in evidence
diode_power_dissipation_pct	50% (50)	ECSS-Q-ST-30-11C Rev.2 where PD is defined	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_margin_c	40 °C	ECSS-Q-ST-30-11C Rev.2 Tj max - 40 C	Applied by the AI analysis where the rating is in evidence
diode_junction_temperature_cap_c	110 °C	ECSS-Q-ST-30-11C Rev.2 110 C	Applied by the AI analysis where the rating is in evidence
regulator_input_voltage_pct	10% (90)	ECSS-Q-ST-30-11C Rev.2 Table 6-21 linear (90 % of max rated)	Applied by the AI analysis where the rating is in evidence
regulator_output_current_pct	20% (80)	ECSS-Q-ST-30-11C Rev.2 Table 6-21	Applied by the AI analysis where the rating is in evidence
regulator_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - Tj-controlled no PD row	Not applied - the AI is not given this parameter
regulator_junction_temperature_margin_c	40 °C	ECSS-Q-ST-30-11C Rev.2 Tj max - 40 C	Applied by the AI analysis where the rating is in evidence
regulator_junction_temperature_cap_c	110 °C	ECSS-Q-ST-30-11C Rev.2 110 C	Applied by the AI analysis where the rating is in evidence
ic_output_current_pct	20% (80)	ECSS-Q-ST-30-11C Rev.2 Table 6-21	Applied by the AI analysis where the rating is in evidence
ic_power_dissipation_pct	Not derated by this scheme - the manufacturer's rating is the limit	ECSS-Q-ST-30-11C Rev.2 - no PD row (MMIC only)	Not applied - the AI is not given this parameter
ic_junction_temperature_margin_c	40 °C	ECSS-Q-ST-30-11C Rev.2 Tj max - 40 C	Applied by the AI analysis where the rating is in evidence
ic_junction_temperature_cap_c	110 °C	ECSS-Q-ST-30-11C Rev.2 110 C	Applied by the AI analysis where the rating is in evidence
connector_current_per_contact_pct	50% (50)	ECSS-Q-ST-30-11C Rev.2 Table 6-10	Applied by the AI analysis where the rating is in evidence
connector_voltage_pct	25% (75)	ECSS-Q-ST-30-11C Rev.2 75 % of rated working (or 25 % DWV)	Applied by the AI analysis where the rating is in evidence
connector_temperature_margin_c	30 °C	ECSS-Q-ST-30-11C Rev.2 30 C	Applied by the AI analysis where the rating is in evidence
tvs_junction_temperature_margin_c	40 °C	ECSS-Q-ST-30-11C Rev.2 as diodes	Applied by the AI analysis where the rating is in evidence
tvs_junction_temperature_cap_c	110 °C	ECSS-Q-ST-30-11C Rev.2 as diodes	Applied by the AI analysis where the rating is in evidence
switch_contact_current_resistive_pct	25% (75)	ECSS-Q-ST-30-11C Rev.2 (shared relay table)	Applied by the AI analysis where the rating is in evidence

2.4 Strap Pins Missing from Symbol

Each device's reset-time strap pins were looked up in its datasheet's pin table by number. A strap pin the datasheet numbers but the symbol does not carry cannot be wired on this board or checked against the datasheet, so the device may not start as intended. The symbol needs the pin.

	Observation	Status
RefDesModule401 Part NumberCM5 PinUSB_OTG_ID	The datasheet samples USB_OTG_ID (pin 101) at reset to set USB 2.0 OTG role (host or device); the symbol has no pin 101	High

2.5 Part Lifecycle and Silicon Errata

Status as found on the manufacturer's website by the AI enrichment run, on the date shown; the page read is linked. Silicon errata: whether the manufacturer publishes an errata sheet for the part - its presence only. No errata document is read or analysed, and no action is implied by its existence.

Item	Lifecycle	Silicon errata
C103, C104, C105, C108 (T591D476M025ATE060)	There isn't a life-cycle marking on the datasheet obtained 2026-11-02	—
C106, C107 (GRM21BZ71E106KE15L)	In Production, as of 2026-11-02	—
C302, C305, C306, C308, C311, C312 (GCJ32EC71E226KE02L)	In Production, as of 2026-11-02	—
C307, C309 (CL10B105KA8NNNC)	There isn't a life-cycle marking on the datasheet obtained 2026-10-26	—
D101, D102, D103 (XZFRS53FVF-1)	There isn't a life-cycle marking on the datasheet obtained 2026-11-02	—
D104 (150060WS75000)	There is a Valid marking on the datasheet obtained 2026-11-02	—
D105 (150060VS55040)	There is a Valid marking on the datasheet obtained 2026-11-02	—
D201 (ESD751DYAR)	ACTIVE, as of 2026-11-02	—
D401 (BAS116LT1G)	Active, as of 2026-11-02	—
SW101, SW102 (KMS223GP LFG)	Active, as of 2026-11-02	—
U101, U102, U103, U201, U202, U601 (TPD4E1B06DRLR)	Active Production, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02
U301, U303 (TPS2121RUXR)	ACTIVE, as of 2026-10-18	None found on the manufacturer's website, as of 2026-10-18
U302 (FS1603A-5000-AL)	Production, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02
U304 (FS1603A-3300-AL)	Production, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02
U401 (SN74AHCT1G04DBVR)	ACTIVE, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02
U501 (ASEK-32.768KHZ-L-R-T)	Active, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02
U801 (IAM-20380)	Active, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02
U802 (CY15B102Q-SXET)	Active and preferred, as of 2026-11-02	None found on the manufacturer's website, as of 2026-11-02

3 Pin Connectivity Report

3.1 Unconnected Pins

Unconnected pins that are not marked NO_ERC.

77 unconnected pin(s) found:

Refdes_Pin	Pin Function	Pin Property	Device Type	Net Name
D401_1	A	Passive	BAS116	Net-(D401-A)
Module401_3	Ethernet_Pair3_P	Passive	CM5 GPIO	ETH_PI.TRD3_P
Module401_5	Ethernet_Pair3_N	Passive	CM5 GPIO	ETH_PI.TRD3_N
Module401_9	Ethernet_Pair2_N	Passive	CM5 GPIO	ETH_PI.TRD2_N
Module401_11	Ethernet_Pair2_P	Passive	CM5 GPIO	ETH_PI.TRD2_P
Module401_16	FAN_TACHO	Input	CM5 GPIO	FAN_TACHO
Module401_17	Ethernet_nLED2(3.3v)	Output	CM5 GPIO	LED_ETH_1G
Module401_18	Ethernet_SYNC_OUT(3.3v)	Input	CM5 GPIO	SYNC_OUT
Module401_19	FAN_PWM	Output	CM5 GPIO	FAN_PWM
Module401_24	GPIO26	Passive	CM5 GPIO	GPIO26
Module401_28	GPIO13	Passive	CM5 GPIO	GPIO13
Module401_31	GPIO12	Passive	CM5 GPIO	GPIO12
Module401_34	GPIO5	Passive	CM5 GPIO	GPIO5
Module401_48	GPIO27	Passive	CM5 GPIO	GPIO27
Module401_54	GPIO4	Passive	CM5 GPIO	GPIO4
Module401_57	SD_CLK	Passive	CM5 GPIO	SD_CLK
Module401_61	SD_DAT3	Passive	CM5 GPIO	SD_DAT3
Module401_62	SD_CMD	Passive	CM5 GPIO	SD_CMD
Module401_63	SD_DAT0	Passive	CM5 GPIO	SD_DAT0
Module401_64	SD_DAT5	Passive	CM5 GPIO	SD_DAT5
Module401_67	SD_DAT1	Passive	CM5 GPIO	SD_DAT1
Module401_68	SD_DAT4	Passive	CM5 GPIO	SD_DAT4
Module401_69	SD_DAT2	Passive	CM5 GPIO	SD_DAT2
Module401_70	SD_DAT7	Passive	CM5 GPIO	SD_DAT7
Module401_72	SD_DAT6	Passive	CM5 GPIO	SD_DAT6
Module401_73	SD_VDD_Override	Input	CM5 GPIO	SD_VDD_Override
Module401_75	SD_PWR_ON	Output	CM5 GPIO	SD_PWR_ON
Module402_102	PCIe_nCLKREQ	Input	CM5 HSS	PCIE_PI.nCLKREQ
Module402_104	PCIE_nWAKE	Input	CM5 HSS	PCIE_PI.nWAKE
Module402_106	PCIE_PWR_EN	Output	CM5 HSS	M.2_PWR_EN
Module402_109	PCIe_nRST	Output	CM5 HSS	PCIE_PI.nRST
Module402_110	PCIe_CLK_P	Output	CM5 HSS	PCIE_PI.CLK_P
Module402_111	VBUS_EN	Output	CM5 HSS	VBUS_EN
Module402_112	PCIe_CLK_N	Output	CM5 HSS	PCIE_PI.CLK_N
Module402_116	PCIe_RX_P	Input	CM5 HSS	PCIE_PI.RX_P
Module402_118	PCIe_RX_N	Input	CM5 HSS	PCIE_PI.RX_N
Module402_122	PCIe_TX_P	Output	CM5 HSS	PCIE_PI.TX_P
Module402_124	PCIe_TX_N	Output	CM5 HSS	PCIE_PI.TX_N
Module402_128	USB3-0-RX_N	Input	CM5 HSS	USB3-0-RX_N
Module402_130	USB3-0-RX_P	Input	CM5 HSS	USB3-0-RX_P
Module402_140	USB3-0-TX_N	Output	CM5 HSS	USB3-0-TX_N
Module402_142	USB3-0-TX_P	Output	CM5 HSS	USB3-0-TX_P
Module402_143	HDMI1_HOTPLUG	Input	CM5 HSS	HDMI1_HOTPLUG
Module402_145	HDMI1_SDA	Bidirectional	CM5 HSS	HDMI1_SDA
Module402_146	HDMI1_TX2_P	Output	CM5 HSS	HDMI1_D2_P
Module402_147	HDMI1_SCL	Open Collector	CM5 HSS	HDMI1_SCL
Module402_148	HDMI1_TX2_N	Output	CM5 HSS	HDMI1_D2_N
Module402_149	HDMI1_CEC	Open Collector	CM5 HSS	HDMI1_CEC
Module402_151	HDMI0_CEC	Open Collector	CM5 HSS	HDMI_PI.CEC
Module402_152	HDMI1_TX1_P	Output	CM5 HSS	HDMI1_D1_P
Module402_153	HDMI0_HOTPLUG	Input	CM5 HSS	HDMI_PI.HOTPLUG
Module402_154	HDMI1_TX1_N	Output	CM5 HSS	HDMI1_D1_N
Module402_157	USB3-1-RX_N	Input	CM5 HSS	USB3-1-RX_N
Module402_158	HDMI1_TX0_P	Output	CM5 HSS	HDMI1_D0_P
Module402_159	USB3-1-RX_P	Input	CM5 HSS	USB3-1-RX_P
Module402_160	HDMI1_TX0_N	Output	CM5 HSS	HDMI1_D0_N
Module402_163	USB3-1-D_P	Passive	CM5 HSS	USB3-1-D_P
Module402_164	HDMI1_CLK_P	Output	CM5 HSS	HDMI1_CK_P
Module402_165	USB3-1-D_N	Passive	CM5 HSS	USB3-1-D_N
Module402_166	HDMI1_CLK_N	Output	CM5 HSS	HDMI1_CK_N
Module402_169	USB3-1-TX_N	Output	CM5 HSS	USB3-1-TX_N
Module402_170	HDMI0_TX2_P	Output	CM5 HSS	HDMI_PI.D2_P
Module402_171	USB3-1-TX_P	Output	CM5 HSS	USB3-1-TX_P
Module402_172	HDMI0_TX2_N	Output	CM5 HSS	HDMI_PI.D2_N
Module402_176	HDMI0_TX1_P	Output	CM5 HSS	HDMI_PI.D1_P
Module402_178	HDMI0_TX1_N	Output	CM5 HSS	HDMI_PI.D1_N
Module402_182	HDMI0_TX0_P	Output	CM5 HSS	HDMI_PI.D0_P
Module402_184	HDMI0_TX0_N	Output	CM5 HSS	HDMI_PI.D0_N
Module402_188	HDMI0_CLK_P	Output	CM5 HSS	HDMI_PI.CK_P
Module402_190	HDMI0_CLK_N	Output	CM5 HSS	HDMI_PI.CK_N
Module402_199	HDMI0_SDA	Bidirectional	CM5 HSS	HDMI_PI.SDA
Module402_200	HDMI0_SCL	Open Collector	CM5 HSS	HDMI_PI.SCL
TP102_1	1	Passive	+3V3_M.2	+3V3_M.2
TP107_1	1	Passive	PMUX2_ST	PMUX2_ST
TP108_1	1	Passive	I2C_4_SCL	I2C_4_SCL
TP109_1	1	Passive	I2C_4_SDA	I2C_4_SDA
TP304_1	1	Passive	VSW2	Net-(U304-VSW)

3.2 Implied/Hidden Net Connections

Pins with implied net connections not visible on the schematic. Includes Altium HiddenNetName library parameters and KiCad hidden pins of any electrical type stacked behind visible pins in the symbol.

Implied Net Connections
Component	Type	Pin	Net	Status
SW101	CK KMS223GP LFG	3 (3)	GND	Hidden pin not visible on schematic
SW101	CK KMS223GP LFG	4 (4)	GND	Hidden pin not visible on schematic
SW101	CK KMS223GP LFG	5 (5)	PWR_BUT	Hidden pin not visible on schematic
SW102	CK KMS223GP LFG	3 (3)	GND	Hidden pin not visible on schematic
SW102	CK KMS223GP LFG	4 (4)	GND	Hidden pin not visible on schematic
SW102	CK KMS223GP LFG	5 (5)	RESET	Hidden pin not visible on schematic
U301	TI TPS2121RUX	1_1 (OUT__1)	+5V	Hidden pin not visible on schematic
U301	TI TPS2121RUX	8 (OUT__2)	+5V	Hidden pin not visible on schematic
U301	TI TPS2121RUX	8_1 (OUT__3)	+5V	Hidden pin not visible on schematic
U303	TI TPS2121RUX	1_1 (OUT__1)	5V_MUX	Hidden pin not visible on schematic
U303	TI TPS2121RUX	8 (OUT__2)	5V_MUX	Hidden pin not visible on schematic
U303	TI TPS2121RUX	8_1 (OUT__3)	5V_MUX	Hidden pin not visible on schematic
J201	USB-C	A9 (VBUS)	+5V_USB	Hidden pin not visible on schematic
J201	USB-C	B1 (GND)	GND	Hidden pin not visible on schematic
J201	USB-C	A12 (GND)	GND	Hidden pin not visible on schematic
J201	USB-C	B4 (VBUS)	+5V_USB	Hidden pin not visible on schematic
J201	USB-C	B9 (VBUS)	+5V_USB	Hidden pin not visible on schematic
J201	USB-C	B12 (GND)	GND	Hidden pin not visible on schematic

3.3 Open-Collector Pull-up Audit

Examined 7 candidate pin(s) on 6 net(s). 5 off-board (mating assembly).

Finding	Recommended Action	Severity
Open-collector / open-drain outputs need an external pull-up resistor to a power rail to function. This audit lists pins where a pull-up appears to be missing or where the pin type may not match the schematic library.
Module401_21 (LED_nACT) on LED_PI_ACT Module401 (CM5 GPIO) Amphenol 10164227-1001A1RLF off-board via JP104 · library: Open Collector	Likely pulled up on the mating assembly. Document the dependency.	Review
Module402_151 (HDMI0_CEC) on HDMI_PI.CEC Module402 (CM5 HSS) Amphenol 10164227-1001A1RLF off-board via Module402 · library: Open Collector	Likely pulled up on the mating assembly. Document the dependency.	Review
Module402_147 (HDMI1_SCL) on HDMI1_SCL Module402 (CM5 HSS) Amphenol 10164227-1001A1RLF off-board via Module402 · library: Open Collector	Likely pulled up on the mating assembly. Document the dependency.	Review
Module402_149 (HDMI1_CEC) on HDMI1_CEC Module402 (CM5 HSS) Amphenol 10164227-1001A1RLF off-board via Module402 · library: Open Collector	Likely pulled up on the mating assembly. Document the dependency.	Review
Module402_200 (HDMI0_SCL) on HDMI_PI.SCL Module402 (CM5 HSS) Amphenol 10164227-1001A1RLF off-board via Module402 · library: Open Collector	Likely pulled up on the mating assembly. Document the dependency.	Review
U304_2 (PG) on (unconnected) U304 (TDK FS1603A-3300-AL) Non-Isolated PoL Module, Digital DC DC Converter 1 Output 3.3V 3A 4.5V - 16V Input on-board only · library: Output (name suggests OC)	Power-good output not used: nothing else is connected to it, so it does not need a pull-up or a test point.	Information

3.4 Diode Polarity / Orientation

Diode	Connections	Orientation	Severity
Diode polarity and orientation are read from the schematic. IPC-7351B (surface mount) / IPC-7251 (through-hole) Zero Component Orientation (ZCO) requires pin 1, the cathode, on the left with the footprint at zero rotation. Tomachie calls out symbols that do not meet ZCO because the PCB layout may have an error, assembly may insert the part backwards, initial ATE test generation from a netlist of only pins 1 and 2 will fail, or a novice may wrongly indict a correct part — consistency is the least-expensive path for everyone who handles the PCB.
D401 BAS116LT1G array · multi-pin	Pin 1 (A): Net-(D401-A) Pin 2 (NC): - Pin 3 (K): VBAT_RTC	3-pin diode package will need to be checked against the datasheet in one of the AI enrichment sections.	Information
D201 ESD751DYAR bidirectional · symbol_graphic	Pin 1 (A1): GND Pin 2 (A2): +5V_USB	Bidirectional (symmetric) — no single anode/cathode, so there is no orientation to check.	Information

3.5 Polarized Capacitor Orientation

Capacitor	Connections	Polarity	Severity
Aluminum-electrolytic, tantalum, and polymer capacitors are polarized: pin 1 is the positive (+) terminal. IPC-7351B (surface-mount) and IPC-7251 (through-hole) fix pin 1 as positive in the land pattern — the square pad, the silkscreen "+", and (through-hole) the notch or plated hole all mark it. Footprint selection, pick-and-place assembly, and in-circuit / flying-probe test all reference pin 1, so the schematic symbol's pin 1 MUST match: pin 1 = positive. If a symbol instead draws "+" on pin 2, pin 1 — the footprint's positive pad — is wired to the wrong net and the assembled part sits backwards. (The part's own body marking is not a reliable guide: aluminum electrolytics stripe the NEGATIVE lead, tantalums mark the POSITIVE — so the land-pattern pin 1 = positive is the fixed reference.) Each polarized capacitor below is checked against this convention.
C108 T591D476M025ATE060	Pin 1 (+): +VBAT_BUS Pin 2: GND
C103 T591D476M025ATE060	Pin 1 (+): — Pin 2: —	Not judged: both terminals are on signal nets, so the direction depends on the circuit's DC levels. Check it against them.	Information
C105 T591D476M025ATE060	Pin 1 (+): +VBAT_BUS Pin 2: GND
C104 T591D476M025ATE060	Pin 1 (+): — Pin 2: —	Not judged: both terminals are on signal nets, so the direction depends on the circuit's DC levels. Check it against them.	Information

3.6 Checks Not Performed

Items this report did not check, with the reason. None of these is a finding against the design - an item that was not checked says nothing about it either way.

Note 3: The figure these checks need was not taken from the part's datasheet, so they were not performed. This is a limitation of the analysis, not a finding on the design.

Checks the AI review could not perform are listed at Review severity in each AI section's Findings table, each naming the input that was missing.

Item	Not checked	Notes
Part Number vs Stated Values	55 of 59 fitted resistor/inductor/capacitor part(s) carry no ordering part number: C101, C102, C111, C112, C113, C114, C115, C301, C303, C304, C701, C702, .... Without a part number the BOM cannot state what to buy, and none of the part-number cross-checks in this section can run for these parts. Add a manufacturer part number to each part in the library. AC parameters are not available for AI analysis or PDN Analysis as the part numbers and datasheets are unknown.
Capacitors and resistors (datasheets and parameter curves)	Datasheets for capacitors and resistors, and the parameter curves they carry (ripple current, derating against temperature, DC bias, a jumper's temperature rise), are obtained on the premium tier only. This standard-tier run reads a datasheet already on file and otherwise states no rating for these parts. The exception is a capacitor on a regulator's input or output rail: this tier obtains its datasheet and curves as well.
U301 (TPS2121RUXR)	40 °C margin between predicted junction temperature and maximum junction temperature under the ECSS-Q-ST-30-11C derating (maximum junction temperature (Tj max))	See note 3
C305, C306 (GCJ32EC71E226KE02L)	Ripple self-heating read from the 'Temp.Rise from ripple Characteristics' curve at U302's 1.4 MHz switching frequency (U302 output ripple current (internal inductor ripple))	See note 3
Module402 (10164227-1001A1RLF (CM5))	Bandwidth of the camera FPC path (J701, J702) against the CSI-2 lane rate (MIPI0/MIPI1 D-PHY maximum lane data rate)	See note 3
U302 (FS1603A-5000-AL)	Clamp level of U103 on I2C_3_SCL and I2C_3_SDA against the U302 SCL and SDA pin rating (SCL/SDA pin absolute maximum voltage)	See note 3

3.7 Summary

Total NO_ERC markers in design	101
Pins needing attention (warnings)	77
Pins for information only	0

4 Power Overview

Power rails	9
Power management sources identified	4

Analysis of passive component footprint suitability, voltage ratings, and power dissipation is not performed in this revision.

Power architecture overview. For test point coverage, see Design-for-Test section.

4.1 Values Entered for This Analysis

These values were entered by the designer for this analysis; they are not read from the schematic. Every check in this report that needs one of them uses the figure shown here.

Kind	Entered for	Value entered
Power input	+5V_USB	5 V nominal, 4.75-5.5 V operating
Power input	+VBAT_BUS	7.4 V nominal, 7-8.4 V operating
Power input	VBAT_RTC	3 V nominal, 2.5-3.3 V operating

4.2 Power Rail Analysis

Power Rails
Rail	Voltage	Source	Consumers
+VBAT_BUS	7.40V	J101 External	U302 (FS1603A-5000-AL)
+5V	5.00V	U301 TPS2121RUXR	Module401 (CM5), U202 (TPD4E1B06DRLR), U401 (SN74AHCT1G04DBVR)
+5V_BUS	5.00V	-	-
+5V_USB	5.00V	J201 External	U301 (TPS2121RUXR)
5V_POL	5.00V	U302 FS1603A-5000-AL	U301 (TPS2121RUXR)
+3V3	3.30V	Module401 CM5	U801 (IAM-20380), U802 (CY15B102Q-SXET)
+3V3_M.2	3.30V	-	-
VBAT_RTC	3.00V	BT401	Module401 (CM5)
GND	-	U801 IAM-20380	-

4.2.1 Rail Voltage Annotation

The preferred way to state a rail's voltage is to record it in the design itself, where it travels with the schematic, survives every re-run, and can be read by anyone who opens the design: add VOLTAGE_NOM, VOLTAGE_MIN and VOLTAGE_MAX properties to the rail's net class directive, and VOLTAGE_EXCURSION_MAX for a survivable level outside normal operation.

3 power input(s) into this board were identified and characterized as follows. These are the levels the analysis uses.

Rail	Voltage supplied
VBAT_BUS	7.40 V nominal, 7.00-8.40 V operating
5V_USB	5.00 V nominal, 4.75-5.50 V operating
VBAT_RTC	3.00 V nominal, 2.50-3.30 V operating

4.3 Regulator Enable Pull Resistors

1 regulator enable pin(s) examined for what drives them and which way they are pulled. 0 pulled toward the enabling level while a power output drives the net.

	Finding	Severity
RegulatorU302 [TDK FS1603A-5000-AL] Enable pinU302_3 (EN) (enabled high) NetNet-(U302-EN) Driven by- Pull-upR301 43k -> +VBAT_BUS Pull-downR302 10k -> GND	No driver on the net; the pull resistor sets the level.	Information

4.4 Power Tree Diagram

This diagram shows how power flows on this board, from the schematic: where it enters, each regulator, each rail, the parts it passes through and the loads on each rail. A large tree is split into several figures; a rail that continues in another figure names that figure.

Figure 4-1: Power tree overview

Back to the overview

Figure 4-2: power entering at BT401, J101, J201

4.5 Rail Currents

What each rail carries, load by load, so every total can be checked. Continuous is each load's steady running figure; Max is its highest stated figure (a radio's transmit burst, a converter at full load). A rail's total adds the input of every regulator it feeds and the rails behind its series parts. A total marked "at least" leaves out the loads it names.

Rail	Load	Figure Used	Continuous (A)	Max (A)	Source
+VBAT_BUS	U302 [FS1603A-5000-AL]	input from its output power: 1.4005 A continuous, 1.4005 A max out, at 89.7 % efficiency	1.0549	1.0550	-
+VBAT_BUS	R301	R301 - R302 -> GND	0.0002	0.0002	-
+VBAT_BUS	R312	not known	-	-	-
+VBAT_BUS	Total +VBAT_BUS, at least: R312 not included		1.0551	1.0551
+5V	Module401 [CM5]	operation_current (typ)	0.9000	0.9000	datasheet page 28
+5V	U202 [TPD4E1B06DRLR]	input_leakage 0.5 nA max at 2.5 V, p.5	0.0000	0.0000	datasheet page 5
+5V	U401 [SN74AHCT1G04DBVR]	icc (max)	0.0000	0.0000	datasheet page 5
+5V	J202 [533984004]	stated by the designer	0.5000	0.5000	-
+5V	Total +5V		1.4000	1.4000
+5V_USB	U301 [TPS2121RUXR]	input = output + quiescent: 1.4000 A + 0.0003 A continuous, 1.4000 A + 0.0003 A max	1.4003	1.4003	-
+5V_USB	R304	R304 - R305 -> GND	0.0002	0.0002	-
+5V_USB	R308	R308 - R309 -> GND	0.0001	0.0001	-
+5V_USB	Total +5V_USB		1.4006	1.4006
5V_POL	U301 [TPS2121RUXR]	input = output + quiescent: 1.4000 A + 0.0003 A continuous, 1.4000 A + 0.0003 A max	1.4003	1.4003	-
5V_POL	R306	R306 - R307 -> GND	0.0001	0.0001	-
5V_POL	R310	R310 - R311 -> GND	0.0001	0.0001	-
5V_POL	Total 5V_POL		1.4005	1.4005
+3V3	U801 [IAM-20380]	idd_normal (typ) / idd_normal typ 2.6 mA, 3-axis gyroscope normal mode; no max printed, p.17	0.0026	0.0026	datasheet page 17
+3V3	U802 [CY15B102Q-SXET]	standby_current (typ) / icc (max)	0.0001	0.0050	datasheet page 13
+3V3	J701 [FH12A-22S-0.5SH(55)]	stated by the designer	0.3500	0.3500	-
+3V3	J702 [FH12A-22S-0.5SH(55)]	stated by the designer	0.3500	0.3500	-
+3V3	R802	R802 -> U802_1 (the pulled pin low 50 % of the time)	0.0002	0.0003	-
+3V3	R803	R803 -> Module401_49 (the pulled pin low 50 % of the time)	0.0002	0.0003	-
+3V3	Total +3V3		0.7030	0.7083
VBAT_RTC	Module401 [CM5]	rtc_current (typ) / rtc_current typ 6 uA at VIN = 0 V, p.28	0.0000	0.0000	datasheet page 28
VBAT_RTC	Total VBAT_RTC		0.0000	0.0000

4.6 DC Power Integrity (Pre-Layout)

The schematic part of power integrity, at each rail's worst-case current: 2 rails with series parts, 5 loads with a datasheet minimum supply voltage, 2 regulators. Each margin starts from the rail's low end: the minimum stated for it, else its regulator's output band (the datasheet accuracy figure and the feedback resistors' tolerance), else only its nominal. Line and load regulation are not included. The copper part - IR drop in traces, planes and vias - is checked after layout, against the copper budget given here for each rail.

4.6.1 Power Budget Findings

	Finding	Severity
Rail+5V	+5V cannot guarantee Module401, U401's supply: at its stated minimum the rail is 4.750 V, and its series parts (U301 100 mΩ, J201 cable (USB Type-C allowance) 250 mΩ) take 490.1 mV, below the minimum of each load named: Module401 by 490.1 mV (4.750 V minimum), U401 by 240.1 mV (4.500 V minimum), before any copper drop. At 5.000 V nominal at J201, Module401 keeps 110.0 mV above its minimum for copper. A shortfall occurs when a USB power source is within the USB specification but at its 4.75 V minimum allowed. The power-source cable will lower the voltage arriving at J201 even further. Build more margin into this rail before layout. Suggested remedy: On the built board, power it from a USB supply that holds close to 5 V over a short, good cable, and keep the copper from J201 through U301 to the +5V loads short and wide: the 0.25 Ω cable allowance and the 0.1 Ω of the TPS2121 (U301) pull the rail below the CM5's 4.75 V minimum, and U401 needs 4.5 V. That cannot guarantee the worst case on its own, because the rail's own low end already sits at the CM5's 4.75 V minimum. The design change is a regulated buck-boost converter after U301 with a tight output accuracy that makes +5V at the loads, keeping its high end at or below the CM5's 5.25 V maximum (tighter than U401's 5.5 V) and its draw, losses included, within what the USB input J201 can deliver.	Medium

4.6.2 Regulator Output Band

Rail	Regulator	Rail Nominal (V)	Band at 25 °C (V)	Band at 85 °C (V)	Worked Out From	Status	Severity
5V_POL	U302 [FS1603A-5000-AL]	5.000	4.950 - 5.050	4.950 - 5.050	Output accuracy ±1 % (datasheet page 6)	4.950 - 5.050 V at 85 °C	Information

4.6.3 Series Parts on Each Rail

Rail	From	Worst-Case Current (A)	Series Parts	Drop (mV)	Drop from Source (mV)	Notes	Status	Severity
+5V	+5V_USB	1.400	U301 100.0 mOhm	140.0	490.1	At least this much: the current of Module401 is not fully known	Drop at least 140.0 mV	Information
+5V_USB		1.401	J201 cable (USB Type-C allowance) 250.0 mOhm	350.1	350.1	At least this much: the current of U301 is not fully known	Drop at least 350.1 mV	Information

4.6.4 Load Margin Before Copper

Rail ⇅	Load ⇅	Rail Nominal (V) ⇅	Drop (mV) ⇅	Load Minimum (V) ⇅	Rail Low End at 25 °C (V) ⇅	Margin at 25 °C (mV) ⇅	Rail Low End at 85 °C (V) ⇅	Margin at 85 °C (mV) ⇅	Status ⇅	Severity ⇅
+5V	Module401	5.000	490.1	4.750	4.750	-490.1	4.750	-490.1	Below its 4.75 V minimum by 490 mV before any copper; series drop at least 490.1 mV (not every current on the rail is known)	Medium
+5V	U401	5.000	490.1	4.500	4.750	-240.1	4.750	-240.1	Below its 4.50 V minimum by 240 mV before any copper; series drop at least 490.1 mV (not every current on the rail is known)	Medium
VBAT_RTC	Module401	3.000	0.0	2.500	2.500	0.0	2.500	0.0	Only 0 mV (0.0 %) left for copper	Medium
+3V3	U801	3.300	0.0	1.710	3.300	1590.0	3.300	1590.0	1590 mV left for copper	Information
+3V3	U802	3.300	0.0	2.000	3.300	1300.0	3.300	1300.0	1300 mV left for copper	Information

4.6.5 Regulator Input and Output

Regulator	Type	Input Rail	Worst-Case Input (V)	Input Range (V)	Output Current (A)	Rated (A)	Notes	Status	Severity
U301 [TPS2121RUXR]	load_switch	+5V_USB	4.400	2.8 - 22	1.400	4.5	from the source's stated minimum	For typical USB operation at 5 V, U301 sees 4.65 V at its input. If USB drops to its 4.75 V minimum, U301 sees 4.40 V, at or above the 2.8 V minimum input its manufacturer specifies (datasheet page 6). 1.400 A of 4.5 A	Information
U302 [FS1603A-5000-AL]	switching	+VBAT_BUS	7.000	6.75 - 16	1.401	3	from the source's stated minimum	For typical +VBAT_BUS operation at 7.4 V, U302 sees 7.40 V at its input. If +VBAT_BUS drops to its 7 V minimum, U302 sees 7.00 V, at or above the 6.75 V minimum input its manufacturer specifies (datasheet page 6). 1.401 A of 3 A	Information

4.7 AC Power Integrity Inputs

The values an AC impedance analysis of this board needs, and where each came from. They are written to the power delivery network export for a solver; this report does not solve AC impedance. A value the datasheets do not state is left unknown here rather than guessed.

4.7.1 What Was Found

Value	From the Part's Own Data	Estimated	Not Known
Load current step	2	0	3
Regulator loop bandwidth	0	1	0
Capacitance kept at rated voltage	11	0	8
Capacitor ESR	11	8	0

4.7.2 Regulator Loop Bandwidth

Regulator	Switching Frequency (kHz)	Bandwidth (kHz)	Source
U302 [FS1603A-5000-AL]	1400	140	estimated: switching frequency / 10

4.7.3 Load Current Steps

Rail	Load	Current Step (A)	Source
+5V	Module401 [CM5]	-	a module's datasheet gives no step per supply
+5V	U401 [SN74AHCT1G04DBVR]	-	its datasheet states no current step
+3V3	U801 [IAM-20380]	0.002594	stated in the datasheet, datasheet page 10: Table 2: normal-mode 3-axis gyroscope supply current 2.6 mA minus full-chip sleep current 6 µA; chip-level step, not apportioned between the two supply pins (page 10)
+3V3	U802 [CY15B102Q-SXET]	0.00485	stated in the datasheet, datasheet page 12: Operating IDD maximum 5 mA at 25 MHz minus standby ISB maximum 150 µA at 25 °C (DC Electrical Characteristics). (page 12)
VBAT_RTC	Module401 [CM5]	-	a module's datasheet gives no step per supply

4.7.4 Capacitor AC Data

Rail	Capacitor	Part	Rated (V)	Dielectric	ESR	Kept at Rated Voltage
+VBAT_BUS	C105 47u	T591D476M025ATE060	25	solid tantalum	60 mΩ: stated in the datasheet, datasheet page 12: esr	100 %: calculated from datasheet figures: solid tantalum: a dielectric whose capacitance does not fall with DC bias
+VBAT_BUS	C108 47u	T591D476M025ATE060	25	solid tantalum	60 mΩ: stated in the datasheet, datasheet page 12: esr	100 %: calculated from datasheet figures: solid tantalum: a dielectric whose capacitance does not fall with DC bias
+VBAT_BUS	C111 10u	no part number; no GCM part with 10 uF, 25 V, X7R in 0805 is on file	25	X7R	5 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+VBAT_BUS	C112 0.1u	GCM188R71E104KA57 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 100 nF, 25 V, X7R, 0603)	25	X7R	16.3 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E104K080AA's measured S-parameters - the equivalent of GCM188R71E104KA57 (same case 0603, X7R, 100 nF, 25 V; matched by decode), not this part's own, at resonance	83.7 %: read from a datasheet graph: the DC-bias curve at the rated voltage
+VBAT_BUS	C304 2u2	no part number; no GCM part with 2.2 uF, 25 V, X7R in 0603 is on file	25	X7R	6.81 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+5V	C101 0.1u	GCM188R71E104KA57 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 100 nF, 25 V, X7R, 0603)	25	X7R	16.3 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E104K080AA's measured S-parameters - the equivalent of GCM188R71E104KA57 (same case 0603, X7R, 100 nF, 25 V; matched by decode), not this part's own, at resonance	83.7 %: read from a datasheet graph: the DC-bias curve at the rated voltage
+5V	C102 0.1u	GCM188R71E104KA57 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 100 nF, 25 V, X7R, 0603)	25	X7R	16.3 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E104K080AA's measured S-parameters - the equivalent of GCM188R71E104KA57 (same case 0603, X7R, 100 nF, 25 V; matched by decode), not this part's own, at resonance	83.7 %: read from a datasheet graph: the DC-bias curve at the rated voltage
5V_POL	C305 22u	GCJ32EC71E226KE02L	25	X7S	3.46 mΩ: from the maker's measured S-parameters	43.6 %: read from a datasheet graph, datasheet page 3: the DC-bias curve at the rated voltage
5V_POL	C306 22u	GCJ32EC71E226KE02L	25	X7S	3.46 mΩ: from the maker's measured S-parameters	43.6 %: read from a datasheet graph, datasheet page 3: the DC-bias curve at the rated voltage
+3V3	C113 10u	no part number; no GCM part with 10 uF, 25 V, X7R in 0805 is on file	25	X7R	5 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+3V3	C114 0.1u	GCM188R71E104KA57 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 100 nF, 25 V, X7R, 0603)	25	X7R	16.3 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E104K080AA's measured S-parameters - the equivalent of GCM188R71E104KA57 (same case 0603, X7R, 100 nF, 25 V; matched by decode), not this part's own, at resonance	83.7 %: read from a datasheet graph: the DC-bias curve at the rated voltage
+3V3	C115 10u	no part number; no GCM part with 10 uF, 25 V, X7R in 0805 is on file	25	X7R	5 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+3V3	C701 10u	no part number; no GCM part with 10 uF, 25 V, X7R in 0805 is on file	25	X7R	5 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+3V3	C702 10u	no part number; no GCM part with 10 uF, 25 V, X7R in 0805 is on file	25	X7R	5 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+3V3	C801 2u2	no part number; no GCM part with 2.2 uF, 25 V, X7R in 0603 is on file	25	X7R	6.81 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+3V3	C802 0.1u	GCM188R71E104KA57 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 100 nF, 25 V, X7R, 0603)	25	X7R	16.3 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E104K080AA's measured S-parameters - the equivalent of GCM188R71E104KA57 (same case 0603, X7R, 100 nF, 25 V; matched by decode), not this part's own, at resonance	83.7 %: read from a datasheet graph: the DC-bias curve at the rated voltage
+3V3	C804 10n	GCM188R71E103KA37 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 10 nF, 25 V, X7R, 0603)	25	X7R	53.8 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E103K080AA's measured S-parameters - the equivalent of GCM188R71E103KA37 (same case 0603, X7R, 10 nF, 25 V; matched by decode), not this part's own, at resonance	92.1 %: read from a datasheet graph: the DC-bias curve at the rated voltage
+3V3	C805 10u	no part number; no GCM part with 10 uF, 25 V, X7R in 0805 is on file	25	X7R	5 mΩ: Estimated: typical ceramic ESR near resonance for its capacitance, taken as ceramic (unpolarized symbol, no part-number decode)	not known
+3V3	C806 0.1u	GCM188R71E104KA57 (series match, no part number stated: the stated GCM series (Murata_GCM.pdf), 100 nF, 25 V, X7R, 0603)	25	X7R	16.3 mΩ: from an equivalent part's measured S-parameters: TDK C1608X7R1E104K080AA's measured S-parameters - the equivalent of GCM188R71E104KA57 (same case 0603, X7R, 100 nF, 25 V; matched by decode), not this part's own, at resonance	83.7 %: read from a datasheet graph: the DC-bias curve at the rated voltage

4.8 Short-Circuit Protection

0 current limiter(s) checked. For a short to ground on each rail a limiter feeds, the table names the part that feeds the short, the most current that part is shown delivering, and whether the limiter trips.

4.8.1 Short-Circuit Protection Findings

	Finding	Severity
Rail+VBAT_BUS	Nothing on the board limits a short to ground on +VBAT_BUS: these rails come from J101 with no fuse, eFuse or current-limited switch in between, so a short draws whatever the source delivers. A fuse or a current-limited switch after J101 limits it.	Medium
Rail+5V_USB	Nothing on the board limits a short to ground on +5V_USB, +5V: these rails come from J201 with no fuse, eFuse or current-limited switch in between, so a short draws whatever the source delivers. A fuse or a current-limited switch after J201 limits it.	Medium

4.8.2 Shorts to Ground Checked

Current Limiter	Trips At (A)	Rail Shorted to Ground	Part Feeding the Short	Current Into the Short (A)	Result
J101 [SFM-120-01-X-D], no limiter	-	+VBAT_BUS	J101 [SFM-120-01-X-D]	-	Nothing on the board limits it: the source at J101 feeds it directly
J101 [SFM-120-01-X-D], no limiter	-	5V_POL	U302 [FS1603A-5000-AL]	4.3	U302 limits it to 4.3 A (datasheet page 7)
J201 [DX07S016JA1R1500], no limiter	-	+5V_USB	J201 [DX07S016JA1R1500]	-	Nothing on the board limits it: the source at J201 feeds it directly
J201 [DX07S016JA1R1500], no limiter	-	+5V	J201 [DX07S016JA1R1500]	-	Nothing on the board limits it: the source at J201 feeds it directly

4.9 AI-Assisted Analysis

This section is created by AI and should be reviewed for accuracy. There may be some incorrect analysis, especially if any errors are called out in the Design Summary or Component Value sections. STANDARD MODE — this analysis was produced by the standard model tier.

4.9.1 Power Tree Overview

AI-Assisted — The board has two power sources. The battery bus +VBAT_BUS enters on the payload connector J101 pins 1-4 at 7.40 V nominal, within a stated 7.00-8.40 V band. C105 and C108 (47 µF polymer tantalum), C111 (10 µF) and C112 (0.1 µF) sit beside the connector on sheet connectors-blackwing. This rail feeds only U302, a TDK FS1603A-5000-AL fixed-5 V µPOL module on sheet power, which produces 5V_POL. The second source is USB Type-C VBUS: +5V_USB from J201, 4.75-5.50 V, protected by D201 (TI ESD751).

U301, a TI TPS2121 2:1 power multiplexer, takes +5V_USB on IN1 and 5V_POL on IN2 and produces +5V. +5V feeds the CM5 (Module401) on its six +5 V input pins, the power-LED inverter U401, the ESD array U202 and the off-board USB host port on J202 pin 1. The CM5 sources +3V3 from its pins 84 and 86, which supplies the gyroscope U801, the FRAM U802, two indicator LEDs and pin 22 of camera connectors J701 and J702. VBAT_RTC (2.50-3.30 V) runs from the coin cell BT401 to CM5 pin 76, with D401 (BAS116) on that node.

No rail has a ferrite or series filter element; U302's inductor is internal to the module. The M.2 3.3 V branch is drawn and marked not fitted, as the designer's notes on sheets power and connectors-blackwing state. That branch is TPS2121 U303, FS1603A-3300 U304 and their passives. As a result +3V3_M.2 is unpowered on this build and +5V_BUS (J101 pins 37-40) has no load.

The known +5V load is 0.90 A. That is the CM5's 900 mA typical operation current (Raspberry Pi CM5 datasheet p.28, source: Tomachie) plus LED paths of under 1 mA each. It does not include the J202 host port or the camera supplies. At that load U302 draws about 0.73 A from a 7.0 V battery.

4.9.2 FS1603A-5000 Point-of-Load Converter (U302)

AI-Assisted — U302 is a 5.0 V, 3 A module with an integrated inductor, factory-preset to 1.4 MHz (TDK FS1603A datasheet p.18, Datasheet). It runs in single-supply mode: PVIN is on +VBAT_BUS directly and VIN goes through the R312/C303 filter. Its internal LDO then makes VCC (4.9-5.5 V) on net VCC1. FB senses VOUT directly, so 5V_POL is the preset 5.0 V ±1 % and there is no divider to compute.

The enable is a pull-only divider: R301 (43 kΩ) from +VBAT_BUS and R302 (10 kΩ) to GND, in parallel with the 1 MΩ internal pull-down. At the typical 1.2 V and 1.0 V thresholds this gives 6.41 V rising and 5.34 V falling. The designer's note quotes 6.8 V and 5.7 V, which belong to a 47 kΩ top resistor. At the tolerance corner the start threshold reaches 7.12 V, just above the 7.00 V bottom of the battery band. The stop threshold is always below the 6.75 V recommended PVIN minimum. The 1.2:1 EN hysteresis cannot place the start below 7.00 V and the stop above 6.75 V at the same time.

On Murata's DC-bias data, C305 and C306 keep about 21.3 µF each at 5 V. That is above the 22 µF-class minimum and well inside the 132 µF ceramic ceiling.

The gap is at VCC. The LDO output has no capacitor. A 2.2 µF part, C304, matches the value the datasheet shows for VCC but is drawn on +VBAT_BUS instead. The not-fitted U304 repeats the same placement with C310. If C304 moves to VCC, the only ceramic on PVIN on this sheet goes with it.

PG is pulled to VCC through R325 and brought to TP301; nothing is sequenced from it. The I²C port shares I2C_3 with the CM5 and U801 at 3.3 V. It needs its bus-voltage selector set to the 3.3-5.0 V range and relies on CM5-side pull-ups.

At the 0.90 A known load the datasheet's 12 V loss curve gives about 0.50 W. That puts the estimated junction near 96 °C at 85 °C ambient.

4.9.3 TPS2121 Source Multiplexer (U301) and the +5V Rail

AI-Assisted — U301 runs in automatic switchover with priority (XCOMP), as the designer's note states (TI TPS2121 datasheet, source: Tomachie). R306 and R307 hold CP2 at 1.163 V from 5V_POL, above the VREF band. The device therefore compares PR1, which is +5V_USB × 0.3125 through R304 and R305, against CP2. USB is used above 3.72 V; below that the output moves to 5V_POL with the 5 µs fast switchover. With the battery absent, CP2 is at 0 V and the device falls back to VREF priority, so USB alone still powers +5V.

OV1 and OV2 use the same 47 kΩ / 10 kΩ divider and trip at 6.04 V typical, matching the note. The 1.01-1.10 V VREF band spreads this to 5.76-6.27 V. The top of that range exceeds the CM5's 6.0 V absolute maximum.

R303 sets the current limit to 2.37 A typical, below U302's own 3.6 A minimum limit. U301 therefore holds any +5V short, U302 never reaches hiccup, and U301's 160 °C thermal shutdown ends a sustained short. C301 slows the +5V ramp to roughly 45 ms. ST goes only to TP106 and has no pull-up.

When USB is selected, +5V is unregulated. The stated 4.75-5.50 V USB band, the 3.72 V handover and the U301 drop together put the CM5 +5 V input outside its 4.75-5.25 V recommended window at both ends. Raising the handover to about 4.84 V (R304 = 31.6 kΩ) still leaves USB-only operation intact. With CP2 at 0 V, PR1 at 4.75 V × 0.2404 = 1.14 V is above VREF, so IN1 stays selected.

On-board bulk on +5V is only C101 and C102 (0.2 µF). At 0.9 A over the 5 µs switchover that alone would fall by I·t/C = 22.5 V, so ride-through depends on the CM5's internal input capacitance. Adding 22 µF effective would hold the droop near 0.2 V.

D201 on +5V_USB has ample standoff. However, it clamps above U301's 24 V absolute maximum: 25.5 V breakdown minimum and 36.5 V at 2.8 A.

4.9.4 Downstream Rails, RTC Supply and Unpopulated Branches

AI-Assisted — +3V3 is the CM5's 3.3 V output: 600 mA total, 300 mA per pin, ±5 % (Raspberry Pi CM5 datasheet p.20, source: Tomachie). Its known load is about 10 mA:

- U801 at 2.6 mA in normal gyroscope mode (TDK IAM-20380 datasheet p.17, Datasheet).
- U802 at 5 mA maximum with a 25 MHz SPI clock (Infineon CY15B102Q datasheet p.13, Datasheet).
- D101 at about 0.8 mA through R101 (1 kΩ).
- D105 at about 1.5 mA through R105 (1 kΩ).
- Up to 0.66 mA in R802 and R803 when their lines are held low.

The camera supplies on J701 and J702 are not included in that figure. Decoupling on +3V3 totals 52.51 µF nominal. U801 and U802 share 2.2 µF, 10 µF, two 0.1 µF and 10 nF locally on sheet peripherals.

VBAT_RTC carries BT401 to CM5 pin 76, inside the CM5's 2.5-3.5 V VBAT window. The designer's note labelling the battery 1.65-3.6 V is wider than that window. D401's cathode sits on this node with at most 3.3 V reverse bias against a 75 V rating. Its leakage at 3.3 V is about 0.04 nA at 25 °C, negligible beside the CM5's 1.7-6 µA RTC current.

The not-fitted M.2 branch (U303, U304) mirrors the populated pair, and two of its drawn options do not match their annotations:

- R313 (1.13 kΩ) on ADDR2 matches no row of the address table in the TDK FS1603A datasheet that covers U302.
- R314 (47 kΩ) on U303 ILIM gives 2.37 A, not the 1.2 A the note promises for 100 kΩ.

Its OV3/OV4 dividers repeat the 47 kΩ / 10 kΩ values, so they would carry the same 6.27 V top-corner trip.

4.9.5 Power Sequencing

AI-Assisted — Nothing on the board sequences from a power-good signal. The start-up order follows from input thresholds and soft-start ramps alone.

Battery only:
+VBAT_BUS rises at J101.
U302 enables at 6.41 V typical (5.88-7.12 V across tolerance) and soft-starts at 1 V/ms (TDK FS1603A datasheet p.6). 5V_POL reaches 5.0 V in about 5 ms, and PG at TP301 rises at 90 % of VOUT.
When 5V_POL passes 4.56 V (VREF 1.06 V / 0.23256), CP2 crosses VREF. With +5V_USB absent, U301 selects IN2.
U301 ramps +5V at about 0.11 V/ms, set by C301 (1 µF), taking roughly 45 ms.
The CM5 starts from +5V and brings up +3V3, which powers U801, U802 and the +3V3 LEDs.

USB present: U301 selects IN1 once +5V_USB clears its 2.65 V typical UVLO. With the battery also present, USB keeps priority until +5V_USB falls below 3.72 V, and the output then transfers to 5V_POL in about 5 µs.

VBAT_RTC comes from BT401 independently of both sequences. The +3V3 timing is set inside the CM5.

4.10 Observations

AI-Assisted — The main risk is the 5 V path into the CM5. With USB selected, +5V is VBUS less a few tens of millivolts. Both the stated USB band and the 3.72 V priority handover put the CM5 +5 V input outside its 4.75-5.25 V recommended range. The two ends need different changes:

- At the low end, raise the XCOMP handover.
- At the high end, either tighten the USB input requirement or add regulation on the IN1 path.

The overvoltage dividers on both TPS2121 inputs are correct at typical VREF but not at the worst VREF corner. There they pass 6.27 V against the CM5's 6.0 V absolute maximum. 44.2 kΩ top resistors close that gap.

D201's 24 V-class clamp starts conducting only above U301's 24 V absolute maximum. The protective fix is a lower-standoff part matched to U301 IN1 and its PR1 and OV1 divider pins.

On the battery side, U302 is well applied in most respects. Its input sits inside the recommended range, its output capacitance is correct after DC bias, and its predicted junction is about 96 °C at the known load. Two points remain:

- Its VCC LDO output carries no capacitor, while the matching 2.2 µF part is drawn on the input rail.
- The EN divider's start threshold reaches the bottom of the battery band at the tolerance corner.

The tantalum bulk C105 and C108 is correctly rated at 25 V, although the part-number decode reads otherwise. The ceramics around U302 and on +5V and +3V3 carry no voltage property.

At 85 °C ambient and the known load, U301 runs at about 90 °C and U302 at about 96 °C. The USB host port on J202 and the cameras on J701 and J702 are the loads still unquantified behind every current margin above.

4.11 Findings

AI-Assisted —

#	Device	Rail	Observation	Severity
4.11.1	+5V rail (U301 to Module401)	+5V_USB, +5V	+5V exceeds the CM5's recommended maximum at the top of the USB band. +5V follows +5V_USB through U301 (56-100 mΩ). At the 5.50 V top of the stated USB band, CM5 +5 V input pins 77-87 see up to 5.5 V. That is above the 4.75-5.25 V recommended range (Raspberry Pi CM5 datasheet p.20, source: Tomachie). U401's 4.5-5.5 V range is met. Given the ±4 % VREF band, no OV1 divider can admit the full 4.75-5.50 V band while rejecting above 5.25 V. Fix, one of: state the USB input requirement at J201 as 4.75-5.25 V; or add a regulating stage on the IN1 path. The 44.2 kΩ OV1 setting above hands over to 5V_POL from 5.47-5.96 V when the battery is present.	High
4.11.2	+5V rail (U301 to Module401), R304	+5V_USB, +5V	+5V falls below the CM5's recommended minimum at the bottom of the USB band and during the handover delay. At the 4.75 V USB minimum the CM5 sees 4.67 V (0.9 A × 90 mΩ maximum on-resistance, TI TPS2121 datasheet p.7, source: Tomachie). That is below its 4.75 V recommended minimum (Raspberry Pi CM5 datasheet p.20, source: Tomachie). Worse, the 3.72 V XCOMP handover keeps USB selected down to 3.72 V even when 5V_POL is available. That is below both the CM5's 4.75 V and U401's 4.5 V minimum (TI SN74AHCT1G04 datasheet p.4, Datasheet). Fix: a handover at or above 4.83 V keeps the CM5 in range whenever the battery is present. R304 = 31.6 kΩ with R305 at 10 kΩ gives 4.84 V typical, before the 5-40 mV comparator offset. USB-only operation still needs at least 4.83 V at the board.	High
4.11.3	U301 (TPS2121RUXR), R308, R309	+5V_USB	IN1 overvoltage trip does not protect the CM5 at the worst VREF corner. R308 (47 kΩ) and R309 (10 kΩ), ratio 0.17544, trip IN1 at 6.04 V typical and 5.76-6.27 V across the 1.01-1.10 V VREF band (p.8). The top end passes 6.27 V to +5V, above the 6.0 V absolute maximum of the CM5 +5 V input (Raspberry Pi CM5 datasheet p.26, source: Tomachie). Fix: R308 = 44.2 kΩ (ratio 0.1845) gives a 5.47-5.96 V trip before resistor tolerance, below 6.0 V at every VREF corner. Source: TI TPS2121 datasheet, source: Tomachie	Medium
4.11.4	U301 (TPS2121RUXR), R310, R311	5V_POL	IN2 overvoltage trip does not protect the CM5 at the worst VREF corner. R310 (47 kΩ) and R311 (10 kΩ) trip IN2 at 5.76-6.27 V. The top end exceeds the CM5's 6.0 V absolute maximum (Raspberry Pi CM5 datasheet p.26, source: Tomachie) if U302's output rises toward +VBAT_BUS. Fix: R310 = 44.2 kΩ gives a 5.47-5.96 V trip, which still clears the 5.05 V maximum of 5V_POL. Source: TI TPS2121 datasheet p.8, source: Tomachie	Medium
4.11.5	D201 (ESD751DYAR)	+5V_USB	D201 clamps above the voltage that U301 can withstand. VBR(min) is 25.5 V at 10 mA and clamping is 36.5 V typical at 2.8 A, 8/20 µs (TI ESD751 datasheet p.5, Datasheet). Both exceed the 24 V absolute maximum of U301 IN1, which states no transient rating, so the absolute maximum is used as the bound (TI TPS2121 datasheet p.6, source: Tomachie). No resistance separates D201 from U301_7. The same 36.5 V also puts 6.4 V on OV1 and 11.4 V on PR1, above their 6 V absolute maximum. Fix: a TVS with standoff of at least 5.5 V whose clamping voltage at the expected surge current stays below 19 V. That keeps IN1 below 24 V and PR1 below 6 V.	Medium
4.11.6	U302 (FS1603A-5000-AL), R301, R302	+VBAT_BUS	EN note does not match the fitted divider. The designer's note on sheet power gives EN UVLO of about 6.8 V rising and 5.7 V falling for 47 kΩ / 10 kΩ. The drawn R301 is 43 kΩ. With R302 (10 kΩ), the 1 MΩ internal pull-down and the 1.2 V / 1.0 V typical thresholds (p.7), the drawn values give 6.41 V rising and 5.34 V falling. The note's figures correspond to 47 kΩ (6.84 V / 5.70 V). Update the note to the fitted value. Source: TDK FS1603A datasheet	Low
4.11.7	U302 (FS1603A-5000-AL), R301	+VBAT_BUS	Start-up is not assured at the bottom of the battery band. At the worst corner (EN rising threshold 1.3 V maximum, internal pull-down 500 kΩ minimum, R301 +1 %, R302 -1 %) the rising threshold is 7.12 V. That is above the 7.00 V bottom of the stated band (typical is 6.41 V). Fix: R301 = 41.2 kΩ 1 % brings the worst case to 6.87 V (typical 6.19 V rising, 5.16 V falling). Source: TDK FS1603A datasheet p.7	Low
4.11.8	U302 (FS1603A-5000-AL)	VCC1	VCC has no capacitor. U302_10 VCC (internal LDO output, 4.9-5.5 V) has only R325 on its net. The datasheet reference circuit shows 2.2 µF on VCC, and its component-selection text recommends 2.2 µF X7R close to VCC (pp.21-22). C304, a 2.2 µF part, is drawn from +VBAT_BUS to GND instead. The not-fitted U304 repeats this, with C310 (2.2 µF) on 5V_MUX and nothing on VCC2. Fix: move C304 to VCC1-GND at U302_10, and C310 to VCC2. Source: TDK FS1603A datasheet	Review
4.11.9	U302 (FS1603A-5000-AL)	+VBAT_BUS	Little ceramic input capacitance at U302. The only ceramic on +VBAT_BUS on sheet power is C304 (2.2 µF). C111, C112, C105 and C108 sit at J101 on sheet connectors-blackwing. C302 (22 µF) is drawn but marked not fitted, per the designer's note. The 2 × 22 µF ceramic input on p.22 is the datasheet's reference circuit, not a stated minimum. If C304 moves to VCC, PVIN has no ceramic on this sheet. Source: TDK FS1603A datasheet	Review
4.11.10	U302 (FS1603A-5000-AL)	+VBAT_BUS	U302 keeps running below its recommended PVIN minimum on a discharging battery. The falling threshold is 4.81-5.66 V (0.9-1.06 V EN band), below the 6.75 V recommended PVIN minimum (p.6). This happens only outside the stated 7.00-8.40 V normal band. The 1.2:1 EN hysteresis cannot put the start below 7.00 V and the stop above 6.75 V together, so any deep-discharge cut-off has to come from the battery side. Source: TDK FS1603A datasheet	Review
4.11.11	C305, C306 (GCJ32EC71E226KE02L)	5V_POL	Voltage rating is over-specified. The parts are rated 25 V (Murata datasheet p.2) with 5 V applied. The ECSS-Q-ST-30-11C derating selected for this schematic analysis permits 15 V (a 40 % derating, capacitor_voltage_pct = 60). A 16 V rating would serve, although the 25 V body is what keeps the DC-bias loss at about 3 %. Source: Murata datasheet	Review
4.11.12	U302 (FS1603A-5000-AL)	I2C_3_SCL, I2C_3_SDA	I²C pull-ups depend on the CM5. U302 pin 4 SCL and pin 1 SDA need a 4.99 kΩ pull-up to the bus voltage when I²C is used (p.2), and neither net has a resistor to a rail. The designer's note on sheet cm5 credits internal 1.8 kΩ CM5 pull-ups. The CM5 datasheet states those for pins 80 and 82 (SCL0/SDA0), but this bus uses GPIO3 and GPIO2 (Module401 pins 56 and 58). Check that the CM5 provides pull-ups on GPIO2 and GPIO3. Sources: TDK FS1603A datasheet; Raspberry Pi CM5 datasheet p.19, source: Tomachie	Review
4.11.13	U302 (FS1603A-5000-AL)	I2C_3_SCL, I2C_3_SDA	Firmware should set the I²C bus-voltage selector. The bus runs at 3.3 V (CM5 GPIO_VREF on +3V3). The FS1603A selector defaults to 1.8-2.5 V and has a 3.3-5.0 V setting (pp.2, 13); firmware should select the 3.3-5.0 V range. Source: TDK FS1603A datasheet	Review
4.11.14	U302 (FS1603A-5000-AL)	5V_POL	Thermal estimate passes, with caveats. 'Typical efficiency and power loss at PVIN = 12V' (p.12) gives about 0.50 W loss and 89.7 % efficiency at the 0.90 A known load, interpolated between 0.75 A and 1 A. With θJA 22.6 °C/W (evaluation board, p.4) the junction is about 96 °C at 85 °C ambient. The ECSS-Q-ST-30-11C limit is 110 °C (the lower of 110 °C and 40 °C below the 150 °C Tj max), so this passes. At the full 3 A the same reading gives 109.5 °C. Caveats: the curve is at 12 V, not this board's 7.0-8.4 V, and θJA is the evaluation board's. Source: TDK FS1603A datasheet	Review
4.11.15	U302 (FS1603A-5000-AL)	5V_POL, +5V	Output current headroom depends on unquantified loads. U302 permits 2.4 A (3 A rated, p.6, 20 % output-current derating). The known +5V load is 0.90 A: Module401 at 0.90 A typical; D102 and D103 at about 0.75 mA each (SunLED 'Forward Current vs. Forward Voltage' p.2, Datasheet); D104 at most 0.13 mA; U401 at most 10 µA. This excludes the off-board USB host port on J202 pin 1. Check that the total stays below 2.4 A. Source: TDK FS1603A datasheet	Review
4.11.16	U301 (TPS2121RUXR)	PMUX1_ST	Status output has no pull-up. U301_9 ST goes only to TP106. The datasheet calls for a 6-20 kΩ pull-up, or GND when unused (pp.4, 6). As drawn, TP106 reads an undriven node whenever IN1 is selected. Fix: a 10 kΩ pull-up to +3V3 makes the test point show the selected source. Source: TI TPS2121 datasheet, source: Tomachie	Review
4.11.17	+5V rail, C101, C102	+5V	On-board +5V capacitance cannot bridge the switchover. +5V has 0.2 µF on the board (C101, C102). Over the 5 µs fast switchover (TI TPS2121 datasheet p.7, source: Tomachie), a 0.9 A load would drain I·t/C = 22.5 V from 0.2 µF. Check that the CM5 module's own input capacitance holds +5V through 5 µs at its load. Adding 22 µF effective on +5V limits the droop to about 0.2 V.	Review
4.11.18	VBAT_RTC (BT401 to Module401)	VBAT_RTC	Designer's battery-range note is wider than the CM5 allows. The note on sheet cm5 labels the RTC backup battery 1.65-3.6 V, but the CM5 states 2.5-3.5 V for VBAT (Raspberry Pi CM5 datasheet p.15, source: Tomachie). The drawn 2.50-3.30 V band is inside the CM5 window; the note's range is not.	Review
4.11.19	+3V3 rail (Module401 output)	+3V3	CM5 3.3 V output headroom depends on camera load. The CM5 permits 600 mA (300 mA per pin, Raspberry Pi CM5 datasheet p.20, source: Tomachie). The known +3V3 load is about 10 mA: U801 2.6 mA; U802 5 mA maximum; D101 about 0.8 mA (SunLED 'Forward Current vs. Forward Voltage' p.2); D105 about 1.5 mA (Würth 'Forward Current vs. Forward Voltage' p.3, Datasheet); R802 and R803 up to 0.66 mA. This excludes the camera supplies on J701 and J702 pin 22. Check that the total stays below 600 mA.	Review
4.11.20	Module401 GPIO bank limit	+3V3	GPIO bank current has wide headroom. The 28-GPIO bank total is 50 mA (Raspberry Pi CM5 datasheet p.11, source: Tomachie). The known sink is R803 (10 kΩ from +3V3) on GPIO18 (FRAM_H̅O̅L̅D̅), 0.33 mA when driven low. That leaves 49.7 mA for GPIO loads not quantified here.	Review
4.11.21	U401 supply-current limit	+5V	U401 output load is not quantified. The SN74AHCT1G04 VCC/GND continuous current limit is ±50 mA (TI SN74AHCT1G04 datasheet p.4, Datasheet). Its single output's load is not sized here, so the full 50 mA is headroom for it; quiescent current is at most 10 µA.	Review
4.11.22	C105, C108 (T591D476M025ATE060)	+VBAT_BUS	Voltage rating is correct but not stated in a Voltage property. The parts are rated 25 V (KEMET datasheet p.12, Datasheet) with 8.40 V applied. The ECSS-Q-ST-30-11C derating selected for this schematic analysis permits 15 V (capacitor_voltage_pct = 60), so they are correctly sized; a 16 V rating (9.6 V permitted) would serve. The part-number decode reads 200000 V, which is not the part's rating. State 25 V in a named Voltage property.	Review
4.11.23	C105, C108 (T591D476M025ATE060)	+VBAT_BUS	Ripple rating covers the estimate, but at a different frequency. Input RMS ripple, Iout·√(D(1−D)), is 0.44 A at the 0.90 A known load and 1.47 A at the full 3 A at 8.4 V. The 2.74 A rms per-capacitor rating (KEMET pp.12, 20; multiplier 1.00 up to 85 °C) covers both. However, the rating is at 100 kHz and U302 switches at 1.4 MHz, so the figures are not at the same frequency. Source: KEMET datasheet	Review
4.11.24	C105, C108 (T591D476M025ATE060)	+VBAT_BUS	Endurance note. Endurance is 2000 h at 125 °C at 2/3 of rated voltage (p.4). Here the parts see 8.40 V (34 % of rated) at up to 85 °C ambient on an always-on battery input. The datasheet gives no life-acceleration model for that point. Source: KEMET datasheet	Review
4.11.25	C111, C112, C304, C303	+VBAT_BUS, VIN1	Voltage ratings missing on battery-side ceramics. C111 (10 µF), C112 (0.1 µF) and C304 (2.2 µF) on +VBAT_BUS (8.40 V maximum), and C303 (1 µF) on VIN1, have no voltage rating stated in the schematic data. Under the ECSS-Q-ST-30-11C derating, 8.40 V needs at least a 14 V rating, so 16 V or higher.	Review
4.11.26	C101, C102, C301, C113, C114, C115, C701, C702, C801, C802, C804, C805, C806	+5V, Net-(U301-SS), +3V3	Voltage ratings missing on +5V, SS and +3V3 ceramics. C101 and C102 on +5V (5.5 V maximum), C301 on U301 SS, and the +3V3 capacitors (3.47 V maximum) have no voltage rating stated in the schematic data.	Review
4.11.27	J101 (SFM-120-01-X-D)	+VBAT_BUS	Connector contact current needs checking. J101 carries +VBAT_BUS on pins 1-4. At the 0.90 A known +5V load, U302 draws about 0.73 A at 7.0 V (5 V × 0.90 A / 0.897 / 7.0 V, plus 16 mA), about 0.18 A per contact if shared evenly. Check that the contact rating, derated 50 % under the ECSS-Q-ST-30-11C derating, covers the per-contact current. The contact current rating was not available at report generation time.	Review
4.11.28	R313 (not fitted), U304 (not fitted)	ADDR2	Address strap value matches no table row. R313 (1.13 kΩ) on U304 ADDR2 matches no row of the address-strap table in the TDK FS1603A datasheet that covers U302 (p.15: 0 Ω, 10, 20, 30.1, 39, 47, 56, 68 kΩ). The nearest rows are 0 Ω (offset 0) and 10 kΩ (offset 1). The designer's note promises 0x09, one above U302's 0x08, which corresponds to the 10 kΩ row. Source: TDK FS1603A datasheet	Review
4.11.29	R314 (not fitted), U303 (not fitted)	Net-(U303-ILIM)	Current-limit resistor does not match the designer's note. The note on sheet power states about 1.2 A for 100 kΩ, which ILM = 65.2 / 100^0.861 = 1.24 A confirms. The drawn R314 is 47 kΩ, which gives 2.37 A typical. Source: TI TPS2121 datasheet p.8, source: Tomachie	Review
4.11.30	U302 (FS1603A-5000-AL)	GND	I²C address strap selects offset 0. U302_6 ADDR is tied to GND, which is the 0 Ω row of the strap table (p.15); the designer's notes give the address as 0x08. A 10 kΩ resistor would select offset 1. Source: TDK FS1603A datasheet	Info
4.11.31	U301 (TPS2121RUXR), C301	Net-(U301-SS)	Soft-start configuration (designer's choice). C301 (1 µF) is on SS. On 'Output Slew Rate vs CSS Capacitor' (p.9), the 5 V curve ends at 981.7 nF at 0.112 V/ms; that nearest point is used. +5V therefore ramps in about 45 ms. A 100 nF capacitor would give 3.5 V/ms, about 1.4 ms. Source: TI TPS2121 datasheet, source: Tomachie	Info
4.11.32	+5V_BUS (J101)	+5V_BUS	+5V_BUS is unused on this build. J101 pins 37-40 (+5V_BUS, 5 V) have no on-board load. The designer's note states this rail would feed the 3.3 V POL path, which is not fitted.	Info
4.11.33	+3V3_M.2 (U304 not fitted)	+3V3_M.2	+3V3_M.2 is unpowered on this build. The net reaches only TP102. Its source U304, the mux U303 and their passives are drawn and marked not fitted, as the designer's note on sheet power states.	Info
4.11.34	U302 (FS1603A-5000-AL)	+VBAT_BUS, VIN1, GND	Supply and ground pins all have DC connections. PVIN pins 12, 13, 14 and 17 are on +VBAT_BUS. VIN pin 11 is on VIN1 through R312 (2.7 Ω). PGND pins 8 and 16 and AGND pin 9 are on GND. Source: TDK FS1603A datasheet p.2, Datasheet	✓
4.11.35	U302 (FS1603A-5000-AL)	+VBAT_BUS	Input voltage is correctly rated. The 7.00-8.40 V band lies inside the 6.75-16 V recommended PVIN range. The 18 V absolute maximum, derated 10 % (regulator_input_voltage_pct = 90), permits 16.2 V against 8.40 V applied. Source: TDK FS1603A datasheet pp.4, 6	✓
4.11.36	U302 (FS1603A-5000-AL)	VIN1	VIN filter matches the datasheet. R312 (2.7 Ω) and C303 (1 µF) to GND are the specified 2.7 Ω / 1 µF pair (p.25). At the 18.6 mA maximum VIN current the drop is 50 mV, so VIN stays inside the 5.5-16 V range that gives VCC 4.9-5.5 V (p.7). Source: TDK FS1603A datasheet	✓
4.11.37	U302 (FS1603A-5000-AL)	+VBAT_BUS	EN voltage is within rating. EN reaches 1.58 V at 8.40 V (divider ratio 0.18868), inside the -0.3 to 18 V absolute maximum. Source: TDK FS1603A datasheet p.4	✓
4.11.38	U302 (FS1603A-5000-AL), C305, C306	5V_POL	Output capacitance meets the datasheet. C305 and C306 (22 µF X7S 1210) on 5V_POL, both returned to GND, satisfy the at-least-one 22 µF output requirement (p.21). With C101 and C102 downstream, the 44.2 µF nominal total is below the 132 µF low-ESR ceramic ceiling (p.21). Source: TDK FS1603A datasheet	✓
4.11.39	C305, C306 (GCJ32EC71E226KE02L)	5V_POL	Effective capacitance after DC bias is adequate. Murata 'C-DC bias (capchange, 25.0degC, AC0.5Vrms)' product data reads -3.3 % at 5 V, interpolated between -2.07 % at 4.375 V and -5.86 % at 6.25 V. That leaves about 21.3 µF each and 42.5 µF in total, above the 22 µF-class minimum. Source: Murata datasheet	✓
4.11.40	U302 (FS1603A-5000-AL), R325	VCC1	PG pull-up is correct. U302_2 PG is pulled up by R325 (47 kΩ) to VCC1 (U302_10 VCC); the datasheet calls for 49.9 kΩ to VCC (p.2). PG absolute maximum is VCC (p.4), which this pull-up respects. PG is brought to TP301. The 0.11 mA pull-up current is well below the 9 mA typical PG sink. Source: TDK FS1603A datasheet	✓
4.11.41	U302 (FS1603A-5000-AL)	5V_POL	Feedback is connected as required. U302_5 FB connects directly to VOUT on 5V_POL, as the preset-output module requires (p.2), giving 5.0 V ±1 % (p.6). Source: TDK FS1603A datasheet	✓
4.11.42	U302 (FS1603A-5000-AL)	Net-(U302-VSW)	VSW is connected as required. U302_15 VSW goes only to the isolated test pad TP302, as the datasheet requires (p.2). Source: TDK FS1603A datasheet	✓
4.11.43	U301 (TPS2121RUXR), U302 (FS1603A-5000-AL)	+5V, 5V_POL	Current limits coordinate correctly. U302's limit is 3.6-4.3 A (TDK FS1603A datasheet p.7). U301's 47 kΩ ILIM lies between the 2-3 A and 1-2 A rows, so it limits at 2.37 A typical and at most 3 A. U301 therefore limits a +5V short before U302 reaches its own limit, and U302 stays within its 3 A rating. U301's 160 °C thermal shutdown ends a sustained short. Source: TI TPS2121 datasheet p.8, source: Tomachie	✓
4.11.44	U301 (TPS2121RUXR)	+5V_USB, 5V_POL, +5V	Supply and ground pins are correctly connected and inside range. IN1 pins 7 and 7_1 are on +5V_USB, IN2 pins 2 and 2_1 on 5V_POL, OUT pins 1, 1_1, 8 and 8_1 on +5V, and GND pin 12 on GND. Both inputs (4.75-5.50 V and 5.0 V ±1 %) are inside the 2.8-22 V range. Source: TI TPS2121 datasheet p.6, source: Tomachie	✓
4.11.45	U301 (TPS2121RUXR), R304-R307	+5V_USB, 5V_POL	XCOMP priority divider matches the designer's note. CP2 = 5.0 V × 0.23256 = 1.163 V, above the 1.10 V VREF maximum, so XCOMP is engaged. IN1 stays selected while +5V_USB × 0.3125 exceeds CP2, that is, above 3.72 V, matching the note's 'about 3.7 V'. PR1, CP2, OV1 and OV2 stay within 0-5.5 V; the highest is PR1 at 1.72 V. Source: TI TPS2121 datasheet pp.4, 8, source: Tomachie	✓
4.11.46	U301 (TPS2121RUXR), R303	+5V	Current-limit setting matches the designer's note. R303 (47 kΩ) is within the 18-100 kΩ ILIM range. ILM = 65.2 / 47^0.861 = 2.37 A typical, matching the note's 'about 2.4 A'. Source: TI TPS2121 datasheet pp.6, 8, source: Tomachie	✓
4.11.47	U301 (TPS2121RUXR)	+5V	Input current is within rating. The 4.5 A input rating (p.6), derated 20 %, permits 3.6 A. Both the 0.90 A known load and the 3 A maximum current limit are within that. Source: TI TPS2121 datasheet, source: Tomachie	✓
4.11.48	U301 (TPS2121RUXR)	+5V	Thermal check passes. At 0.90 A, the 90 mΩ maximum on-resistance (-40 to 105 °C, p.7) dissipates 73 mW. With θJA 72.2 °C/W (p.6) the junction is about 90 °C at 85 °C ambient, below the 110 °C ECSS-Q-ST-30-11C limit. Source: TI TPS2121 datasheet, source: Tomachie	✓
4.11.49	D201 (ESD751DYAR)	+5V_USB	Standoff voltage is adequate. A 24 V standoff is adequate for a 5.5 V maximum rail. The part is bidirectional, so there is no orientation to check. Sources: TI ESD751 datasheet p.5, Datasheet; USB Type-C specification (vSafe5V)	✓
4.11.50	D201 (ESD751DYAR)	+5V_USB	Junction temperature is within limits. Leakage at 5.5 V is at most 50 nA (the figure is rated at 24 V, p.5), so dissipation is under 0.3 µW. With θJA 746.3 °C/W the junction stays at about the 85 °C ambient, below the 110 °C ECSS-Q-ST-30-11C limit and the 150 °C Tj max. Source: TI ESD751 datasheet	✓
4.11.51	D401 (BAS116LT1G)	VBAT_RTC	Reverse voltage and leakage pass. The cathode on VBAT_RTC sees at most 3.3 V reverse. The 75 V rating, derated 25 %, permits 56.25 V, so the part is correctly sized. 'Leakage Current' (p.3) reads about 0.04 nA at 3.3 V and 25 °C, and about 8.9 nA at 150 °C. Both are negligible against the CM5's 1.7-6 µA RTC current. Source: onsemi BAS116L datasheet	✓
4.11.52	+3V3 rail (U801, U802)	+3V3	+3V3 range suits both loads. 3.3 V ±5 % (3.135-3.465 V) lies inside U801 VDD/VDDIO 1.71-3.6 V (TDK IAM-20380 datasheet p.17, Datasheet) and U802 VDD 2.0-3.6 V (Infineon CY15B102Q datasheet p.13, Datasheet).	✓
4.11.53	C105, C108 (T591D476M025ATE060)	+VBAT_BUS	ESR suits the role. tan δ is 10 % at 120 Hz and ESR is 60 mΩ at 100 kHz (p.12), which suits bulk hold-up at the battery entry; switching bypass at 1.4 MHz is the job of ceramics at U302. Source: KEMET datasheet	✓
4.11.54	C105, C108 (T591D476M025ATE060)	+VBAT_BUS	Leakage is acceptable on the battery bus. The 0.1CV limit is 117.5 µA per capacitor at the rated 25 V and 25 °C (p.12), bounding the pair at 235 µA. That compares with U302's 2.1 mA EN-low standby current (TDK FS1603A datasheet p.6) and the 0.16 mA EN divider. Source: KEMET datasheet	✓
4.11.55	C105, C108 (T591D476M025ATE060)	+VBAT_BUS	Polarity is correct. Pin 1 (positive) of C105 and C108 is on +VBAT_BUS. Source: KEMET datasheet p.8, Datasheet	✓
4.11.56	R301, R302, R312, R325, R303-R311	+VBAT_BUS, VIN1, VCC1, +5V_USB, 5V_POL	Resistor dissipation is well within derated limits. All are 0.1 W parts, which the 50 % ECSS-Q-ST-30-11C derating limits to 50 mW. The largest dissipations are R301 at 1.08 mW (6.82 V across 43 kΩ) and R312 at 0.93 mW (18.6 mA through 2.7 Ω).	✓

4.12 Citations

AI-Assisted —

References
150060VS55040 (Würth Elektronik eiSos GmbH & Co. KG) — datasheet www.we-online.com/components/products/datasheet/150060VS5...
150060WS75000 (Würth Elektronik eiSos GmbH & Co. KG) — datasheet www.we-online.com/components/products/datasheet/150060WS7...
BAS116L (ON Semiconductor) — datasheet www.mouser.com/datasheet/2/308/BAS116LT1-D-1802066.pdf
CY15B102Q (Cypress Semiconductor Corporation) — datasheet www.infineon.com/dgdl/Infineon-CY15B102Q_2-Mbit_(256_K_8)...
ESD751 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/esd751.pdf
FS1603A-5000 (TDK Corporation) — datasheet product.tdk.cn/system/files/dam/doc/product/power/switchi...
GCJ32EC71E226KE02L (Murata Manufacturing Co., Ltd.) — datasheet www.farnell.com/datasheets/3410916.pdf
IAM-20380 (TDK InvenSense) — datasheet d17t6iyxenbwp1.cloudfront.net/s3fs-public/2026-02/DS-0001...
SN74AHCT1G04 (Texas Instruments) — datasheet www.ti.com/lit/gpn/SN74AHCT1G04
T591D476M025ATE060 (KEMET) — datasheet content.kemet.com/datasheets/KEM_T2073_T59X.pdf
TPD4E1B06 (Texas Instruments) — datasheet www.ti.com/lit/gpn/TPD4E1B06
XZFRS53FVF-1 (SunLED) — datasheet www.sunledusa.com/products/spec/XZFRS53FVF-1.pdf

5 Connector Pinouts

Total connectors

5.1 J101 SFM-120-01-X-D

J101 - SFM-120-01-X-D (SFM-120-01-X-D)
Pin	Pin Name	Net	Notes
1	1	+VBAT_BUS
2	2	+VBAT_BUS
3	3	+VBAT_BUS
4	4	+VBAT_BUS
5	5	I2C_SCL
6	6	GND
7	7	I2C_SDA
8	8	GND
9	9	SPI_PICO
10	10	GND
11	11	SPI_POCI
12	12	GND
13	13	SPI_SCK
14	14	GND
15	15	SPI_CS0
16	16	GND
17	17	UART_TX
18	18	GND
19	19	UART_RX
20	20	GND
21	21	UART_CTS
22	22	GND
23	23	UART_RTS
24	24	GND
25	25	3V3
26	26	3V3
27	27	3V3
28	28	3V3
29	29	GPIO
30	30	GND
31	31	RESET
32	32	GND
33	33	NC
34	34	NC
35	35	NC
36	36	NC
37	37	+5V_BUS
38	38	+5V_BUS
39	39	+5V_BUS
40	40	+5V_BUS

5.2 J102 SolderJumper_2_Open

J102 - SolderJumper_2_Open
Pin	Pin Name	Net	Notes
1	A	BOOT
2	B	GND

5.3 J103 SolderJumper_2_Open

J103 - SolderJumper_2_Open
Pin	Pin Name	Net	Notes
1	A	WL-EN
2	B	GND

5.4 J104 SolderJumper_2_Open

J104 - SolderJumper_2_Open
Pin	Pin Name	Net	Notes
1	A	BT-EN
2	B	GND

5.5 J105 SolderJumper_2_Open

J105 - SolderJumper_2_Open
Pin	Pin Name	Net	Notes
1	A	USBOTG_ID
2	B	GND

5.6 J106 SolderJumper_2_Open

J106 - SolderJumper_2_Open
Pin	Pin Name	Net	Notes
1	A	EEPROM_WP
2	B	GND

5.7 J107 Conn_01x02_Socket

J107 - Conn_01x02_Socket
Pin	Pin Name	Net	Notes
1	Pin_1	3V3	DNP
2	Pin_2	GND	DNP

5.8 J108 Conn_01x02_Socket

J108 - Conn_01x02_Socket
Pin	Pin Name	Net	Notes
1	Pin_1	+5V_BUS	DNP
2	Pin_2	GND	DNP

5.9 J201 DX07S016JA1R1500

J201 - DX07S016JA1R1500 (DX07S016JA1R1500)
Pin	Pin Name	Net	Notes
A1	GND	GND
A4	VBUS	+5V_USB
A5	CC1	USB_CC1
A6	D+	USB1_PI.D_P
A7	D-	USB1_PI.D_N
A8	SBU1	NC
A9	VBUS	+5V_USB
A12	GND	GND
B1	GND	GND
B4	VBUS	+5V_USB
B5	CC2	USB_CC2
B6	D+	USB1_PI.D_P
B7	D-	USB1_PI.D_N
B8	SBU2	NC
B9	VBUS	+5V_USB
B12	GND	GND
S1	SHIELD	GND

5.10 J202 533984004

J202 - 533984004 (533984004)
Pin	Pin Name	Net	Notes
1	1	+5V
2	2	USB2_PI.D_P
3	3	USB2_PI.D_N
4	4	GND

5.11 J501 MDT420M01002

J501 - MDT420M01002 (MDT420M01002)
Pin	Pin Name	Net	Notes
1	GND	GND	DNP
2	3.3V	+3V3_M.2	DNP
3	GND	GND	DNP
4	3.3V	+3V3_M.2	DNP
5	PERn3	NC
6	NC	NC
7	PERp3	NC
8	NC	NC
9	GND	GND	DNP
10	DAS/DSS/LED1	LED_M.2	DNP
11	PETn3	NC
12	3.3V	+3V3_M.2	DNP
13	PETp3	NC
14	3.3V	+3V3_M.2	DNP
15	GND	GND	DNP
16	3.3V	+3V3_M.2	DNP
17	PERn2	NC
18	3.3V	+3V3_M.2	DNP
19	PERp2	NC
20	NC	GPIO4	DNP
21	GND	GND	DNP
22	NC	GPIO5	DNP
23	PETn2	NC
24	NC	NC
25	PETp2	NC
26	NC	NC
27	GND	GND	DNP
28	NC	NC
29	PERn1	NC
30	NC	NC
31	PERp1	NC
32	NC	NC
33	GND	GND	DNP
34	NC	NC
35	PETn1	NC
36	NC	NC
37	PETp1	NC
38	DEVSLP	NC
39	GND	GND	DNP
40	NC	NC
41	PERn0	PCIE_PI.RX_N	DNP
42	NC	NC
43	PERp0	PCIE_PI.RX_P	DNP
44	NC	NC
45	GND	GND	DNP
46	NC	NC
47	PETn0	PCIE_PI.TX_N	DNP
48	NC	NC
49	PETp0	PCIE_PI.TX_P	DNP
50	PERST	PCIE_PI.nRST	DNP
51	GND	GND	DNP
52	CLKREQ	PCIE_PI.nCLKREQ	DNP
53	REFCLKn	PCIE_PI.CLK_N	DNP
54	PEWAKE	PCIE_PI.nWAKE	DNP
55	REFCLKp	PCIE_PI.CLK_P	DNP
56	NC	NC
57	GND	GND	DNP
58	NC	NC
67	NC	NC
68	SUSCLK	Net-(J501-SUSCLK)	DNP
69	PEDET	NC
70	3.3V	+3V3_M.2	DNP
71	GND	GND	DNP
72	3.3V	+3V3_M.2	DNP
73	GND	GND	DNP
74	3.3V	+3V3_M.2	DNP
75	GND	GND	DNP
S1	S1	GND	DNP
S2	S2	GND	DNP

5.12 J601 533984004

J601 - 533984004 (533984004)
Pin	Pin Name	Net	Notes
1	1	ETH_PI.TRD1_N
2	2	ETH_PI.TRD1_P
3	3	ETH_PI.TRD0_N
4	4	ETH_PI.TRD0_P

5.13 J701 FH12A-22S-0.5SH(55)

J701 - FH12A-22S-0.5SH(55) (FH12A-22S-0.5SH(55))
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	DPHY1_PI.D0_N
3	Pin_3	DPHY1_PI.D0_P
4	Pin_4	GND
5	Pin_5	DPHY1_PI.D1_N
6	Pin_6	DPHY1_PI.D1_P
7	Pin_7	GND
8	Pin_8	DPHY1_PI.C_N
9	Pin_9	DPHY1_PI.C_P
10	Pin_10	GND
11	Pin_11	DPHY1_PI.D2_N
12	Pin_12	DPHY1_PI.D2_P
13	Pin_13	GND
14	Pin_14	DPHY1_PI.D3_N
15	Pin_15	DPHY1_PI.D3_P
16	Pin_16	GND
17	Pin_17	CAM1_GPIO1
18	Pin_18	CAM1_GPIO2
19	Pin_19	GND
20	Pin_20	I2C_1_SCL
21	Pin_21	I2C_1_SDA
22	Pin_22	+3V3

5.14 J702 FH12A-22S-0.5SH(55)

J702 - FH12A-22S-0.5SH(55) (FH12A-22S-0.5SH(55))
Pin	Pin Name	Net	Notes
1	Pin_1	GND
2	Pin_2	DPHY2_PI.D0_N
3	Pin_3	DPHY2_PI.D0_P
4	Pin_4	GND
5	Pin_5	DPHY2_PI.D1_N
6	Pin_6	DPHY2_PI.D1_P
7	Pin_7	GND
8	Pin_8	DPHY2_PI.C_N
9	Pin_9	DPHY2_PI.C_P
10	Pin_10	GND
11	Pin_11	DPHY2_PI.D2_N
12	Pin_12	DPHY2_PI.D2_P
13	Pin_13	GND
14	Pin_14	DPHY2_PI.D3_N
15	Pin_15	DPHY2_PI.D3_P
16	Pin_16	GND
17	Pin_17	GPIO7
18	Pin_18	GPIO8
19	Pin_19	GND
20	Pin_20	I2C_2_SCL
21	Pin_21	I2C_2_SDA
22	Pin_22	+3V3

5.15 JP101 SolderJumper_2_Bridged

JP101 - SolderJumper_2_Bridged
Pin	Pin Name	Net	Notes
1	A	Net-(D101-K)
2	B	GND

5.16 JP102 SolderJumper_2_Bridged

JP102 - SolderJumper_2_Bridged
Pin	Pin Name	Net	Notes
1	A	Net-(D102-K)
2	B	GND

5.17 JP103 SolderJumper_2_Bridged

JP103 - SolderJumper_2_Bridged
Pin	Pin Name	Net	Notes
1	A	Net-(D103-K)
2	B	LED_PI_PWR

5.18 JP104 SolderJumper_2_Bridged

JP104 - SolderJumper_2_Bridged
Pin	Pin Name	Net	Notes
1	A	Net-(D104-K)
2	B	LED_PI_ACT

5.19 JP105 SolderJumper_2_Bridged

JP105 - SolderJumper_2_Bridged
Pin	Pin Name	Net	Notes
1	A	Net-(D105-K)
2	B	LED_ETH

5.20 JP106 SolderJumper_2_Bridged

JP106 - SolderJumper_2_Bridged
Pin	Pin Name	Net	Notes
1	A	Net-(D106-K)	DNP
2	B	LED_M.2	DNP

5.21 Module402 10164227-1001A1RLF

Module402 - 10164227-1001A1RLF (10164227-1001A1RLF)
Pin	Pin Name	Net	Notes
101	USB_OTG_ID	USBOTG_ID
102	PCIe_nCLKREQ	PCIE_PI.nCLKREQ
103	USB2_N	USB1_PI.D_N
104	PCIE_nWAKE	PCIE_PI.nWAKE
105	USB2_P	USB1_PI.D_P
106	PCIE_PWR_EN	M.2_PWR_EN
107	GND	GND
108	GND	GND
109	PCIe_nRST	PCIE_PI.nRST
110	PCIe_CLK_P	PCIE_PI.CLK_P
111	VBUS_EN	VBUS_EN
112	PCIe_CLK_N	PCIE_PI.CLK_N
113	GND	GND
114	GND	GND
115	MIPI0_D0_N	DPHY1_PI.D0_N
116	PCIe_RX_P	PCIE_PI.RX_P
117	MIPI0_D0_P	DPHY1_PI.D0_P
118	PCIe_RX_N	PCIE_PI.RX_N
119	GND	GND
120	GND	GND
121	MIPI0_D1_N	DPHY1_PI.D1_N
122	PCIe_TX_P	PCIE_PI.TX_P
123	MIPI0_D1_P	DPHY1_PI.D1_P
124	PCIe_TX_N	PCIE_PI.TX_N
125	GND	GND
126	GND	GND
127	MIPI0_C_N	DPHY1_PI.C_N
128	USB3-0-RX_N	USB3-0-RX_N
129	MIPI0_C_P	DPHY1_PI.C_P
130	USB3-0-RX_P	USB3-0-RX_P
131	GND	GND
132	GND	GND
133	MIPI0_D2_N	DPHY1_PI.D2_N
134	USB3-0-D_P	USB2_PI.D_P
135	MIPI0_D2_P	DPHY1_PI.D2_P
136	USB3-0-D_N	USB2_PI.D_N
137	GND	GND
138	GND	GND
139	MIPI0_D3_N	DPHY1_PI.D3_N
140	USB3-0-TX_N	USB3-0-TX_N
141	MIPI0_D3_P	DPHY1_PI.D3_P
142	USB3-0-TX_P	USB3-0-TX_P
143	HDMI1_HOTPLUG	HDMI1_HOTPLUG
144	GND	GND
145	HDMI1_SDA	HDMI1_SDA
146	HDMI1_TX2_P	HDMI1_D2_P
147	HDMI1_SCL	HDMI1_SCL
148	HDMI1_TX2_N	HDMI1_D2_N
149	HDMI1_CEC	HDMI1_CEC
150	GND	GND
151	HDMI0_CEC	HDMI_PI.CEC
152	HDMI1_TX1_P	HDMI1_D1_P
153	HDMI0_HOTPLUG	HDMI_PI.HOTPLUG
154	HDMI1_TX1_N	HDMI1_D1_N
155	GND	GND
156	GND	GND
157	USB3-1-RX_N	USB3-1-RX_N
158	HDMI1_TX0_P	HDMI1_D0_P
159	USB3-1-RX_P	USB3-1-RX_P
160	HDMI1_TX0_N	HDMI1_D0_N
161	GND	GND
162	GND	GND
163	USB3-1-D_P	USB3-1-D_P
164	HDMI1_CLK_P	HDMI1_CK_P
165	USB3-1-D_N	USB3-1-D_N
166	HDMI1_CLK_N	HDMI1_CK_N
167	GND	GND
168	GND	GND
169	USB3-1-TX_N	USB3-1-TX_N
170	HDMI0_TX2_P	HDMI_PI.D2_P
171	USB3-1-TX_P	USB3-1-TX_P
172	HDMI0_TX2_N	HDMI_PI.D2_N
173	GND	GND
174	GND	GND
175	MIPI1_D0_N	DPHY2_PI.D0_N
176	HDMI0_TX1_P	HDMI_PI.D1_P
177	MIPI1_D0_P	DPHY2_PI.D0_P
178	HDMI0_TX1_N	HDMI_PI.D1_N
179	GND	GND
180	GND	GND
181	MIPI1_D1_N	DPHY2_PI.D1_N
182	HDMI0_TX0_P	HDMI_PI.D0_P
183	MIPI1_D1_P	DPHY2_PI.D1_P
184	HDMI0_TX0_N	HDMI_PI.D0_N
185	GND	GND
186	GND	GND
187	MIPI1_C_N	DPHY2_PI.C_N
188	HDMI0_CLK_P	HDMI_PI.CK_P
189	MIPI1_C_P	DPHY2_PI.C_P
190	HDMI0_CLK_N	HDMI_PI.CK_N
191	GND	GND
192	GND	GND
193	MIPI1_D2_N	DPHY2_PI.D2_N
194	MIPI1_D3_N	DPHY2_PI.D3_N
195	MIPI1_D2_P	DPHY2_PI.D2_P
196	MIPI1_D3_P	DPHY2_PI.D3_P
197	GND	GND
198	GND	GND
199	HDMI0_SDA	HDMI_PI.SDA
200	HDMI0_SCL	HDMI_PI.SCL

6 Indicator Documentation

6 indicator device(s) found.

6.1 Indicator Assignments

Indicators
RefDes	Type	Color	Signal	Sheet	Notes
D106	WE 150060VS55040 LED G	-		blackwing-cm5-payload-v1.kicad_sch	No current-limiting resistor
D105	WE 150060VS55040 LED G	-	Net-(D105-K)	blackwing-cm5-payload-v1.kicad_sch	LOW = On; R105 (1k); A:Net-(D105-A) K:Net-(D105-K)
D102	SunLED XZFRS53FVF-1 LED P	-	Net-(D102-K)	blackwing-cm5-payload-v1.kicad_sch	LOW = On; R102 (3k3); A:Net-(D102-A) K:Net-(D102-K)
D104	WE 150060WS75000 LED W	-	Net-(D104-K)	blackwing-cm5-payload-v1.kicad_sch	LOW = On; R104 (39k); A:Net-(D104-A) K:Net-(D104-K)
D101	SunLED XZFRS53FVF-1 LED P	-	Net-(D101-K)	blackwing-cm5-payload-v1.kicad_sch	LOW = On; R101 (1k); A:Net-(D101-A) K:Net-(D101-K)
D103	SunLED XZFRS53FVF-1 LED P	-	Net-(D103-K)	blackwing-cm5-payload-v1.kicad_sch	LOW = On; R103 (3k3); A:Net-(D103-A) K:Net-(D103-K)

6.2 Indicator Testability

0 of 0 indicators have test coverage. 6 indicator(s) illuminate on their own (power-on / rail-fed / module-driven) and do not need a test point.

Indicator Testability
RefDes	Driver	Control Signal	DFT Status	Testable
D106	Direct		Power indicator	✓
D105	Direct	Net-(D105-K)	Driven by the mating module via JP105 — the off-board side owns the stimulus. No on-board test point applicable.	✓
D102	Direct	Net-(D102-K)	Driven by the mating module via JP102 — the off-board side owns the stimulus. No on-board test point applicable.	✓
D104	Direct	Net-(D104-K)	Driven by the mating module via JP104 — the off-board side owns the stimulus. No on-board test point applicable.	✓
D101	Direct	Net-(D101-K)	Driven by the mating module via JP101 — the off-board side owns the stimulus. No on-board test point applicable.	✓
D103	Direct	Net-(D103-K)	Driven by the mating module via JP103 — the off-board side owns the stimulus. No on-board test point applicable.	✓

7 Switch Documentation

2 switch(es) found in design.

7.1 Switch Configurations

SW101 Contact Pairs (CK KMS223GP LFG)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	PWR_BUT	3	GND	SIGNAL	LOW

SW101 All Pins
Pin #	Pin Name	Net	Paired With	Type
1	1	PWR_BUT	3	CONTACT
3	3	GND	1	CONTACT
4	4	GND	1	CONTACT
2	2	GND	1	CONTACT
5	5	PWR_BUT	3	CONTACT

SW102 Contact Pairs (CK KMS223GP LFG)
Contact	Pin A	Net A	Pin B	Net B	When Open	When Closed	Notes
1	1	RESET	3	GND	SIGNAL	LOW

SW102 All Pins
Pin #	Pin Name	Net	Paired With	Type
1	1	RESET	3	CONTACT
3	3	GND	1	CONTACT
4	4	GND	1	CONTACT
2	2	GND	1	CONTACT
5	5	RESET	3	CONTACT

7.2 Switch DFT Analysis

Switches for mode selection are useful for development and manual debug, but production test environments require electrical override capability. A latching switch (DIP, slide, toggle) holds the signal at the rail it closes onto until somebody moves it, so ATE cannot drive past the contact: it needs a test point and a series isolation resistor between the switch and that rail. A momentary switch (push button) does not hold the signal — the bias resistor sets the level again as soon as the button is released — so it needs only a test point for ATE stimulus access.

Design Rationale: Switches for mode selection are valuable for engineering development and bench debug. However, production test and field returns require electrical override capability without manual intervention. Adding test points and isolation resistors creates a lifecycle-robust design that works across development, production test, and field returns without requiring procedure documentation or specialized knowledge of switch positions. The goal is a self-documenting, procedure-proof test interface. BOM impact: One 0201/0402 resistor per controlled signal.

Switch	Signal	Function	Pullup	Rail	Issue	Test Point?
SW102	RESET	Reset/power-on-reset	(not found)	GND	No test point — Momentary — ATE needs probe access
SW101	PWR_BUT	Momentary control	(not found)	GND	No test point — Momentary — ATE needs probe access

8 Low-Speed Serial Interfaces (LSSI)

Detected: 3 I2C, 1 SPI, 2 UART

8.1 I2C

I2C: Module401
Topology: Module401 » Targets (J701)
Signal	Net Name	Connector	Test Point	Target Pin
SCL	I2C_1_SCL / I2C_1_SCL / CAM1_SCL	J701_20	(none)	Module401_80 (SCL0)
SDA	I2C_1_SDA / I2C_1_SDA / CAM1_SDA	J701_21	(none)	Module401_82 (SDA0)

I2C: Module401
Topology: Module401 » Targets (J702)
Signal	Net Name	Connector	Test Point	Target Pin
SCL	I2C_2_SCL / I2C_2_SCL / CAM2_SCL	J702_20	(none)	Module401_35 (ID_SC)
SDA	I2C_2_SDA / I2C_2_SDA / CAM2_SDA	J702_21	(none)	Module401_36 (ID_SD)

I2C: Module401 -> U103, U302, U801
Topology: Module401 » Targets (U103, U302, U801, J101)
Sig	Nets	Conn/TP	Target Pin
SCL	I2C_3_SCL » R107 » I2C_SCL	J101_5	Module401_56 (GPIO3), U103_4, U302_4 (SCL), U801_2 (SCL/SPC)
SDA	I2C_3_SDA » R108 » I2C_SDA	J101_7	Module401_58 (GPIO2), U103_6, U302_1 (SDA), U801_3 (SDA/SDI)
Address	Target	Industry Type	Description
	U103	TI TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages
0x08	U302	TDK FS1603A-5000-AL	Non-Isolated PoL Module, Digital DC DC Converter 1 Output 5V 3A 4.5V - 16V Input Address: port I²C serial bus (SCL on I2C_3_SCL), strap-set address - The default Base_address is 0x08; the base is user-programmable in memory. The resistor sets offsets 0 through 7. The ADDR pin may be left open when I²C communication is not used. SDA and SCL each need an external 4.99kΩ pull-up for bus operation. The user register Bus_voltage_sel selects 1.8–2.5V (default) or 3.3–5.0V bus operation, datasheet pages 2, 13 and 15., ADDR=GND (low)
0x68	U801	TDK IAM-20380	Gyroscope X (Pitch), Y (Roll), Z (Yaw) ±250, 500, 1000, 2000 27kHz I2C, SPI 16-LGA (3x3) Address: port I2C (SCL/SPC on I2C_3_SCL), strap-set address, SA0/SDO=GND (low)

I2C Pull-up Check
Net	Component	Status
I2C_1_SDA		Pull-up not found on I2C_1_SDA as a resistor on this board. Module401 pulls this line high itself: its datasheet states a pull-up on Module401_82 (SDA0) (1.8k), so no resistor is needed on the board. The designer's note on sheet cm5 says: "External pull-ups have been omitted for I2C 1-3. Selected GPIOs have internal 1.8K P/Us.".	✓
I2C_1_SCL		Pull-up not found on I2C_1_SCL as a resistor on this board. Module401 pulls this line high itself: its datasheet states a pull-up on Module401_80 (SCL0) (1.8k), so no resistor is needed on the board. The designer's note on sheet cm5 says: "External pull-ups have been omitted for I2C 1-3. Selected GPIOs have internal 1.8K P/Us.".	✓
I2C_2_SDA		Pull-up not found on I2C_2_SDA. This bus is mastered on-board by Module401 and its addressable targets are off-board through J702; the interface standard for the attached device determines which side supplies the pull-up - confirm it is provided there. The designer's note on sheet cm5 says: "External pull-ups have been omitted for I2C 1-3. Selected GPIOs have internal 1.8K P/Us.". The datasheet of Module401 states no pull-up on Module401_36 (ID_SD); the weak bias every GPIO has is not an I2C pull-up, so this line needs a resistor on this board or in the attached device.	✓
I2C_2_SCL		Pull-up not found on I2C_2_SCL. This bus is mastered on-board by Module401 and its addressable targets are off-board through J702; the interface standard for the attached device determines which side supplies the pull-up - confirm it is provided there. The designer's note on sheet cm5 says: "External pull-ups have been omitted for I2C 1-3. Selected GPIOs have internal 1.8K P/Us.". The datasheet of Module401 states no pull-up on Module401_35 (ID_SC); the weak bias every GPIO has is not an I2C pull-up, so this line needs a resistor on this board or in the attached device.	✓
I2C_SDA		Pull-up not found on I2C_SDA as a resistor on this board. Module401 pulls this line high itself: its datasheet states a pull-up on Module401_58 (GPIO2) (1.8k), so no resistor is needed on the board. The designer's note on sheet cm5 says: "External pull-ups have been omitted for I2C 1-3. Selected GPIOs have internal 1.8K P/Us.".	✓
I2C_SCL		Pull-up not found on I2C_SCL as a resistor on this board. Module401 pulls this line high itself: its datasheet states a pull-up on Module401_56 (GPIO3) (1.8k), so no resistor is needed on the board. The designer's note on sheet cm5 says: "External pull-ups have been omitted for I2C 1-3. Selected GPIOs have internal 1.8K P/Us.".	✓

8.2 SPI

SPI: Module401 -> U802
Topology: Module401 » Targets (U802, TP110, J101)
Sig	Nets	Conn/TP	Target Pin
MOSI	SPI_1_PICO	-	-
MISO	SPI_1_POCI » R801 » Net-(U802-SO)	-	U802_2 (SO)
SCK	SPI_1_SCL » R402 » SCLK_GPIO21_PT	-	Module401_25 (GPIO21), U802_6 (SCK)
CS	SPI_1_CS » R403 » CS_GPIO24_PT	J101_15 / TP110_1	Module401_45 (GPIO24), U802_1 (CS)
Target	CS Net	Industry Type	Description
U802	SPI_1_CS (1 CS)	Infineon CY15B102Q-SXET	FRAM (Ferroelectric RAM) Memory IC 2Mbit SPI 25 MHz 8-SOIC

8.3 UART

UART [UART]
Topology: Access (J101, TP114, TP115)
Signal	Net Name	Connector	Test Point
TX	UART_TX / UART_TX	J101_17	TP115_1
RX	UART_RX / UART_RX	J101_19	TP114_1

UART [UART_1] -> Module401
Topology: Access (J101, TP114, TP115) » Targets (Module401)
Sig	Nets	Conn/TP	Target Pin
TX	UART_1_TX » R114 » UART_RX	J101_19 / TP114_1	Module401_55 (GPIO14)
RX	UART_1_RX » R113 » UART_TX	J101_17 / TP115_1	Module401_51 (GPIO15)
Target	Industry Type	Description
Module401	CM5 GPIO	Amphenol 10164227-1001A1RLF

8.4 LSSI DFT Analysis

8 signal(s) missing test point coverage. Test points allow ATE to run tests without requiring operator intervention and setup. They should be considered mandatory for high volume products.

During test, ATE can override functional operation to explicitly test through the interface in ways that functional operation cannot, or is not available at certain test stages.

Missing Test Points
Signal	Net Name	Connector	Interface
SCL	I2C_1_SCL	J701_20	I2C: Module401
SDA	I2C_1_SDA	J701_21	I2C: Module401
SCL	I2C_2_SCL	J702_20	I2C: Module401
SDA	I2C_2_SDA	J702_21	I2C: Module401
CS	CS_GPIO24_PT	J101_15	SPI: Module401 -> U802
MISO	Net-(U802-SO)	(none)	SPI: Module401 -> U802
MOSI	SPI_1_PICO	(none)	SPI: Module401 -> U802
SCK	SCLK_GPIO21_PT	(none)	SPI: Module401 -> U802

9 High-Speed Serial Interfaces (HSSI)

64 differential pair(s), 25 single-ended controlled impedance signal(s), 10 controlled impedance path(s)

Differential pairs detected from _P/_N naming convention which KiCad uses for differential pair identification. Designer should consider explicit assignment to distinct net classes for each SERDES type to explicitly document layout intent.

8 HDMI differential pair(s) have no controlled-impedance net class assigned. Assign a 100 Ohm differential net class so the impedance intent carries into PCB layout and length tuning.

9.1 Differential Pairs

Differential pairs with designer-specified class annotations.

8 of 32 differential pairs do not specify a target impedance (the Impedance column is blank). Strongly suggested: put the value in the class name - e.g. 100_OHM.

Differential Pairs
Net Name	Class	Impedance	Notes
DPHY1_PI.C_P/N	100Ω differential	100 Ohm
DPHY1_PI.D0_P/N	100Ω differential	100 Ohm
DPHY1_PI.D1_P/N	100Ω differential	100 Ohm
DPHY1_PI.D2_P/N	100Ω differential	100 Ohm
DPHY1_PI.D3_P/N	100Ω differential	100 Ohm
DPHY2_PI.C_P/N	100Ω differential	100 Ohm
DPHY2_PI.D0_P/N	100Ω differential	100 Ohm
DPHY2_PI.D1_P/N	100Ω differential	100 Ohm
DPHY2_PI.D2_P/N	100Ω differential	100 Ohm
DPHY2_PI.D3_P/N	100Ω differential	100 Ohm
ETH_PI.TRD0_P/N	100Ω differential	100 Ohm
ETH_PI.TRD1_P/N	100Ω differential	100 Ohm
ETH_PI.TRD2_P/N	100Ω differential	100 Ohm
ETH_PI.TRD3_P/N	100Ω differential	100 Ohm
PCIE_PI.CLK_P/N	90Ω differential	90 Ohm
PCIE_PI.RX_P/N	90Ω differential	90 Ohm
PCIE_PI.TX_P/N	90Ω differential	90 Ohm
USB1_PI.D_P/N	90Ω differential	90 Ohm
USB2_PI.D_P/N	90Ω differential	90 Ohm
USB3-0-RX_P/N	90Ω differential	90 Ohm
USB3-0-TX_P/N	90Ω differential	90 Ohm
USB3-1-D_P/N	90Ω differential	90 Ohm
USB3-1-RX_P/N	90Ω differential	90 Ohm
USB3-1-TX_P/N	90Ω differential	90 Ohm
HDMI1_CK_P/N	HDMI
HDMI1_D0_P/N	HDMI
HDMI1_D1_P/N	HDMI
HDMI1_D2_P/N	HDMI
HDMI_PI.CK_P/N	HDMI
HDMI_PI.D0_P/N	HDMI
HDMI_PI.D1_P/N	HDMI
HDMI_PI.D2_P/N	HDMI

9.2 Controlled Impedance Signals

Single-ended signals requiring controlled impedance. Grouped by target impedance value.

90 Ohm Signals
Net Name	Impedance Class	Notes
PCIE_PI.nCLKREQ	90Ω differential
PCIE_PI.nRST	90Ω differential
PCIE_PI.nWAKE	90Ω differential

50 Ohm Signals
Net Name	Impedance Class	Notes
I2C_1_SCL	50Ω single-ended
I2C_1_SDA	50Ω single-ended
I2C_2_SCL	50Ω single-ended
I2C_2_SDA	50Ω single-ended
I2C_3_SCL	50Ω single-ended
I2C_3_SDA	50Ω single-ended
I2C_4_SCL	50Ω single-ended
I2C_4_SDA	50Ω single-ended
I2C_SCL	50Ω single-ended
I2C_SDA	50Ω single-ended
SPI_1_CS	50Ω single-ended
SPI_1_PICO	50Ω single-ended
SPI_1_POCI	50Ω single-ended
SPI_1_SCL	50Ω single-ended
SPI_2_CS	50Ω single-ended
SPI_2_PICO	50Ω single-ended
SPI_2_POCI	50Ω single-ended
SPI_2_SCL	50Ω single-ended
SPI_CS0	50Ω single-ended
SPI_PICO	50Ω single-ended
SPI_POCI	50Ω single-ended
SPI_SCK	50Ω single-ended

9.3 Controlled Impedance Paths

Signal paths through inline components (capacitors, inductors, chokes, resistors) where at least one net segment has a controlled impedance class. Each row shows the full endpoint-to-endpoint path.

Controlled Impedance Paths
From	To	Components	Net Path	Status
U802_5	Module401_27	R401	SPI_1_PICO (50Ω single-ended) » PICO_GPIO20_PT (-)
Module401_26	U802_2	R801	SPI_1_POCI (50Ω single-ended) » Net-(U802-SO) (-)
U802_1	Module401_45	R403	SPI_1_CS (50Ω single-ended) » CS_GPIO24_PT (-)
U802_6	Module401_25	R402	SPI_1_SCL (50Ω single-ended) » SCLK_GPIO21_PT (-)
J101_5	Module401_56	R107	I2C_SCL (50Ω single-ended) » I2C_3_SCL (50Ω single-ended)	✓ All 50Ω single-ended
J101_9	Module401_44	R109	SPI_PICO (50Ω single-ended) » SPI_2_PICO (50Ω single-ended)	✓ All 50Ω single-ended
J101_7	Module401_58	R108	I2C_SDA (50Ω single-ended) » I2C_3_SDA (50Ω single-ended)	✓ All 50Ω single-ended
J101_15	Module401_46	R112	SPI_CS0 (50Ω single-ended) » SPI_2_CS (50Ω single-ended)	✓ All 50Ω single-ended
J101_11	Module401_40	R110	SPI_POCI (50Ω single-ended) » SPI_2_POCI (50Ω single-ended)	✓ All 50Ω single-ended
J101_13	Module401_38	R111	SPI_SCK (50Ω single-ended) » SPI_2_SCL (50Ω single-ended)	✓ All 50Ω single-ended

9.4 HSSI Checks

Impedance continuity across controlled impedance paths. Each path is traced end-to-end through inline components (capacitors, inductors, chokes, resistors) and verified to have consistent impedance class assignments on every net segment.

10 controlled impedance path(s) checked for continuity. 6 pass, 4 fail.

Net segments along controlled impedance paths are missing an impedance class assignment or have mismatched values. Layout may not route these segments at controlled impedance, creating a discontinuity.

Impedance Class Errors
Nets	Expected Class	Components	From	To
PICO_GPIO20_PT	50Ω single-ended	R401	U802_5	Module401_27
Net-(U802-SO)	50Ω single-ended	R801	Module401_26	U802_2
CS_GPIO24_PT	50Ω single-ended	R403	U802_1	Module401_45
SCLK_GPIO21_PT	50Ω single-ended	R402	U802_6	Module401_25

9.5 AI-Assisted Analysis

9.5.1 CSI-2 Camera Interfaces (J701, J702)

AI-Assisted — The CM5 has two 4-lane MIPI D-PHY ports. MIPI0 is on Module402 pins 115 to 141 and runs on nets DPHY1_PI.*; it shares camera I2C_1 on SCL0/SDA0 (Module401_80/82) with J701. MIPI1 is on Module402 pins 175 to 196 and runs on nets DPHY2_PI.*; it shares I2C_2 on ID_SC/ID_SD (Module401_35/36) with J702. The receptacles are 22-pin 0.5 mm FPC connectors, so both ports carry camera-direction CSI-2 over D-PHY.

The Raspberry Pi Ltd CM5 datasheet (source: Tomachie) requires 100 Ω differential impedance and at most 0.15 mm intra-pair mismatch (p.10). Both the CM5-side DPHY*_PI nets and the connector-side DPHY*_C nets carry a 100 Ω differential class.

D-PHY switches between low-power single-ended signalling and high-speed differential signalling on the same pair. The lanes must therefore stay DC-coupled, and high-speed termination sits on-die in the receiver. The lanes have no series capacitors and no external terminators, which is correct.

The CM5-side lane nets contain only the Module402 pins. Nothing in the schematic shows which element joins them to the DPHY1_C and DPHY2_C nets, so the loss and impedance of that link were not assessed.

J701 and J702 interleave ground on pins 1, 4, 7, 10, 13, 16 and 19, which follows the Raspberry Pi 22-pin camera arrangement. CAM_GPIO0 reaches J701_17 and CAM_GPIO1 reaches J701_18, as the CM5 datasheet recommends (pp.14, 21). Note that the net carrying CAM_GPIO0 is labelled CAM1_GPIO1. J702 uses GPIO7 and GPIO8 for its pins 17 and 18 instead.

9.5.2 USB 2.0, USB 3.0 and USB-C (J201, J202)

AI-Assisted — There are two USB 2.0 pairs on the CM5 side. USB1_PI.D_P/N is on Module402 USB2_P/USB2_N (pins 105/103), the OTG-capable port that the designer's notes assign to the Type-C device connector J201. USB2_PI.D_P/N is on Module402 USB3-0-D_P/N (pins 134/136) and serves the PicoBlade host connector J202. Both pairs carry a 90 Ω differential class, matching the 90 Ω the CM5 datasheet requires (p.9), with a 0.15 mm intra-pair limit.

USB 2.0 high-speed is DC-coupled with on-chip termination, so no series parts are required. As with the camera lanes, the CM5-side nets contain only the module pins. No element joining them to the connector-side nets USB1_C.D_P/N and USB2_C.D_P/N is drawn. If the link is genuinely absent, J201 has no data path, and the designer's note relies on that path for RPIBOOT firmware install.

J201_A5/B5 CC1/CC2 go to Module401_94/96, as the CM5 datasheet requires for USB-PD negotiation (pp.14, 21). J105, an open solder jumper, leaves USB_OTG_ID floating, which gives device/OTG operation.

J202 is a 1.25 mm wire-to-board header and is not impedance-controlled. Its VBUS pin, J202_1, sits directly on +5V. VBUS_EN (Module402_111) goes nowhere, so the CM5 cannot switch host-port power.

Both USB 3.0 SuperSpeed ports have their TX/RX pairs ending at the Module402 pins. They are unused, they carry a 90 Ω class, and their TX coupling capacitors are on the CM5 (p.9).

9.5.3 PCIe Gen 2 and HDMI (Unused)

AI-Assisted — The designer's note on the top sheet states that the M.2 card is not implemented in this version. PCIE_PI.TX, PCIE_PI.RX and the 100 MHz PCIE_PI.CLK pairs each end at a single Module402 pin. They carry a 90 Ω class, which matches the CM5 datasheet's PCIe requirement (p.9).

The datasheet requires 220 nF series capacitors on PCIe_RX near the peripheral transmitter (p.9). That requirement applies only once a device is fitted. PCIE_nWAKE may be left unconnected (p.21). PCIe_CLK_nREQ must be driven to obtain the reference clock, which matters only when a device is fitted.

The single-ended sideband nets PCIE_PI.nRST, PCIE_PI.nCLKREQ and PCIE_PI.nWAKE carry a 90 Ω differential class. That class does not fit single-ended reset, request and wake lines.

All sixteen HDMI0/HDMI1 TMDS nets are single-pin labels on Module402 with no impedance class. The CM5 requires 100 Ω differential impedance for HDMI (p.10). HDMI0/HDMI1 SDA and SCL have internal 1.8 kΩ pull-ups, and CEC has internal 27 kΩ pull-ups (pp.22-23), so leaving these pins open is acceptable.

9.5.4 Ethernet

AI-Assisted — ETH_PI.TRD0 to TRD3 are on Module401 pins 3 to 12 and carry a 100 Ω differential class. This matches the 100 Ω and 0.15 mm intra-pair mismatch that the CM5 datasheet sets for Ethernet (p.8).

On the connector side only ETH_C.TRD0 and ETH_C.TRD1 exist. They are grouped as differential pairs but have no impedance class, which leaves the 100 Ω requirement out of the layout constraints for that segment.

No element joining the ETH_PI pairs to the ETH_C pairs is identified. ETH_PI.TRD2 and ETH_PI.TRD3 have no connector-side counterpart.

The datasheet's reference schematic places a 100 nF capacitor on the magnetics centre tap and TPD4EUSB30 arrays on the pairs (p.8). None of the Ethernet nets reviewed here carries such parts.

9.6 Findings

AI-Assisted —

#	Interface	Protocol	Finding	Severity
9.6.1	Ethernet (connector side)	Ethernet	ETH_C.TRD0_P/N and ETH_C.TRD1_P/N are grouped as differential pairs but have no impedance class. Assign a 100 Ω differential class (CM5 datasheet p.8).	Low
9.6.2	SPI1 (U802)	SPI	PICO_GPIO20_PT, SCLK_GPIO21_PT, CS_GPIO24_PT and Net-(U802-SO) carry no impedance class, while their partner segments across R401, R402, R403 and R801 carry 50 Ω single-ended. Assign the 50 Ω class to all four nets.	Low
9.6.3	SPI1 (U802)	SPI	U802_3 W̅P̅ is tied directly to +3V3, so the Status Register block-protect bits are writable at all times (Infineon CY15B102Q datasheet p.7). Route W̅P̅ to a spare CM5 GPIO with a pull-down to GND, so firmware holds the block-protect bits protected and raises W̅P̅ only to change them.	Low
9.6.4	CSI-2 camera 0/1	MIPI D-PHY	DPHY1_PI.* and DPHY2_PI.* contain only the Module402 MIPI0/MIPI1 pins, and no element joining them to DPHY1_C.* and DPHY2_C.* toward J701/J702 is identified. Check that every lane reaches J701/J702 pins 2-15 and that any series element at that boundary is suited to D-PHY high-speed rates.	Review
9.6.5	CSI-2 connectors J701, J702	MIPI CSI-2	FH12A-22S-0.5SH(55) 22-pin 0.5 mm FPC connectors with GND on pins 1, 4, 7, 10, 13, 16 and 19 between lane pairs, following the Raspberry Pi 22-pin camera arrangement.	Review
9.6.6	Camera I2C_2 (J702)	I2C	I2C_2_SCL and I2C_2_SDA (J702_20/21) are on ID_SC/ID_SD, which is MIPI1's I2C (CM5 datasheet pp.11, 19). The datasheet states no internal pull-up for these pins and none is fitted on the board, so the bus depends on pull-ups on the camera module attached at J702. Otherwise, fit pull-ups from both lines to +3V3.	Review
9.6.7	USB 2.0 (J201, J202)	USB 2.0 High-Speed	The CM5-side USB1_PI and USB2_PI nets contain only the Module402 pins, and no element joining them to USB1_C.D_P/N and USB2_C.D_P/N is identified. Check the link: without it, J201's device port, which the designer's note uses for RPIBOOT firmware install, has no data path.	Review
9.6.8	USB host connector J202	USB 2.0 High-Speed	J202 is a 1.25 mm PicoBlade wire-to-board header and is not impedance-controlled. Keep the mating harness a short 90 Ω twisted pair for 480 Mb/s.	Review
9.6.9	USB host VBUS (J202)	USB 2.0	J202_1 VBUS is wired directly to +5V, and VBUS_EN (Module402_111) has no connection. The CM5 datasheet uses VBUS_EN to drive an external port power switch (p.9). As drawn, the CM5 cannot remove host-port power, and the port is limited only by U301's current limit.	Review
9.6.10	PCIe sideband	PCIe Gen 2	PCIE_PI.nRST, PCIE_PI.nCLKREQ and PCIE_PI.nWAKE are single-ended but carry a 90 Ω differential class. Move them to a single-ended class before the M.2 path is implemented.	Review
9.6.11	HDMI0, HDMI1	HDMI TMDS	All sixteen TMDS nets are unused single-pin labels on Module402 with no impedance class. The CM5 requires 100 Ω (p.10) if they are routed. DDC and CEC have internal pull-ups, so leaving the pins open is acceptable (pp.22-23).	Review
9.6.12	Ethernet	Ethernet	No element joining the ETH_PI pairs to the ETH_C pairs is identified, and ETH_PI.TRD2 and TRD3 have no connector-side counterpart. Check the pair mapping to the magnetics.	Review
9.6.13	SPI1 (U802)	SPI	U802 SCK is specified at 25 MHz maximum, with tCH/tCL of 18 ns minimum (Infineon CY15B102Q datasheet p.15). Check that the CM5 SPI1 clock is set at or below 25 MHz.	Review
9.6.14	SPI1 (U802)	SPI	U802 must not see C̅S̅ low until 1 ms (tPU) after VDD reaches 2.0 V (Infineon CY15B102Q datasheet p.17). Check that the CM5's first access to U802 occurs at least 1 ms after +3V3 rises.	Review
9.6.15	Camera control J702	GPIO	J702_17 and J702_18 are driven from GPIO7 and GPIO8 (Module401_37/39), a designer's choice the CM5 permits for general GPIO. Using the CAM_GPIO pins is the alternative, but both of them already serve J701.	Info
9.6.16	USB OTG ID	USB 2.0	USB_OTG_ID goes to GND only through the open solder jumper J105. Open, the port operates as a device/OTG peripheral; shorted, it takes the host role with the correct OS driver (CM5 datasheet p.21).	Info
9.6.17	USB 3.0 ports 0/1	USB 3.0 SuperSpeed	Both ports' TX/RX pairs end at Module402 pins and are unused. They carry a 90 Ω class, and TX coupling capacitors are on the CM5 (CM5 datasheet p.9). No action is needed.	Info
9.6.18	PCIe x1	PCIe Gen 2	Unused per the designer's note on the top sheet. TX, RX and the 100 MHz CLK end at Module402 pins with a 90 Ω class. The 220 nF RX coupling-capacitor requirement (p.9) applies once a device is fitted, and PCIE_nWAKE may stay unconnected (p.21).	Info
9.6.19	CSI-2 camera 0/1 (J701, J702)	MIPI CSI-2 over D-PHY	DPHY1_PI., DPHY2_PI., DPHY1_C.* and DPHY2_C.* lanes all carry a 100 Ω differential class. This matches the 100 Ω the CM5 requires (Raspberry Pi Ltd CM5 datasheet p.10, source: Tomachie).	✓
9.6.20	CSI-2 camera 0/1	MIPI D-PHY	The lanes have no series capacitors. D-PHY is DC-coupled because the same pairs carry low-power single-ended signalling, so none are required. High-speed termination is on-die in the CM5 receiver (MIPI D-PHY specification).	✓
9.6.21	Camera control J701	GPIO	CAM_GPIO0 (Module401_97) goes to J701_17 and CAM_GPIO1 (Module401_100) to J701_18, as the CM5 datasheet recommends (pp.14, 21). The net on CAM_GPIO0 is labelled CAM1_GPIO1, a naming inconsistency only.	✓
9.6.22	Camera I2C_1 (J701)	I2C	I2C_1_SCL and I2C_1_SDA (J701_20/21) are on SCL0/SDA0, which have internal 1.8 kΩ pull-ups to CM5_3.3V. No external pull-up is needed (CM5 datasheet pp.19-20).	✓
9.6.23	USB 2.0 (J201, J202)	USB 2.0 High-Speed	USB1_PI.D_P/N (Module402_105/103) and USB2_PI.D_P/N (Module402_134/136) carry a 90 Ω differential class, matching the CM5 requirement (p.9).	✓
9.6.24	USB-C CC (J201)	USB Type-C / PD	J201_A5 CC1 and J201_B5 CC2 go to Module401_94/96, as the CM5 requires for USB-PD power negotiation (CM5 datasheet pp.14, 21; USB Type-C specification).	✓
9.6.25	Ethernet (CM5 side)	Ethernet	ETH_PI.TRD0-TRD3 (Module401 pins 3-12) carry a 100 Ω differential class, matching the CM5 requirement (p.8).	✓
9.6.26	SPI1 (U802)	SPI	There is a 22 Ω series resistor at each driver: R401, R402 and R403 on the CM5-driven lines and R801 on U802 SO.	✓
9.6.27	SPI1 (U802)	SPI	Logic levels are compatible. GPIO_VREF is on +3V3, giving 3.3 V signalling (CM5 p.20). CM5 VOH is at least 2.9 V against the U802 VIH minimum of 2.31 V (2.43 V at 3.465 V), and CM5 VOL is at most 0.4 V against VIL 0.99 V. U802 VOH is at least 3.1 V and VOL at most 0.2 V, against CM5 VIH 2.0 V and VIL 0.8 V. Sources: CM5 pp.26-27; Infineon CY15B102Q datasheet p.12, Datasheet	✓
9.6.28	SPI1 (U802)	SPI	C̅S̅ has R802 (10 kΩ) from SPI_1_CS to +3V3, holding the device deselected while the CM5 GPIO is undriven. H̅O̅L̅D̅ has R803 (10 kΩ) from FRAM_H̅O̅L̅D̅ to +3V3, meeting the datasheet's tie-high requirement (pp.3, 10) while GPIO18 retains control.	✓
9.6.29	Payload SPI2 / I2C_3 (J101)	SPI / I2C	SPI_2 and I2C_3 paths through R107-R112 (22 Ω) carry a 50 Ω single-ended class on both segments. The ESD arrays U101-U103 add at most 0.95 pF per line (TI TPD4E1B06 datasheet p.5, Datasheet).	✓

9.7 Citations

AI-Assisted —

References
CY15B102Q (Cypress Semiconductor Corporation) — datasheet www.infineon.com/dgdl/Infineon-CY15B102Q_2-Mbit_(256_K_8)...
M2_Socket3_Key_M — PCI Express M.2 Specification Rev 0.7, Table 49 (PDF p.150), Table 42 (p.139) pcisig.com/specifications
TPD4E1B06 (Texas Instruments) — datasheet www.ti.com/lit/gpn/TPD4E1B06

10 Memory Interface Analysis

No memory devices with detectable bus interfaces found.

10.1 AI-Assisted Analysis

Memory Interface Analysis AI enrichment was not selected.

11 Functional Analysis

14 device(s) to review across 4 category(ies)

Device Inventory
RefDes	Category	Part Number	Description	Interfaces	HSSI
BT401	BATTERY	Keystone 2998	Battery Retainer Coin, 6.8mm 1x 6.8x2.1mm cell	-	-
U101	DEVICE	TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages	-	-
U102	DEVICE	TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages	-	-
U103	DEVICE	TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages	I2C	-
U201	DEVICE	TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages	-	-
U202	DEVICE	TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages	-	-
U401	DEVICE	SN74AHCT1G04DBVR	Single NOT Gate, Low-Voltage CMOS	-	-
U601	DEVICE	TPD4E1B06DRLR	Quad 0.7-pF, ±5.5-V, ±12-kV ESD protection diode with 0.5-nA max leakage in SOT & SC70 packages	-	-
D101	DIODE	XZFRS53FVF-1	Cosmic Violet LED, diffused, 3.3V, 0603	-	-
D102	DIODE	XZFRS53FVF-1	Cosmic Violet LED, diffused, 3.3V, 0603	-	-
D103	DIODE	XZFRS53FVF-1	Cosmic Violet LED, diffused, 3.3V, 0603	-	-
D104	DIODE	150060WS75000	White LED, diffused, 2.8V, 0603	-	-
D105	DIODE	150060VS55040	Green 573nm LED, diffused, 2V, 0603	-	-
U801	SENSOR	IAM-20380	Gyroscope X (Pitch), Y (Roll), Z (Yaw) ±250, 500, 1000, 2000 27kHz I2C, SPI 16-LGA (3x3)	I2C	-

11.1 Reset-Time Strap Configuration

Each device below takes part of its start-up configuration from resistors the board fits on pins it samples at reset. Every setting is resolved against that device's own datasheet tables - the combination this board selects, and whether the datasheet marks that combination reserved or invalid.

RefDes	Pin	Read From	Sets
Module401	nRPIBOOT (Module401_93)	open (no strap resistor fitted)	boot source during startup = normal boot source (eMMC); pin not used, left floating
Module401	EEPROM_nWP (Module401_20)	open (no strap resistor fitted)	hardware write protection on the on-board boot EEPROM = EEPROM not write-protected (leave floating)
Module401	SD_VDD_OVERRIDE (Module401_73)	open (no strap resistor fitted)	SD card/eMMC (SDIO) interface signalling voltage = 3.3 V signalling on the SD card/eMMC interface
Module401	USB_OTG_ID		the datasheet's pin 101 is not on this symbol - a reset-time strap that cannot be wired or checked

11.2 Functional Analysis

11.2.1 BT401 RTC Backup Battery Holder

AI-Assisted — BT401 holds the RTC backup cell on sheet cm5. Its negative contact is on GND. Contact P2 is on VBAT_RTC together with Module401_76 VBAT and the D401 cathode. The designer left BT401_P1 unconnected.

The charge path runs from +3V3 through R406 (10 kΩ) into the D401 anode. D401's cathode is on VBAT_RTC, so +3V3 can charge the cell while the cell cannot back-feed +3V3. R406 is drawn and marked not fitted. On this build the D401 anode is therefore open and the cell is never charged, which matches the non-rechargeable option in the designer's note. That note, however, tells the assembler to fit or omit R805, and no R805 is drawn; the part in that position is R406.

With R406 fitted, the cell floats one D401 forward drop below +3V3. The 25 °C 'Forward Voltage' graph in the onsemi BAS116L datasheet (p.3, Datasheet) reads 0.68 V at its lowest plotted current, 0.105 mA. At the microamp currents near end of charge the drop is smaller and is not characterised. The float level is therefore above 2.62 V and below 3.3 V.

The VBAT range itself is covered in the power review.

11.2.2 Payload Connector ESD Arrays U101, U102, U103

AI-Assisted — U101, U102 and U103 are quad TPD4E1B06DRLR arrays on the CM5 side of the 22 Ω series resistors R107-R118 toward J101. Whether this protection sequence is correct is left to the EMC/ESD review.

The channels are assigned as follows. U101 carries R̅E̅S̅E̅T̅ (PMIC_ENABLE), GPIO2_BUS, UART_1_RTS and UART_1_CTS. U102 carries UART_1_TX, UART_1_RX, SPI_2_SCL and SPI_2_CS. U103 carries SPI_2_POCI, SPI_2_PICO, I2C_3_SCL and I2C_3_SDA.

GPIO_VREF is on +3V3, so the GPIO channels see at most 3.465 V. That is inside the ±5.5 V standoff and the 5.5 V pin-to-pin limit (TI TPD4E1B06 datasheet p.4-5, Datasheet). The CM5 sets the idle level of PMIC_ENABLE internally.

The array's protection level is a minimum breakdown of 7 V at 1 mA, with clamping of 10.9 V typical at 1 A and 14.5 V at 3 A, both 8/20 µs (p.5). U103's I²C channels share their node directly with U801_2 and U801_3. Those pins have an absolute maximum of VDDIO + 0.5 V, which is 3.635-3.965 V across the +3V3 band (TDK IAM-20380 datasheet p.44, Datasheet). U801's absolute maximum is crossed well before U103 reaches its breakdown. U801's own input structures therefore carry whatever surge current R107 and R108 let through.

U302_4 and U302_1 are on the same node. The remaining channels reach only CM5 GPIOs and test points.

11.2.3 USB Host and Ethernet ESD Arrays U202, U601

AI-Assisted — U202 protects the J202 USB host header. U202_1 is on USB2_C.D_N, U202_3 on USB2_C.D_P and U202_4 on +5V (J202_1 VBUS). Channel U202_6 and NC pin U202_5 are left unconnected by the designer.

USB 2.0 signalling stays below 3.6 V, inside the ±5.5 V standoff. +5V reaches 5.50 V at the top of the +5V_USB band through U301. That equals the 5.5 V standoff and the 5.5 V pin-to-pin limit (TI TPD4E1B06 datasheet p.4-5), so it is adequate but leaves no headroom.

On +5V the array begins breakdown at 7 V minimum at 1 mA and clamps at 10.9 V typical at 1 A, 8/20 µs. U401_5 VCC is on the same net with no series resistance, and its absolute maximum is 7 V (TI SN74AHCT1G04 datasheet p.4, Datasheet). U401 states no transient rating, so that absolute maximum is the bound. The VBUS channel therefore protects U401 only from the level at which U401's own rating ends.

U601 protects the four ETH_C.TRD0 and ETH_C.TRD1 lines at J601. Per the designer's note, the magnetics are on the external switch. The 0.95 pF maximum line capacitance and 3.4 Gbps channel capability easily cover 480 Mb/s USB and 100 Mb/s Ethernet. The MDI levels that the CM5 PHY presents to U601 are set inside the CM5.

11.2.4 U401 Power LED Inverter

AI-Assisted — U401 (SN74AHCT1G04) is supplied from +5V on U401_5 and returns on GND at U401_3. Across this board's +5V band of about 4.67 V to 5.50 V it sits inside the 4.5-5.5 V recommended VCC range (TI SN74AHCT1G04 datasheet p.4).

No bypass capacitor is drawn on sheet cm5 at U401_5. The nearest +5V capacitors are C101 and C102 (0.1 µF), which are on another sheet. The datasheet shows and recommends a 0.1 µF bypass at VCC (p.9-10).

Input U401_2 is on LED_PI_P̅W̅R̅, driven by Module401_95 LED_nPWR. Its TTL thresholds are VIH 2 V minimum and VIL 0.8 V maximum. Output U401_4 sinks D103 through the bridged JP103.

The inverter reverses the sense of the CM5 output. D103 lights when LED_nPWR is high, that is, when the active-low indication is deasserted. Whether that is intended depends on the designer's purpose for the stage labelled 'Power LED logic inverter'.

The sink current is at most 0.9 mA, against the 8 mA recommended IOL. Dissipation is below 0.2 mW. U401_1 is an internal no-connect and is left open.

11.2.5 Indicator LEDs D101, D102, D103

AI-Assisted — All three LEDs are XZFRS53FVF-1 Cosmic Violet parts, each with its anode fed through a series resistor and its cathode routed through a closed solder jumper. D101 runs from +3V3 through R101 (1 kΩ) to GND via JP101. D102 runs from +5V through R102 (3.3 kΩ) to GND via JP102. D103 runs from +5V through R103 (3.3 kΩ) to U401_4 via JP103. All three orientations are consistent with their drive.

The operating points were solved against the 25 °C 'Forward Current vs. Forward Voltage' graph (SunLED datasheet p.2, Datasheet

D101: about 0.78 mA at 2.52 V, rising to 0.93 mA at 3.465 V.
D102 and D103: about 0.75 mA at 5.0 V, rising to 0.90 mA at 5.5 V.

These currents sit far below the roughly 5 mA the derating curve allows at the 85 °C design ambient.

At these currents the 'Luminous Intensity vs. Forward Current' graph gives roughly 4% of the 20 mA intensity. D101 is the most sensitive case. Its 3.3 V supply equals the part's typical forward voltage at 20 mA, and the maximum forward voltage is 4.0 V (p.1). A unit at the high end of that spread will therefore emit less than the typical curve shows.

When U401_4 is high, D103 sees essentially zero reverse voltage, well inside the 5 V rating.

11.2.6 D104 Activity LED

AI-Assisted — D104 is a Würth 150060WS75000 white chip LED on the top sheet. Its anode is fed from +5V through R104 (39 kΩ). Its cathode reaches LED_PI_ACT, which is Module401_21 LED_nACT, through the bridged solder jumper JP104. The CM5 activity output sinks the LED, and the anode-to-+5V, cathode-to-sink orientation is consistent with that drive.

The forward current is very low. On the 'Forward Current vs. Forward Voltage' graph (Würth datasheet p.4, Datasheet) the lowest plotted point is 0.69 mA at 2.0 V. R104 sets a current below that point, so the forward voltage is under 2.0 V. The current is therefore bounded between 0.068 mA (4.67 V less 2.0 V, over 39 kΩ) and 0.141 mA (5.5 V over 39 kΩ). The 'Luminous Intensity vs. Forward Current' graph (p.3) gives about 3-7 mcd at that current, interpolated between its 0 mA and 2 mA points. That is adequate for an indicator.

The Würth pin table assigns the anode to pin 1 and the cathode to pin 2. The schematic symbol assigns K to pin 1 and A to pin 2. The circuit orientation is correct as drawn, but the pad mapping of footprint WE-150060WS75000-LED-W decides how the part lands at assembly.

When LED_nACT is off, its pin floats up toward +5V through D104 and R104.

11.2.7 D105 Ethernet LED

AI-Assisted — D105 is a Würth 150060VS55040 green chip LED on the top sheet. Its anode is fed from +3V3 through R105 (1 kΩ). Its cathode goes to LED_ETH, which is Module401_15 Ethernet_nLED3, through the bridged JP105. The orientation is consistent with a low-side sink. The datasheet pin table (cathode pin 1, anode pin 2) matches the symbol.

The operating point comes from solving the R105 load line against the 'Forward Current vs. Forward Voltage' graph (Würth datasheet p.3, Datasheet). At 3.3 V it gives about 1.55 mA at 1.75 V. With +3V3 at 3.465 V and R105 at its 1 % low limit, the current rises to 1.73 mA. Both figures neglect the low-level output voltage of the CM5 pin, so they are upper bounds.

The 'Derating Curve' (p.4) allows 20 mA up to 50 °C, falling 0.5 mA/°C to 2.5 mA at 85 °C. That 85 °C figure is also the end of the rated operating range, -40 to 85 °C, which therefore just covers the design ambient. A 25 % derating leaves 1.875 mA, which still clears 1.73 mA. The 'Luminous Intensity vs. Forward Current' graph (p.4) gives about 5 mcd at 1.6 mA.

11.2.8 U801 Gyroscope IAM-20380

AI-Assisted — U801 is on sheet peripherals. U801_16 VDD and U801_1 VDDIO are both on +3V3, and the power review has already confirmed that the +3V3 range suits this part. U801_13 GND and reserved pins U801_9, U801_10, U801_11, U801_12 and U801_15 are on GND. U801_7 RESV is left unconnected, and U801_8 FSYNC is on GND. All of these follow the pin table (TDK IAM-20380 datasheet p.16, Datasheet).

The local +3V3 capacitors are C802 and C806 (0.1 µF), C801 (2.2 µF), C804 (10 nF) and C805 (10 µF). These meet the values the datasheet asks for on VDD and VDDIO. They also serve U802 on the same net.

U801_14 REGOUT carries C803 (1 µF), about twice the 0.47 µF the datasheet specifies.

U801_5 CS on +3V3 selects I2C mode. U801_4 SA0/SDO on GND selects 7-bit address 0x68 (p.24). That matches the designer's notes and does not clash with U302 at 0x08.

U801_2 and U801_3 are on I2C_3_SCL and I2C_3_SDA, which are CM5 GPIO3 and GPIO2. No pull-up resistor is drawn on either net. The designer's note on sheet cm5 states that the selected CM5 GPIOs carry internal 1.8 kΩ pull-ups. With that value, a low level draws at most 1.93 mA, within the 3 mA the part sinks at 0.4 V (p.21).

U801_6 INT drives GYRO_INT into Module401_47 GPIO23 with no pull resistor on the net.

The surge exposure of the I²C pins is reported with the payload ESD arrays.

11.2.9 SPI1 FRAM and Payload Single-Ended Lines

AI-Assisted — SPI1 runs from the CM5 (GPIO19, GPIO20, GPIO21 and GPIO24) to U802, a CY15B102Q-SXET. Each line has a 22 Ω series resistor at its driver: R401 on PICO, R402 on SCK and R403 on C̅S̅, all driven by the CM5, and R801 on SO, driven by U802.

The U802-side segments carry a 50 Ω single-ended class. The CM5-side segments (PICO_GPIO20_PT, SCLK_GPIO21_PT, CS_GPIO24_PT) and the FRAM-side SO segment Net-(U802-SO) carry none.

GPIO_VREF (Module401_78) is on +3V3, which selects 3.3 V signalling, so both ends share the same supply. CM5 VOH is at least 2.9 V against the U802 VIH minimum of 2.31 V (0.7 × 3.3 V), rising to 2.43 V at the 3.465 V rail maximum. CM5 VOL is at most 0.4 V against the U802 VIL maximum of 0.99 V. In the other direction, U802 VOH is at least 3.1 V and VOL at most 0.2 V, against CM5 VIH 2.0 V and VIL 0.8 V.

R802 (10 kΩ, from SPI_1_CS to +3V3) holds C̅S̅ high while the CM5 GPIO is undriven. R803 (10 kΩ, from FRAM_H̅O̅L̅D̅ to +3V3) satisfies the datasheet's tie-high rule while GPIO18 controls H̅O̅L̅D̅. U802_3 W̅P̅ is tied directly to +3V3.

The payload SPI2 and I2C_3 paths through J101 (R107 to R112, 22 Ω) carry a 50 Ω class on both segments. U101 to U103 load those lines with at most 0.95 pF each.

11.2.10 Observations and Findings

AI-Assisted — The recurring issue across the high-speed interfaces is the boundary between CM5-side and connector-side nets. The camera lanes, both USB 2.0 pairs and the Ethernet pairs each change name between the module and the connector. The element at that boundary is not identified, so its effect on impedance and loss is open for every one of these links.

The second theme is net-class consistency. Impedance classes are present on the CM5 high-speed pairs and the payload lines but missing on the ETH_C pairs and the SPI1 module-side segments. A differential class is also applied to the single-ended PCIe sideband nets.

I2C_2 to J702 depends on pull-ups on the camera module. The CM5 states an internal 1.8 kΩ pull-up only for GPIO2/GPIO3 and SCL0/SDA0 (pp.19-20). The designer's note on sheet cm5 refers to internal 1.8 kΩ pull-ups on selected GPIOs, but ID_SC/ID_SD are not among the pins the datasheet lists.

U802 is held writable for its Status Register at all times by W̅P̅ on +3V3. Per the datasheet, W̅P̅ guards the block-protect bits only when WPEN = 1.

11.3 Findings

AI-Assisted —

#	Device	Finding	Severity
11.3.1	U103 (TPD4E1B06DRLR), U801	U103_4 and U103_6 on I2C_3_SCL and I2C_3_SDA connect directly to U801_2 SCL/SPC and U801_3 SDA/SDI, with no series resistance between them. U103 begins breakdown at 7 V minimum at 1 mA and clamps at 10.9 V typical at 1 A, 8/20 µs (TI TPD4E1B06 p.5). U801 states no transient rating, so its absolute maximum is used as the bound: VDDIO + 0.5 V, which is 3.635 V at the 3.135 V bottom of +3V3 (TDK IAM-20380 p.44). U801's input structures therefore conduct before U103 does and carry the surge current let through by R107 and R108 (22 Ω). Series resistance between the I2C_3 node and U801_2/U801_3 would limit that current; size it against the I²C rise-time budget.	Medium
11.3.2	U202 (TPD4E1B06DRLR), U401	U202_4 on +5V begins breakdown at 7 V minimum at 1 mA and clamps at 10.9 V typical at 1 A, 8/20 µs (TI TPD4E1B06 p.5). U401_5 VCC is on the same net with no series resistance and has a 7 V absolute maximum (TI SN74AHCT1G04 p.4, Datasheet). U401 states no transient rating, so the absolute maximum is used as the bound. The array protects U401 only from the level at which U401's rating ends. A rail-class TVS on J202_1 VBUS whose maximum clamping voltage at the expected surge current stays below 7 V closes the gap.	Medium
11.3.3	BT401, R406	The designer's note on sheet cm5 says to leave R805 unfitted for a non-rechargeable cell and to fit 10 kΩ to enable charging. No R805 is drawn; the charging resistor in that position is R406 (10 kΩ, +3V3 to Net-(D401-A)). Correct the note to R406 so the assembly instruction matches the schematic.	Low
11.3.4	BT401 (Keystone 2998)	BT401_P1 is left unconnected by the designer, and only P2 carries the positive contact. Whether P1 and P2 are a common contact could not be checked. A datasheet for Keystone 2998 could not be obtained. On a subsequent report generation, include one in the datasheets directory of the project to improve the report.	Review
11.3.5	BT401, D401 (BAS116LT1G)	With R406 fitted, the cell floats one D401 forward drop below +3V3. The 25 °C 'Forward Voltage' graph (onsemi BAS116L datasheet p.3, Datasheet) reads 0.68 V at its lowest point, 0.105 mA, so the float level lies above 2.62 V and below 3.3 V. Check that this float level suits the charge voltage the chosen rechargeable cell requires.	Review
11.3.6	U101 (TPD4E1B06DRLR)	U101_1 is on R̅E̅S̅E̅T̅ (Module401_99 PMIC_ENABLE, R404 180 kΩ to GND, SW102 to GND), and the array's standoff is ±5.5 V. Check that the CM5 PMIC_ENABLE idle level stays at or below 5.5 V. The PMIC_ENABLE level was not available at report generation time.	Review
11.3.7	U101, U102, U103 (TPD4E1B06DRLR), Module401	The arrays clamp at 10.9 V typical at 1 A and 14.5 V at 3 A, 8/20 µs (TI TPD4E1B06 p.5), directly on the CM5 GPIO nets. Check that the CM5 GPIO pins on these nets are rated for this waveform.	Review
11.3.8	U601 (TPD4E1B06DRLR)	U601 has a ±5.5 V standoff on ETH_C.TRD0_P/N and ETH_C.TRD1_P/N at J601. Check that the CM5 PHY's MDI common-mode level plus signal swing stays within ±5.5 V. The PHY MDI level was not available at report generation time.	Review
11.3.9	U401 (SN74AHCT1G04DBVR)	No bypass capacitor is drawn at U401_5 VCC on sheet cm5. The nearest +5V capacitors are C101 and C102 (0.1 µF) on another sheet. The datasheet shows and recommends 0.1 µF from VCC to GND close to the pin (p.9-10). Place a 0.1 µF capacitor at U401_5.	Review
11.3.10	U401 (SN74AHCT1G04DBVR), Module401	U401_2 is driven by Module401_95 LED_nPWR on LED_PI_P̅W̅R̅, and it requires VIH of 2 V minimum and VIL of 0.8 V maximum (TI SN74AHCT1G04 p.4). Check that the CM5 LED_nPWR output levels meet these thresholds. The LED_nPWR VOH/VOL values were not available at report generation time.	Review
11.3.11	U401 (SN74AHCT1G04DBVR), D103	U401 inverts LED_nPWR onto the D103 cathode. With LED_nPWR low, U401_4 is high and D103 is off; with LED_nPWR high, U401_4 is low and D103 lights (TI SN74AHCT1G04 p.8). The CM5 pin is named active-low, so D103 lights while the indication is deasserted. Check that this inverted sense is the indication intended by the 'Power LED logic inverter' stage on sheet cm5.	Review
11.3.12	D101, D102, D103 (XZFRS53FVF-1)	At 0.75-0.93 mA, the 'Luminous Intensity vs. Forward Current' graph (p.2), which reads 0.255 at 5.27 mA, gives about 4% of the 20 mA intensity. D101's 3.3 V supply equals the 3.3 V typical forward voltage at 20 mA (4.0 V maximum, p.1), so a high-forward-voltage unit emits less than the typical curve shows. Check indicator visibility under the intended viewing conditions.	Review
11.3.13	D104 (150060WS75000)	The Würth datasheet pin table gives anode on pin 1 and cathode on pin 2 (Datasheet). The schematic symbol has K on pin 1 and A on pin 2. Check that the cathode pad and polarity mark of footprint WE-150060WS75000-LED-W follow the part's cathode marking, so the LED is not placed reversed.	Review
11.3.14	D104, Module401	With LED_nACT off, Module401_21 is pulled toward +5V through R104 (39 kΩ) and D104, reaching up to 5.5 V less the D104 forward drop at leakage current. Check that the CM5 LED_nACT open-collector output tolerates a load returned to +5V. The LED_nACT maximum pin voltage was not available at report generation time.	Review
11.3.15	D105, Module401	D105 sinks up to 1.73 mA into Module401_15 Ethernet_nLED3. Check that the CM5 Ethernet_nLED3 output is rated to sink 1.73 mA. The Ethernet_nLED3 output current rating was not available at report generation time.	Review
11.3.16	U801 (IAM-20380), C801, C802, C804, C806	The datasheet calls for X7R ±10 % parts for the VDD and VDDIO bypass (p.17). The schematic states the ±10 % tolerance but no dielectric for C801, C802, C804 and C806.	Review
11.3.17	U801 (IAM-20380), C803	U801_14 REGOUT has C803 (1 µF) to GND. The datasheet specifies a 0.47 µF X7R ±10 % filter capacitor (p.17), and the schematic states no dielectric or voltage rating for C803. A 0.47 µF X7R part matches the datasheet value.	Review
11.3.18	U801 (IAM-20380)	U801_2 SCL/SPC and U801_3 SDA/SDI on I2C_3_SCL and I2C_3_SDA need external pull-ups (p.17, p.24), and no resistor to a rail is drawn on either net. The designer's note on sheet cm5 states the selected CM5 GPIOs carry internal 1.8 kΩ pull-ups; I2C_3 is on Module401_56 GPIO3 and Module401_58 GPIO2. Check that these two CM5 pins are among those with the internal pull-ups.	Review
11.3.19	U801 (IAM-20380)	U801 supports up to 400 kHz Fast-mode I²C (p.24), while U302 on the same bus supports up to 1 MHz. Check that the CM5 I2C3 clock is set at or below 400 kHz.	Review
11.3.20	U801 (IAM-20380)	U801_6 INT drives GYRO_INT into Module401_47 GPIO23 with no pull resistor on the net. INT is configurable as totem-pole or open-drain (p.16, p.21). Firmware must select totem-pole mode, or enable a GPIO23 pull-up if open-drain is chosen.	Review
11.3.21	U801 (IAM-20380)	A valid power-on reset requires a monotonic +3V3 ramp of 0.01-100 ms, 10 % to 90 % (p.21). Check that the CM5 +3.3 V output ramp falls within this window. The CM5 +3.3 V output ramp time was not available at report generation time.	Review
11.3.22	U801 (IAM-20380)	Registers are accessible 100 ms maximum after power-up (p.21). Check that the CM5's first I²C access to address 0x68 occurs at least 100 ms after +3V3 is valid.	Review
11.3.23	BT401, R406, D401	R406 is drawn and marked not fitted, so the D401 anode is open and BT401 is not charged on this build. This suits a primary cell. Fitting R406 charges the cell from +3V3 through D401, whose anode-to-+3V3, cathode-to-VBAT_RTC orientation blocks back-feed into +3V3.	Info
11.3.24	JP101, JP102, JP103	Closed solder jumpers sit in the D101, D102 and D103 cathode paths (JP101_2 and JP102_2 on GND, JP103_2 on LED_PI_PWR). Cutting a jumper disables that indicator; left closed, all three indicators are active.	Info
11.3.25	JP104, JP105	Bridged solder jumpers sit in the D104 and D105 cathode paths. Cutting one disables that indicator; left closed, both indicators are active.	Info
11.3.26	U801 (IAM-20380)	U801_4 SA0/SDO is on GND, which selects 7-bit I2C address 0x68 (p.24) and matches the designer's notes on the top sheet and sheet peripherals. Tying it to VDDIO would select 0x69. The address does not clash with U302 at 0x08 on I2C_3.	Info
11.3.27	BT401 (Keystone 2998)	BT401_N is on GND. BT401_P2 is on VBAT_RTC together with Module401_76 VBAT and the D401 cathode, so the cell is connected to the CM5 RTC supply.	✓
11.3.28	U101, U102, U103, U202, U601 (TPD4E1B06DRLR)	Pin 2 GND of each array is on GND, as the datasheet requires (TI TPD4E1B06 datasheet).	✓
11.3.29	U101, U102, U103, U202, U601 (TPD4E1B06DRLR)	Pin 5 NC is left unconnected on all five arrays, and the unused channel U202_6 is unconnected. The datasheet states the NC pin need not be routed, and it places no requirement on an unused I/O channel.	✓
11.3.30	U101, U102, U103 (TPD4E1B06DRLR)	GPIO, UART, SPI_2 and I2C_3 channels see at most 3.465 V (GPIO_VREF on +3V3). A ±5.5 V standoff is adequate for a 3.465 V maximum signal, and the 5.5 V pin-to-pin limit is met (TI TPD4E1B06 datasheet p.4-5).	✓
11.3.31	U202 (TPD4E1B06DRLR)	U202_4 is on +5V (J202_1 VBUS), which reaches 5.50 V at the top of the +5V_USB band through U301. A 5.5 V standoff is adequate for a 5.5 V maximum rail. The 5.5 V pin-to-pin limit to the USB data channels is met at that edge (TI TPD4E1B06 p.4-5).	✓
11.3.32	U202, U601 (TPD4E1B06DRLR)	Line capacitance is 0.95 pF maximum and channel capability is 3.4 Gbps (TI TPD4E1B06 p.5, p.14). Both are adequate for 480 Mb/s USB 2.0 on USB2_C.D_P/N and 100 Mb/s Ethernet on ETH_C.TRD0/TRD1. USB 2.0 levels below 3.6 V are inside the ±5.5 V standoff.	✓
11.3.33	U101, U102, U103, U202, U601 (TPD4E1B06DRLR)	The rated operating range of -40 to 125 °C (TI TPD4E1B06 p.4) covers the 85 °C design ambient.	✓
11.3.34	U401 (SN74AHCT1G04DBVR)	U401_5 VCC is on +5V and U401_3 GND is on GND. +5V spans about 4.67 V (the 4.75 V USB minimum less the U301 drop at 0.9 A) to 5.50 V, inside the 4.5-5.5 V recommended VCC range. The 7 V absolute maximum is not approached (TI SN74AHCT1G04 p.4).	✓
11.3.35	U401 (SN74AHCT1G04DBVR)	U401_4 sinks only the D103 current, at most 0.9 mA (R103 3.3 kΩ from +5V at 5.5 V). This is within the 8 mA recommended IOL, the 25 mA absolute-maximum output current derated 20% to 20 mA (ics_output_current_pct = 80), and the ±50 mA VCC/GND limit (TI SN74AHCT1G04 p.4).	✓
11.3.36	U401 (SN74AHCT1G04DBVR)	U401_1 NC is left unconnected; the datasheet states it has no internal connection (TI SN74AHCT1G04 p.3).	✓
11.3.37	U401 (SN74AHCT1G04DBVR)	The rated range of -40 to 125 °C covers 85 °C. Dissipation is below 0.2 mW, so with θJA of 278 °C/W the predicted junction temperature is about 85 °C, below the 110 °C limit of the ECSS-Q-ST-30-11C derating selected for this schematic analysis (TI SN74AHCT1G04 p.4-5).	✓
11.3.38	D101 (XZFRS53FVF-1)	The anode is fed through R101 (1 kΩ) from +3V3, and the cathode returns to GND through JP101. The orientation is consistent with the drive.	✓
11.3.39	D101 (XZFRS53FVF-1)	From the 25 °C 'Forward Current vs. Forward Voltage' graph (SunLED datasheet p.2, Datasheet) with R101 (1 kΩ), the operating point is 0.78 mA at 3.3 V and 0.93 mA at 3.465 V. This is below the roughly 5 mA permitted at 85 °C on the 'Forward Current Derating Curve' (p.2).	✓
11.3.40	D102 (XZFRS53FVF-1)	The anode is fed through R102 (3.3 kΩ) from +5V, and the cathode returns to GND through JP102. From the same graph (p.2), the current is 0.75 mA at 5.0 V and 0.90 mA at 5.5 V, below the roughly 5 mA permitted at 85 °C. The orientation is consistent.	✓
11.3.41	D103 (XZFRS53FVF-1)	The anode is fed through R103 (3.3 kΩ) from +5V, and the cathode goes to U401_4 through JP103. The current is at most 0.9 mA when U401_4 is low, below the roughly 5 mA permitted at 85 °C (SunLED p.2). When U401_4 is high the reverse voltage is near 0 V, within the 5 V rating (p.1).	✓
11.3.42	D101, D102, D103 (XZFRS53FVF-1)	Dissipation is at most 2.4 mW against the 120 mW rating at 25 °C (p.1). Even scaled by the derating curve to 85 °C (5 mA of 30 mA) and halved (diode_power_pct = 50), the limit of 10 mW clears this. The rated operating range of -40 to 85 °C covers the 85 °C design ambient.	✓
11.3.43	R101, R102, R103	Series resistor dissipation is 0.86 mW for R101 and at most 2.7 mW for R102 and R103. These are 0.1 W parts, which the ECSS-Q-ST-30-11C derating selected for this schematic analysis limits to 50 mW (a 50% derating, resistor_power_pct = 50).	✓
11.3.44	D104 (150060WS75000)	Anode via R104 (39 kΩ) from +5V; cathode through JP104 to LED_PI_ACT (Module401_21 LED_nACT). The orientation is consistent with a low-side sink by the CM5 activity output.	✓
11.3.45	D104 (150060WS75000)	Forward current is 0.068-0.141 mA, bounded from R104 (39 kΩ) because the operating point lies below the lowest point (0.69 mA at 2.0 V) of the 'Forward Current vs. Forward Voltage' graph (p.4). The 'Derating Curve' (p.4) allows 5 mA at 85 °C, which is 3.75 mA after a 25 % derating (diode_forward_current_pct = 75), so the part passes.	✓
11.3.46	D104 (150060WS75000)	Dissipation is below 0.3 mW (0.141 mA at under 2.0 V), against a 100 mW rating at 25 °C (p.1) that a 50 % derating (diode_power_pct = 50) limits to 50 mW. The rated range of -40 to 85 °C covers the 85 °C design ambient.	✓
11.3.47	D104 (150060WS75000)	The 'Luminous Intensity vs. Forward Current' graph (p.3) gives about 3-7 mcd at 0.068-0.141 mA, interpolated between its 0 mA and 2 mA points. This is adequate for an indicator.	✓
11.3.48	D104, R104	The open-collector LED_nACT output on LED_PI_ACT has the D104 and R104 string as its load from +5V, so no separate pull-up is needed for the indicator function.	✓
11.3.49	D105 (150060VS55040)	Anode via R105 (1 kΩ) from +3V3; cathode through JP105 to LED_ETH (Module401_15 Ethernet_nLED3). The orientation is consistent, and the datasheet pin table (cathode pin 1, anode pin 2) matches the symbol (Würth datasheet).	✓
11.3.50	D105 (150060VS55040)	The R105 load line on the 'Forward Current vs. Forward Voltage' graph (p.3) gives about 1.55 mA at 1.75 V with 3.3 V, and 1.73 mA with 3.465 V and R105 at -1 %. The CM5 output's low level is neglected, so these are upper bounds. The 'Derating Curve' (p.4) allows 2.5 mA at 85 °C, which is 1.875 mA after a 25 % derating (diode_forward_current_pct = 75), so the part passes.	✓
11.3.51	D105 (150060VS55040)	Dissipation is at most 3.0 mW (1.73 mA at 1.75 V), against a 48 mW rating at 25 °C (p.1) that a 50 % derating (diode_power_pct = 50) limits to 24 mW. The rated range of -40 to 85 °C reaches exactly the 85 °C design ambient.	✓
11.3.52	D105 (150060VS55040)	The 'Luminous Intensity vs. Forward Current' graph (p.4) gives about 5 mcd at 1.6 mA, interpolated between its 1 mA and 3 mA points. This is adequate for an indicator.	✓
11.3.53	R104, R105	Dissipation is 0.78 mW for R104 and 3.0 mW for R105. These are 0.1 W parts, which the ECSS-Q-ST-30-11C derating selected for this schematic analysis limits to 50 mW (a 50 % derating, resistor_power_pct = 50).	✓
11.3.54	U801 (IAM-20380)	U801_16 VDD and U801_1 VDDIO are on +3V3, and U801_13 GND is on GND. The supply range is inside the recommended 1.71-3.6 V and below the 4 V absolute maximum (TDK IAM-20380 datasheet p.17, p.44).	✓
11.3.55	U801 (IAM-20380)	C802 and C806 (0.1 µF), C801 (2.2 µF) and C804 (10 nF) are local to U801 on +3V3. Together they meet the datasheet's 0.1 µF plus 2.2 µF on VDD and 10 nF on VDDIO (p.17); VDD and VDDIO share one net. The same capacitors also serve U802.	✓
11.3.56	U801 (IAM-20380)	U801_5 CS is on +3V3 (VDDIO). Per the pin table, tied to VDDIO selects I2C mode (p.16). Because CS is held high, the unsupported power-up state of SCL and CS both low cannot occur.	✓
11.3.57	U801 (IAM-20380)	U801_8 FSYNC is on GND, as the datasheet requires when unused (p.16).	✓
11.3.58	U801 (IAM-20380)	U801_9, U801_10, U801_11, U801_12 and U801_15 RESV are on GND, and U801_7 RESV is left unconnected. Both follow the datasheet's reserved-pin requirements (p.16).	✓
11.3.59	U801 (IAM-20380)	With the designer-stated 1.8 kΩ pull-ups, a low level draws at most 1.93 mA (3.465 V over 1.8 kΩ), within the 3 mA U801 sinks at 0.4 V (p.21). The 0.4 V low level is below the 0.94 V VIL maximum (0.3 × 3.135 V). The pull-ups return to the same +3V3 as VDDIO, so the high level stays within VDDIO + 0.5 V.	✓
11.3.60	U801 (IAM-20380)	The specified range of -40 to +85 °C (p.17, p.44) covers the 85 °C design ambient at its upper edge. Normal-mode current of 2.6 mA typical (p.17) at 3.465 V dissipates 9.0 mW, a rise of 0.8 °C with θJA of 84.58 °C/W (p.44).	✓

11.4 Citations

AI-Assisted —

References
150060VS55040 (Würth Elektronik eiSos GmbH & Co. KG) — datasheet www.we-online.com/components/products/datasheet/150060VS5...
150060WS75000 (Würth Elektronik eiSos GmbH & Co. KG) — datasheet www.we-online.com/components/products/datasheet/150060WS7...
BAS116L (ON Semiconductor) — datasheet www.mouser.com/datasheet/2/308/BAS116LT1-D-1802066.pdf
ESD751 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/esd751.pdf
FS1603A-5000 (TDK Corporation) — datasheet product.tdk.cn/system/files/dam/doc/product/power/switchi...
GCJ32EC71E226KE02L (Murata Manufacturing Co., Ltd.) — datasheet www.farnell.com/datasheets/3410916.pdf
IAM-20380 (TDK InvenSense) — datasheet d17t6iyxenbwp1.cloudfront.net/s3fs-public/2026-02/DS-0001...
M2_Socket3_Key_M — PCI Express M.2 Specification Rev 0.7, Table 49 (PDF p.150), Table 42 (p.139) pcisig.com/specifications
SN74AHCT1G04 (Texas Instruments) — datasheet www.ti.com/lit/gpn/SN74AHCT1G04
T591D476M025ATE060 (KEMET) — datasheet content.kemet.com/datasheets/KEM_T2073_T59X.pdf
TPD4E1B06 (Texas Instruments) — datasheet www.ti.com/lit/gpn/TPD4E1B06
XZFRS53FVF-1 (SunLED) — datasheet www.sunledusa.com/products/spec/XZFRS53FVF-1.pdf

12 Designer Annotated Nets

No additional annotations are present beyond those already reported in previous sections.

13 EMC & ESD Protection Checks

Checks run	1
Passed	0
Issues found	1

EMC Check Summary
Check	Issues	Status
Connector Shell Grounding	1

13.1 Connector Shell Grounding

RefDes	Type	Issue	Recommendation	Severity
J201	USB-C	J201 (DX07S016JA1R1500): Shell pins share the logic GND net, so the shield-bond strategy is not captured as design intent.	USB Type-C R2.5 §3.2.1 requires the receptacle shell to be connected to the PCB ground plane; a shield net bonded to logic GND through R\|\|C satisfies it and does not leave the shell floating. Assign a dedicated schematic net per connector (e.g. SHIELD_GND_TYPE_C, SHIELD_GND_SD) so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MΩ \|\| 4.7 nF (≥2 kV) from the shield net to logic GND. IEC 61000-4-2.

13.2 ESD/TVS Protection Audit

Audit of connector-facing signal nets for ESD/TVS protection presence and orientation correctness.

Connector-facing signal nets analyzed: 4 connector-facing signal(s). 4 protected, 0 unprotected, 0 to review, 0 orientation issue(s).

13.2.1 Protected Signal Nets

Signal Net	Connector	Protection Device	Device Type	Rail Connection	Orientation	Status
USB_CC1	J201	U201	TI TPD4E1B06DRLR	GND	Not applicable (array); rail pins correct	Protected
USB_CC2	J201	U201	TI TPD4E1B06DRLR	GND	Not applicable (array); rail pins correct	Protected
USB1_PI.D_P	J201	U201	TI TPD4E1B06DRLR	GND	Not applicable (array); rail pins correct	Protected
USB1_PI.D_N	J201	U201	TI TPD4E1B06DRLR	GND	Not applicable (array); rail pins correct	Protected

13.3 EMC & ESD Analysis

13.3.1 EMC Architecture, Grounding and Filtering

AI-Assisted — The board has a single ground, GND. It serves as the logic, power and connector return, and no chassis or shield net is drawn. The following all sit on GND: every connector ground contact, the J201 shell contact S1, the body pins of SW101 and SW102, and the mounting holes H101-H104. Logic ground therefore meets the mechanical structure directly wherever those holes are fastened. Keeping digital, analog and power returns on one ground is correct.

Entry-point protection is by shunt clamps. TPD4E1B06 arrays (U101-U103, U201, U202, U601) sit on every signal contact of J101, J201, J202 and J601, all returned to GND. D201 clamps the J201 VBUS contacts. The payload signals also pass through 22 Ω series resistors, R107-R118, which slow the edges leaving the board. None of the connector nets examined carries a common-mode choke or a series ferrite.

The main emissions source is U302. This 1.4 MHz nominal point-of-load module (TDK FS1603A datasheet p.18, Datasheet) draws from +VBAT_BUS. That rail is one net from J101 pins 1-4 to U302 PVIN, filtered only by capacitors.

The board is judged at the industrial level:
- Immunity to IEC 61000-6-2, with ESD tested per IEC 61000-4-2 at ±4 kV contact and ±8 kV air.
- Emissions to IEC 61000-6-4 (CISPR 11 limits).

13.3.2 USB Type-C Device Port J201

AI-Assisted — J201 is a horizontal, top-mount Type-C receptacle used as the device port. It provides USB boot and firmware install through B̅O̅O̅T̅ and the USB power input. It is an external, user-facing hot-plug entry.

Of the three Type-C grounding checks, two are met:
- The GND contacts A1, A12, B1 and B12 are hard on logic GND.
- The protection parts reference logic GND (U201_2, D201_1).

The third is not met. The outer shell contact S1 is also on GND. This is judged at the professional level because the board is classified industrial and will meet IEC 61000-4-2 testing. A direct stitch remains the simplification for an untested design. Where the opening is in a plastic housing with no chassis, the RC bond changes where and how the strike enters GND, not whether it does. The symbol carries no mid-plate pin.

Signal protection is as follows:
- D+ (A6, B6), D- (A7, B7), CC1 and CC2 each reach a U201 channel.
- SBU1 and SBU2 are unconnected and offer no entry path.
- VBUS has D201. This bidirectional clamp has no orientation to check and is rated ±22 kV contact and air (TI ESD751 datasheet p.4, Datasheet), well above the industrial test level.

D201's clamping level against U301 is covered in the power review.

13.3.3 USB Host Header J202 and Ethernet Header J601

AI-Assisted — J202 and J601 are 1.25 mm PicoBlade wire-to-board headers with no shell contact in their symbols. Each takes a harness to equipment off the board.

On J202, D+, D- and the +5V VBUS contact each have a U202 channel returned to GND. On J601, all four ETH_C lines have a U601 channel returned to GND.

The designer's note on sheet ethernet places the magnetics on the external switch. U601 therefore sits on the PHY side of the magnetics and references signal ground, which is the placement Ethernet protection requires. The CM5 reference schematic shows a different array (Raspberry Pi CM5 datasheet p.8, source: Tomachie); that is an application example, not a requirement.

Because the J601 harness carries unmagnetised MDI pairs, the switch's magnetics are the isolation boundary. Up to that boundary, the harness shares this board's GND potential with the switch.

Neither harness has a shield return or common-mode filtering on the board. The radiated emissions they produce therefore depend on harness length, twist and routing. This matters most where either harness approaches an enclosure opening.

13.3.4 Payload Connector J101

AI-Assisted — J101 is the 40-position 1.27 mm Samtec receptacle carrying the Sparrow payload interface. It is a board-to-board or internal-harness entry.

Every one of its 12 signal contacts follows the same path: through a 22 Ω resistor (R107-R118) to a CM5-side net that carries a U101, U102 or U103 channel. Protection is therefore complete, beyond what an internal interface normally needs. The ten signal contacts on pins 5-23 alternate with the ten GND contacts on pins 6-24, which gives each a local return.

The arrays sit on the same net as the CM5 pins, so no resistance lies between the clamp and the pin. The CM5 states no transient rating for its GPIO. Its GPIO absolute maximum is VGPIO_VREF + 0.5 V, which is 3.8 V with GPIO_VREF on +3V3 (Raspberry Pi CM5 datasheet p.26, source: Tomachie). The functional review reports the array clamp at 10.9 V typical at 1 A, 8/20 µs. That is far above the CM5 bound, so the module's on-die protection shares the strike.

Moving each array to the connector side of its resistor changes the protection, not the termination. The R107-R118 damping function stays the same, and each 22 Ω then limits the current into the CM5 pin's internal clamp to about (10.9 - 3.3 - 0.7) V / 22 Ω = 0.31 A.

+VBAT_BUS on pins 1-4 has no clamp. U302 PVIN is rated 18 V absolute maximum (TDK FS1603A datasheet p.4) against the 8.40 V battery maximum.

The 3V3 contacts (pins 25-28) and +5V_BUS contacts (pins 37-40) reach only parts marked not fitted.

13.3.5 Camera FPC Connectors and Internal Interfaces

AI-Assisted — J701 and J702 are 22-way 0.5 mm FPC connectors for internal camera flex cables. Each has seven GND contacts interleaved between pairs, which gives the CSI lanes a good return structure. Their I2C and camera-control contacts (pins 17, 18, 20 and 21) reach CM5 pins directly, with no clamp and no series resistance. That is acceptable while the flex stays inside the enclosure. A camera that is replaced in service exposes those pins to handling discharge.

The other internal interfaces need no protection:
- Module402 is the CM5 high-speed module connector, internal and board-to-module.
- J102-J106 and JP101-JP105 are solder-jumper pads with no external exposure.

SW102 is a side-actuated right-angle tactile switch, so it is a touch point at the board edge. Its contacts SW102_1 and SW102_5 are on R̅E̅S̅E̅T̅, which carries the U101_1 clamp. Its body pins are on GND. The functional review covers the U101 standoff on that net.

The WL-E̅N̅ and BT-E̅N̅ jumpers (J103, J104) are the board's radio-compliance option. Shorting a jumper takes the CM5 WiFi_nDisable or BT_nDisable input low and disables that radio in hardware (Raspberry Pi CM5 datasheet p.7, source: Tomachie).

13.4 Observations

AI-Assisted — The protection scheme is consistent across every cabled entry. Each signal contact on J101, J201, J202 and J601 reaches a ground-referenced clamp, and the J201 VBUS contacts have a ±22 kV-rated clamp. The open points are coordination and emissions, not missing parts.

First, the J101 arrays sit on the CM5 side of the 22 Ω resistors. The CM5 pins therefore take the full clamp level with no current limiting. Reordering the array and resistor fixes this at no part cost.

Second, the J201 shell is on logic GND. An ESD strike to the shell therefore enters the logic plane at the connector with no designed entry point. A dedicated shield net with an RC bond is the professional-level remedy.

Third, +VBAT_BUS couples U302's 1.4 MHz switching current and harmonics onto the payload bus through capacitors alone. The same net is the only power entry without a transient clamp. Its 9.6 V margin to the U302 18 V absolute maximum is the budget any clamp must fit within.

The unshielded harnesses on J202 and J601 are the likeliest radiated-emissions paths, and their impact depends on the harness design rather than the schematic.

The EEPROM write-protect choice on J106 belongs to the functional review and is listed once.

13.5 Findings

AI-Assisted —

#	Connector	Finding	Severity
13.5.1	J201	J201 shell contact S1 shares the logic GND net, so the shield-bond strategy is not captured as design intent. Assign a dedicated SHIELD_GND_J201 net so the pour and bond parts are explicit. A copper pour under the connector and stitched directly to logic GND is an acceptable simplification for a board that has no access to an earth ground and will not be ESD-tested. For professional designs, with or without earth ground access, use a 1 MOhm \|\| 4.7 nF (>= 2 kV) from SHIELD_GND_J201 to logic GND. USB Type-C R2.5 section 3.2.1; IEC 61000-4-2.	Medium
13.5.2	J202	USB2_C.D_P and USB2_C.D_N leave on an unshielded PicoBlade harness, with no shell return and no common-mode filtering drawn. Radiated emissions at 480 Mb/s depend on harness length and routing. Where the harness reaches an enclosure opening, a USB 2.0 common-mode choke at J202 is the remedy. CISPR 11 / IEC 61000-6-4.	Review
13.5.3	J601	The unmagnetised MDI pairs leave on an unshielded harness. The switch's magnetics are the isolation boundary, so the harness shares this board's GND with the switch, and any common-mode current on it radiates. Keep the harness as a short twisted pair inside the enclosure. CISPR 11 / IEC 61000-6-4.	Review
13.5.4	J101	The U101-U103 clamps sit on the CM5-side nets, with no series resistance to the CM5 pins. The CM5 states no transient rating, so its GPIO absolute maximum of VGPIO_VREF + 0.5 V (3.8 V with GPIO_VREF on +3V3; Raspberry Pi CM5 datasheet p.26, source: Tomachie) is used as the bound. The functional review reports a 10.9 V typical clamp at 1 A (8/20 µs), well above that bound. Placing each array on the connector-side net keeps R107-R118 as damping resistors and limits the current into the CM5 internal clamp to about 0.31 A, from (10.9 - 3.3 - 0.7) V / 22 Ω.	Review
13.5.5	J101	+VBAT_BUS (pins 1-4) has no transient clamp. It feeds U302 PVIN, rated 18 V absolute maximum (TDK FS1603A datasheet p.4, Datasheet), against an 8.40 V battery maximum. Where the payload bus specification calls for surge or EFT immunity, a unidirectional TVS at J101 should have a standoff of at least 8.40 V and a clamp below 18 V at the specified pulse current. IEC 61000-4-5, IEC 61000-4-4.	Review
13.5.6	J101	U302 switches at 1.4 MHz nominal (TDK FS1603A datasheet p.18). +VBAT_BUS runs from J101 pins 1-4 to U302 PVIN as one net, with capacitors only and no series filter element. Switching ripple and its harmonics are therefore conducted onto the payload bus. Judge this against the payload bus's conducted-emission limit, or CISPR 11 / IEC 61000-6-4 where none is set.	Review
13.5.7	J701, J702	The I2C and camera-control contacts (pins 17, 18, 20, 21) reach CM5 pins directly, with no clamp. The CM5 GPIO absolute maximum is VGPIO_VREF + 0.5 V (Raspberry Pi CM5 datasheet p.26, source: Tomachie). This is acceptable for internal camera flex cables. Where cameras are replaced in service, a low-capacitance array on these contacts adds handling protection. IEC 61000-4-2.	Review
13.5.8	J106	For the functional review: EEPROM_W̅P̅ goes to GND only through open jumper J106. The CM5 boot EEPROM is therefore writable on every unit unless J106 is shorted, which is the maker's own write-protect method (Raspberry Pi CM5 datasheet section 5.3, p.28, source: Tomachie).	Review
13.5.9	U101-U103, U201, U202, U601	The part description states ±12 kV ESD protection, which exceeds the IEC 61000-6-2 industrial levels of ±4 kV contact and ±8 kV air. This rating comes from the part description.	Review
13.5.10	H101-H104	The mounting holes are on GND, so logic ground bonds directly to the mounting structure at each hole. Where the structure is a chassis, this is the board's chassis bond and ESD return. A frame that carries other subsystems' currents shares them with logic GND at these points.	Info
13.5.11	J101	The 3V3 contacts (pins 25-28) and +5V_BUS contacts (pins 37-40) have no fitted part on board. C103, C106, C109 and J107, and C104, C107, C110 and J108, are drawn and marked not fitted, so no clamp is needed on this build.	Info
13.5.12	J103, J104	With the WL-E̅N̅ and BT-E̅N̅ jumpers open, Wi-Fi and Bluetooth are enabled. Shorting either jumper takes WiFi_nDisable or BT_nDisable low, which disables that radio in hardware (Raspberry Pi CM5 datasheet p.7, source: Tomachie). This lets builds without radio approval meet regulatory limits.	Info
13.5.13	Board ground	A single GND serves logic, power and connector returns, and digital, analog and power grounds are not split. This is correct for a board with no chassis net. The J201 shield net is the only separation an ESD-tested product needs. IEC 61000-4-2.	✓
13.5.14	J201	GND contacts A1, A12, B1 and B12 are hard on logic GND, as the specification requires. The symbol carries no mid-plate pin. USB Type-C R2.5.	✓
13.5.15	J201	The protection parts reference logic GND, not a shield net: U201_2 and D201_1 are on GND. IEC 61000-4-2.	✓
13.5.16	J201	Every signal contact has a clamp: D+ (A6/B6) on U201_3, D- (A7/B7) on U201_1, CC1 (A5) on U201_6 and CC2 (B5) on U201_4. This suits an external hot-plug port. IEC 61000-4-2.	✓
13.5.17	J201	VBUS contacts A4, A9, B4 and B9 (+5V_USB) are clamped by D201. D201 is rated ±22 kV contact and ±22 kV air per IEC 61000-4-2 (TI ESD751 datasheet p.4, Datasheet), above the IEC 61000-6-2 industrial test levels of ±4 kV contact and ±8 kV air.	✓
13.5.18	J201	SBU1 (A8) and SBU2 (B8) are unconnected, so they form no entry path to any device and need no clamp.	✓
13.5.19	J202	Every signal contact has a clamp referenced to GND: D+ (pin 2) on U202_3, D- (pin 3) on U202_1, and +5V VBUS (pin 1) on U202_4. IEC 61000-4-2.	✓
13.5.20	J601	All four ETH_C lines have U601 channels returned to signal ground. Because the magnetics are on the external switch (designer's note, sheet ethernet), the clamps are on the PHY side of the magnetics, as required. The CM5 reference schematic shows a different array on page 8 (Raspberry Pi CM5 datasheet, source: Tomachie); that is an application example, not a requirement.	✓
13.5.21	J101	The 12 signal contacts (pins 5-23 odd, 29, 31) each reach a TPD4E1B06 channel on U101, U102 or U103 through 22 Ω (R107-R118). Protection is complete on this internal interface.	✓
13.5.22	J101	The ten GND contacts on pins 6-24 alternate with the ten signal contacts on pins 5-23, giving each signal a local return. GND pins 30 and 32 sit beside pins 29 and 31.	✓
13.5.23	J701, J702	Seven GND contacts per connector (pins 1, 4, 7, 10, 13, 16, 19) are interleaved with the signal groups, giving a continuous return across the flex.	✓
13.5.24	Module402	The CM5 high-speed connector is an internal board-to-module interface, so no ESD protection is required.	✓
13.5.25	J102-J106, JP101-JP105	These solder-jumper pads are internal configuration points with no external exposure, so no ESD protection is required.	✓
13.5.26	SW102	The side-actuated tactile switch is a touch point at the board edge. Its contacts SW102_1 and SW102_5 are on R̅E̅S̅E̅T̅, which carries the U101_1 clamp, and its body pins 2, 3 and 4 are on GND. IEC 61000-4-2.	✓

13.6 Citations

AI-Assisted —

References
BAS116L (ON Semiconductor) — datasheet www.mouser.com/datasheet/2/308/BAS116LT1-D-1802066.pdf
ESD751 (Texas Instruments) — datasheet www.ti.com/lit/ds/symlink/esd751.pdf
FS1603A-5000 (TDK Corporation) — datasheet product.tdk.cn/system/files/dam/doc/product/power/switchi...
IAM-20380 (TDK InvenSense) — datasheet d17t6iyxenbwp1.cloudfront.net/s3fs-public/2026-02/DS-0001...
M2_Socket3_Key_M — PCI Express M.2 Specification Rev 0.7, Table 49 (PDF p.150), Table 42 (p.139) pcisig.com/specifications
SN74AHCT1G04 (Texas Instruments) — datasheet www.ti.com/lit/gpn/SN74AHCT1G04

14 Design-for-Test

Design for Testability (DFT) analysis for ICT/bed-of-nails test coverage.

14.1 DFx Options Selected

Option	Setting	Description
Test Point Insertion
Insert on power rails	Yes	Place test points on power rail nets in schematic
Insert on LSSI buses	Yes	Place test points on every LSSI bus signal (JTAG, SWD, I2C, I3C, MDIO, SPI, QSPI, UART) that has none
Insert on all nets	No	Extend TP insertion to signal nets beyond power rails
Insert on feedback pins	Yes	Place a test point on each regulator feedback / set net that has none, so its divider can be checked
Insert on power-good nets	No	Place a test point on each used power-good net that has none and no boundary scan
Insert on NVM programming nets	No	Place test points on the nets used to program on-board memory (QSPI, etc.)
Exclude HSSI nets	Yes	Exclude HSSI/differential pair nets from TP insertion
Exclude DRAM nets	Yes	Exclude SDRAM/DDR nets from TP insertion
Exclude BSCAN opens (full)	Yes	Exclude nets with 100% boundary scan opens coverage
Exclude BSCAN opens (partial)	No	Exclude nets with partial boundary scan opens coverage
Exclude BSCAN shorts	No	Exclude nets with boundary scan shorts coverage
Target PCOLA-SOQ	0%	Insert TPs in priority order until this PCOLA-SOQ % is reached
Target solder-joint testability	0%	Insert TPs in priority order until this shorts/opens solder-joint testability % is reached
Kelvin min resistance	0.000 ohm	Lower bound (ohms) for Kelvin 4-wire TP insertion range
Kelvin max resistance	1.000 ohm	Upper bound (ohms) for Kelvin 4-wire TP insertion range
Tester Styles
Optical	AOI	Automated Optical Inspection of visible solder joints
AXI	Yes	Automated X-ray Inspection of hidden solder joints (BGA, QFN)
ATE	Flying_probe	Digital IO, DMM, shorts/opens via flying probe
Test Access
JTAG/LSSI Connector	Yes	Connector access to JTAG, SPI, I2C buses
IO Connectors	No	IO connectors available for external stimulus/observation
TP Access	Flying_probe	Flying probe access without fixture
Test Point Identification
BON TP refdes	TP#,TP-,TP_,TP#*	Refdes patterns identifying BON test points
BON TP footprints	*	All footprints accepted
FP TP refdes	TP#,TP-,TP_,TP#*,MP#	Refdes patterns identifying flying probe test points
FP TP footprints	*	All footprints accepted
Flying prober lands on passive end-caps	No	Off: a passive is a probe point only where its IPC-named land extends past the terminal; other passives are listed for a toe extension. Flat leads (SOIC, QFP, SOT, SOD, exposed connector pins) are probe points. A joint whose net is reached only by pressing on it gets no opens credit: the probe can push a lifted joint onto its pad.
Loopback	None	No loopback cables
Test Types
Powered-Off Shorts/Opens	Yes	Unpowered shorts and opens detection via probe access
Passives	Yes	R, C, L value measurement via probe or fixture access
Active Analog	No	Voltage regulator, reference, and op-amp output verification
Non-BSCAN Digital	No	Digital ICs without boundary scan: pin observability analysis
Boundary Scan	1149.1_1149.6	IEEE 1149.1-2001 + 1149.6-2003 AC boundary scan
LSSI	No	JTAG chain, SPI, I2C, UART bus test coverage analysis
JTAG Functional	No	Functional verification beyond structural scan
Require Rail TPs for Diode Test	No	Require TPs on all IO power rails for ESD diode opens test (default: basic test with GND TP only)
Capacitance Probe Plate Target Devices	—	Refdes or footprint patterns for capacitance probe plate targets (ICs and vertical connectors)
Use Boundary Scan for Capacitance Probe Plate Stimulus	No	Count boundary scan drive cells on other devices as valid stimulus for the capacitance probe plate (applicable to VTEP / IEEE 1149.8.1-capable hardware)
Smallest gain to advise a capacitive plate	100	A part is advised for a capacitive plate only when its plate gives at least this many fewer bad boards per million: each plate costs a sensor, fixture electronics, a drilled and aligned hole and its validation
NVM Programming
Default Method	Direct	Program via direct pin access; TPs on flash data/control lines
Environment
Test environment	lab	Prototype/NPI: manual probing, bench JTAG, longer test times acceptable
Testability Confidence (traffic-light markup)
Defect rate	50 DPMO (4.3 nines of process yield)	Defects per million solder joints (DPMO) the line makes before test, as entered
DPMO by package	BGA 50 / LGA 50 / QFN / DFN 50 / QFP 50 / SOIC 50 / SOT 50 / SOD 50 / Chip 0402 and larger 50 / Chip 0201 and smaller 50 / Crystal / oscillator 50 / Connector 50 / Through-hole 50	Defects per million solder joints for each package family, as entered; a part whose package is not known takes the board's DPMO
AOI catch (nines)	2D: S 1.9 / O 1.9 / Q 3	How many nines AOI catches shorts (S), opens (O) and solder junction quality (Q) on a joint it can see
AXI catch (nines)	2D: S 1.3 / O 1.3 / Q 0.5 / O on BGA, LGA 0.5	How many nines AXI catches shorts, opens and solder junction quality; its own opens figure on BGA / LGA balls
Inspection by package (nines)	BGA: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 0.5 / Q 0.5; LGA: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 0.5 / Q 0.5; QFN / DFN: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; QFP: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; SOIC: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; SOT: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; SOD: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; Chip 0402 and larger: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; Chip 0201 and smaller: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; Crystal / oscillator: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; Connector: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5; Through-hole: AOI S 1.9 / O 1.9 / Q 3, AXI S 1.3 / O 1.3 / Q 0.5	A package family's own AOI and AXI catch, as entered; a family not listed takes the board's AOI and AXI figures
Electrical test, Full (nines)	3	How many nines an electrical test catches on a joint Tomachie scores Full; Partial counts half
Required for green	Nothing beyond the levels; connector opens by inspection	What a pin needs on top of the green levels
Green at (nines)	S 2 / O 2 / O best achievable 0.3	The nines a pin needs for green; best achievable for power / ground pins, paralleled capacitors and connector pins judged on inspection
Red at or below (nines)	S 0 / O 0 / O best achievable 0; red when both are low	A pin at or below these levels is red
Part square	80% / 50%	Green from / red below, by the part's PCOLA-SOQ percentage
Expected escapes	About 5488 bad boards per million shipped (2.3 nines outgoing)	Each joint's defect rate times the share its selected tests miss, summed over 553 joints (the Williams-Brown defect level, joint by joint)
Expected escapes with test points or toe extensions	About 3941 bad boards per million shipped (2.4 nines outgoing), 1.4 times fewer	Nets with an extended toe: 14; test points: 45 - on nets that have no probe access (flying probe only; the nets are listed in 'Nets that need an extended toe on at least one pin')

14.2 Where the expected escapes are

The parts whose solder joints carry most of the board's 5488 expected bad boards per million shipped, worst first, and which test would catch more of them. The 4 parts listed carry 93% of the total.

Part	Package	Joints	Bad boards per million	Share	Weaker defect	What would catch more
Module401	Not known	100	4357	79%	Opens	Test points on its 35 nets without probe access: about 1455 fewer
U801	LGA	16	253	5%	Opens	None of these: its opens are judged on inspection only (power / ground pins, connector pins, paralleled capacitors)
Module402	Connector	100	251	5%	Opens	None of these: its opens are judged on inspection only (power / ground pins, connector pins, paralleled capacitors)
U302	LGA	17	237	4%	Opens	Test points on its 3 nets without probe access: about 47 fewer

14.3 Nets the flying prober reaches on other parts' joints

60 nets with no test point that the flying prober reaches by landing on another part's solder joint: the flat heel of a lead, an exposed connector pin, a passive's land extended at least 0.30 mm past its terminal (named by its IPC footprint), or, where the prober is set to, a passive's end-cap. Every other joint on the net is tested as from a test point. A probe pressing on a lead or an end-cap can push a lifted joint onto its pad, so a joint that is its net's only such landing gets no opens credit of its own; the last column names it. Check that your prober reaches the joints listed.

Net	Joints the prober lands on	Landed joint without opens credit
SPI_1_PICO	U802_5 (lead)	U802_5
LED_PI_PWR	U401_4 (lead)	U401_4
RESET	U101_1 (lead)	U101_1
Net-(D101-A)	D101_2 (lead)	D101_2
Net-(D104-K)	D104_1 (lead)	D104_1
Net-(D105-K)	D105_1 (lead)	D105_1
Net-(D102-K)	D102_1 (lead)	D102_1
Net-(D104-A)	D104_2 (lead)	D104_2
CAM1_GPIO1	J701_17 (lead)	J701_17
I2C_3_SCL	U103_4 (lead)	U103_4
GPIO7	J702_17 (lead)	J702_17
Net-(D103-K)	D103_1 (lead)	D103_1
SPI_1_CS	U802_1 (lead)	U802_1
I2C_3_SDA	U103_6 (lead)	U103_6
GPIO8	J702_18 (lead)	J702_18
SPI_1_SCL	U802_6 (lead)	U802_6
CAM1_GPIO2	J701_18 (lead)	J701_18
FRAM_HOLD	U802_7 (lead)	U802_7
Net-(D105-A)	D105_2 (lead)	D105_2
Net-(D102-A)	D102_2 (lead)	D102_2
USB_CC1	U201_6 (lead)	U201_6
USB_CC2	U201_4 (lead)	U201_4
Net-(D103-A)	D103_2 (lead)	D103_2
Net-(D101-K)	D101_1 (lead)	D101_1
DPHY2_PI.D3_N	J702_14 (lead)	J702_14
VBAT_RTC	D401_3 (lead)	D401_3
I2C_2_SDA	J702_21 (lead)	J702_21
LED_PI_PWR	U401_2 (lead)	U401_2
I2C_2_SCL	J702_20 (lead)	J702_20
DPHY2_PI.D3_P	J702_15 (lead)	J702_15
I2C_1_SDA	J701_21 (lead)	J701_21
I2C_1_SCL	J701_20 (lead)	J701_20
+5V_USB	D201_2 (lead)	D201_2
Net-(U802-SO)	U802_2 (lead)	U802_2
ETH_PI.TRD0_P	J601_4 (lead), U601_1 (lead)	-
ETH_PI.TRD0_N	J601_3 (lead), U601_3 (lead)	-
ETH_PI.TRD1_P	J601_2 (lead), U601_4 (lead)	-
ETH_PI.TRD1_N	J601_1 (lead), U601_6 (lead)	-
DPHY1_PI.D0_N	J701_2 (lead)	J701_2
DPHY1_PI.D0_P	J701_3 (lead)	J701_3
DPHY1_PI.D1_N	J701_5 (lead)	J701_5
DPHY1_PI.D1_P	J701_6 (lead)	J701_6
DPHY1_PI.D2_N	J701_11 (lead)	J701_11
DPHY1_PI.D2_P	J701_12 (lead)	J701_12
DPHY1_PI.D3_N	J701_14 (lead)	J701_14
DPHY1_PI.D3_P	J701_15 (lead)	J701_15
DPHY1_PI.C_N	J701_8 (lead)	J701_8
DPHY1_PI.C_P	J701_9 (lead)	J701_9
DPHY2_PI.D0_N	J702_2 (lead)	J702_2
DPHY2_PI.D0_P	J702_3 (lead)	J702_3
DPHY2_PI.D1_N	J702_5 (lead)	J702_5
DPHY2_PI.D1_P	J702_6 (lead)	J702_6
DPHY2_PI.D2_N	J702_11 (lead)	J702_11
DPHY2_PI.D2_P	J702_12 (lead)	J702_12
DPHY2_PI.C_N	J702_8 (lead)	J702_8
DPHY2_PI.C_P	J702_9 (lead)	J702_9
USB1_PI.D_P	U201_3 (lead)	U201_3
USB1_PI.D_N	U201_1 (lead)	U201_1
USB2_PI.D_P	J202_2 (lead), U202_3 (lead)	-
USB2_PI.D_N	J202_3 (lead), U202_1 (lead)	-

Part pins the flying prober lands on
18 parts whose solder joints the flying prober lands on in place of test points. ICs and connectors are listed first and marked: the probe comes in at an angle beside their bodies, so check that the layout leaves the probe room to reach the joints listed.
Part	Type	Target	Electrical Opens	Purpose
U101	IC	U101_1 pin	No	Only probe point on its net; Provides opens testing to R118_1, R404_1
U103	IC	U103_4 pin	No	Only probe point on its net; Provides opens testing to R107_1
U103	IC	U103_6 pin	No	Only probe point on its net; Provides opens testing to R108_1
U201	IC	U201_1 pin	No	Only probe point on its net
U201	IC	U201_3 pin	No	Only probe point on its net
U201	IC	U201_4 pin	No	Only probe point on its net
U201	IC	U201_6 pin	No	Only probe point on its net
U202	IC	U202_1 pin	Yes	Shorts testing on its net
U202	IC	U202_3 pin	Yes	Shorts testing on its net
U401	IC	U401_2 pin	No	Only probe point on its net
U401	IC	U401_4 pin	No	Only probe point on its net
U601	IC	U601_1 pin	No	Shorts testing on its net
U601	IC	U601_3 pin	No	Shorts testing on its net
U601	IC	U601_4 pin	No	Shorts testing on its net
U601	IC	U601_6 pin	No	Shorts testing on its net
U802	IC	U802_1 pin	No	Only probe point on its net; Provides opens testing to R403_1, R802_2
U802	IC	U802_2 pin	No	Only probe point on its net; Provides opens testing to R801_1
U802	IC	U802_5 pin	No	Only probe point on its net; Provides opens testing to R401_1
U802	IC	U802_6 pin	No	Only probe point on its net; Provides opens testing to R402_1
U802	IC	U802_7 pin	No	Only probe point on its net; Provides opens testing to R803_2
J202	Connector	J202_2 pin	No	Provides opens testing to U202_3
J202	Connector	J202_3 pin	No	Provides opens testing to U202_1
J601	Connector	J601_1 pin	No	Shorts testing on its net
J601	Connector	J601_2 pin	No	Shorts testing on its net
J601	Connector	J601_3 pin	No	Shorts testing on its net
J601	Connector	J601_4 pin	No	Shorts testing on its net
J701	Connector	J701_11 pin	No	Only probe point on its net
J701	Connector	J701_12 pin	No	Only probe point on its net
J701	Connector	J701_14 pin	No	Only probe point on its net
J701	Connector	J701_15 pin	No	Only probe point on its net
J701	Connector	J701_17 pin	No	Only probe point on its net; Provides opens testing to Module401_97
J701	Connector	J701_18 pin	No	Only probe point on its net; Provides opens testing to Module401_100
J701	Connector	J701_2 pin	No	Only probe point on its net
J701	Connector	J701_20 pin	No	Only probe point on its net; Provides opens testing to Module401_80
J701	Connector	J701_21 pin	No	Only probe point on its net; Provides opens testing to Module401_82
J701	Connector	J701_3 pin	No	Only probe point on its net
J701	Connector	J701_5 pin	No	Only probe point on its net
J701	Connector	J701_6 pin	No	Only probe point on its net
J701	Connector	J701_8 pin	No	Only probe point on its net
J701	Connector	J701_9 pin	No	Only probe point on its net
J702	Connector	J702_11 pin	No	Only probe point on its net
J702	Connector	J702_12 pin	No	Only probe point on its net
J702	Connector	J702_14 pin	No	Only probe point on its net
J702	Connector	J702_15 pin	No	Only probe point on its net
J702	Connector	J702_17 pin	No	Only probe point on its net; Provides opens testing to Module401_37
J702	Connector	J702_18 pin	No	Only probe point on its net; Provides opens testing to Module401_39
J702	Connector	J702_2 pin	No	Only probe point on its net
J702	Connector	J702_20 pin	No	Only probe point on its net; Provides opens testing to Module401_35
J702	Connector	J702_21 pin	No	Only probe point on its net; Provides opens testing to Module401_36
J702	Connector	J702_3 pin	No	Only probe point on its net
J702	Connector	J702_5 pin	No	Only probe point on its net
J702	Connector	J702_6 pin	No	Only probe point on its net
J702	Connector	J702_8 pin	No	Only probe point on its net
J702	Connector	J702_9 pin	No	Only probe point on its net
D101	Other part	D101_1 pin	No	Only probe point on its net
D101	Other part	D101_2 pin	No	Only probe point on its net; Provides opens testing to R101_1
D102	Other part	D102_1 pin	No	Only probe point on its net
D102	Other part	D102_2 pin	No	Only probe point on its net; Provides opens testing to R102_1
D103	Other part	D103_1 pin	No	Only probe point on its net
D103	Other part	D103_2 pin	No	Only probe point on its net; Provides opens testing to R103_1
D104	Other part	D104_1 pin	No	Only probe point on its net
D104	Other part	D104_2 pin	No	Only probe point on its net; Provides opens testing to R104_1
D105	Other part	D105_1 pin	No	Only probe point on its net
D105	Other part	D105_2 pin	No	Only probe point on its net; Provides opens testing to R105_1
D201	Other part	D201_2 pin	No	Only probe point on its net
D401	Other part	D401_3 pin	No	Only probe point on its net

14.4 Nets that need an extended toe on at least one pin

14 nets with no probe access where an extended toe on at least one of the passive pins listed - the land extended by the IPC nominal toe plus 0.15 to 0.25 mm past the part's terminal, so bare copper stays exposed after reflow - lets the flying prober land on the net instead of a new test point. The layout engineer picks which pin; a net class on these nets carries the request to layout. Landing on that copper never touches the part, so its own joints are tested too. Only a flying prober uses it: a bed-of-nails fixture still needs test points.

Net	Passive pins that can take it	Other parts on the net	Fewer bad boards per million
Net-(U302-EN)	R301_2, R302_1	U302	18
VCC1	R325_1	U302	17
VIN1	C303_1, R312_2	U302	17
Net-(U801-REGOUT)	C803_1	U801	16
PR1	R304_2, R305_1	U301	4.8
OV1	R308_2, R309_1	U301	4.8
Net-(U301-ILIM)	R303_1	U301	3.6
OV2	R310_2, R311_1	U301	3.6
CP2	R306_2, R307_1	U301	3.6
Net-(U301-SS)	C301_2	U301	2.5
SPI_1_POCI	R801_2	Module401	2.1
SCLK_GPIO21_PT	R402_2	Module401	2.1
PICO_GPIO20_PT	R401_2	Module401	2.1
CS_GPIO24_PT	R403_2	Module401	2.1

14.5 Parts a capacitive plate would test best

1 parts where a capacitive plate on the tester's fixture would catch open solder joints that nothing else on this board catches, most gained first. A plate costs a fixture and programming time for each part it covers, so these are the parts where this board's own figures say it pays. The plate senses one pin at a time while a signal is driven onto the pin's net from a probe point elsewhere - a test point, a through-hole pin or a flying-probe landing on another part; the stimulus column counts the nets that still need one. Pins it cannot test: supply and ground pins (a signal on ground reaches every ground pin at once), pins sharing a net with another pin of the same part, and pins joined to another of its pins through a low resistance. Connectors with a metal shell or a right-angle body are left out: the plate cannot sense through metal or sit on them.

Only parts whose plate gives at least 100 fewer bad boards per million are listed: each plate costs a 4 x 4 mm sensor, electronics in the fixture, a drilled and aligned hole and its validation. That smallest gain is a setting you can change.

Part	Package	Pins the plate tests	Nets that need a probe point	Fewer bad boards per million
Module401	Module socket - the plate sits over the socket; the module is not fitted while the board is tested	21	1	999

14.6 Power Rail Test Point Check

Power rails found	8
Rails with TPs	5
Rails without TPs	3

3 power rail(s) need test points in the submitted design.

15 test point(s) inserted in modified output. Download modified schematics to see placements.

Power Rail Coverage
Net Name	Annotation	Test Point	Status
+3V3		TP101	✓
+5V		TP103	✓
+5V_BUS		J101_37, J101_38, J101_39, J101_40 (through-hole)	✓
+5V_USB		-	NEEDS TP
+VBAT_BUS		TP104	✓
5V_POL		-	NEEDS TP
GND		TP105	✓
VBAT_RTC		-	NEEDS TP

Inserted Test Points (Modified Output)
Test Point	Net	Sheet
TP313	VBAT_RTC	cm5.kicad_sch
TP317	5V_POL	power.kicad_sch
TP319	+5V_USB	usb.kicad_sch

Signal Net Test Points (Modified Output)
Test Point	Net	Sheet
TP305	CS_GPIO24_PT	cm5.kicad_sch
TP306	I2C_1_SCL	cm5.kicad_sch
TP307	I2C_1_SDA	cm5.kicad_sch
TP308	I2C_2_SCL	cm5.kicad_sch
TP309	I2C_2_SDA	cm5.kicad_sch
TP310	PWR_BUT	cm5.kicad_sch
TP311	SCLK_GPIO21_PT	cm5.kicad_sch
TP312	SPI_1_PICO	cm5.kicad_sch
TP314	RESET	connectors-blackwing.kicad_sch
TP315	Net-(U802-SO)	peripherals.kicad_sch
TP316	SPI_1_CS	peripherals.kicad_sch
TP318	Net-(U301-ILIM)	power.kicad_sch

14.7 IC Enable Test Point Check

ICs with enable pins (power switches, regulators, etc.) require test points for fixture-based test to disable the device during test.

IC	Type	Pin Name	Pin #	Issue
U302	TDK FS1603A-5000-AL	EN	3	EN has pull-up resistor but no test point at R301_2, R302_1, U302_3

14.8 Kelvin Test Points Check

Threshold	0.000 < R ≤ 1.000 Ω
Current sense resistors found	0

No current sense resistors found in range (0 < R < 1.000 ohm).

14.9 Current Test Points

Total test points

Test Points by Footprint
Footprint	Description	Count
TestPoint_Pad_D1.0mm	SPI_2_CS	22

14.9.1 By Sheet

Test Point	Net Name	Footprint
blackwing-cm5-payload-v1 (18 test points)
TP101	+3V3	TestPoint_Pad_D1.0mm
TP102	+3V3_M.2	TestPoint_Pad_D1.0mm
TP103	+5V	TestPoint_Pad_D1.0mm
TP104	+VBAT_BUS	TestPoint_Pad_D1.0mm
TP105	GND	TestPoint_Pad_D1.0mm
TP106	PMUX1_ST	TestPoint_Pad_D1.0mm
TP107	PMUX2_ST	TestPoint_Pad_D1.0mm
TP108	I2C_4_SCL	TestPoint_Pad_D1.0mm
TP109	I2C_4_SDA	TestPoint_Pad_D1.0mm
TP110	SPI_2_CS	TestPoint_Pad_D1.0mm
TP111	SPI_2_PICO	TestPoint_Pad_D1.0mm
TP112	SPI_2_POCI	TestPoint_Pad_D1.0mm
TP113	SPI_2_SCL	TestPoint_Pad_D1.0mm
TP114	UART_1_TX	TestPoint_Pad_D1.0mm
TP115	UART_1_RX	TestPoint_Pad_D1.0mm
TP116	UART_1_RTS	TestPoint_Pad_D1.0mm
TP117	UART_1_CTS	TestPoint_Pad_D1.0mm
TP118	GPIO2_BUS	TestPoint_Pad_D1.0mm
power (4 test points)
TP301	Net-(U302-PG)	TestPoint_Pad_D1.0mm
TP302	Net-(U302-VSW)	TestPoint_Pad_D1.0mm
TP303	M.2_PGOOD	TestPoint_Pad_D1.0mm
TP304	Net-(U304-VSW)	TestPoint_Pad_D1.0mm

14.9.2 All Test Points

Test Point	Net Name	Sheet	Footprint
TP101	+3V3	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP102	+3V3_M.2	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP103	+5V	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP104	+VBAT_BUS	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP105	GND	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP106	PMUX1_ST	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP107	PMUX2_ST	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP108	I2C_4_SCL	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP109	I2C_4_SDA	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP110	SPI_2_CS	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP111	SPI_2_PICO	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP112	SPI_2_POCI	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP113	SPI_2_SCL	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP114	UART_1_TX	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP115	UART_1_RX	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP116	UART_1_RTS	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP117	UART_1_CTS	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP118	GPIO2_BUS	blackwing-cm5-payload-v1	TestPoint_Pad_D1.0mm
TP301	Net-(U302-PG)	power	TestPoint_Pad_D1.0mm
TP302	Net-(U302-VSW)	power	TestPoint_Pad_D1.0mm
TP303	M.2_PGOOD	power	TestPoint_Pad_D1.0mm
TP304	Net-(U304-VSW)	power	TestPoint_Pad_D1.0mm

14.10 Powered-off Testing

96 nets with test points: 59 pins with opens coverage, 37 pins with partial opens, 425 pins with shorts coverage.

Open pin faults may be masked when two or more IC pins share a net (current flow through one internal pin ESD diode may mask the open on another).

Powered-off Test Coverage by Net
Pin ⇅	Net ⇅	Type ⇅	Opens ⇅	Shorts ⇅
C113_1	+3V3	Capacitor	-	●
C114_1	+3V3	Capacitor	-	●
C115_1	+3V3	Capacitor	-	●
C701_1	+3V3	Capacitor	-	●
C702_1	+3V3	Capacitor	-	●
C801_1	+3V3	Capacitor	-	●
C802_1	+3V3	Capacitor	-	●
C804_1	+3V3	Capacitor	-	●
C805_1	+3V3	Capacitor	-	●
C806_1	+3V3	Capacitor	-	●
J701_22	+3V3	Connector	-	●
J702_22	+3V3	Connector	-	●
Module401_78	+3V3	IC	-	●
Module401_84	+3V3	IC	-	●
Module401_86	+3V3	IC	-	●
R101_2	+3V3	Passive	●	●
R105_2	+3V3	Passive	●	●
R802_1	+3V3	Passive	●	●
R803_1	+3V3	Passive	●	●
U801_1	+3V3	IC	-	●
U801_5	+3V3	IC	-	●
U801_16	+3V3	IC	-	●
U802_3	+3V3	IC	-	●
U802_8	+3V3	IC	-	●
C101_1	+5V	Capacitor	-	●
C102_1	+5V	Capacitor	-	●
J202_1	+5V	Connector	-	●
Module401_77	+5V	IC	-	●
Module401_79	+5V	IC	-	●
Module401_81	+5V	IC	-	●
Module401_83	+5V	IC	-	●
Module401_85	+5V	IC	-	●
Module401_87	+5V	IC	-	●
R102_2	+5V	Passive	●	●
R103_2	+5V	Passive	●	●
R104_2	+5V	Passive	●	●
U202_4	+5V	IC	-	●
U301_1	+5V	IC	-	●
U301_1_1	+5V	IC	-	●
U301_8	+5V	IC	-	●
U301_8_1	+5V	IC	-	●
U401_5	+5V	IC	-	●
J101_37	+5V_BUS	Connector	-	●
J101_38	+5V_BUS	Connector	-	●
J101_39	+5V_BUS	Connector	-	●
J101_40	+5V_BUS	Connector	-	●
D201_2	+5V_USB	Passive	-	●
J201_A4	+5V_USB	Connector	-	●
J201_A9	+5V_USB	Connector	-	●
J201_B4	+5V_USB	Connector	-	●
J201_B9	+5V_USB	Connector	-	●
R304_1	+5V_USB	Passive	-	●
R308_1	+5V_USB	Passive	-	●
U301_7	+5V_USB	IC	-	●
U301_7_1	+5V_USB	IC	-	●
C105_1	+VBAT_BUS	Capacitor	-	●
C108_1	+VBAT_BUS	Capacitor	-	●
C111_1	+VBAT_BUS	Capacitor	-	●
C112_1	+VBAT_BUS	Capacitor	-	●
C304_1	+VBAT_BUS	Capacitor	-	●
J101_1	+VBAT_BUS	Connector	-	●
J101_2	+VBAT_BUS	Connector	-	●
J101_3	+VBAT_BUS	Connector	-	●
J101_4	+VBAT_BUS	Connector	-	●
R301_1	+VBAT_BUS	Passive	-	●
R312_1	+VBAT_BUS	Passive	-	●
U302_12	+VBAT_BUS	IC	-	●
U302_13	+VBAT_BUS	IC	-	●
U302_14	+VBAT_BUS	IC	-	●
U302_17	+VBAT_BUS	IC	-	●
J101_25	3V3	Connector	-	●
J101_26	3V3	Connector	-	●
J101_27	3V3	Connector	-	●
J101_28	3V3	Connector	-	●
J701_17	CAM1_GPIO1	Connector	-	●
Module401_97	CAM1_GPIO1	IC	●	●
J701_18	CAM1_GPIO2	Connector	-	●
Module401_100	CAM1_GPIO2	IC	●	●
J701_8	DPHY1_PI.C_N	Connector	-	●
Module402_127	DPHY1_PI.C_N	Connector	-	●
J701_9	DPHY1_PI.C_P	Connector	-	●
Module402_129	DPHY1_PI.C_P	Connector	-	●
J701_2	DPHY1_PI.D0_N	Connector	-	●
Module402_115	DPHY1_PI.D0_N	Connector	-	●
J701_3	DPHY1_PI.D0_P	Connector	-	●
Module402_117	DPHY1_PI.D0_P	Connector	-	●
J701_5	DPHY1_PI.D1_N	Connector	-	●
Module402_121	DPHY1_PI.D1_N	Connector	-	●
J701_6	DPHY1_PI.D1_P	Connector	-	●
Module402_123	DPHY1_PI.D1_P	Connector	-	●
J701_11	DPHY1_PI.D2_N	Connector	-	●
Module402_133	DPHY1_PI.D2_N	Connector	-	●
J701_12	DPHY1_PI.D2_P	Connector	-	●
Module402_135	DPHY1_PI.D2_P	Connector	-	●
J701_14	DPHY1_PI.D3_N	Connector	-	●
Module402_139	DPHY1_PI.D3_N	Connector	-	●
J701_15	DPHY1_PI.D3_P	Connector	-	●
Module402_141	DPHY1_PI.D3_P	Connector	-	●
J702_8	DPHY2_PI.C_N	Connector	-	●
Module402_187	DPHY2_PI.C_N	Connector	-	●
J702_9	DPHY2_PI.C_P	Connector	-	●
Module402_189	DPHY2_PI.C_P	Connector	-	●
J702_2	DPHY2_PI.D0_N	Connector	-	●
Module402_175	DPHY2_PI.D0_N	Connector	-	●
J702_3	DPHY2_PI.D0_P	Connector	-	●
Module402_177	DPHY2_PI.D0_P	Connector	-	●
J702_5	DPHY2_PI.D1_N	Connector	-	●
Module402_181	DPHY2_PI.D1_N	Connector	-	●
J702_6	DPHY2_PI.D1_P	Connector	-	●
Module402_183	DPHY2_PI.D1_P	Connector	-	●
J702_11	DPHY2_PI.D2_N	Connector	-	●
Module402_193	DPHY2_PI.D2_N	Connector	-	●
J702_12	DPHY2_PI.D2_P	Connector	-	●
Module402_195	DPHY2_PI.D2_P	Connector	-	●
J702_14	DPHY2_PI.D3_N	Connector	-	●
Module402_194	DPHY2_PI.D3_N	Connector	-	●
J702_15	DPHY2_PI.D3_P	Connector	-	●
Module402_196	DPHY2_PI.D3_P	Connector	-	●
J601_3	ETH_PI.TRD0_N	Connector	-	●
Module401_10	ETH_PI.TRD0_N	IC	◐	●
U601_3	ETH_PI.TRD0_N	IC	◐	●
J601_4	ETH_PI.TRD0_P	Connector	-	●
Module401_12	ETH_PI.TRD0_P	IC	◐	●
U601_1	ETH_PI.TRD0_P	IC	◐	●
J601_1	ETH_PI.TRD1_N	Connector	-	●
Module401_6	ETH_PI.TRD1_N	IC	◐	●
U601_6	ETH_PI.TRD1_N	IC	◐	●
J601_2	ETH_PI.TRD1_P	Connector	-	●
Module401_4	ETH_PI.TRD1_P	IC	◐	●
U601_4	ETH_PI.TRD1_P	IC	◐	●
Module401_49	FRAM_HOLD	IC	◐	●
R803_2	FRAM_HOLD	Passive	●	●
U802_7	FRAM_HOLD	IC	-	●
BT401_N	GND	Passive	-	●
C101_2	GND	Capacitor	-	●
C102_2	GND	Capacitor	-	●
C105_2	GND	Capacitor	-	●
C108_2	GND	Capacitor	-	●
C111_2	GND	Capacitor	-	●
C112_2	GND	Capacitor	-	●
C113_2	GND	Capacitor	-	●
C114_2	GND	Capacitor	-	●
C115_2	GND	Capacitor	-	●
C301_1	GND	Capacitor	-	●
C303_2	GND	Capacitor	-	●
C304_2	GND	Capacitor	-	●
C305_2	GND	Capacitor	-	●
C306_2	GND	Capacitor	-	●
C701_2	GND	Capacitor	-	●
C702_2	GND	Capacitor	-	●
C801_2	GND	Capacitor	-	●
C802_2	GND	Capacitor	-	●
C803_2	GND	Capacitor	-	●
C804_2	GND	Capacitor	-	●
C805_2	GND	Capacitor	-	●
C806_2	GND	Capacitor	-	●
D201_1	GND	Passive	●	●
H101_1	GND	Passive	●	●
H102_1	GND	Passive	●	●
H103_1	GND	Passive	●	●
H104_1	GND	Passive	●	●
JP101_2	GND	Connector	-	●
JP102_2	GND	Connector	-	●
J101_6	GND	Connector	-	●
J101_8	GND	Connector	-	●
J101_10	GND	Connector	-	●
J101_12	GND	Connector	-	●
J101_14	GND	Connector	-	●
J101_16	GND	Connector	-	●
J101_18	GND	Connector	-	●
J101_20	GND	Connector	-	●
J101_22	GND	Connector	-	●
J101_24	GND	Connector	-	●
J101_30	GND	Connector	-	●
J101_32	GND	Connector	-	●
J102_2	GND	Connector	-	●
J103_2	GND	Connector	-	●
J104_2	GND	Connector	-	●
J105_2	GND	Connector	-	●
J106_2	GND	Connector	-	●
J201_A1	GND	Connector	-	●
J201_A12	GND	Connector	-	●
J201_B1	GND	Connector	-	●
J201_B12	GND	Connector	-	●
J201_S1	GND	Connector	-	●
J202_4	GND	Connector	-	●
J701_1	GND	Connector	-	●
J701_4	GND	Connector	-	●
J701_7	GND	Connector	-	●
J701_10	GND	Connector	-	●
J701_13	GND	Connector	-	●
J701_16	GND	Connector	-	●
J701_19	GND	Connector	-	●
J702_1	GND	Connector	-	●
J702_4	GND	Connector	-	●
J702_7	GND	Connector	-	●
J702_10	GND	Connector	-	●
J702_13	GND	Connector	-	●
J702_16	GND	Connector	-	●
J702_19	GND	Connector	-	●
Module401_1	GND	IC	-	●
Module401_2	GND	IC	-	●
Module401_7	GND	IC	-	●
Module401_8	GND	IC	-	●
Module401_13	GND	IC	-	●
Module401_14	GND	IC	-	●
Module401_22	GND	IC	-	●
Module401_23	GND	IC	-	●
Module401_32	GND	IC	-	●
Module401_33	GND	IC	-	●
Module401_42	GND	IC	-	●
Module401_43	GND	IC	-	●
Module401_52	GND	IC	-	●
Module401_53	GND	IC	-	●
Module401_59	GND	IC	-	●
Module401_60	GND	IC	-	●
Module401_65	GND	IC	-	●
Module401_66	GND	IC	-	●
Module401_71	GND	IC	-	●
Module401_74	GND	IC	-	●
Module401_98	GND	IC	-	●
Module402_107	GND	Connector	-	●
Module402_108	GND	Connector	-	●
Module402_113	GND	Connector	-	●
Module402_114	GND	Connector	-	●
Module402_119	GND	Connector	-	●
Module402_120	GND	Connector	-	●
Module402_125	GND	Connector	-	●
Module402_126	GND	Connector	-	●
Module402_131	GND	Connector	-	●
Module402_132	GND	Connector	-	●
Module402_137	GND	Connector	-	●
Module402_138	GND	Connector	-	●
Module402_144	GND	Connector	-	●
Module402_150	GND	Connector	-	●
Module402_155	GND	Connector	-	●
Module402_156	GND	Connector	-	●
Module402_161	GND	Connector	-	●
Module402_162	GND	Connector	-	●
Module402_167	GND	Connector	-	●
Module402_168	GND	Connector	-	●
Module402_173	GND	Connector	-	●
Module402_174	GND	Connector	-	●
Module402_179	GND	Connector	-	●
Module402_180	GND	Connector	-	●
Module402_185	GND	Connector	-	●
Module402_186	GND	Connector	-	●
Module402_191	GND	Connector	-	●
Module402_192	GND	Connector	-	●
Module402_197	GND	Connector	-	●
Module402_198	GND	Connector	-	●
R302_2	GND	Passive	-	●
R303_2	GND	Passive	-	●
R305_2	GND	Passive	-	●
R307_2	GND	Passive	-	●
R309_2	GND	Passive	-	●
R311_2	GND	Passive	-	●
R404_2	GND	Passive	●	●
SW101_2	GND	Passive	-	●
SW101_3	GND	Passive	-	●
SW101_4	GND	Passive	-	●
SW102_2	GND	Passive	-	●
SW102_3	GND	Passive	-	●
SW102_4	GND	Passive	-	●
U101_2	GND	IC	-	●
U102_2	GND	IC	-	●
U103_2	GND	IC	-	●
U201_2	GND	IC	-	●
U202_2	GND	IC	-	●
U301_12	GND	IC	-	●
U302_6	GND	IC	-	●
U302_8	GND	IC	-	●
U302_9	GND	IC	-	●
U302_16	GND	IC	-	●
U401_3	GND	IC	-	●
U601_2	GND	IC	-	●
U801_4	GND	IC	-	●
U801_8	GND	IC	-	●
U801_9	GND	IC	-	●
U801_10	GND	IC	-	●
U801_11	GND	IC	-	●
U801_12	GND	IC	-	●
U801_13	GND	IC	-	●
U801_15	GND	IC	-	●
U802_4	GND	IC	-	●
J101_29	GPIO	Connector	-	●
R117_2	GPIO	Passive	●	●
Module401_41	GPIO2_BUS	IC	◐	●
R117_1	GPIO2_BUS	Passive	●	●
U101_3	GPIO2_BUS	IC	◐	●
J702_17	GPIO7	Connector	-	●
Module401_37	GPIO7	IC	●	●
J702_18	GPIO8	Connector	-	●
Module401_39	GPIO8	IC	●	●
J701_20	I2C_1_SCL	Connector	-	●
Module401_80	I2C_1_SCL	IC	●	●
J701_21	I2C_1_SDA	Connector	-	●
Module401_82	I2C_1_SDA	IC	●	●
J702_20	I2C_2_SCL	Connector	-	●
Module401_35	I2C_2_SCL	IC	●	●
J702_21	I2C_2_SDA	Connector	-	●
Module401_36	I2C_2_SDA	IC	●	●
Module401_56	I2C_3_SCL	IC	◐	●
R107_1	I2C_3_SCL	Passive	●	●
U103_4	I2C_3_SCL	IC	-	●
U302_4	I2C_3_SCL	IC	◐	●
U801_2	I2C_3_SCL	IC	◐	●
Module401_58	I2C_3_SDA	IC	◐	●
R108_1	I2C_3_SDA	Passive	●	●
U103_6	I2C_3_SDA	IC	-	●
U302_1	I2C_3_SDA	IC	◐	●
U801_3	I2C_3_SDA	IC	◐	●
J101_5	I2C_SCL	Connector	-	●
R107_2	I2C_SCL	Passive	●	●
J101_7	I2C_SDA	Connector	-	●
R108_2	I2C_SDA	Passive	●	●
JP103_2	LED_PI_PWR	Connector	-	●
U401_4	LED_PI_PWR	IC	-	●
Module401_95	LED_PI_PWR	IC	◐	●
U401_2	LED_PI_PWR	IC	-	●
Module401_30	M.2_PGOOD	IC	●	●
D101_2	Net-(D101-A)	Passive	-	●
R101_1	Net-(D101-A)	Passive	●	●
D101_1	Net-(D101-K)	Passive	-	●
JP101_1	Net-(D101-K)	Connector	-	●
D102_2	Net-(D102-A)	Passive	-	●
R102_1	Net-(D102-A)	Passive	●	●
D102_1	Net-(D102-K)	Passive	-	●
JP102_1	Net-(D102-K)	Connector	-	●
D103_2	Net-(D103-A)	Passive	-	●
R103_1	Net-(D103-A)	Passive	●	●
D103_1	Net-(D103-K)	Passive	-	●
JP103_1	Net-(D103-K)	Connector	-	●
D104_2	Net-(D104-A)	Passive	-	●
R104_1	Net-(D104-A)	Passive	●	●
D104_1	Net-(D104-K)	Passive	-	●
JP104_1	Net-(D104-K)	Connector	-	●
D105_2	Net-(D105-A)	Passive	-	●
R105_1	Net-(D105-A)	Passive	●	●
D105_1	Net-(D105-K)	Passive	-	●
JP105_1	Net-(D105-K)	Connector	-	●
R325_2	Net-(U302-PG)	Passive	-	●
U302_2	Net-(U302-PG)	IC	●	●
U302_15	Net-(U302-VSW)	IC	●	●
R801_1	Net-(U802-SO)	Passive	-	●
U802_2	Net-(U802-SO)	IC	-	●
U301_9	PMUX1_ST	IC	●	●
J101_31	RESET	Connector	-	●
R118_2	RESET	Passive	●	●
R403_1	SPI_1_CS	Passive	-	●
R802_2	SPI_1_CS	Passive	●	●
U802_1	SPI_1_CS	IC	-	●
R401_1	SPI_1_PICO	Passive	-	●
U802_5	SPI_1_PICO	IC	-	●
R402_1	SPI_1_SCL	Passive	-	●
U802_6	SPI_1_SCL	IC	-	●
Module401_46	SPI_2_CS	IC	◐	●
R112_1	SPI_2_CS	Passive	●	●
U102_6	SPI_2_CS	IC	◐	●
Module401_44	SPI_2_PICO	IC	◐	●
R109_1	SPI_2_PICO	Passive	●	●
U103_3	SPI_2_PICO	IC	◐	●
Module401_40	SPI_2_POCI	IC	◐	●
R110_1	SPI_2_POCI	Passive	●	●
U103_1	SPI_2_POCI	IC	◐	●
Module401_38	SPI_2_SCL	IC	◐	●
R111_1	SPI_2_SCL	Passive	●	●
U102_4	SPI_2_SCL	IC	◐	●
J101_15	SPI_CS0	Connector	-	●
R112_2	SPI_CS0	Passive	●	●
J101_9	SPI_PICO	Connector	-	●
R109_2	SPI_PICO	Passive	●	●
J101_11	SPI_POCI	Connector	-	●
R110_2	SPI_POCI	Passive	●	●
J101_13	SPI_SCK	Connector	-	●
R111_2	SPI_SCK	Passive	●	●
Module401_29	UART_1_CTS	IC	◐	●
R116_1	UART_1_CTS	Passive	●	●
U101_6	UART_1_CTS	IC	◐	●
Module401_50	UART_1_RTS	IC	◐	●
R115_1	UART_1_RTS	Passive	●	●
U101_4	UART_1_RTS	IC	◐	●
Module401_51	UART_1_RX	IC	◐	●
R113_1	UART_1_RX	Passive	●	●
U102_3	UART_1_RX	IC	◐	●
Module401_55	UART_1_TX	IC	◐	●
R114_1	UART_1_TX	Passive	●	●
U102_1	UART_1_TX	IC	◐	●
J101_21	UART_CTS	Connector	-	●
R115_2	UART_CTS	Passive	●	●
J101_23	UART_RTS	Connector	-	●
R116_2	UART_RTS	Passive	●	●
J101_19	UART_RX	Connector	-	●
R114_2	UART_RX	Passive	●	●
J101_17	UART_TX	Connector	-	●
R113_2	UART_TX	Passive	●	●
J201_A7	USB1_PI.D_N	Connector	-	●
J201_B7	USB1_PI.D_N	Connector	-	●
Module402_103	USB1_PI.D_N	Connector	-	●
U201_1	USB1_PI.D_N	IC	-	●
J201_A6	USB1_PI.D_P	Connector	-	●
J201_B6	USB1_PI.D_P	Connector	-	●
Module402_105	USB1_PI.D_P	Connector	-	●
U201_3	USB1_PI.D_P	IC	-	●
J202_3	USB2_PI.D_N	Connector	-	●
Module402_136	USB2_PI.D_N	Connector	-	●
U202_1	USB2_PI.D_N	IC	●	●
J202_2	USB2_PI.D_P	Connector	-	●
Module402_134	USB2_PI.D_P	Connector	-	●
U202_3	USB2_PI.D_P	IC	●	●
J201_A5	USB_CC1	Connector	-	●
Module401_94	USB_CC1	IC	◐	●
U201_6	USB_CC1	IC	-	●
J201_B5	USB_CC2	Connector	-	●
Module401_96	USB_CC2	IC	◐	●
U201_4	USB_CC2	IC	-	●
BT401_P2	VBAT_RTC	Passive	-	●
D401_3	VBAT_RTC	Passive	-	●
Module401_76	VBAT_RTC	IC	-	●
Module401_99	RESET	IC	◐	●
R118_1	RESET	Passive	●	●
R404_1	RESET	Passive	●	●
SW102_1	RESET	Passive	-	●
SW102_5	RESET	Passive	-	●
U101_1	RESET	IC	-	●

14.11 Powered-on Testing

Power rail voltage verification via test points. Measuring the output voltage under load verifies the path from regulator output through series passives to the rail.

5 power rail nets with test points: 1 source-path pins (opens + shorts), 213 sink pins (shorts only).

Powered-on Test Coverage by Power Rail
Pin ⇅	Net ⇅	Role ⇅	Opens ⇅	Shorts ⇅
C113_1	+3V3	Sink	-	●
C114_1	+3V3	Sink	-	●
C115_1	+3V3	Sink	-	●
C701_1	+3V3	Sink	-	●
C702_1	+3V3	Sink	-	●
C801_1	+3V3	Sink	-	●
C802_1	+3V3	Sink	-	●
C804_1	+3V3	Sink	-	●
C805_1	+3V3	Sink	-	●
C806_1	+3V3	Sink	-	●
J701_22	+3V3	Sink	-	●
J702_22	+3V3	Sink	-	●
Module401_78	+3V3	Sink	-	●
Module401_84	+3V3	Sink	-	●
Module401_86	+3V3	Sink	-	●
R101_2	+3V3	Sink	-	●
R105_2	+3V3	Sink	-	●
R802_1	+3V3	Sink	-	●
R803_1	+3V3	Sink	-	●
TP101_1	+3V3	Sink	-	●
U801_1	+3V3	Sink	-	●
U801_5	+3V3	Sink	-	●
U801_16	+3V3	Sink	-	●
U802_3	+3V3	Sink	-	●
U802_8	+3V3	Sink	-	●
TP102_1	+3V3_M.2	Sink	-	●
C101_1	+5V	Sink	-	●
C102_1	+5V	Sink	-	●
J202_1	+5V	Sink	-	●
Module401_77	+5V	Sink	-	●
Module401_79	+5V	Sink	-	●
Module401_81	+5V	Sink	-	●
Module401_83	+5V	Sink	-	●
Module401_85	+5V	Sink	-	●
Module401_87	+5V	Sink	-	●
R102_2	+5V	Sink	-	●
R103_2	+5V	Sink	-	●
R104_2	+5V	Sink	-	●
TP103_1	+5V	Sink	-	●
U202_4	+5V	Sink	-	●
U301_1	+5V	Source (OUT)	●	●
U301_1_1	+5V	Sink	-	●
U301_8	+5V	Sink	-	●
U301_8_1	+5V	Sink	-	●
U401_5	+5V	Sink	-	●
C105_1	+VBAT_BUS	Sink	-	●
C108_1	+VBAT_BUS	Sink	-	●
C111_1	+VBAT_BUS	Sink	-	●
C112_1	+VBAT_BUS	Sink	-	●
C304_1	+VBAT_BUS	Sink	-	●
J101_1	+VBAT_BUS	Sink	-	●
J101_2	+VBAT_BUS	Sink	-	●
J101_3	+VBAT_BUS	Sink	-	●
J101_4	+VBAT_BUS	Sink	-	●
R301_1	+VBAT_BUS	Sink	-	●
R312_1	+VBAT_BUS	Sink	-	●
TP104_1	+VBAT_BUS	Sink	-	●
U302_12	+VBAT_BUS	Sink	-	●
U302_13	+VBAT_BUS	Sink	-	●
U302_14	+VBAT_BUS	Sink	-	●
U302_17	+VBAT_BUS	Sink	-	●
BT401_N	GND	Sink	-	●
C101_2	GND	Sink	-	●
C102_2	GND	Sink	-	●
C105_2	GND	Sink	-	●
C108_2	GND	Sink	-	●
C111_2	GND	Sink	-	●
C112_2	GND	Sink	-	●
C113_2	GND	Sink	-	●
C114_2	GND	Sink	-	●
C115_2	GND	Sink	-	●
C301_1	GND	Sink	-	●
C303_2	GND	Sink	-	●
C304_2	GND	Sink	-	●
C305_2	GND	Sink	-	●
C306_2	GND	Sink	-	●
C701_2	GND	Sink	-	●
C702_2	GND	Sink	-	●
C801_2	GND	Sink	-	●
C802_2	GND	Sink	-	●
C803_2	GND	Sink	-	●
C804_2	GND	Sink	-	●
C805_2	GND	Sink	-	●
C806_2	GND	Sink	-	●
D201_1	GND	Sink	-	●
H101_1	GND	Sink	-	●
H102_1	GND	Sink	-	●
H103_1	GND	Sink	-	●
H104_1	GND	Sink	-	●
JP101_2	GND	Sink	-	●
JP102_2	GND	Sink	-	●
J101_6	GND	Sink	-	●
J101_8	GND	Sink	-	●
J101_10	GND	Sink	-	●
J101_12	GND	Sink	-	●
J101_14	GND	Sink	-	●
J101_16	GND	Sink	-	●
J101_18	GND	Sink	-	●
J101_20	GND	Sink	-	●
J101_22	GND	Sink	-	●
J101_24	GND	Sink	-	●
J101_30	GND	Sink	-	●
J101_32	GND	Sink	-	●
J102_2	GND	Sink	-	●
J103_2	GND	Sink	-	●
J104_2	GND	Sink	-	●
J105_2	GND	Sink	-	●
J106_2	GND	Sink	-	●
J201_A1	GND	Sink	-	●
J201_A12	GND	Sink	-	●
J201_B1	GND	Sink	-	●
J201_B12	GND	Sink	-	●
J201_S1	GND	Sink	-	●
J202_4	GND	Sink	-	●
J701_1	GND	Sink	-	●
J701_4	GND	Sink	-	●
J701_7	GND	Sink	-	●
J701_10	GND	Sink	-	●
J701_13	GND	Sink	-	●
J701_16	GND	Sink	-	●
J701_19	GND	Sink	-	●
J702_1	GND	Sink	-	●
J702_4	GND	Sink	-	●
J702_7	GND	Sink	-	●
J702_10	GND	Sink	-	●
J702_13	GND	Sink	-	●
J702_16	GND	Sink	-	●
J702_19	GND	Sink	-	●
Module401_1	GND	Sink	-	●
Module401_2	GND	Sink	-	●
Module401_7	GND	Sink	-	●
Module401_8	GND	Sink	-	●
Module401_13	GND	Sink	-	●
Module401_14	GND	Sink	-	●
Module401_22	GND	Sink	-	●
Module401_23	GND	Sink	-	●
Module401_32	GND	Sink	-	●
Module401_33	GND	Sink	-	●
Module401_42	GND	Sink	-	●
Module401_43	GND	Sink	-	●
Module401_52	GND	Sink	-	●
Module401_53	GND	Sink	-	●
Module401_59	GND	Sink	-	●
Module401_60	GND	Sink	-	●
Module401_65	GND	Sink	-	●
Module401_66	GND	Sink	-	●
Module401_71	GND	Sink	-	●
Module401_74	GND	Sink	-	●
Module401_98	GND	Sink	-	●
Module402_107	GND	Sink	-	●
Module402_108	GND	Sink	-	●
Module402_113	GND	Sink	-	●
Module402_114	GND	Sink	-	●
Module402_119	GND	Sink	-	●
Module402_120	GND	Sink	-	●
Module402_125	GND	Sink	-	●
Module402_126	GND	Sink	-	●
Module402_131	GND	Sink	-	●
Module402_132	GND	Sink	-	●
Module402_137	GND	Sink	-	●
Module402_138	GND	Sink	-	●
Module402_144	GND	Sink	-	●
Module402_150	GND	Sink	-	●
Module402_155	GND	Sink	-	●
Module402_156	GND	Sink	-	●
Module402_161	GND	Sink	-	●
Module402_162	GND	Sink	-	●
Module402_167	GND	Sink	-	●
Module402_168	GND	Sink	-	●
Module402_173	GND	Sink	-	●
Module402_174	GND	Sink	-	●
Module402_179	GND	Sink	-	●
Module402_180	GND	Sink	-	●
Module402_185	GND	Sink	-	●
Module402_186	GND	Sink	-	●
Module402_191	GND	Sink	-	●
Module402_192	GND	Sink	-	●
Module402_197	GND	Sink	-	●
Module402_198	GND	Sink	-	●
R302_2	GND	Sink	-	●
R303_2	GND	Sink	-	●
R305_2	GND	Sink	-	●
R307_2	GND	Sink	-	●
R309_2	GND	Sink	-	●
R311_2	GND	Sink	-	●
R404_2	GND	Sink	-	●
SW101_2	GND	Sink	-	●
SW101_3	GND	Sink	-	●
SW101_4	GND	Sink	-	●
SW102_2	GND	Sink	-	●
SW102_3	GND	Sink	-	●
SW102_4	GND	Sink	-	●
TP105_1	GND	Sink	-	●
U101_2	GND	Sink	-	●
U102_2	GND	Sink	-	●
U103_2	GND	Sink	-	●
U201_2	GND	Sink	-	●
U202_2	GND	Sink	-	●
U301_12	GND	Sink	-	●
U302_6	GND	Sink	-	●
U302_8	GND	Sink	-	●
U302_9	GND	Sink	-	●
U302_16	GND	Sink	-	●
U401_3	GND	Sink	-	●
U601_2	GND	Sink	-	●
U801_4	GND	Sink	-	●
U801_8	GND	Sink	-	●
U801_9	GND	Sink	-	●
U801_10	GND	Sink	-	●
U801_11	GND	Sink	-	●
U801_12	GND	Sink	-	●
U801_13	GND	Sink	-	●
U801_15	GND	Sink	-	●
U802_4	GND	Sink	-	●

14.12 Boundary Scan Testability

No boundary scan capable devices were found in this design.

14.13 Inspection

Total: 88 components, 388 of 464 pins with inspection coverage.

14.13.1 AOI

Package Identified from the Footprint Name (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251, but each one names its package: a chip size code (0201 or larger) or a package name such as SOT, SOIC or QFP. These solder joints count toward inspection coverage.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Blackwing CM5 v1
Infineon-CY15B102Q-SXET			SOIC/SOP	Part data	1	8	U802
TI-TPD4E1B06DRL [SOT-5X3 (DRL)]			SOIC/SOP	Part data	6	29	U101, U102, U103, U201, U202, U601
Package_TO_SOT_SMD
SOT-23-3			SOT (Small Outline Transistor)	Footprint	1	1	D401
SOT-23-5			SOT (Small Outline Transistor)	Footprint	1	4	U401
Blackwing CM5 v1
C-0603			Chip Passive	Footprint size	3	6	C304, C801, C804
C-0603-0.1u			Chip Passive	Footprint size	6	12	C101, C102, C112, C114, C802, C806
C-0603-1u			Chip Passive	Footprint size	3	6	C301, C303, C803
C-0805-10u			Chip Passive	Footprint size	6	12	C111, C113, C115, C701, C702, C805
C-2917 [D/7343-31]			Chip Passive	Part data	2	4	C105, C108
R-0603			Chip Passive	Footprint size	28	56	R102, R103, R104, R107, R108, R109, R110, R111 ...+20 more
R-0603-10k			Chip Passive	Footprint size	7	14	R302, R305, R307, R309, R311, R802, R803
R-0603-1k			Chip Passive	Footprint size	2	4	R101, R105
Capacitor_SMD
C_1210_3225Metric			Chip Passive	Footprint size	2	4	C305, C306
Blackwing CM5 v1
WE-150060VS55040-LED-G [WL-SMCD SMT Mono-color Chip LED Diffused (0603)]			SOD (Diode Package)	Part data	1	2	D105
WE-150060WS75000-LED-W [0603]			SOD (Diode Package)	Part data	1	2	D104
Diode_SMD
D_0603_1608Metric [SOT-5X3 (DYA)]			SOD (Diode Package)	Part data	1	2	D201
Blackwing CM5 v1
Hirose-FH12A-22S-0.5SH-FPC-CSI-DSI			Connector	Part data	2	44	J701, J702
Molex-0533984004-PicoBlade-53398			Connector	Part data	2	8	J202, J601
Samtec-SFM-120-01-X-D			Connector	Part data	1	36	J101
CK-KMS223GP-LFG [KMS Series]			Unclassified	Part data	2	10	SW101, SW102
Subtotal: 78 components, 264 pins

Assumed Classification (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251. Package type inferred from Pkg Type property or designator prefix. Classification may be incorrect.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Opens + Shorts (all joints visible)
Blackwing CM5 v1
Amphenol-10164227-1001A1RLF-CM5-GPIO			SOIC/SOP	Designator	1	74	Module401
Subtotal: 1 components, 74 pins

14.13.2 AXI

Package Identified from the Footprint Name (Non-IPC Footprints)
Footprint names are not IPC-7351B or IPC-7251, but each one names its package (QFN, DFN, BGA or LGA). These hidden joints count toward X-ray inspection coverage.
Footprint	Size (mil)	Pkg Type	Classification	Method	Count	Pins	Refdes
Blackwing CM5 v1
TDK-FS1606 [17L Open Top LGA SiP (A01)]			LGA (Land Grid Array)	Part data	1	17	U302
TDK-IAM-20380_IVS			LGA (Land Grid Array)	Part data	1	15	U801
TI-TPS2121			QFN/DFN (No-Lead)	Part data	1	16	U301
SunLED-XZFRS53FVF-1 [1.6 x 0.8 mm SMD Chip LED Lamp]			SOD (Diode Package)	Part data	3	6	D101, D102, D103
Amphenol-10164227-1001A1RLF-CM5-HSS			Connector	Part data	1	55	Module402
JAE-DX07S016JA1R1500			Connector	Part data	1	15	J201
Subtotal: 8 components, 124 pins

14.13.3 Unclassified Components

Footprint	Classification	Method	Count	Pins	Refdes
These components could not be classified for inspection. The library symbol lacks a Pkg Type property and the footprint name is not IPC-7351B or IPC-7251.
Blackwing CM5 v1
Keystone-2998	Unclassified	Unknown	1	2	BT401
Subtotal: 1 components, 2 pins

14.14 Solder-Joint Testability

Predicted status of each pin for shorts and opens based on DFx options selected in section 14.1.

14.14.1 Solder-Joint Testability Summary

Solder-Joint Testability Summary (484 solder joints)
Test Method	Opens	Shorts
X-ray (AXI)	132 (27.3%)	132 (27.3%)
Optical (AOI)	264 (54.5%)	264 (54.5%)
Electrical
Powered-off Testing	60 (12.4%)	421 (87.0%)
Boundary Scan	0 (0.0%)	0 (0.0%)
LSSI	-	-
Total	68 (14.0%)	439 (90.7%)
Total Solder-Joint Testability	401 (82.9%)	467 (96.5%)
No coverage	83 (17.1%)	17 (3.5%)

14.14.2 Untestable Solder Joints (17)

Pin ⇅	Net ⇅
These pins have no electrical, optical, or X-ray test coverage even with all available test techniques applied.
JP104_2	LED_PI_ACT
J105_1	USBOTG_ID
J103_1	WL-EN
J102_1	BOOT
J106_1	EEPROM_WP
JP105_2	LED_ETH
J104_1	BT-EN
Module401_15	LED_ETH
Module401_20	EEPROM_WP
Module401_21	LED_PI_ACT
Module401_47	GYRO_INT
Module401_88	1V8_CM5
Module401_89	WL-EN
Module401_90	1V8_CM5
Module401_91	BT-EN
Module401_92	PWR_BUT
Module401_93	BOOT

14.14.3 Per-Solder-Joint Testability Matrix

● = Detected ◐ = Partially detected - = Not tested | E = Electrical (ICT/flying probe) O = Optical (AOI) X = X-ray (AXI)

Pin ⇅	Net ⇅	E Opens ⇅	E Shorts ⇅	O Opens ⇅	O Shorts ⇅	X Opens ⇅	X Shorts ⇅
R102_1	Net-(D102-A)	●	●	●	◐	-	-
R102_2	+5V	●	●	●	◐	-	-
SW102_1	RESET	-	●	●	◐	-	-
SW102_3	GND	-	●	●	◐	-	-
SW102_4	GND	-	●	●	◐	-	-
SW102_2	GND	-	●	●	◐	-	-
SW102_5	RESET	-	●	●	◐	-	-
R105_1	Net-(D105-A)	●	●	●	◐	-	-
R105_2	+3V3	●	●	●	◐	-	-
JP104_1	Net-(D104-K)	-	●	-	-	-	-
JP104_2	LED_PI_ACT	-	-	-	-	-	-
D105_1	Net-(D105-K)	-	●	●	◐	-	-
D105_2	Net-(D105-A)	-	●	●	◐	-	-
J105_1	USBOTG_ID	-	-	-	-	-	-
J105_2	GND	-	●	-	-	-	-
R101_1	Net-(D101-A)	●	●	●	◐	-	-
R101_2	+3V3	●	●	●	◐	-	-
SW101_1	PWR_BUT	-	-	●	◐	-	-
SW101_3	GND	-	●	●	◐	-	-
SW101_4	GND	-	●	●	◐	-	-
SW101_2	GND	-	●	●	◐	-	-
SW101_5	PWR_BUT	-	-	●	◐	-	-
J103_1	WL-EN	-	-	-	-	-	-
J103_2	GND	-	●	-	-	-	-
D102_1	Net-(D102-K)	-	●	-	-	●	◐
D102_2	Net-(D102-A)	-	●	-	-	●	◐
JP102_1	Net-(D102-K)	-	●	-	-	-	-
JP102_2	GND	-	●	-	-	-	-
C101_1	+5V	-	●	●	◐	-	-
C101_2	GND	-	●	●	◐	-	-
JP103_1	Net-(D103-K)	-	●	-	-	-	-
JP103_2	LED_PI_PWR	-	●	-	-	-	-
R103_1	Net-(D103-A)	●	●	●	◐	-	-
R103_2	+5V	●	●	●	◐	-	-
C113_1	+3V3	-	●	●	◐	-	-
C113_2	GND	-	●	●	◐	-	-
C102_1	+5V	-	●	●	◐	-	-
C102_2	GND	-	●	●	◐	-	-
J102_1	BOOT	-	-	-	-	-	-
J102_2	GND	-	●	-	-	-	-
R104_1	Net-(D104-A)	●	●	●	◐	-	-
R104_2	+5V	●	●	●	◐	-	-
J106_1	EEPROM_WP	-	-	-	-	-	-
J106_2	GND	-	●	-	-	-	-
JP105_1	Net-(D105-K)	-	●	-	-	-	-
JP105_2	LED_ETH	-	-	-	-	-	-
J104_1	BT-EN	-	-	-	-	-	-
J104_2	GND	-	●	-	-	-	-
D104_1	Net-(D104-K)	-	●	●	◐	-	-
D104_2	Net-(D104-A)	-	●	●	◐	-	-
C114_1	+3V3	-	●	●	◐	-	-
C114_2	GND	-	●	●	◐	-	-
D101_1	Net-(D101-K)	-	●	-	-	●	◐
D101_2	Net-(D101-A)	-	●	-	-	●	◐
C115_1	+3V3	-	●	●	◐	-	-
C115_2	GND	-	●	●	◐	-	-
JP101_1	Net-(D101-K)	-	●	-	-	-	-
JP101_2	GND	-	●	-	-	-	-
D103_1	Net-(D103-K)	-	●	-	-	●	◐
D103_2	Net-(D103-A)	-	●	-	-	●	◐
Module402_101	USBOTG_ID	-	-	-	-	●	◐
Module402_103	USB1_PI.D_N	-	●	-	-	●	◐
Module402_105	USB1_PI.D_P	-	●	-	-	●	◐
Module402_107	GND	-	●	-	-	●	◐
Module402_108	GND	-	●	-	-	●	◐
Module402_113	GND	-	●	-	-	●	◐
Module402_114	GND	-	●	-	-	●	◐
Module402_115	DPHY1_PI.D0_N	-	●	-	-	●	◐
Module402_117	DPHY1_PI.D0_P	-	●	-	-	●	◐
Module402_119	GND	-	●	-	-	●	◐
Module402_120	GND	-	●	-	-	●	◐
Module402_121	DPHY1_PI.D1_N	-	●	-	-	●	◐
Module402_123	DPHY1_PI.D1_P	-	●	-	-	●	◐
Module402_125	GND	-	●	-	-	●	◐
Module402_126	GND	-	●	-	-	●	◐
Module402_127	DPHY1_PI.C_N	-	●	-	-	●	◐
Module402_129	DPHY1_PI.C_P	-	●	-	-	●	◐
Module402_131	GND	-	●	-	-	●	◐
Module402_132	GND	-	●	-	-	●	◐
Module402_133	DPHY1_PI.D2_N	-	●	-	-	●	◐
Module402_134	USB2_PI.D_P	-	●	-	-	●	◐
Module402_135	DPHY1_PI.D2_P	-	●	-	-	●	◐
Module402_136	USB2_PI.D_N	-	●	-	-	●	◐
Module402_137	GND	-	●	-	-	●	◐
Module402_138	GND	-	●	-	-	●	◐
Module402_139	DPHY1_PI.D3_N	-	●	-	-	●	◐
Module402_141	DPHY1_PI.D3_P	-	●	-	-	●	◐
Module402_144	GND	-	●	-	-	●	◐
Module402_150	GND	-	●	-	-	●	◐
Module402_155	GND	-	●	-	-	●	◐
Module402_156	GND	-	●	-	-	●	◐
Module402_161	GND	-	●	-	-	●	◐
Module402_162	GND	-	●	-	-	●	◐
Module402_167	GND	-	●	-	-	●	◐
Module402_168	GND	-	●	-	-	●	◐
Module402_173	GND	-	●	-	-	●	◐
Module402_174	GND	-	●	-	-	●	◐
Module402_175	DPHY2_PI.D0_N	-	●	-	-	●	◐
Module402_177	DPHY2_PI.D0_P	-	●	-	-	●	◐
Module402_179	GND	-	●	-	-	●	◐
Module402_180	GND	-	●	-	-	●	◐
Module402_181	DPHY2_PI.D1_N	-	●	-	-	●	◐
Module402_183	DPHY2_PI.D1_P	-	●	-	-	●	◐
Module402_185	GND	-	●	-	-	●	◐
Module402_186	GND	-	●	-	-	●	◐
Module402_187	DPHY2_PI.C_N	-	●	-	-	●	◐
Module402_189	DPHY2_PI.C_P	-	●	-	-	●	◐
Module402_191	GND	-	●	-	-	●	◐
Module402_192	GND	-	●	-	-	●	◐
Module402_193	DPHY2_PI.D2_N	-	●	-	-	●	◐
Module402_194	DPHY2_PI.D3_N	-	●	-	-	●	◐
Module402_195	DPHY2_PI.D2_P	-	●	-	-	●	◐
Module402_196	DPHY2_PI.D3_P	-	●	-	-	●	◐
Module402_197	GND	-	●	-	-	●	◐
Module402_198	GND	-	●	-	-	●	◐
R402_1	SPI_1_SCL	●	●	●	◐	-	-
R402_2	SCLK_GPIO21_PT	●	◐	●	◐	-	-
R404_1	RESET	●	●	●	◐	-	-
R404_2	GND	●	●	●	◐	-	-
Module401_1	GND	-	●	-	-	-	-
Module401_2	GND	-	●	-	-	-	-
Module401_4	ETH_PI.TRD1_P	-	●	-	-	-	-
Module401_6	ETH_PI.TRD1_N	-	●	-	-	-	-
Module401_7	GND	-	●	-	-	-	-
Module401_8	GND	-	●	-	-	-	-
Module401_10	ETH_PI.TRD0_N	-	●	-	-	-	-
Module401_12	ETH_PI.TRD0_P	-	●	-	-	-	-
Module401_13	GND	-	●	-	-	-	-
Module401_14	GND	-	●	-	-	-	-
Module401_15	LED_ETH	-	-	-	-	-	-
Module401_20	EEPROM_WP	-	-	-	-	-	-
Module401_21	LED_PI_ACT	-	-	-	-	-	-
Module401_22	GND	-	●	-	-	-	-
Module401_23	GND	-	●	-	-	-	-
Module401_25	SCLK_GPIO21_PT	●	◐	-	-	-	-
Module401_26	SPI_1_POCI	●	◐	-	-	-	-
Module401_27	PICO_GPIO20_PT	●	◐	-	-	-	-
Module401_29	UART_1_CTS	-	●	-	-	-	-
Module401_30	M.2_PGOOD	●	●	-	-	-	-
Module401_32	GND	-	●	-	-	-	-
Module401_33	GND	-	●	-	-	-	-
Module401_35	I2C_2_SCL	●	●	-	-	-	-
Module401_36	I2C_2_SDA	●	●	-	-	-	-
Module401_37	GPIO7	●	●	-	-	-	-
Module401_38	SPI_2_SCL	-	●	-	-	-	-
Module401_39	GPIO8	●	●	-	-	-	-
Module401_40	SPI_2_POCI	-	●	-	-	-	-
Module401_41	GPIO2_BUS	-	●	-	-	-	-
Module401_42	GND	-	●	-	-	-	-
Module401_43	GND	-	●	-	-	-	-
Module401_44	SPI_2_PICO	-	●	-	-	-	-
Module401_45	CS_GPIO24_PT	●	◐	-	-	-	-
Module401_46	SPI_2_CS	-	●	-	-	-	-
Module401_47	GYRO_INT	-	-	-	-	-	-
Module401_49	FRAM_HOLD	-	●	-	-	-	-
Module401_50	UART_1_RTS	-	●	-	-	-	-
Module401_51	UART_1_RX	-	●	-	-	-	-
Module401_52	GND	-	●	-	-	-	-
Module401_53	GND	-	●	-	-	-	-
Module401_55	UART_1_TX	-	●	-	-	-	-
Module401_56	I2C_3_SCL	-	●	-	-	-	-
Module401_58	I2C_3_SDA	-	●	-	-	-	-
Module401_59	GND	-	●	-	-	-	-
Module401_60	GND	-	●	-	-	-	-
Module401_65	GND	-	●	-	-	-	-
Module401_66	GND	-	●	-	-	-	-
Module401_71	GND	-	●	-	-	-	-
Module401_74	GND	-	●	-	-	-	-
Module401_76	VBAT_RTC	-	●	-	-	-	-
Module401_77	+5V	-	●	-	-	-	-
Module401_78	+3V3	-	●	-	-	-	-
Module401_79	+5V	-	●	-	-	-	-
Module401_80	I2C_1_SCL	●	●	-	-	-	-
Module401_81	+5V	-	●	-	-	-	-
Module401_82	I2C_1_SDA	●	●	-	-	-	-
Module401_83	+5V	-	●	-	-	-	-
Module401_84	+3V3	-	●	-	-	-	-
Module401_85	+5V	-	●	-	-	-	-
Module401_86	+3V3	-	●	-	-	-	-
Module401_87	+5V	-	●	-	-	-	-
Module401_88	1V8_CM5	-	-	-	-	-	-
Module401_89	WL-EN	-	-	-	-	-	-
Module401_90	1V8_CM5	-	-	-	-	-	-
Module401_91	BT-EN	-	-	-	-	-	-
Module401_92	PWR_BUT	-	-	-	-	-	-
Module401_93	BOOT	-	-	-	-	-	-
Module401_94	USB_CC1	-	●	-	-	-	-
Module401_95	LED_PI_PWR	-	●	-	-	-	-
Module401_96	USB_CC2	-	●	-	-	-	-
Module401_97	CAM1_GPIO1	●	●	-	-	-	-
Module401_98	GND	-	●	-	-	-	-
Module401_99	RESET	-	●	-	-	-	-
Module401_100	CAM1_GPIO2	●	●	-	-	-	-
R403_1	SPI_1_CS	●	●	●	◐	-	-
R403_2	CS_GPIO24_PT	●	◐	●	◐	-	-
R401_1	SPI_1_PICO	●	●	●	◐	-	-
R401_2	PICO_GPIO20_PT	●	◐	●	◐	-	-
BT401_N	GND	-	●	-	-	-	-
BT401_P2	VBAT_RTC	-	●	-	-	-	-
U401_2	LED_PI_PWR	-	●	●	◐	-	-
U401_3	GND	-	●	●	◐	-	-
U401_4	LED_PI_PWR	-	●	●	◐	-	-
U401_5	+5V	-	●	●	◐	-	-
D401_3	VBAT_RTC	-	●	●	◐	-	-
D201_1	GND	●	●	●	◐	-	-
D201_2	+5V_USB	-	●	●	◐	-	-
U202_1	USB2_PI.D_N	●	●	●	◐	-	-
U202_2	GND	-	●	●	◐	-	-
U202_3	USB2_PI.D_P	●	●	●	◐	-	-
U202_4	+5V	-	●	●	◐	-	-
U201_1	USB1_PI.D_N	-	●	●	◐	-	-
U201_2	GND	-	●	●	◐	-	-
U201_3	USB1_PI.D_P	-	●	●	◐	-	-
U201_4	USB_CC2	-	●	●	◐	-	-
U201_6	USB_CC1	-	●	●	◐	-	-
J202_1	+5V	-	●	●	◐	●	◐
J202_2	USB2_PI.D_P	-	●	●	◐	●	◐
J202_3	USB2_PI.D_N	-	●	●	◐	●	◐
J202_4	GND	-	●	●	◐	●	◐
J201_A1	GND	-	●	-	-	●	◐
J201_A4	+5V_USB	-	●	-	-	●	◐
J201_A5	USB_CC1	-	●	-	-	●	◐
J201_A6	USB1_PI.D_P	-	●	-	-	●	◐
J201_A7	USB1_PI.D_N	-	●	-	-	●	◐
J201_A9	+5V_USB	-	●	-	-	●	◐
J201_A12	GND	-	●	-	-	●	◐
J201_B1	GND	-	●	-	-	●	◐
J201_B4	+5V_USB	-	●	-	-	●	◐
J201_B5	USB_CC2	-	●	-	-	●	◐
J201_B6	USB1_PI.D_P	-	●	-	-	●	◐
J201_B7	USB1_PI.D_N	-	●	-	-	●	◐
J201_B9	+5V_USB	-	●	-	-	●	◐
J201_B12	GND	-	●	-	-	●	◐
J201_S1	GND	-	●	-	-	●	◐
J601_1	ETH_PI.TRD1_N	-	●	●	◐	●	◐
J601_2	ETH_PI.TRD1_P	-	●	●	◐	●	◐
J601_3	ETH_PI.TRD0_N	-	●	●	◐	●	◐
J601_4	ETH_PI.TRD0_P	-	●	●	◐	●	◐
U601_1	ETH_PI.TRD0_P	-	●	●	◐	-	-
U601_2	GND	-	●	●	◐	-	-
U601_3	ETH_PI.TRD0_N	-	●	●	◐	-	-
U601_4	ETH_PI.TRD1_P	-	●	●	◐	-	-
U601_6	ETH_PI.TRD1_N	-	●	●	◐	-	-
R301_1	+VBAT_BUS	-	●	●	◐	-	-
R301_2	Net-(U302-EN)	-	-	●	◐	-	-
U302_1	I2C_3_SDA	-	●	-	-	●	◐
U302_2	Net-(U302-PG)	●	●	-	-	●	◐
U302_3	Net-(U302-EN)	-	-	-	-	●	◐
U302_4	I2C_3_SCL	-	●	-	-	●	◐
U302_5	5V_POL	-	●	-	-	●	◐
U302_6	GND	-	●	-	-	●	◐
U302_7	5V_POL	-	●	-	-	●	◐
U302_8	GND	-	●	-	-	●	◐
U302_9	GND	-	●	-	-	●	◐
U302_10	VCC1	-	●	-	-	●	◐
U302_11	VIN1	-	-	-	-	●	◐
U302_12	+VBAT_BUS	-	●	-	-	●	◐
U302_13	+VBAT_BUS	-	●	-	-	●	◐
U302_14	+VBAT_BUS	-	●	-	-	●	◐
U302_15	Net-(U302-VSW)	●	●	-	-	●	◐
U302_16	GND	-	●	-	-	●	◐
U302_17	+VBAT_BUS	-	●	-	-	●	◐
R306_1	5V_POL	-	●	●	◐	-	-
R306_2	CP2	-	-	●	◐	-	-
C303_1	VIN1	-	-	●	◐	-	-
C303_2	GND	-	●	●	◐	-	-
R307_1	CP2	-	-	●	◐	-	-
R307_2	GND	-	●	●	◐	-	-
C306_1	5V_POL	-	●	●	◐	-	-
C306_2	GND	-	●	●	◐	-	-
R325_1	VCC1	-	●	●	◐	-	-
R325_2	Net-(U302-PG)	-	●	●	◐	-	-
R311_1	OV2	-	-	●	◐	-	-
R311_2	GND	-	●	●	◐	-	-
C304_1	+VBAT_BUS	-	●	●	◐	-	-
C304_2	GND	-	●	●	◐	-	-
R308_1	+5V_USB	-	●	●	◐	-	-
R308_2	OV1	-	-	●	◐	-	-
C305_1	5V_POL	-	●	●	◐	-	-
C305_2	GND	-	●	●	◐	-	-
R303_1	Net-(U301-ILIM)	-	-	●	◐	-	-
R303_2	GND	-	●	●	◐	-	-
R305_1	PR1	-	-	●	◐	-	-
R305_2	GND	-	●	●	◐	-	-
U301_1	+5V	●	●	-	-	●	◐
U301_1_1	+5V	-	●	-	-	●	◐
U301_2	5V_POL	-	●	-	-	●	◐
U301_2_1	5V_POL	-	●	-	-	●	◐
U301_3	CP2	-	-	-	-	●	◐
U301_4	OV2	-	-	-	-	●	◐
U301_5	OV1	-	-	-	-	●	◐
U301_6	PR1	-	-	-	-	●	◐
U301_7	+5V_USB	-	●	-	-	●	◐
U301_7_1	+5V_USB	-	●	-	-	●	◐
U301_8	+5V	-	●	-	-	●	◐
U301_8_1	+5V	-	●	-	-	●	◐
U301_9	PMUX1_ST	●	●	-	-	●	◐
U301_10	Net-(U301-ILIM)	-	-	-	-	●	◐
U301_11	Net-(U301-SS)	-	-	-	-	●	◐
U301_12	GND	-	●	-	-	●	◐
R302_1	Net-(U302-EN)	-	-	●	◐	-	-
R302_2	GND	-	●	●	◐	-	-
R309_1	OV1	-	-	●	◐	-	-
R309_2	GND	-	●	●	◐	-	-
R310_1	5V_POL	-	●	●	◐	-	-
R310_2	OV2	-	-	●	◐	-	-
C301_1	GND	-	●	●	◐	-	-
C301_2	Net-(U301-SS)	-	-	●	◐	-	-
R304_1	+5V_USB	-	●	●	◐	-	-
R304_2	PR1	-	-	●	◐	-	-
R312_1	+VBAT_BUS	-	●	●	◐	-	-
R312_2	VIN1	-	-	●	◐	-	-
R109_1	SPI_2_PICO	●	●	●	◐	-	-
R109_2	SPI_PICO	●	●	●	◐	-	-
R111_1	SPI_2_SCL	●	●	●	◐	-	-
R111_2	SPI_SCK	●	●	●	◐	-	-
U101_1	RESET	-	●	●	◐	-	-
U101_2	GND	-	●	●	◐	-	-
U101_3	GPIO2_BUS	-	●	●	◐	-	-
U101_4	UART_1_RTS	-	●	●	◐	-	-
U101_6	UART_1_CTS	-	●	●	◐	-	-
R112_1	SPI_2_CS	●	●	●	◐	-	-
R112_2	SPI_CS0	●	●	●	◐	-	-
C112_1	+VBAT_BUS	-	●	●	◐	-	-
C112_2	GND	-	●	●	◐	-	-
R117_1	GPIO2_BUS	●	●	●	◐	-	-
R117_2	GPIO	●	●	●	◐	-	-
C108_1	+VBAT_BUS	-	●	●	◐	-	-
C108_2	GND	-	●	●	◐	-	-
J101_1	+VBAT_BUS	-	●	●	◐	-	-
J101_2	+VBAT_BUS	-	●	●	◐	-	-
J101_3	+VBAT_BUS	-	●	●	◐	-	-
J101_4	+VBAT_BUS	-	●	●	◐	-	-
J101_5	I2C_SCL	-	●	●	◐	-	-
J101_6	GND	-	●	●	◐	-	-
J101_7	I2C_SDA	-	●	●	◐	-	-
J101_8	GND	-	●	●	◐	-	-
J101_9	SPI_PICO	-	●	●	◐	-	-
J101_10	GND	-	●	●	◐	-	-
J101_11	SPI_POCI	-	●	●	◐	-	-
J101_12	GND	-	●	●	◐	-	-
J101_13	SPI_SCK	-	●	●	◐	-	-
J101_14	GND	-	●	●	◐	-	-
J101_15	SPI_CS0	-	●	●	◐	-	-
J101_16	GND	-	●	●	◐	-	-
J101_17	UART_TX	-	●	●	◐	-	-
J101_18	GND	-	●	●	◐	-	-
J101_19	UART_RX	-	●	●	◐	-	-
J101_20	GND	-	●	●	◐	-	-
J101_21	UART_CTS	-	●	●	◐	-	-
J101_22	GND	-	●	●	◐	-	-
J101_23	UART_RTS	-	●	●	◐	-	-
J101_24	GND	-	●	●	◐	-	-
J101_25	3V3	-	●	●	◐	-	-
J101_26	3V3	-	●	●	◐	-	-
J101_27	3V3	-	●	●	◐	-	-
J101_28	3V3	-	●	●	◐	-	-
J101_29	GPIO	-	●	●	◐	-	-
J101_30	GND	-	●	●	◐	-	-
J101_31	RESET	-	●	●	◐	-	-
J101_32	GND	-	●	●	◐	-	-
J101_37	+5V_BUS	-	●	●	◐	-	-
J101_38	+5V_BUS	-	●	●	◐	-	-
J101_39	+5V_BUS	-	●	●	◐	-	-
J101_40	+5V_BUS	-	●	●	◐	-	-
R113_1	UART_1_RX	●	●	●	◐	-	-
R113_2	UART_TX	●	●	●	◐	-	-
R110_1	SPI_2_POCI	●	●	●	◐	-	-
R110_2	SPI_POCI	●	●	●	◐	-	-
U103_1	SPI_2_POCI	-	●	●	◐	-	-
U103_2	GND	-	●	●	◐	-	-
U103_3	SPI_2_PICO	-	●	●	◐	-	-
U103_4	I2C_3_SCL	-	●	●	◐	-	-
U103_6	I2C_3_SDA	-	●	●	◐	-	-
R116_1	UART_1_CTS	●	●	●	◐	-	-
R116_2	UART_RTS	●	●	●	◐	-	-
R108_1	I2C_3_SDA	●	●	●	◐	-	-
R108_2	I2C_SDA	●	●	●	◐	-	-
C105_1	+VBAT_BUS	-	●	●	◐	-	-
C105_2	GND	-	●	●	◐	-	-
R118_1	RESET	●	●	●	◐	-	-
R118_2	RESET	●	●	●	◐	-	-
U102_1	UART_1_TX	-	●	●	◐	-	-
U102_2	GND	-	●	●	◐	-	-
U102_3	UART_1_RX	-	●	●	◐	-	-
U102_4	SPI_2_SCL	-	●	●	◐	-	-
U102_6	SPI_2_CS	-	●	●	◐	-	-
C111_1	+VBAT_BUS	-	●	●	◐	-	-
C111_2	GND	-	●	●	◐	-	-
R114_1	UART_1_TX	●	●	●	◐	-	-
R114_2	UART_RX	●	●	●	◐	-	-
R115_1	UART_1_RTS	●	●	●	◐	-	-
R115_2	UART_CTS	●	●	●	◐	-	-
R107_1	I2C_3_SCL	●	●	●	◐	-	-
R107_2	I2C_SCL	●	●	●	◐	-	-
J701_1	GND	-	●	●	◐	-	-
J701_2	DPHY1_PI.D0_N	-	●	●	◐	-	-
J701_3	DPHY1_PI.D0_P	-	●	●	◐	-	-
J701_4	GND	-	●	●	◐	-	-
J701_5	DPHY1_PI.D1_N	-	●	●	◐	-	-
J701_6	DPHY1_PI.D1_P	-	●	●	◐	-	-
J701_7	GND	-	●	●	◐	-	-
J701_8	DPHY1_PI.C_N	-	●	●	◐	-	-
J701_9	DPHY1_PI.C_P	-	●	●	◐	-	-
J701_10	GND	-	●	●	◐	-	-
J701_11	DPHY1_PI.D2_N	-	●	●	◐	-	-
J701_12	DPHY1_PI.D2_P	-	●	●	◐	-	-
J701_13	GND	-	●	●	◐	-	-
J701_14	DPHY1_PI.D3_N	-	●	●	◐	-	-
J701_15	DPHY1_PI.D3_P	-	●	●	◐	-	-
J701_16	GND	-	●	●	◐	-	-
J701_17	CAM1_GPIO1	-	●	●	◐	-	-
J701_18	CAM1_GPIO2	-	●	●	◐	-	-
J701_19	GND	-	●	●	◐	-	-
J701_20	I2C_1_SCL	-	●	●	◐	-	-
J701_21	I2C_1_SDA	-	●	●	◐	-	-
J701_22	+3V3	-	●	●	◐	-	-
C701_1	+3V3	-	●	●	◐	-	-
C701_2	GND	-	●	●	◐	-	-
C702_1	+3V3	-	●	●	◐	-	-
C702_2	GND	-	●	●	◐	-	-
J702_1	GND	-	●	●	◐	-	-
J702_2	DPHY2_PI.D0_N	-	●	●	◐	-	-
J702_3	DPHY2_PI.D0_P	-	●	●	◐	-	-
J702_4	GND	-	●	●	◐	-	-
J702_5	DPHY2_PI.D1_N	-	●	●	◐	-	-
J702_6	DPHY2_PI.D1_P	-	●	●	◐	-	-
J702_7	GND	-	●	●	◐	-	-
J702_8	DPHY2_PI.C_N	-	●	●	◐	-	-
J702_9	DPHY2_PI.C_P	-	●	●	◐	-	-
J702_10	GND	-	●	●	◐	-	-
J702_11	DPHY2_PI.D2_N	-	●	●	◐	-	-
J702_12	DPHY2_PI.D2_P	-	●	●	◐	-	-
J702_13	GND	-	●	●	◐	-	-
J702_14	DPHY2_PI.D3_N	-	●	●	◐	-	-
J702_15	DPHY2_PI.D3_P	-	●	●	◐	-	-
J702_16	GND	-	●	●	◐	-	-
J702_17	GPIO7	-	●	●	◐	-	-
J702_18	GPIO8	-	●	●	◐	-	-
J702_19	GND	-	●	●	◐	-	-
J702_20	I2C_2_SCL	-	●	●	◐	-	-
J702_21	I2C_2_SDA	-	●	●	◐	-	-
J702_22	+3V3	-	●	●	◐	-	-
C801_1	+3V3	-	●	●	◐	-	-
C801_2	GND	-	●	●	◐	-	-
U801_1	+3V3	-	●	-	-	●	◐
U801_2	I2C_3_SCL	-	●	-	-	●	◐
U801_3	I2C_3_SDA	-	●	-	-	●	◐
U801_4	GND	-	●	-	-	●	◐
U801_5	+3V3	-	●	-	-	●	◐
U801_6	GYRO_INT	-	-	-	-	●	◐
U801_8	GND	-	●	-	-	●	◐
U801_9	GND	-	●	-	-	●	◐
U801_10	GND	-	●	-	-	●	◐
U801_11	GND	-	●	-	-	●	◐
U801_12	GND	-	●	-	-	●	◐
U801_13	GND	-	●	-	-	●	◐
U801_14	Net-(U801-REGOUT)	-	-	-	-	●	◐
U801_15	GND	-	●	-	-	●	◐
U801_16	+3V3	-	●	-	-	●	◐
R803_1	+3V3	●	●	●	◐	-	-
R803_2	FRAM_HOLD	●	●	●	◐	-	-
R801_1	Net-(U802-SO)	●	●	●	◐	-	-
R801_2	SPI_1_POCI	●	◐	●	◐	-	-
C806_1	+3V3	-	●	●	◐	-	-
C806_2	GND	-	●	●	◐	-	-
C805_1	+3V3	-	●	●	◐	-	-
C805_2	GND	-	●	●	◐	-	-
U802_2	Net-(U802-SO)	-	●	●	◐	-	-
U802_4	GND	-	●	●	◐	-	-
U802_5	SPI_1_PICO	-	●	●	◐	-	-
U802_6	SPI_1_SCL	-	●	●	◐	-	-
U802_8	+3V3	-	●	●	◐	-	-
U802_1	SPI_1_CS	-	●	●	◐	-	-
U802_3	+3V3	-	●	●	◐	-	-
U802_7	FRAM_HOLD	-	●	●	◐	-	-
C804_1	+3V3	-	●	●	◐	-	-
C804_2	GND	-	●	●	◐	-	-
R802_1	+3V3	●	●	●	◐	-	-
R802_2	SPI_1_CS	●	●	●	◐	-	-
C802_1	+3V3	-	●	●	◐	-	-
C802_2	GND	-	●	●	◐	-	-
C803_1	Net-(U801-REGOUT)	-	-	●	◐	-	-
C803_2	GND	-	●	●	◐	-	-

14.15 Room on the Schematic for Per-Pin Test Marks

Per-pin testability marks were asked for on this run. Each pin carries 1 mark, for the one test, which needs 70 mil (1.8 mm) along the pin from the part body. Where possible, leave that much before the nearest junction, power symbol, other part's pin or net label; on a shorter pin, the rest has to be clear straight wire past its tip. The pins below do not have it: their mark is drawn on the pin only, and the full reading is written as a note on the sheet.

Pin ⇅	Marks run into ⇅	Clear wire needed past the pin tip ⇅
R102_1	another part's pin	40 mil (1.0 mm)
R105_1	another part's pin	40 mil (1.0 mm)
R101_1	another part's pin	40 mil (1.0 mm)
R103_1	another part's pin	40 mil (1.0 mm)
R104_1	another part's pin	40 mil (1.0 mm)
R404_1	a junction dot	40 mil (1.0 mm)
R403_1	a net label	40 mil (1.0 mm)
R401_2	a net label	40 mil (1.0 mm)
R118_1	a junction dot	40 mil (1.0 mm)
R803_1	a power symbol	40 mil (1.0 mm)
R801_2	a net label	40 mil (1.0 mm)
R802_1	a net label	40 mil (1.0 mm)
R802_2	a junction dot	40 mil (1.0 mm)
R301_1	a net label	40 mil (1.0 mm)
R301_2	a junction dot	40 mil (1.0 mm)
R307_1	a net label	40 mil (1.0 mm)
R325_1	a net label	40 mil (1.0 mm)
R325_2	another net's wire crossing it	40 mil (1.0 mm)
R311_1	a net label	40 mil (1.0 mm)
R311_2	a junction dot	40 mil (1.0 mm)
R303_2	a junction dot	40 mil (1.0 mm)
R305_1	a net label	40 mil (1.0 mm)
R302_1	a junction dot	40 mil (1.0 mm)
R302_2	a power symbol	40 mil (1.0 mm)
R309_1	a net label	40 mil (1.0 mm)
R309_2	a junction dot	40 mil (1.0 mm)

14.16 PCOLA/SOQ Testability

PCOLA/SOQ scores how well the configured test methods cover each component and each connection. PCOLA evaluates five device-level properties: Presence, Correctness, Orientation, Live (functional), and Alignment. SOQ evaluates three connection-level properties: Shorts detection, Opens detection, and solder joint Quality. Scores are on a 0–100,000 scale where 100,000 means every property is fully covered. The two scores are reported separately. Weights follow Agilent's published method: Alignment counts 10% of a device and its other relevant properties share the rest; on a pin, Shorts count 40%, Opens 50% and Quality 10%.

14.16.1 Coverage by Test Method

P=Presence C=Correctness O=Orientation L=Live A=Alignment | S=Shorts O(pins)=Opens Q=Quality

Test Method	P	C	O	L	A	S	Opens	Solder Quality
PCOLA/SOQ coverage scores by test method. Scores: 0 (None), 0.5 (Partial), 1.0 (Full).
Electrical Test	59.7%	9.7%	0.0%	24.1%	0.0%	90.9%	14.7%	0.0%
Optical Inspection (AOI)	97.7%	22.7%	81.0%	0.0%	88.6%	56.9%	56.9%	28.4%
X-Ray Inspection (AXI)	0.0%	0.0%	0.0%	0.0%	9.1%	28.4%	28.4%	13.4%
Combined	98.9%	32.4%	81.0%	24.1%	97.7%	97.4%	86.4%	41.8%

14.16.2 PCB Device/Pin Count

Devices (PCOLA): 88
Pins (SOQ): 464

14.16.3 Board-Level Scores

Board-Level Coverage (0 – 100,000 scale)
Dimension	Score	Coverage
PCOLA	59290 / 100,000	59.3%
SOQ	86358 / 100,000	86.4%

Electrical vs Inspection
Source	PCOLA Score	SOQ Score
Electrical Test	26293 / 100,000	43707 / 100,000
Optical/X-ray Inspection	49702 / 100,000	79440 / 100,000
Combined (max)	59290 / 100,000	86358 / 100,000

14.16.4 PCOLA (88 devices)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0) — = N/A (excluded)
* Footprint not IPC-7351B/7251 compliant — no inspection coverage scored

Score ⇅	RefDes ⇅	Type / Footprint ⇅	Class ⇅	P ⇅	C ⇅	O ⇅	L ⇅	A ⇅	Method ⇅
100%	J601	Molex 533984004 / Molex-0533984004-PicoBlade-53398	Connector	●	●	●	—	●	AOI, Powered_Off
100%	J701	Hirose FH12A-22S-0.5SH / Hirose-FH12A-22S-0.5SH-FPC-CSI-DSI	Connector	●	●	●	—	●	AOI, Powered_Off
100%	J101	Samtec SFM-120-01-X-D / Samtec-SFM-120-01-X-D	Connector	●	●	●	—	●	AOI, Powered_Off
100%	J202	Molex 533984004 / Molex-0533984004-PicoBlade-53398	Connector	●	●	●	—	●	AOI, Powered_Off
100%	J702	Hirose FH12A-22S-0.5SH / Hirose-FH12A-22S-0.5SH-FPC-CSI-DSI	Connector	●	●	●	—	●	AOI, Powered_Off
100%	Module402	CM5 HSS / Amphenol-10164227-1001A1RLF-CM5-HSS	Connector	●	●	●	—	●	AOI, AXI, Powered_Off
100%	J201	USB-C / JAE-DX07S016JA1R1500	Connector	●	●	●	—	●	AOI, AXI, Powered_Off
89%	U801	TDK IAM-20380 / TDK-IAM-20380_IVS	IC	●	●	●	◐	●	AOI, AXI, LSSI, Powered_Off
89%	U302	TDK FS1603A-5000-AL / TDK-FS1606 [17L Open Top LGA SiP (A01)]	IC	●	●	●	◐	●	AOI, AXI, LSSI, Powered_Off
89%	U103	TI TPD4E1B06DRLR / TI-TPD4E1B06DRL [SOT-5X3 (DRL)]	IC	●	●	●	◐	●	AOI, LSSI, Powered_Off
89%	U802	Infineon CY15B102Q-SXET / Infineon-CY15B102Q-SXET	IC	●	●	●	◐	●	AOI, LSSI, Powered_Off
85%	C102	0.1u / C-0603-0.1u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C806	0.1u / C-0603-0.1u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C805	10u / C-0805-10u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C804	10n / C-0603	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C304	2u2 / C-0603	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C802	0.1u / C-0603-0.1u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C101	0.1u / C-0603-0.1u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C113	10u / C-0805-10u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C114	0.1u / C-0603-0.1u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C115	10u / C-0805-10u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C112	0.1u / C-0603-0.1u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C111	10u / C-0805-10u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C108	47u / C-2917 [D/7343-31]	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C105	47u / C-2917 [D/7343-31]	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C701	10u / C-0805-10u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C702	10u / C-0805-10u	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
85%	C801	2u2 / C-0603	Capacitor	●	◐	—	●	●	AOI, Passive_Meas, Powered_Off
78%	U201	TI TPD4E1B06DRLR / TI-TPD4E1B06DRL [SOT-5X3 (DRL)]	IC	●	●	●	○	●	AOI, Powered_Off
78%	U102	TI TPD4E1B06DRLR / TI-TPD4E1B06DRL [SOT-5X3 (DRL)]	IC	●	●	●	○	●	AOI, Powered_Off
78%	D401	BAS116 / SOT-23-3	Diode	●	●	●	○	●	AOI, Powered_Off
78%	D201	TI ESD751 / D_0603_1608Metric [SOT-5X3 (DYA)]	Diode	●	●	●	○	●	AOI, Powered_Off
78%	U301	TI TPS2121RUX / TI-TPS2121	IC	●	●	●	○	●	AOI, AXI, Powered_Off
78%	U202	TI TPD4E1B06DRLR / TI-TPD4E1B06DRL [SOT-5X3 (DRL)]	IC	●	●	●	○	●	AOI, Powered_Off
78%	U101	TI TPD4E1B06DRLR / TI-TPD4E1B06DRL [SOT-5X3 (DRL)]	IC	●	●	●	○	●	AOI, Powered_Off
78%	U601	TI TPD4E1B06DRLR / TI-TPD4E1B06DRL [SOT-5X3 (DRL)]	IC	●	●	●	○	●	AOI, Powered_Off
78%	U401	74AHCT1G04 / SOT-23-5	IC	●	●	●	○	●	AOI, Powered_Off
44%	SW102	CK KMS223GP LFG / CK-KMS223GP-LFG [KMS Series]	Switch	●	○	◐	○	●	AOI, Powered_Off
44%	D105	WE 150060VS55040 LED G / WE-150060VS55040-LED-G [WL-SMCD SMT Mono-color Chip LED Diffused (0603)]	Diode	●	○	◐	○	●	AOI, Powered_Off
44%	D102	SunLED XZFRS53FVF-1 LED P / SunLED-XZFRS53FVF-1 [1.6 x 0.8 mm SMD Chip LED Lamp]	Diode	●	○	◐	○	●	AOI, AXI, Powered_Off
44%	D101	SunLED XZFRS53FVF-1 LED P / SunLED-XZFRS53FVF-1 [1.6 x 0.8 mm SMD Chip LED Lamp]	Diode	●	○	◐	○	●	AOI, AXI, Powered_Off
44%	D104	WE 150060WS75000 LED W / WE-150060WS75000-LED-W [0603]	Diode	●	○	◐	○	●	AOI, Powered_Off
44%	SW101	CK KMS223GP LFG / CK-KMS223GP-LFG [KMS Series]	Switch	●	○	◐	○	●	AOI, Powered_Off
44%	D103	SunLED XZFRS53FVF-1 LED P / SunLED-XZFRS53FVF-1 [1.6 x 0.8 mm SMD Chip LED Lamp]	Diode	●	○	◐	○	●	AOI, AXI, Powered_Off
40%	R301	43k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R305	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R302	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R309	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R310	47k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	C301	1u / C-0603-1u	Capacitor	●	○	—	○	●	AOI, Powered_Off
40%	R304	22k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R312	2R7 / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R109	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R111	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R303	47k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R112	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R117	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R102	3k3 / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R105	1k / R-0603-1k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R113	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R110	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R101	1k / R-0603-1k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R116	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R103	3k3 / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R104	39k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R118	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R402	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R404	180k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R114	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R115	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R107	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R403	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R401	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R306	33k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R108	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	C303	1u / C-0603-1u	Capacitor	●	○	—	○	●	AOI, Powered_Off
40%	R307	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R803	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R801	22R / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	C306	22u / C_1210_3225Metric	Capacitor	●	○	—	○	●	AOI, Powered_Off
40%	R325	47k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R311	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R308	47k / R-0603	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	R802	10k / R-0603-10k	Resistor	●	○	—	○	●	AOI, Powered_Off
40%	C305	22u / C_1210_3225Metric	Capacitor	●	○	—	○	●	AOI, Powered_Off
40%	C803	1u / C-0603-1u	Capacitor	●	○	—	○	●	AOI, Powered_Off
23%	Module401	CM5 GPIO / Amphenol-10164227-1001A1RLF-CM5-GPIO *	IC	◐	○	○	◐	○	LSSI, Powered_Off
11%	BT401	Keystone 2998 / Keystone-2998 *	Other	◐	○	○	○	○	Powered_Off

14.16.5 SOQ (464 solder joints)

● = Full (1.0) ◐ = Partial (0.5) ○ = None (0)

Score ⇅	Pin ⇅	Net ⇅	S ⇅	O ⇅	Q ⇅
95%	R102_1	Net-(D102-A)	●	●	◐
95%	R102_2	+5V	●	●	◐
95%	SW102_1	RESET	●	●	◐
95%	SW102_3	GND	●	●	◐
95%	SW102_4	GND	●	●	◐
95%	SW102_2	GND	●	●	◐
95%	SW102_5	RESET	●	●	◐
95%	R105_1	Net-(D105-A)	●	●	◐
95%	R105_2	+3V3	●	●	◐
95%	D105_1	Net-(D105-K)	●	●	◐
95%	D105_2	Net-(D105-A)	●	●	◐
95%	R101_1	Net-(D101-A)	●	●	◐
95%	R101_2	+3V3	●	●	◐
95%	SW101_1	PWR_BUT	●	●	◐
95%	SW101_3	GND	●	●	◐
95%	SW101_4	GND	●	●	◐
95%	SW101_2	GND	●	●	◐
95%	SW101_5	PWR_BUT	●	●	◐
95%	D102_1	Net-(D102-K)	●	●	◐
95%	D102_2	Net-(D102-A)	●	●	◐
95%	C101_1	+5V	●	●	◐
95%	C101_2	GND	●	●	◐
95%	R103_1	Net-(D103-A)	●	●	◐
95%	R103_2	+5V	●	●	◐
95%	C113_1	+3V3	●	●	◐
95%	C113_2	GND	●	●	◐
95%	C102_1	+5V	●	●	◐
95%	C102_2	GND	●	●	◐
95%	R104_1	Net-(D104-A)	●	●	◐
95%	R104_2	+5V	●	●	◐
95%	D104_1	Net-(D104-K)	●	●	◐
95%	D104_2	Net-(D104-A)	●	●	◐
95%	C114_1	+3V3	●	●	◐
95%	C114_2	GND	●	●	◐
95%	D101_1	Net-(D101-K)	●	●	◐
95%	D101_2	Net-(D101-A)	●	●	◐
95%	C115_1	+3V3	●	●	◐
95%	C115_2	GND	●	●	◐
95%	D103_1	Net-(D103-K)	●	●	◐
95%	D103_2	Net-(D103-A)	●	●	◐
95%	Module402_101	USBOTG_ID	●	●	◐
95%	Module402_103	USB1_PI.D_N	●	●	◐
95%	Module402_105	USB1_PI.D_P	●	●	◐
95%	Module402_107	GND	●	●	◐
95%	Module402_108	GND	●	●	◐
95%	Module402_113	GND	●	●	◐
95%	Module402_114	GND	●	●	◐
95%	Module402_115	DPHY1_PI.D0_N	●	●	◐
95%	Module402_117	DPHY1_PI.D0_P	●	●	◐
95%	Module402_119	GND	●	●	◐
95%	Module402_120	GND	●	●	◐
95%	Module402_121	DPHY1_PI.D1_N	●	●	◐
95%	Module402_123	DPHY1_PI.D1_P	●	●	◐
95%	Module402_125	GND	●	●	◐
95%	Module402_126	GND	●	●	◐
95%	Module402_127	DPHY1_PI.C_N	●	●	◐
95%	Module402_129	DPHY1_PI.C_P	●	●	◐
95%	Module402_131	GND	●	●	◐
95%	Module402_132	GND	●	●	◐
95%	Module402_133	DPHY1_PI.D2_N	●	●	◐
95%	Module402_134	USB2_PI.D_P	●	●	◐
95%	Module402_135	DPHY1_PI.D2_P	●	●	◐
95%	Module402_136	USB2_PI.D_N	●	●	◐
95%	Module402_137	GND	●	●	◐
95%	Module402_138	GND	●	●	◐
95%	Module402_139	DPHY1_PI.D3_N	●	●	◐
95%	Module402_141	DPHY1_PI.D3_P	●	●	◐
95%	Module402_144	GND	●	●	◐
95%	Module402_150	GND	●	●	◐
95%	Module402_155	GND	●	●	◐
95%	Module402_156	GND	●	●	◐
95%	Module402_161	GND	●	●	◐
95%	Module402_162	GND	●	●	◐
95%	Module402_167	GND	●	●	◐
95%	Module402_168	GND	●	●	◐
95%	Module402_173	GND	●	●	◐
95%	Module402_174	GND	●	●	◐
95%	Module402_175	DPHY2_PI.D0_N	●	●	◐
95%	Module402_177	DPHY2_PI.D0_P	●	●	◐
95%	Module402_179	GND	●	●	◐
95%	Module402_180	GND	●	●	◐
95%	Module402_181	DPHY2_PI.D1_N	●	●	◐
95%	Module402_183	DPHY2_PI.D1_P	●	●	◐
95%	Module402_185	GND	●	●	◐
95%	Module402_186	GND	●	●	◐
95%	Module402_187	DPHY2_PI.C_N	●	●	◐
95%	Module402_189	DPHY2_PI.C_P	●	●	◐
95%	Module402_191	GND	●	●	◐
95%	Module402_192	GND	●	●	◐
95%	Module402_193	DPHY2_PI.D2_N	●	●	◐
95%	Module402_194	DPHY2_PI.D3_N	●	●	◐
95%	Module402_195	DPHY2_PI.D2_P	●	●	◐
95%	Module402_196	DPHY2_PI.D3_P	●	●	◐
95%	Module402_197	GND	●	●	◐
95%	Module402_198	GND	●	●	◐
95%	R402_1	SPI_1_SCL	●	●	◐
95%	R402_2	SCLK_GPIO21_PT	●	●	◐
95%	R404_1	RESET	●	●	◐
95%	R404_2	GND	●	●	◐
95%	J701_14	DPHY1_PI.D3_N	●	●	◐
95%	J701_15	DPHY1_PI.D3_P	●	●	◐
95%	J701_16	GND	●	●	◐
95%	J701_17	CAM1_GPIO1	●	●	◐
95%	J701_18	CAM1_GPIO2	●	●	◐
95%	J701_19	GND	●	●	◐
95%	J701_20	I2C_1_SCL	●	●	◐
95%	J701_21	I2C_1_SDA	●	●	◐
95%	J701_22	+3V3	●	●	◐
95%	C701_1	+3V3	●	●	◐
95%	C701_2	GND	●	●	◐
95%	C702_1	+3V3	●	●	◐
95%	C702_2	GND	●	●	◐
95%	J702_1	GND	●	●	◐
95%	J702_2	DPHY2_PI.D0_N	●	●	◐
95%	J702_3	DPHY2_PI.D0_P	●	●	◐
95%	J702_4	GND	●	●	◐
95%	J702_5	DPHY2_PI.D1_N	●	●	◐
95%	J702_6	DPHY2_PI.D1_P	●	●	◐
95%	J702_7	GND	●	●	◐
95%	J702_8	DPHY2_PI.C_N	●	●	◐
95%	J702_9	DPHY2_PI.C_P	●	●	◐
95%	J702_10	GND	●	●	◐
95%	J702_11	DPHY2_PI.D2_N	●	●	◐
95%	J702_12	DPHY2_PI.D2_P	●	●	◐
95%	J702_13	GND	●	●	◐
95%	J702_14	DPHY2_PI.D3_N	●	●	◐
95%	J702_15	DPHY2_PI.D3_P	●	●	◐
95%	J702_16	GND	●	●	◐
95%	J702_17	GPIO7	●	●	◐
95%	J702_18	GPIO8	●	●	◐
95%	J702_19	GND	●	●	◐
95%	J702_20	I2C_2_SCL	●	●	◐
95%	J702_21	I2C_2_SDA	●	●	◐
95%	J702_22	+3V3	●	●	◐
95%	C801_1	+3V3	●	●	◐
95%	C801_2	GND	●	●	◐
95%	U801_1	+3V3	●	●	◐
95%	U801_2	I2C_3_SCL	●	●	◐
95%	U801_3	I2C_3_SDA	●	●	◐
95%	U801_4	GND	●	●	◐
95%	U801_5	+3V3	●	●	◐
95%	U801_6	GYRO_INT	●	●	◐
95%	U801_8	GND	●	●	◐
95%	U801_9	GND	●	●	◐
95%	U801_10	GND	●	●	◐
95%	U801_11	GND	●	●	◐
95%	U801_12	GND	●	●	◐
95%	U801_13	GND	●	●	◐
95%	U801_14	Net-(U801-REGOUT)	●	●	◐
95%	U801_15	GND	●	●	◐
95%	U801_16	+3V3	●	●	◐
95%	R803_1	+3V3	●	●	◐
95%	R803_2	FRAM_HOLD	●	●	◐
95%	R801_1	Net-(U802-SO)	●	●	◐
95%	R801_2	SPI_1_POCI	●	●	◐
95%	C806_1	+3V3	●	●	◐
95%	C806_2	GND	●	●	◐
95%	C805_1	+3V3	●	●	◐
95%	C805_2	GND	●	●	◐
95%	U802_2	Net-(U802-SO)	●	●	◐
95%	U802_4	GND	●	●	◐
95%	U802_5	SPI_1_PICO	●	●	◐
95%	U802_6	SPI_1_SCL	●	●	◐
95%	U802_8	+3V3	●	●	◐
95%	U802_1	SPI_1_CS	●	●	◐
95%	U802_3	+3V3	●	●	◐
95%	U802_7	FRAM_HOLD	●	●	◐
95%	C804_1	+3V3	●	●	◐
95%	C804_2	GND	●	●	◐
95%	R802_1	+3V3	●	●	◐
95%	R802_2	SPI_1_CS	●	●	◐
95%	C802_1	+3V3	●	●	◐
95%	C802_2	GND	●	●	◐
95%	R403_1	SPI_1_CS	●	●	◐
95%	R403_2	CS_GPIO24_PT	●	●	◐
95%	R401_1	SPI_1_PICO	●	●	◐
95%	R401_2	PICO_GPIO20_PT	●	●	◐
95%	C803_1	Net-(U801-REGOUT)	●	●	◐
95%	C803_2	GND	●	●	◐
95%	U401_2	LED_PI_PWR	●	●	◐
95%	U401_3	GND	●	●	◐
95%	U401_4	LED_PI_PWR	●	●	◐
95%	U401_5	+5V	●	●	◐
95%	D401_3	VBAT_RTC	●	●	◐
95%	D201_1	GND	●	●	◐
95%	D201_2	+5V_USB	●	●	◐
95%	U202_1	USB2_PI.D_N	●	●	◐
95%	U202_2	GND	●	●	◐
95%	U202_3	USB2_PI.D_P	●	●	◐
95%	U202_4	+5V	●	●	◐
95%	U201_1	USB1_PI.D_N	●	●	◐
95%	U201_2	GND	●	●	◐
95%	U201_3	USB1_PI.D_P	●	●	◐
95%	U201_4	USB_CC2	●	●	◐
95%	U201_6	USB_CC1	●	●	◐
95%	J202_1	+5V	●	●	◐
95%	J202_2	USB2_PI.D_P	●	●	◐
95%	J202_3	USB2_PI.D_N	●	●	◐
95%	J202_4	GND	●	●	◐
95%	J201_A1	GND	●	●	◐
95%	J201_A4	+5V_USB	●	●	◐
95%	J201_A5	USB_CC1	●	●	◐
95%	J201_A6	USB1_PI.D_P	●	●	◐
95%	J201_A7	USB1_PI.D_N	●	●	◐
95%	J201_A9	+5V_USB	●	●	◐
95%	J201_A12	GND	●	●	◐
95%	J201_B1	GND	●	●	◐
95%	J201_B4	+5V_USB	●	●	◐
95%	J201_B5	USB_CC2	●	●	◐
95%	J201_B6	USB1_PI.D_P	●	●	◐
95%	J201_B7	USB1_PI.D_N	●	●	◐
95%	J201_B9	+5V_USB	●	●	◐
95%	J201_B12	GND	●	●	◐
95%	J201_S1	GND	●	●	◐
95%	J601_1	ETH_PI.TRD1_N	●	●	◐
95%	J601_2	ETH_PI.TRD1_P	●	●	◐
95%	J601_3	ETH_PI.TRD0_N	●	●	◐
95%	J601_4	ETH_PI.TRD0_P	●	●	◐
95%	U601_1	ETH_PI.TRD0_P	●	●	◐
95%	U601_2	GND	●	●	◐
95%	U601_3	ETH_PI.TRD0_N	●	●	◐
95%	U601_4	ETH_PI.TRD1_P	●	●	◐
95%	U601_6	ETH_PI.TRD1_N	●	●	◐
95%	R301_1	+VBAT_BUS	●	●	◐
95%	R301_2	Net-(U302-EN)	●	●	◐
95%	U302_1	I2C_3_SDA	●	●	◐
95%	U302_2	Net-(U302-PG)	●	●	◐
95%	U302_3	Net-(U302-EN)	●	●	◐
95%	U302_4	I2C_3_SCL	●	●	◐
95%	U302_5	5V_POL	●	●	◐
95%	U302_6	GND	●	●	◐
95%	U302_7	5V_POL	●	●	◐
95%	U302_8	GND	●	●	◐
95%	U302_9	GND	●	●	◐
95%	U302_10	VCC1	●	●	◐
95%	U302_11	VIN1	●	●	◐
95%	U302_12	+VBAT_BUS	●	●	◐
95%	U302_13	+VBAT_BUS	●	●	◐
95%	U302_14	+VBAT_BUS	●	●	◐
95%	U302_15	Net-(U302-VSW)	●	●	◐
95%	U302_16	GND	●	●	◐
95%	U302_17	+VBAT_BUS	●	●	◐
95%	R306_1	5V_POL	●	●	◐
95%	R306_2	CP2	●	●	◐
95%	C303_1	VIN1	●	●	◐
95%	C303_2	GND	●	●	◐
95%	R307_1	CP2	●	●	◐
95%	R307_2	GND	●	●	◐
95%	C306_1	5V_POL	●	●	◐
95%	C306_2	GND	●	●	◐
95%	R325_1	VCC1	●	●	◐
95%	R325_2	Net-(U302-PG)	●	●	◐
95%	R311_1	OV2	●	●	◐
95%	R311_2	GND	●	●	◐
95%	C304_1	+VBAT_BUS	●	●	◐
95%	C304_2	GND	●	●	◐
95%	R308_1	+5V_USB	●	●	◐
95%	R308_2	OV1	●	●	◐
95%	C305_1	5V_POL	●	●	◐
95%	C305_2	GND	●	●	◐
95%	R303_1	Net-(U301-ILIM)	●	●	◐
95%	R303_2	GND	●	●	◐
95%	R305_1	PR1	●	●	◐
95%	R305_2	GND	●	●	◐
95%	U301_1	+5V	●	●	◐
95%	U301_1_1	+5V	●	●	◐
95%	U301_2	5V_POL	●	●	◐
95%	U301_2_1	5V_POL	●	●	◐
95%	U301_3	CP2	●	●	◐
95%	U301_4	OV2	●	●	◐
95%	U301_5	OV1	●	●	◐
95%	U301_6	PR1	●	●	◐
95%	U301_7	+5V_USB	●	●	◐
95%	U301_7_1	+5V_USB	●	●	◐
95%	U301_8	+5V	●	●	◐
95%	U301_8_1	+5V	●	●	◐
95%	U301_9	PMUX1_ST	●	●	◐
95%	U301_10	Net-(U301-ILIM)	●	●	◐
95%	U301_11	Net-(U301-SS)	●	●	◐
95%	U301_12	GND	●	●	◐
95%	R302_1	Net-(U302-EN)	●	●	◐
95%	R302_2	GND	●	●	◐
95%	R309_1	OV1	●	●	◐
95%	R309_2	GND	●	●	◐
95%	R310_1	5V_POL	●	●	◐
95%	R310_2	OV2	●	●	◐
95%	C301_1	GND	●	●	◐
95%	C301_2	Net-(U301-SS)	●	●	◐
95%	R304_1	+5V_USB	●	●	◐
95%	R304_2	PR1	●	●	◐
95%	R312_1	+VBAT_BUS	●	●	◐
95%	R312_2	VIN1	●	●	◐
95%	R109_1	SPI_2_PICO	●	●	◐
95%	R109_2	SPI_PICO	●	●	◐
95%	R111_1	SPI_2_SCL	●	●	◐
95%	R111_2	SPI_SCK	●	●	◐
95%	U101_1	RESET	●	●	◐
95%	U101_2	GND	●	●	◐
95%	U101_3	GPIO2_BUS	●	●	◐
95%	U101_4	UART_1_RTS	●	●	◐
95%	U101_6	UART_1_CTS	●	●	◐
95%	R112_1	SPI_2_CS	●	●	◐
95%	R112_2	SPI_CS0	●	●	◐
95%	C112_1	+VBAT_BUS	●	●	◐
95%	C112_2	GND	●	●	◐
95%	R117_1	GPIO2_BUS	●	●	◐
95%	R117_2	GPIO	●	●	◐
95%	C108_1	+VBAT_BUS	●	●	◐
95%	C108_2	GND	●	●	◐
95%	J101_1	+VBAT_BUS	●	●	◐
95%	J101_2	+VBAT_BUS	●	●	◐
95%	J101_3	+VBAT_BUS	●	●	◐
95%	J101_4	+VBAT_BUS	●	●	◐
95%	J101_5	I2C_SCL	●	●	◐
95%	J101_6	GND	●	●	◐
95%	J101_7	I2C_SDA	●	●	◐
95%	J101_8	GND	●	●	◐
95%	J101_9	SPI_PICO	●	●	◐
95%	J101_10	GND	●	●	◐
95%	J101_11	SPI_POCI	●	●	◐
95%	J101_12	GND	●	●	◐
95%	J101_13	SPI_SCK	●	●	◐
95%	J101_14	GND	●	●	◐
95%	J101_15	SPI_CS0	●	●	◐
95%	J101_16	GND	●	●	◐
95%	J101_17	UART_TX	●	●	◐
95%	J101_18	GND	●	●	◐
95%	J101_19	UART_RX	●	●	◐
95%	J101_20	GND	●	●	◐
95%	J101_21	UART_CTS	●	●	◐
95%	J101_22	GND	●	●	◐
95%	J101_23	UART_RTS	●	●	◐
95%	J101_24	GND	●	●	◐
95%	J101_25	3V3	●	●	◐
95%	J101_26	3V3	●	●	◐
95%	J101_27	3V3	●	●	◐
95%	J101_28	3V3	●	●	◐
95%	J101_29	GPIO	●	●	◐
95%	J101_30	GND	●	●	◐
95%	J101_31	RESET	●	●	◐
95%	J101_32	GND	●	●	◐
95%	J101_37	+5V_BUS	●	●	◐
95%	J101_38	+5V_BUS	●	●	◐
95%	J101_39	+5V_BUS	●	●	◐
95%	J101_40	+5V_BUS	●	●	◐
95%	R113_1	UART_1_RX	●	●	◐
95%	R113_2	UART_TX	●	●	◐
95%	R110_1	SPI_2_POCI	●	●	◐
95%	R110_2	SPI_POCI	●	●	◐
95%	U103_1	SPI_2_POCI	●	●	◐
95%	U103_2	GND	●	●	◐
95%	U103_3	SPI_2_PICO	●	●	◐
95%	U103_4	I2C_3_SCL	●	●	◐
95%	U103_6	I2C_3_SDA	●	●	◐
95%	R116_1	UART_1_CTS	●	●	◐
95%	R116_2	UART_RTS	●	●	◐
95%	R108_1	I2C_3_SDA	●	●	◐
95%	R108_2	I2C_SDA	●	●	◐
95%	C105_1	+VBAT_BUS	●	●	◐
95%	C105_2	GND	●	●	◐
95%	R118_1	RESET	●	●	◐
95%	R118_2	RESET	●	●	◐
95%	U102_1	UART_1_TX	●	●	◐
95%	U102_2	GND	●	●	◐
95%	U102_3	UART_1_RX	●	●	◐
95%	U102_4	SPI_2_SCL	●	●	◐
95%	U102_6	SPI_2_CS	●	●	◐
95%	C111_1	+VBAT_BUS	●	●	◐
95%	C111_2	GND	●	●	◐
95%	R114_1	UART_1_TX	●	●	◐
95%	R114_2	UART_RX	●	●	◐
95%	R115_1	UART_1_RTS	●	●	◐
95%	R115_2	UART_CTS	●	●	◐
95%	R107_1	I2C_3_SCL	●	●	◐
95%	R107_2	I2C_SCL	●	●	◐
95%	J701_1	GND	●	●	◐
95%	J701_2	DPHY1_PI.D0_N	●	●	◐
95%	J701_3	DPHY1_PI.D0_P	●	●	◐
95%	J701_4	GND	●	●	◐
95%	J701_5	DPHY1_PI.D1_N	●	●	◐
95%	J701_6	DPHY1_PI.D1_P	●	●	◐
95%	J701_7	GND	●	●	◐
95%	J701_8	DPHY1_PI.C_N	●	●	◐
95%	J701_9	DPHY1_PI.C_P	●	●	◐
95%	J701_10	GND	●	●	◐
95%	J701_11	DPHY1_PI.D2_N	●	●	◐
95%	J701_12	DPHY1_PI.D2_P	●	●	◐
95%	J701_13	GND	●	●	◐
90%	Module401_36	I2C_2_SDA	●	●	○
90%	Module401_37	GPIO7	●	●	○
90%	Module401_30	M.2_PGOOD	●	●	○
90%	Module401_39	GPIO8	●	●	○
90%	Module401_80	I2C_1_SCL	●	●	○
90%	Module401_35	I2C_2_SCL	●	●	○
90%	Module401_100	CAM1_GPIO2	●	●	○
90%	Module401_97	CAM1_GPIO1	●	●	○
90%	Module401_82	I2C_1_SDA	●	●	○
70%	Module401_25	SCLK_GPIO21_PT	◐	●	○
70%	Module401_26	SPI_1_POCI	◐	●	○
70%	Module401_27	PICO_GPIO20_PT	◐	●	○
70%	Module401_45	CS_GPIO24_PT	◐	●	○
40%	Module401_1	GND	●	○	○
40%	Module401_2	GND	●	○	○
40%	Module401_4	ETH_PI.TRD1_P	●	○	○
40%	Module401_6	ETH_PI.TRD1_N	●	○	○
40%	Module401_7	GND	●	○	○
40%	Module401_8	GND	●	○	○
40%	Module401_10	ETH_PI.TRD0_N	●	○	○
40%	Module401_12	ETH_PI.TRD0_P	●	○	○
40%	Module401_13	GND	●	○	○
40%	Module401_14	GND	●	○	○
40%	Module401_22	GND	●	○	○
40%	Module401_23	GND	●	○	○
40%	Module401_29	UART_1_CTS	●	○	○
40%	Module401_32	GND	●	○	○
40%	Module401_33	GND	●	○	○
40%	Module401_38	SPI_2_SCL	●	○	○
40%	Module401_40	SPI_2_POCI	●	○	○
40%	Module401_41	GPIO2_BUS	●	○	○
40%	Module401_42	GND	●	○	○
40%	Module401_43	GND	●	○	○
40%	Module401_44	SPI_2_PICO	●	○	○
40%	Module401_46	SPI_2_CS	●	○	○
40%	Module401_49	FRAM_HOLD	●	○	○
40%	Module401_50	UART_1_RTS	●	○	○
40%	Module401_51	UART_1_RX	●	○	○
40%	Module401_52	GND	●	○	○
40%	Module401_53	GND	●	○	○
40%	Module401_55	UART_1_TX	●	○	○
40%	Module401_56	I2C_3_SCL	●	○	○
40%	Module401_58	I2C_3_SDA	●	○	○
40%	Module401_59	GND	●	○	○
40%	Module401_60	GND	●	○	○
40%	Module401_65	GND	●	○	○
40%	Module401_66	GND	●	○	○
40%	Module401_71	GND	●	○	○
40%	Module401_74	GND	●	○	○
40%	Module401_76	VBAT_RTC	●	○	○
40%	Module401_77	+5V	●	○	○
40%	Module401_78	+3V3	●	○	○
40%	Module401_79	+5V	●	○	○
40%	Module401_81	+5V	●	○	○
40%	Module401_83	+5V	●	○	○
40%	Module401_84	+3V3	●	○	○
40%	Module401_85	+5V	●	○	○
40%	Module401_86	+3V3	●	○	○
40%	Module401_87	+5V	●	○	○
40%	BT401_P2	VBAT_RTC	●	○	○
40%	Module401_94	USB_CC1	●	○	○
40%	Module401_95	LED_PI_PWR	●	○	○
40%	Module401_96	USB_CC2	●	○	○
40%	Module401_98	GND	●	○	○
40%	Module401_99	RESET	●	○	○
40%	BT401_N	GND	●	○	○
0%	Module401_21	LED_PI_ACT	○	○	○
0%	Module401_47	GYRO_INT	○	○	○
0%	Module401_88	1V8_CM5	○	○	○
0%	Module401_89	WL-EN	○	○	○
0%	Module401_20	EEPROM_WP	○	○	○
0%	Module401_90	1V8_CM5	○	○	○
0%	Module401_91	BT-EN	○	○	○
0%	Module401_15	LED_ETH	○	○	○
0%	Module401_92	PWR_BUT	○	○	○
0%	Module401_93	BOOT	○	○	○

14.16.6 Scoring Matrix

PCOLA/SOQ scoring premises used for this analysis. Each cell shows the score assigned when a test method applies to a component or pin.

Method	P	C	O	L	A	S	Opens	Q
AOI	Full	Full	Full	—	Full	Full	Full	Partial
AXI	Full	—	Full	—	Full	Full	Full	Partial
JTAG/BSCAN	Full	Full	Full	Full	—	Full	Full	—
BSCAN_Passives	Full	Full	Full	Full	—	Full	Full	—
I2C	Partial	Partial	—	Partial	—	Partial	Partial	—
SPI	Partial	Partial	—	Partial	—	Partial	Partial	—
UART	—	—	—	Partial	—	—	—	—
Passive_Meas	Full	Partial	Full	Full	—	Full	Full	—
Powered_Off	Partial	—	—	—	—	Full	Full	—

15 Component Properties

Schematic library symbol quality analysis.

15.1 Library Symbol Grades

Grading schematic library symbol quality based on pin electrical type definitions:

A Passive pin counts as typed where Passive is its correct type: a clamp channel of an ESD/TVS protection array, a channel of an analog switch, or an analog pin whose net carries only resistors, capacitors or inductors (column PasOK). Column Pas counts the Passive pins that should carry a direction.

Grade Definitions
Grade	Rating	Description
A	Excellent	Has Power pins AND properly typed I/O pins (>=90% typed)
B	Good	>=70% typed OR (>=50% typed AND has Power)
C	Fair	Mix of typed and Passive pins (>=40% typed)
D	Poor	Mostly Passive with few typed pins (>=10% typed)
F	Fail	All pins Passive/Unknown (<10% typed, no ERC)

IC Library Symbol Grades (sorted worst to best)
RefDes	Grd	Pins	Pwr	In	Out	IO	OC	OE	HiZ	Pas	PasOK	Part Number	Creator
Module401	C	100	30	7	5	0	1	0	0	50	7	CM5 GPIO
U301	C	16	1	8	1	0	0	0	0	4	2	TI TPS2121RUX
U303	C	16	1	8	1	0	0	0	0	6	0	TI TPS2121RUX
U302	B	17	9	5	2	1	0	0	0	0	0	TDK FS1603A-5000-AL
U304	B	17	9	5	2	1	0	0	0	0	0	TDK FS1603A-3300-AL
U501	B	4	2	1	1	0	0	0	0	0	0	Abracon ASEK-32.768KHZ-L-R-T
U101	A	6	1	1	0	4	0	0	0	0	0	TI TPD4E1B06DRLR
U102	A	6	1	1	0	4	0	0	0	0	0	TI TPD4E1B06DRLR
U103	A	6	1	1	0	4	0	0	0	0	0	TI TPD4E1B06DRLR
U201	A	6	1	1	0	4	0	0	0	0	0	TI TPD4E1B06DRLR
U202	A	6	1	1	0	4	0	0	0	0	0	TI TPD4E1B06DRLR
U401	A	5	2	2	1	0	0	0	0	0	0	74AHCT1G04
U601	A	6	1	1	0	4	0	0	0	0	0	TI TPD4E1B06DRLR
U801	A	16	8	3	3	2	0	0	0	0	0	TDK IAM-20380
U802	A	8	2	5	1	0	0	0	0	0	0	Infineon CY15B102Q-SXET

15.1.1 Library Quality Summary

Total ICs evaluated	15
Grade A (excellent)	9 (60.0%)
Grade B (good)	3 (20.0%)
Grade C (fair)	3 (20.0%)
Grade D (poor)	0 (0.0%)
Grade F (fail)	0 (0.0%)
OVERALL LIBRARY QUALITY	A (3.76/4.00)

15.2 Component Library Validation

Checking for generic/incomplete library symbols using statistical patterns.

Library Symbol Issues (5 symbols)
Library Name	Industry Name	Part Number	RefDes	Pins	Distribution	Issues
Abracon ASEK-32.768KHZ-L-R-T	ASEK-32.768KHZ-L-R-T	-	U501	4	Pwr:2 I:1 O:1	Power-named pins not typed as Power - library pin types incomplete [OUT=Output]
CM5 GPIO	10164227-1001A1RLF	-	Module401	100	P:57 Pwr:30 I:7 O:5 OC:1	Power-named pins not typed as Power - library pin types incomplete [VBAT=Passive]
TDK FS1603A-3300-AL	FS1603A-3300-AL	-	U304	17	Pwr:9 Bi:1 I:2 O:2 ?:3	Power-named pins not typed as Power - library pin types incomplete; No Industry Name property - BOM and procurement tools require this field [VOUT=Output]
TDK FS1603A-5000-AL	FS1603A-5000-AL	-	U302	17	Pwr:9 Bi:1 I:2 O:2 ?:3	Power-named pins not typed as Power - library pin types incomplete [VOUT=Output]
TI TPS2121RUX	TPS2121RUXR	-	U301, U303	16	P:6 Pwr:1 I:8 O:1	Pin 1 (OUT) at same location as pin 1_1 (OUT__1); Pin 1 (OUT) at same location as pin 8 (OUT__2); Pin 1 (OUT) at same location as pin 8_1 (OUT__3); Pin 1_1 (OUT__1) at same location as pin 8 (OUT__2); Pin 1_1 (OUT__1) at same location as pin 8_1 (OUT__3); Pin 8 (OUT__2) at same location as pin 8_1 (OUT__3); Power-named pins not typed as Power - library pin types incomplete [OUT=Passive]

15.2.1 Validation Heuristics

All pins same type: Generic library with no electrical rules

High % passive pins on IC: Incomplete type information

No power pins: May indicate separate power symbol

Low type diversity: Very underspecified library symbol

Power-named pins not typed as Power: Library pin types incomplete

15.3 Symbol vs Datasheet Pin Table

Each symbol's pin numbers are compared with the pin table of its datasheet. A datasheet pin the symbol lacks is a warning only when the datasheet calls it electrical; a pin the datasheet marks NC or mechanical, or a symbol pin the table does not list, is shown for information. An exposed pad is never counted as a mismatch, whether the symbol names it or numbers it one past the last pin. Where it was numbered, the row suggests giving it a name, because a bare number does not tell a reader what the pin is.

36 parts compared with their datasheet: 34 agree, 3 differ.

	Observation
RefDesModule401 Part NumberCM5 CM5 GPIO Pinssymbol 100 / datasheet 200	Datasheet pin 101 (USB_OTG_ID) is not on the symbol - a reset-time strap that sets USB 2.0 OTG role (host or device)
RefDesU301 Part NumberTPS2121RUXR TI TPS2121RUX Pinssymbol 16 / datasheet 12	Symbol pin 1_1 is not in the datasheet pin table Symbol pin 2_1 is not in the datasheet pin table Symbol pin 7_1 is not in the datasheet pin table Symbol pin 8_1 is not in the datasheet pin table
RefDesU303 Part NumberTPS2121RUXR TI TPS2121RUX Pinssymbol 16 / datasheet 12	Symbol pin 1_1 is not in the datasheet pin table Symbol pin 2_1 is not in the datasheet pin table Symbol pin 7_1 is not in the datasheet pin table Symbol pin 8_1 is not in the datasheet pin table

15.4 Shielded Connector Symbol Quality

Shielded connectors with missing pin names

All shielded connectors have proper pin names for EMC analysis.

15.5 I/O Bank Power

Module401 Raspberry-Pi@CM5.e654adfc.model.json: 1 I/O banks checked against the vendor package file; 84 of 84 symbol pin names agree with it

15.6 Footprints and Other Models

Components with model data

Component Model Assignments
RefDes	Industry Name	Pins	Model Type	Model
BT401	-	3	Footprint	Blackwing CM5 v1:Keystone-2998
D401	BAS116LT1G	3	Footprint	Package_TO_SOT_SMD:SOT-23-3
J101	SFM-120-01-X-D	40	Footprint	Blackwing CM5 v1:Samtec-SFM-120-01-X-D
J201	DX07S016JA1R1500	17	Footprint	Blackwing CM5 v1:JAE-DX07S016JA1R1500
J202	533984004	4	Footprint	Blackwing CM5 v1:Molex-0533984004-PicoBlade-53398
J501	MDT420M01002	69	Footprint	Blackwing CM5 v1:Amphenol-MDT420M01002-M.2-Key-M-2230-2242
J601	533984004	4	Footprint	Blackwing CM5 v1:Molex-0533984004-PicoBlade-53398
J701	FH12A-22S-0.5SH(55)	22	Footprint	Blackwing CM5 v1:Hirose-FH12A-22S-0.5SH-FPC-CSI-DSI
J702	FH12A-22S-0.5SH(55)	22	Footprint	Blackwing CM5 v1:Hirose-FH12A-22S-0.5SH-FPC-CSI-DSI
M501	M2.5	1	Footprint	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
M502	M2.5	1	Footprint	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
M503	M2.5	1	Footprint	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
M504	M2.5	1	Footprint	Blackwing CM5 v1:WE-9774025151R-SPACER-M2.5-2.5MM
Module401	10164227-1001A1RLF	100	Footprint	Blackwing CM5 v1:Amphenol-10164227-1001A1RLF-CM5-GPIO
Module402	10164227-1001A1RLF	100	Footprint	Blackwing CM5 v1:Amphenol-10164227-1001A1RLF-CM5-HSS
SW101	KMS223GP LFG	5	Footprint	Blackwing CM5 v1:CK-KMS223GP-LFG
SW102	KMS223GP LFG	5	Footprint	Blackwing CM5 v1:CK-KMS223GP-LFG
TP101	+3V3	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP102	+3V3_M.2	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP103	+5V	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP104	-	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP105	-	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP106	PMUX1_ST	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP107	PMUX2_ST	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP108	I2C_4_SCL	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP109	I2C_4_SDA	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP110	SPI_2_CS	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP111	SPI_2_PICO	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP112	SPI_2_POCI	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP113	SPI_2_SCL	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP114	UART_1_TX	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP115	UART_1_RX	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP116	UART_1_RTS	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP117	UART_1_CTS	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP118	GPIO2_BUS	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP301	PG1	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP302	VSW1	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP303	M.2_PGOOD	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
TP304	VSW2	1	Footprint	TestPoint:TestPoint_Pad_D1.0mm
U101	TPD4E1B06DRLR	6	Footprint	Blackwing CM5 v1:TI-TPD4E1B06DRL
U102	TPD4E1B06DRLR	6	Footprint	Blackwing CM5 v1:TI-TPD4E1B06DRL
U103	TPD4E1B06DRLR	6	Footprint	Blackwing CM5 v1:TI-TPD4E1B06DRL
U201	TPD4E1B06DRLR	6	Footprint	Blackwing CM5 v1:TI-TPD4E1B06DRL
U202	TPD4E1B06DRLR	6	Footprint	Blackwing CM5 v1:TI-TPD4E1B06DRL
U301	TPS2121RUXR	16	Footprint	Blackwing CM5 v1:TI-TPS2121
U302	FS1603A-5000-AL	17	Footprint	Blackwing CM5 v1:TDK-FS1606
U303	TPS2121RUXR	16	Footprint	Blackwing CM5 v1:TI-TPS2121
U304	FS1603A-3300-AL	17	Footprint	Blackwing CM5 v1:TDK-FS1606
U401	SN74AHCT1G04DBVR	5	Footprint	Package_TO_SOT_SMD:SOT-23-5
U501	ASEK-32.768KHZ-L-R-T	4	Footprint	Crystal:Crystal_SMD_3225-4Pin_3.2x2.5mm
U601	TPD4E1B06DRLR	6	Footprint	Blackwing CM5 v1:TI-TPD4E1B06DRL
U801	IAM-20380	16	Footprint	Blackwing CM5 v1:TDK-IAM-20380_IVS
U802	CY15B102Q-SXET	8	Footprint	Blackwing CM5 v1:Infineon-CY15B102Q-SXET

15.7 IC Pin Electrical Properties

Unique IC symbols	9
Total IC instances	15

IC Library Symbols
Industry Name	Library Name	RefDes	Notes
SN74AHCT1G04DBVR	74AHCT1G04	U401
ASEK-32.768KHZ-L-R-T	Abracon ASEK-32.768KHZ-L-R-T	U501
10164227-1001A1RLF	CM5 GPIO	Module401
CY15B102Q-SXET	Infineon CY15B102Q-SXET	U802
FS1603A-3300-AL	TDK FS1603A-3300-AL	U304
FS1603A-5000-AL	TDK FS1603A-5000-AL	U302
IAM-20380	TDK IAM-20380	U801
TPD4E1B06DRLR	TI TPD4E1B06DRLR	U101, U102, U103, U201, U202, U601
TPS2121RUXR	TI TPS2121RUX	U301, U303

15.7.1 74AHCT1G04 (SN74AHCT1G04DBVR)

Pin	Pin Name	Electrical
1	NC	Unknown
2		Input
3	GND	Power In
4		Output
5	VCC	Power In

15.7.2 Abracon ASEK-32.768KHZ-L-R-T (ASEK-32.768KHZ-L-R-T)

Pin	Pin Name	Electrical
1	OE	Input
2	GND	Power In
3	OUT	Output
4	Vdd	Power In

15.7.3 CM5 GPIO (10164227-1001A1RLF)

Pin	Pin Name	Electrical
1	GND	Power In
2	GND	Power In
3	Ethernet_Pair3_P	Passive
4	Ethernet_Pair1_P	Passive
5	Ethernet_Pair3_N	Passive
6	Ethernet_Pair1_N	Passive
7	GND	Power In
8	GND	Power In
9	Ethernet_Pair2_N	Passive
10	Ethernet_Pair0_N	Passive
11	Ethernet_Pair2_P	Passive
12	Ethernet_Pair0_P	Passive
13	GND	Power In
14	GND	Power In
15	Ethernet_nLED3(3.3v)	Output
16	FAN_TACHO	Input
17	Ethernet_nLED2(3.3v)	Output
18	Ethernet_SYNC_OUT(3.3v)	Input
19	FAN_PWM	Output
20	EEPROM_nWP	Passive
21	LED_nACT	Open Collector
22	GND	Power In
23	GND	Power In
24	GPIO26	Passive
25	GPIO21	Passive
26	GPIO19	Passive
27	GPIO20	Passive
28	GPIO13	Passive
29	GPIO16	Passive
30	GPIO6	Passive
31	GPIO12	Passive
32	GND	Power In
33	GND	Power In
34	GPIO5	Passive
35	ID_SC	Passive
36	ID_SD	Passive
37	GPIO7	Passive
38	GPIO11	Passive
39	GPIO8	Passive
40	GPIO9	Passive
41	GPIO25	Passive
42	GND	Power In
43	GND	Power In
44	GPIO10	Passive
45	GPIO24	Passive
46	GPIO22	Passive
47	GPIO23	Passive
48	GPIO27	Passive
49	GPIO18	Passive
50	GPIO17	Passive
51	GPIO15	Passive
52	GND	Power In
53	GND	Power In
54	GPIO4	Passive
55	GPIO14	Passive
56	GPIO3	Passive
57	SD_CLK	Passive
58	GPIO2	Passive
59	GND	Power In
60	GND	Power In
61	SD_DAT3	Passive
62	SD_CMD	Passive
63	SD_DAT0	Passive
64	SD_DAT5	Passive
65	GND	Power In
66	GND	Power In
67	SD_DAT1	Passive
68	SD_DAT4	Passive
69	SD_DAT2	Passive
70	SD_DAT7	Passive
71	GND	Power In
72	SD_DAT6	Passive
73	SD_VDD_Override	Input
74	GND	Power In
75	SD_PWR_ON	Output
76	VBAT	Passive
77	+5v_(Input)	Power In
78	GPIO_VREF(1.8v/3.3v_Input)	Power In
79	+5v_(Input)	Power In
80	SCL0	Passive
81	+5v_(Input)	Power In
82	SDA0	Passive
83	+5v_(Input)	Power In
84	+3.3v_(Output)	Power Out
85	+5v_(Input)	Power In
86	+3.3v_(Output)	Passive
87	+5v_(Input)	Power In
88	+1.8v_(Output)	Power Out
89	WiFi_nDisable	Input
90	+1.8v_(Output)	Passive
91	BT_nDisable	Input
92	PWR_BUT	Passive
93	nRPIBOOT	Input
94	CC1	Passive
95	LED_nPWR	Output
96	CC2	Passive
97	CAM_GPIO0	Passive
98	GND	Power In
99	PMIC_ENABLE	Input
100	CAM_GPIO1	Passive

15.7.4 Infineon CY15B102Q-SXET (CY15B102Q-SXET)

Pin	Pin Name	Electrical
1	CS	Input
2	SO	Output
3	WP	Input
4	VSS	Power Out
5	SI	Input
6	SCK	Input
7	HOLD	Input
8	VDD	Power In

15.7.5 TDK FS1603A-3300-AL (FS1603A-3300-AL)

Pin	Pin Name	Electrical
1	SDA	Bidirectional
2	PG	Output
3	EN	Input
4	SCL	Input
5	FB	Unknown
6	ADDR	Unknown
7	VOUT	Output
8	PGND	Power Out
9	AGND	Power Out
10	VCC	Power In
11	VIN	Power In
12	PVIN	Power In
13	PVIN	Power In
14	PVIN	Power In
15	VSW	Unknown
16	PGND	Power Out
17	PVIN	Power In

15.7.6 TDK FS1603A-5000-AL (FS1603A-5000-AL)

Pin	Pin Name	Electrical
1	SDA	Bidirectional
2	PG	Output
3	EN	Input
4	SCL	Input
5	FB	Unknown
6	ADDR	Unknown
7	VOUT	Output
8	PGND	Power Out
9	AGND	Power Out
10	VCC	Power In
11	VIN	Power In
12	PVIN	Power In
13	PVIN	Power In
14	PVIN	Power In
15	VSW	Unknown
16	PGND	Power Out
17	PVIN	Power In

15.7.7 TDK IAM-20380 (IAM-20380)

Pin	Pin Name	Electrical
1	VDDIO	Power In
2	SCL/SPC	Bidirectional
3	SDA/SDI	Input
4	SA0/SDO	Output
5	CS	Bidirectional
6	INT	Output
7	RESV	Unknown
8	FSYNC	Input
9	RESV	Power Out
10	RESV	Power Out
11	RESV	Power Out
12	RESV	Power Out
13	GND	Power Out
14	REGOUT	Output
15	RESV	Power Out
16	VDD	Power In

15.7.8 TI TPD4E1B06DRLR (TPD4E1B06DRLR)

Pin	Pin Name	Electrical
1		Bidirectional
2	GND	Power In
3		Bidirectional
4		Bidirectional
5	NC	Unknown
6		Bidirectional

15.7.9 TI TPS2121RUX (TPS2121RUXR)

Pin	Pin Name	Electrical
1	OUT	Passive
1_1	OUT__1	Passive
2	IN2	Input
2_1	IN2__1	Input
3	CP2	Input
4	OV2	Input
5	OV1	Input
6	PR1	Input
7	IN1	Input
7_1	IN1__1	Input
8	OUT__2	Passive
8_1	OUT__3	Passive
9	ST	Output
10	ILIM	Passive
11	SS	Passive
12	GND	Power In