Raspberry Pi Compute Module Carrier Board — PCB Design Review

A full PCB design review of a real Raspberry Pi Compute Module carrier board schematic, recorded with the engineer who designed it. The three parts follow the same order a submission does: first the design itself and what a review looks for; then the free preliminary report — hierarchy, component and property consistency, part numbers, rail voltages and test point coverage, with the score that comes out of it; and finally the AI enrichment pass, which reads the component datasheets and checks values, configuration strapping, absolute maximum ratings and derating margins against them. The reports on screen were produced by the tool on this design, and the designer answers each finding as it comes up.

CM4 carrier, CM5 carrier, CM4S carrier — the same schematic review

The board reviewed in these videos is a CM4S carrier — Compute Module 4 silicon in the SODIMM form factor of the earlier modules. Nothing in the review is module-specific: the hierarchy and property checks, the part numbers, the rail voltage annotation, the test point and DFT coverage, and the datasheet and derating work are all done on the schematic. If you are designing a Raspberry Pi Compute Module carrier board — a CM4 carrier, a CM5 carrier, or a CM4S carrier — this is the same review your design would get.

The designer is Petr Dvorak, known in the KiCad community as That KiCad guy.

PCB Design Review for Raspberry Pi CM4S

English subtitles are available from the CC button in each player.

Part 1 — The design, and what a schematic review looks for (39 min)

A walkthrough of the CM4S carrier design itself, and of what makes a schematic worth reviewing before layout: missing or conflicting data, datasheet questions nobody has time to chase, and test access that has to be designed in rather than added later. Sets up what the platform is doing and why the review happens at schematic stage.

Part 2 — The preliminary report and the score (1 h 3 min)

The preliminary report for this design, section by section: hierarchy and sheet count, component and property consistency, footprint and property naming, part numbers and vendor links, rail voltage annotation, differential pair naming, and the test point and DFT coverage the report asks for. The design scores 88 out of 100, and the discussion covers where the points went and which findings the designer agrees with. This pass costs nothing to run.

Part 3 — AI enrichment: datasheets, ratings and derating (1 h 31 min)

The AI enrichment pass on the same design: the design overview it writes, power elements and USB Type-C, resistor values and configuration strapping, absolute maximum ratings, and the derating margins checked against each component datasheet. The designer responds to the findings one by one, both the ones that turn out to be minor and the ones worth changing.