Why Tomachie?
Engineers leave. Companies get acquired. Contractors rotate. The new hire inherits fifteen sheets of someone else’s thinking with no documentation.
Tomachie surfaces what’s in the design so the next engineer isn’t starting from zero—and so the original designer has documentation they never had to write.
Three capabilities set Tomachie apart. Generative DFT automatically inserts test points to hit your stuck-at fault coverage targets before layout begins. Semantic auditing traces impedance paths across devices, validates JTAG chains against BSDL, and catches the library errors that human reviews miss. PCOLA-SOQ scoring quantifies your manufacturing risk with letter grades (A–F) based on real-world testability metrics.
You know your design is good — prove it to stakeholders with a Tomachie score. Every analysis produces a score out of 100 with detailed breakdown of what needs to change to rank higher. If you wish, your top score is shared on our statistics page alongside the top designers.
Generative DFT: Dial in Fault Coverage Automatically
Most ERC tools complain. Tomachie acts. Set a target, get a hardened design back.
Targeted Coverage
Set your stuck-at fault coverage or PCOLA-SOQ target percentage. Tomachie figures out which nets need test points and how many to add to hit it.
Automated Insertion
Test point components are placed directly in your schematic files — native Altium symbols, native KiCad symbols. No manual pad-by-pad guesswork. The modified project comes back ready to open.
Space Budget for Layout
Adding test points at the schematic stage gives layout a defined footprint count from the start. No late-stage routing congestion. No signal-integrity compromises from shoehorned TPs after the fact.
The first time you run Tomachie with a target, your modified schematic comes back with the test points already in place. Open it in Altium or KiCad — the work is done.
Report Contents
- Design Summary
- Pin Connectivity Report
- Memory Interface Analysis
- Low-Speed Serial Interfaces
- Connector Pinouts
- Physical Testpoint DFT
- EMC Design Checks
- Schematic Library Quality
- Switch Documentation
- HSSI / Differential Pair Analysis
- Boundary Scan / JTAG Chain Validation
- PCOLA-SOQ Scoring
Analysis Engines
See detailed engine documentation →
Schematic Lint Engine
Semantic auditing beyond native ERC — catches mischaracterized pins, broken impedance paths, and property errors invisible to standard rule checks.
Library Model Evaluation
Letter-grades library model quality, enforces uniformity across the design.
Schematic Review Engine
Cross-sheet consistency, interface validation, EMC checks, LSSI/HSSI usage.
Documentation Engine
Connector pinouts, signal tables, test point tables, component summaries.
DFT Engine
Generative design-for-test: set your target stuck-at fault coverage or PCOLA-SOQ percentage and Tomachie auto-inserts test point components into your schematic. Predicts AXI, AOI, ICT, flying probe, and boundary scan coverage. Returns a modified project ready for layout.