Example Design Review Documents

Standard ERC looks at nets. Tomachie looks at paths — verifying differential pair integrity and impedance continuity across the entire signal chain, even through passive components and connectors. It finds what's hidden: mischaracterized pins, broken impedance paths, and invisible property errors that break your layout wizards. These pre-generated reports show the full analysis output, each containing 10,000+ words of DFT analysis, EMC checks, PCOLA-SOQ scoring, connector pinouts, and testpoint coverage documentation:

• FPGA1394V3 Design Review — IEEE 1394 FireWire interface with Xilinx XC7Z020 FPGA, BSDL boundary scan analysis, JTAG chain validation
• MB1191 Design Review — STM32 Nucleo-144 development board with ARM Cortex-M processor
• TIDA-050036 Design Review — Texas Instruments industrial base board reference design

Sample Report Output

Tomachie generates an interactive HTML report with navigable sections. Here's what you'll receive:

Switch DFT analysis — identifies configuration switches lacking test override capability, calculates isolation resistor values for ATE compatibility.

Testpoint inventory with power rail coverage analysis — every power net checked for test access.

EMC design checks, component library validation, and footprint/model audit — all in one report.

The left navigation panel lets you jump directly to any section. Reports include Design Summary, Pin Connectivity, Memory Interfaces, Serial Interfaces, Connector Pinouts, DFT Analysis, Library Quality grades, and more.

What to Upload

ZIP your schematic files and upload. Here's what we need:

Tip: When requesting schematics from a designer or contractor, ask for the project files (.PrjPcb or .kicad_pro) along with the schematic files. Many designers forget to include them.